Array substrate and liquid crystal display panel

Abstract

The present application provides an array substrate and a liquid crystal display panel. The array substrate includes a substrate, a first metal layer, a second metal layer, and a pixel electrode layer stacked in sequence. The first metal layer includes a plurality of scan lines extending along a first direction. The second metal layer includes a plurality of first shared electrodes extending along the first direction and a plurality of data lines extending along a second direction. The pixel electrode layer includes a plurality of pixel electrodes, including a primary pixel electrode and a secondary pixel electrode. The orthographic projection of the scan line on the substrate is located between the orthographic projection of the primary pixel electrode and the orthographic projection of the secondary pixel electrode on the substrate, and the orthographic projection of the first shared electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate. At least one first shared electrode is provided on either side of a center plane of the scan line. The array substrate provided by the present application can improve signal interference between the scan line and the pixel electrode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to an array substrate and a liquid crystal display panel. Background Art

[0002] Because traditional vertically aligned liquid crystal display (LCD) panels suffer from limited viewing angles, multi-domain vertical alignment (MDVA) technology is often used to improve the viewing angle characteristics of LCD panels. This technology divides a sub-pixel into a primary pixel and a secondary pixel, each further divided into multiple domains. In a multi-domain LCD panel structure, scan lines are typically placed between the primary and secondary pixels to improve the aperture ratio. However, this arrangement causes the scan line signal to interfere with the pixel electrode signal, impacting the performance of the LCD panel. Summary of the Invention

[0003] The present application provides an array substrate and a liquid crystal display panel to improve the signal interference problem between scan lines and pixel electrodes.

[0004] The present application provides an array substrate, comprising:

[0005] substrate;

[0006] a first metal layer disposed on the substrate, the first metal layer comprising a plurality of scanning lines extending along a first direction;

[0007] a second metal layer disposed on the first metal layer, the second metal layer comprising a plurality of first common electrodes extending along the first direction and a plurality of data lines extending along a second direction, the second direction being perpendicular to the first direction;

[0008] a pixel electrode layer, disposed on the second metal layer, the pixel electrode layer comprising a plurality of pixel electrodes, the pixel electrodes comprising a primary pixel electrode and a secondary pixel electrode;

[0009] The orthographic projection of the scan line on the substrate is located between the orthographic projection of the primary pixel electrode on the substrate and the orthographic projection of the secondary pixel electrode on the substrate, the first shared electrode is arranged close to the scan line, and the orthographic projection of the first shared electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate;

[0010] The scan line has a central plane extending along the first direction. The scan line is symmetrical about the central plane. At least one first common electrode is disposed on each side of the central plane.

[0011] In one embodiment, the pixel electrode includes a plurality of trunk electrodes and a plurality of branch electrodes, the plurality of trunk electrodes intersect to define a plurality of domains, and the branch electrodes are located in the domains;

[0012] The main pixel electrode includes a first trunk electrode extending along a first direction and a second trunk electrode extending along a second direction, wherein the first trunk electrode intersects with the second trunk electrode to divide the main pixel electrode into four domains arranged along the first direction;

[0013] The sub-pixel electrode includes a third trunk electrode extending along a first direction and a fourth trunk electrode extending along a second direction. The third trunk electrode intersects with the fourth trunk electrode to divide the sub-pixel electrode into four domains arranged along the first direction.

[0014] In one embodiment, along the first direction, the branch electrodes in two adjacent domains are mirror-imaged with respect to the main electrode between the two adjacent domains.

[0015] In one embodiment, the orthographic projection of the first shared electrode on the substrate at least partially overlaps with the orthographic projection of the trunk electrode on the substrate.

[0016] In one embodiment, the second metal layer further includes a second common electrode extending along the first direction, the orthographic projection of the second common electrode on the substrate is located between the gaps between the orthographic projections of two adjacent pixel electrodes on the substrate, and the second common electrode is connected to the first common electrode.

[0017] In one embodiment, the array substrate further includes a first thin film transistor, a second thin film transistor, and a third thin film transistor located at one end of the pixel electrode in the first direction, the first thin film transistor is connected to the main pixel electrode, the second thin film transistor is connected to the sub-pixel electrode, and the third thin film transistor is connected to the second shared electrode.

[0018] In one embodiment, the first metal layer further includes a common electrode extending along the first direction, and a gap between orthographic projections of two adjacent pixel electrodes on the substrate is within the range of the orthographic projection of the common electrode on the substrate.

[0019] In one embodiment, the array substrate further includes a first shielding electrode and a second shielding electrode, wherein the orthographic projection of the first shielding electrode on the substrate covers the orthographic projection of the scan line on the substrate, and the orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate.

[0020] In one embodiment, the intersection of the scan line and the data line defines a plurality of sub-pixels, and one sub-pixel includes one pixel electrode; the plurality of sub-pixels are arranged in an array, including a plurality of sub-pixels of the same color arranged along the first direction, and a plurality of sub-pixels of different colors periodically arranged along the second direction.

[0021] The present application also provides a liquid crystal display panel, comprising the array substrate as described above.

[0022] The present application provides an array substrate and a liquid crystal display panel. The array substrate of the present application stacks a scan line, a first common electrode, and a pixel electrode in sequence, that is, the first common electrode is arranged between the scan line and the pixel electrode in a direction perpendicular to the substrate, and in a direction parallel to the substrate, first common electrodes are respectively arranged on both sides of the center plane of the scan line. The first common electrode in the array substrate is used as a shielding electrode to shield or reduce the interference of the scan line signal on the pixel electrode signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A driving architecture diagram of an array substrate provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a pixel structure of an array substrate provided in an embodiment of the present application;

[0026] Figure 3 A schematic structural diagram of a first metal layer of an array substrate provided in an embodiment of the present application;

[0027] Figure 4 A schematic structural diagram of a second metal layer of an array substrate provided in an embodiment of the present application;

[0028] Figure 5 A schematic structural diagram of a pixel electrode layer of an array substrate provided in an embodiment of the present application;

[0029] Figure 6 for Figure 2 Schematic diagram of the cross section at AA in the middle;

[0030] Figure 7 for Figure 2 Schematic diagram of the cross section at the middle BB;

[0031] Figure 8 A schematic diagram of the pixel structure of another array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0033] In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0034] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0035] Please refer to Figure 1-Figure 5 The present application provides an array substrate, comprising: a substrate; a first metal layer, arranged on the substrate, the first metal layer comprising a plurality of scanning lines (Gate) 110 extending along a first direction (X direction); a second metal layer, arranged on the first metal layer, the second metal layer comprising a plurality of first shared electrodes (Sharebar) 221 extending along the first direction and a plurality of data lines (Date) 210 extending along a second direction (Y direction), the second direction being perpendicular to the first direction; a pixel electrode layer, arranged on the second metal layer, the pixel electrode layer comprising a plurality of pixel electrodes 300, the pixel electrodes 300 comprising a main pixel electrode 310 and a sub-pixel electrode 320; wherein, the orthographic projection of the scan line 110 on the substrate is located between the orthographic projection of the main pixel electrode 310 on the substrate and the orthographic projection of the sub-pixel electrode 320 on the substrate, the first shared electrode 221 is arranged close to the scan line 110, and the orthographic projection of the first shared electrode 221 on the substrate at least partially overlaps with the orthographic projection of the pixel electrode 300 on the substrate; the scan line 110 has a central plane extending along the first direction, the scan line 110 is symmetrical about the central plane, and at least one first shared electrode 221 is arranged on each side of the central plane.

[0036] In order to improve the aperture ratio, the present application sets the scanning line 110 between the gap between the main pixel electrode 310 and the sub-pixel electrode 320. In order to avoid or reduce the coupling of the signal of the scanning line 110 to the signal of the pixel electrode 300, the present application stacks the scanning line 110, the first shared electrode 221, and the pixel electrode 300 in sequence, so that the first shared electrode 221 is located between the scanning line 110 and the pixel electrode 300 in a direction perpendicular to the substrate. At the same time, the first shared electrodes 221 are respectively arranged on both sides of the center plane of the scanning line 110 in a direction parallel to the substrate. The first shared electrode 221 already in the array substrate is used as a shielding electrode to shield or reduce the signal interference between the scanning line 110 and the pixel electrode 300.

[0037] like Figure 1-2 As shown, the plurality of scanning lines 110 and the plurality of data lines 210 on the array substrate intersect to define a plurality of sub-pixels 100, and the plurality of sub-pixels 100 are arranged in an array, wherein the plurality of sub-pixels 100 include red sub-pixels, green sub-pixels and blue sub-pixels. Taking the tri-gate driving architecture as an example, the array substrate includes a plurality of sub-pixels of the same color arranged along the first direction, and a plurality of sub-pixels of different colors periodically arranged along the second direction. Figure 1 As shown, the Tri-gate drive architecture arranges sub-pixels of the same color in the horizontal direction (X direction) and periodically arranges RGB sub-pixels in the vertical direction (Y direction). The number of data lines 210 in the Tri-gate drive architecture is reduced to 1 / 3 of that in the conventional drive architecture, so the chip-on-film (COF) of the Tri-gate drive architecture is reduced to 1 / 3 of that in the conventional drive architecture, and the number of scan lines 110 is increased to 3 times that of the conventional drive architecture. However, the scan line 110 drive circuit can be integrated on the side of the panel through GOA technology. Compared with the traditional drive architecture, the Tri-gate drive architecture has a higher driving speed and lower power consumption, which greatly reduces the cost.

[0038] A conventional Tri-gate driving architecture generally adopts a 4-domain pixel structure. This application proposes an 8-domain pixel structure of a Tri-gate driving architecture to further illustrate the array substrate structure of this application.

[0039] like Figure 2 As shown, in the array substrate structure, each of the sub-pixels 100 includes a main pixel and a sub-pixel. The main pixel includes the main pixel electrode 310 , and the sub-pixel includes the sub-pixel electrode 320 .

[0040] Each of the pixel electrodes 300 includes a plurality of main electrodes and a plurality of branch electrodes, and the plurality of main electrodes intersect to define a plurality of domain areas, and the branch electrodes are located within the domain areas; wherein, some of the main electrodes extend along the first direction, and some of the main electrodes extend along the second direction, and the branch electrodes are arranged obliquely relative to the main electrodes, and each of the domain areas includes a plurality of obliquely arranged branch electrodes.

[0041] The main pixel electrode 310 includes a first main electrode 311 extending along a first direction and a second main electrode 312 extending along a second direction. The first main electrode 311 and the second main electrode 312 intersect to divide the main pixel electrode 310 into four domains. Figure 5 As shown, the main pixel electrode 310 includes a first domain 301, a second domain 302, a third domain 303 and a fourth domain 304; the sub-pixel electrode 320 includes a third trunk electrode 321 extending along the first direction and a fourth trunk electrode 322 extending along the second direction. The third trunk electrode 321 intersects with the fourth trunk electrode 322 to divide the sub-pixel electrode 320 into four domains. Figure 5 As shown, the sub-pixel electrode 320 includes a fifth domain 305, a sixth domain 306, a seventh domain 307 and an eighth domain 308. In the 8-domain pixel structure, the liquid crystal in one sub-pixel 100 can have 8 different tilt angles, thereby achieving a wide viewing angle.

[0042] Furthermore, the primary pixel electrode 310 and the secondary pixel electrode 320 are arranged along the two directions. The four domains of the primary pixel electrode 310 are arranged along the first direction, namely, the first domain 301, the second domain 302, the third domain 303, and the fourth domain 304 are arranged along the first direction. The four domains of the secondary pixel electrode 320 are arranged along the first direction, namely, the fifth domain 305, the sixth domain 306, the seventh domain 307, and the eighth domain 308 are arranged along the first direction. In this embodiment, the four domains of the primary pixel electrode 310 and the four domains of the secondary pixel electrode 320 are arranged in a straight line from left to right. Compared to the traditional structure where the four domains are arranged vertically, horizontally, or left to right, this is more conducive to wiring layout and improves the aperture ratio.

[0043] In one embodiment, along the first direction, the branch electrodes in two adjacent domains are mirror-imaged with respect to the main electrode between the two adjacent domains. Figure 5As shown, the branch electrodes in the first domain 301 and the branch electrodes in the second domain 302 are mirror-imaged with respect to the second main electrode 312 therebetween; the branch electrodes in the third domain 303 and the branch electrodes in the fourth domain 304 are mirror-imaged with respect to the second main electrode 312 therebetween; the branch electrodes in the fifth domain 305 and the branch electrodes in the sixth domain 306 are mirror-imaged with respect to the fourth main electrode 322 therebetween; and the branch electrodes in the seventh domain 307 and the branch electrodes in the eighth domain 308 are mirror-imaged with respect to the fourth main electrode 322 therebetween. Since the viewing angle characteristics of a liquid crystal display panel are related to the tilting direction of the liquid crystal, which is related to the tilting direction of the branch electrodes, mirror-imaged arrangement of the branch electrodes in two adjacent domains can ensure uniformity in the tilting direction of the liquid crystal, thereby improving the viewing angle characteristics.

[0044] In one embodiment, the orthographic projection of the first common electrode 221 on the substrate at least partially overlaps with the orthographic projection of the main electrode on the substrate, that is, the first common electrode 221 is disposed below the main electrode, reducing the area occupied by the first common electrode 221 to further improve the aperture ratio. Furthermore, the orthographic projection of the first common electrode 221 on the substrate can be covered by the orthographic projection of the main electrode on the substrate.

[0045] like Figure 2 and Figure 4 As shown, the first common electrode 221 can be arranged below the adjacent first trunk electrode 311 and the third trunk electrode 321 between the primary pixel and the secondary pixel, and one first common electrode 221 is arranged on each side of the scan line 110 in the horizontal direction. Figure 6 As shown, Figure 2 In the cross-sectional view at AA, the scan line 110, the first common electrode 221, and the pixel electrode 300 are stacked in sequence. The orthographic projection of the scan line 110 on the substrate is located between the gap between the orthographic projection of the primary pixel electrode 310 and the orthographic projection of the secondary pixel electrode 320 of one of the sub-pixels 100 on the substrate. The scan line 110 has a central plane CC extending in the first direction. The scan line 110 is symmetrical about the central plane CC. A first common electrode 221 is provided on each side of the central plane CC. The first common electrodes 221 on both sides of the scan line 110 can shield or reduce signal coupling between the scan line 110 and the adjacent primary pixel electrode 310 and the secondary pixel electrode 320 on both sides thereof. In addition, the first common electrode 221 can also increase the storage capacitance between the pixel electrode 300 and the first common electrode 221.

[0046] Furthermore, the first shared electrodes 221 on both sides of the center plane CC can be symmetrically arranged about the center plane CC, and the projection of the first shared electrode 221 on the substrate can at least partially overlap with the projection of the scanning line 110 on the substrate to block the gap between the scanning line 110 and the pixel electrode 300 to prevent light leakage.

[0047] like Figure 4 As shown, the second metal layer also includes a second shared electrode 222, which extends along the first direction. The orthographic projection of the second shared electrode 222 on the substrate is located between the gap between the orthographic projections of two adjacent pixel electrodes 300 on the substrate. The second shared electrode 222 is connected to the first shared electrode 221. Using the gap between two adjacent sub-pixels to set the second shared electrode 222 is beneficial for improving the aperture ratio. The second metal layer also includes a third shared electrode 223, which is used to connect the second shared electrode 222 and the first shared electrode 221. The third shared electrode 223 is arranged along the second direction, and the projection of the third shared electrode 223 on the substrate is located within the orthographic projection range of the second trunk electrode 312 and the fourth trunk electrode 322 on the substrate, which is beneficial for improving the aperture ratio.

[0048] In one embodiment, the array substrate further includes a first thin film transistor 230, a second thin film transistor 240, and a third thin film transistor 250 located at one end of the pixel electrode 300 in the first direction, the first thin film transistor 230 is connected to the main pixel electrode 310 to control the main pixel, the second thin film transistor 240 is connected to the sub-pixel electrode 320 to control the sub-pixel, and the third thin film transistor 250 is connected to the second shared electrode 222 as a voltage-dividing thin film transistor.

[0049] Specifically, such as Figure 2 and Figure 4 As shown, each sub-pixel 100 is provided with a first thin film transistor 230, a second thin film transistor 240 and a third thin film transistor 250, and the first thin film transistor 230, the second thin film transistor 240 and the third thin film transistor 250 are provided on the same side of the corresponding sub-pixel 100 to improve the aperture ratio. Figure 2As shown, the first thin film transistor 230, the second thin film transistor 240 and the third thin film transistor 250 can be arranged at the left side or the right side of the sub-pixel at the same time, and the second thin film transistor 240 is located between the first thin film transistor 230 and the third thin film transistor 250, the first thin film transistor 230 is close to the main pixel electrode 310, and the second thin film transistor 240 is close to the sub-pixel electrode 320, and the first thin film transistor 230, the second thin film transistor 240 and the third thin film transistor 250 are arranged along the second direction to reduce the space occupied by the thin film transistors and further improve the aperture ratio.

[0050] Among them, the first thin film transistor 230 includes a first source and a first drain, the first source is connected to the data line 210, and the first drain is connected to the main pixel electrode 310; the second thin film transistor 240 includes a second source and a second drain, the second source is connected to the data line 210, and the second drain is connected to the sub-pixel electrode 320; the third thin film transistor 250 includes a third source and a third drain, the third source is connected to the second source, and the third drain is connected to the second common electrode 222. Therefore, part of the drain current in the second thin film transistor 240 will drive the pixel electrode of the sub-pixel, and the other part of the drain current will be diverted to the second common electrode 222 through the third thin film transistor 250, so that the voltage of the sub-pixel is different from that of the main pixel, so that the liquid crystal molecules of the sub-pixel and the main pixel have different rotation angles, thereby improving the viewing angle.

[0051] In one embodiment, if Figure 3 and Figure 7 As shown, the first metal layer further includes a common electrode 120, which is disposed between two adjacent sub-pixels 100. Utilizing the gap between the two adjacent sub-pixels 100 to dispose the common electrode 120 is beneficial for improving the aperture ratio. Furthermore, the gap between the orthographic projections of two adjacent pixel electrodes 300 on the substrate is within the range of the orthographic projection of the common electrode 120 on the substrate.

[0052] like Figure 2 and Figure 3 As shown, the common electrode 120 includes a first sub-common electrode 121 and a second sub-common electrode 122. The first sub-common electrode 121 is connected to the main pixel electrode 310 through a first via hole 260 to realize a storage capacitor between the common electrode 120 and the main pixel electrode 310. The second sub-common electrode 122 is connected to the sub-pixel electrode 320 through a second via hole 270 to realize a storage capacitor between the common electrode 120 and the sub-pixel electrode 320.

[0053] like Figure 7 As shown, the orthographic projection area of ​​the common electrode 120 on the substrate covers and is larger than the orthographic projection area of ​​the gap between two adjacent pixel electrodes 300 on the substrate, so as to avoid light leakage in the gap between the common electrode 120 and the pixel electrode 300 and reduce the risk of color deviation.

[0054] like Figure 7 As shown, the array substrate further includes an insulating layer 101 , a color resist layer 102 and a passivation layer 103 stacked between the second metal layer and the pixel electrode 300 layer, but is not limited thereto.

[0055] In the present application, the first shared electrode 221 in the array substrate is used as a shielding electrode to shield or reduce the signal interference between the scan line 110 and the pixel electrode 300, and the first shared electrode 221 can also increase the storage capacitance between the pixel electrode 300 and the first shared electrode 221, thereby improving the stability and quality of the product. In addition, the array substrate of the present application does not need to set a shielding electrode above the data line 210, which has a relatively small load on the data line, and the storage capacitance is larger, and the image quality is more stable. In addition, the pixel structure and routing design of the present application can further reduce the distance between pixel electrodes, and the aperture ratio is larger.

[0056] In some embodiments, as Figure 8 As shown, the array substrate may further include a first shielding electrode (GBS) 610 and a second shielding electrode (DBS) 620. The GBS is disposed above the scan line 110, i.e., the projection of the GBS on the substrate covers the projection of the scan line 110 on the substrate, thereby further reducing the coupling of the signal of the scan line 110 with the signal of the pixel electrode 300. The DBS is disposed above the data line 210, i.e., the projection of the DBS on the substrate covers the projection of the data line 210 on the substrate, thereby reducing the coupling of the signal of the data line 210 with the signal of the pixel electrode 300.

[0057] The present application also provides a liquid crystal display panel, comprising the array substrate as described above, an opposing substrate 500 disposed opposite to the array substrate, and a liquid crystal layer 400 located between the array substrate and the opposing substrate 500 .

[0058] The liquid crystal display panel may be a vertical alignment liquid crystal display panel (VA-LCD). Furthermore, the vertical alignment liquid crystal display panel may have a Tri-gate driving architecture and an 8-domain pixel structure.

[0059] This application uses an 8-domain pixel structure with a Tri-gate drive architecture to improve viewing angle characteristics while maintaining the transmittance and quality specifications of the LCD panel, thereby promoting the application of LCD panels in large-size UD products.

[0060] The following further illustrates the liquid crystal display panel of the present application through experimental data.

[0061] Electrical simulation experiments were conducted on a vertically aligned liquid crystal display panel with a 4-domain pixel structure and a vertically aligned liquid crystal display panel with an 8-domain pixel structure using a Tri-gate drive architecture, and the main quality parameters were evaluated as shown in Table 1.

[0062] Table 1

[0063]

[0064] Table 1 shows the storage capacitance ratio and vertical crosstalk level data for the vertical alignment LCD panel with an 8-domain pixel structure using the Tri-gate drive architecture of this application, compared to the traditional vertical alignment LCD panel with a 4-domain pixel structure using the Tri-gate drive architecture. As can be seen from Table 1, the vertical alignment LCD panel with an 8-domain pixel structure using the Tri-gate drive architecture of this application performs better in terms of storage capacitance and vertical crosstalk, and has better stability and quality, approaching mass production levels.

[0065] In summary, the present application provides an array substrate and a liquid crystal display panel. The array substrate of the present application stacks the scanning line, the first common electrode, and the pixel electrode in sequence, that is, in the direction perpendicular to the substrate, the first common electrode is arranged between the scanning line and the pixel electrode, and in the direction parallel to the substrate, the first common electrodes are respectively arranged on both sides of the center plane of the scanning line. The first common electrode in the array substrate is used as a shielding electrode to shield or reduce the interference of the signal of the scanning line on the signal of the pixel electrode.

[0066] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. An array substrate, characterized in that: include: substrate; a first metal layer disposed on the substrate, the first metal layer comprising a plurality of scanning lines extending along a first direction; a second metal layer disposed on the first metal layer, the second metal layer comprising a plurality of first common electrodes extending along the first direction and a plurality of data lines extending along a second direction, the second direction being perpendicular to the first direction; a pixel electrode layer, disposed on the second metal layer, the pixel electrode layer comprising a plurality of pixel electrodes, the pixel electrodes comprising a primary pixel electrode and a secondary pixel electrode; The orthographic projection of the scan line on the substrate is located between the orthographic projection of the primary pixel electrode on the substrate and the orthographic projection of the secondary pixel electrode on the substrate, the first shared electrode is arranged close to the scan line, and the orthographic projection of the first shared electrode on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate; The scan line has a central plane extending along the first direction. The scan line is symmetrical about the central plane. At least one first common electrode is disposed on each side of the central plane.

2. The array substrate according to claim 1, wherein: The pixel electrode includes a plurality of trunk electrodes and a plurality of branch electrodes, wherein the plurality of trunk electrodes intersect to define a plurality of domains, and the branch electrodes are located in the domains; The main pixel electrode includes a first trunk electrode extending along a first direction and a second trunk electrode extending along a second direction, wherein the first trunk electrode intersects with the second trunk electrode to divide the main pixel electrode into four domains arranged along the first direction; The sub-pixel electrode includes a third trunk electrode extending along a first direction and a fourth trunk electrode extending along a second direction. The third trunk electrode intersects with the fourth trunk electrode to divide the sub-pixel electrode into four domains arranged along the first direction.

3. The array substrate according to claim 2, wherein: Along the first direction, the branch electrodes in two adjacent domains are arranged in a mirror image with respect to the main electrode between the two adjacent domains.

4. The array substrate according to claim 2, wherein: The orthographic projection of the first shared electrode on the substrate at least partially overlaps with the orthographic projection of the trunk electrode on the substrate.

5. The array substrate according to claim 1, wherein: The second metal layer further includes a second common electrode extending along the first direction, the orthographic projection of the second common electrode on the substrate is located between the orthographic projections of two adjacent pixel electrodes on the substrate, and the second common electrode is connected to the first common electrode.

6. The array substrate according to claim 5, wherein: The array substrate also includes a first thin film transistor, a second thin film transistor and a third thin film transistor located at one end of the pixel electrode in the first direction, the first thin film transistor is connected to the main pixel electrode, the second thin film transistor is connected to the sub-pixel electrode, and the third thin film transistor is connected to the second shared electrode.

7. The array substrate according to claim 1, wherein: The first metal layer further includes a common electrode extending along a first direction, and a gap between orthographic projections of two adjacent pixel electrodes on the substrate is located within the range of the orthographic projections of the common electrode on the substrate.

8. The array substrate according to claim 1, wherein: The array substrate further includes a first shielding electrode and a second shielding electrode. The orthographic projection of the first shielding electrode on the substrate covers the orthographic projection of the scan line on the substrate. The orthographic projection of the second shielding electrode on the substrate covers the orthographic projection of the data line on the substrate.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The intersection of the scan line and the data line defines a plurality of sub-pixels, and one sub-pixel includes one pixel electrode; the plurality of sub-pixels are arranged in an array, including a plurality of sub-pixels of the same color arranged along the first direction, and a plurality of sub-pixels of different colors periodically arranged along the second direction.

10. A liquid crystal display panel, characterized in that: The invention comprises an array substrate as described in any one of claims 1 to 9.

Images