Phase anomaly detection method, device and computer program product for LED display screen
By using a hardware connection between the FPGA and the driver IC, signals are sent and received and phase anomalies are detected, solving the problem of signal phase differences caused by components and temperature rise in LED displays, and achieving efficient phase anomaly detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU HIKVISION DIGITAL TECHNOLOGY CO LTD
- Filing Date
- 2023-12-27
- Publication Date
- 2026-06-23
AI Technical Summary
LED displays may experience display abnormalities due to signal phase differences caused by factors such as components, backplanes, cables, and ambient temperature rise.
By connecting the FPGA with N driver ICs in a hardware manner, data signals and clock signals are sent and received. Anomalies are detected by comparing the signal phases. The last driver IC returns the processed signal to the FPGA, thus realizing phase anomaly detection.
It improves resource utilization, saves resources for phase anomaly detection, and can automatically detect phase anomalies in LED displays.
Smart Images
Figure CN117636768B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display control, and in particular to methods, devices and computer programs for detecting phase anomalies in LED displays. Background Technology
[0002] Phase is used to indicate the position of a signal wave at a specific moment, such as a crest, trough, or a point between a crest and a trough. Phase measures the waveform change of a signal wave, usually expressed in degrees (angles). When the waveform of a signal wave changes periodically, one complete cycle of the above waveform represents a phase of 360°.
[0003] However, in practical applications, LED displays often experience signal phase differences due to variations in components, backplanes, cables, and ambient temperature rise. These differences can affect the display, such as causing display abnormalities. Summary of the Invention
[0004] This application provides a method, device, and computer program product for detecting phase anomalies in LED displays, so as to realize the detection of phase anomalies in LED displays.
[0005] This application provides a phase anomaly detection method for an LED display screen. The method is applied to an LED display screen, which includes an FPGA, middleware, and N driver ICs, where N is greater than or equal to 1. The FPGA is connected to the first driver IC among the N driver ICs through the middleware, and the last driver IC among the N driver ICs is connected to the FPGA through the middleware. When N is greater than 1, the N driver ICs are cascaded through a cascaded link. The method includes:
[0006] Upon detecting a phase anomaly, a first data signal and a first clock signal associated with the first data signal are sent via the FPGA. This causes the first data signal and the first clock signal to be transmitted via the middleware to the first driver IC and then, starting from the first driver IC, to be transmitted along the cascaded path to the last driver IC. The pulse width of the first data signal is a set pulse width t. 脉宽 The pulse width of the first data signal and the pulse width of the first clock signal meet the set requirements so that the hold time and setup time of the first data signal are equal; when N is 1, the first driver IC is also the last driver IC;
[0007] The FPGA receives a second data signal returned by the last driver IC and a second clock signal associated with the second data signal; the second data signal refers to the data signal after the first data signal passes through the driver IC.
[0008] The phase of the LED display screen is detected to be abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal.
[0009] This application provides an LED display screen, which includes an FPGA, middleware, and N driver ICs, where N is greater than or equal to 1. The FPGA is connected to the first driver IC among the N driver ICs through the middleware, and the last driver IC among the N driver ICs is connected to the FPGA through the middleware. When N is greater than 1, the N driver ICs are cascaded through a cascade link.
[0010] Upon detecting a phase anomaly, the FPGA sends a first data signal and a first clock signal associated with the first data signal. This causes the first data signal and the first clock signal to be transmitted via the middleware to the first driver IC and then along the cascaded path from the first driver IC to the last driver IC. The pulse width of the first data signal is a set pulse width t. 脉宽 The pulse width of the first data signal and the pulse width of the first clock signal meet the set requirements so that the hold time and setup time of the first data signal are equal; when N is 1, the first driver IC is also the last driver IC;
[0011] The FPGA receives a second data signal returned by the last driver IC and a second clock signal associated with the second data signal; the second data signal refers to the data signal after the first data signal passes through the driver IC.
[0012] The FPGA detects whether the phase of the LED display screen is abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal.
[0013] This application provides an electronic device, which includes a processor and a memory; wherein the memory is used to store machine-executable instructions; and the processor is used to read and execute the machine-executable instructions stored in the memory to implement the FPGA execution method described above.
[0014] This application provides a computer program product, which stores a computer program that, when executed by a processor, implements the above method.
[0015] In summary, this embodiment improves upon the previous mechanism where the last driver IC did not output data by setting up a hardware connection method for the LED display screen. Specifically, this hardware connection method involves the FPGA connecting to the first driver IC among the N driver ICs via the aforementioned middleware, and the last driver IC among the N driver ICs connecting to the FPGA via the aforementioned middleware. This hardware connection method improves upon the previous mechanism where the last driver IC did not output data. In this embodiment, the last driver IC returns the processed data signal to the FPGA, enabling the FPGA to automatically detect phase anomalies in the LED display screen using the data and clock signals sent and received through this hardware connection method.
[0016] Furthermore, in this embodiment, when performing phase anomaly detection on the LED display screen, execution is based on the detection of a phase anomaly detection event. This phase anomaly detection event can be configured according to actual needs. For example, since factors affecting the phase of the LED display screen generally include hardware components and temperature rise, this embodiment can set the phase anomaly detection event to occur in the initial stage or after the temperature rise. This can save resources when performing phase anomaly detection on the LED display screen and improve resource utilization. Attached Figure Description
[0017] Figure 1 This is a flowchart illustrating the method in an embodiment of this application;
[0018] Figure 2 This is a schematic diagram of the LED display screen structure shown in the embodiments of this application;
[0019] Figure 3 This is a schematic diagram of temperature sensor deployment shown in an embodiment of this application;
[0020] Figure 4 A flowchart illustrating the implementation of step 103 provided in this application embodiment;
[0021] Figure 5 Another flowchart provided for an embodiment of this application;
[0022] Figure 6 This is a structural diagram of the device shown in the embodiments of this application;
[0023] Figure 7 This is a structural diagram of an electronic device shown in an embodiment of this application. Detailed Implementation
[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0025] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0026] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0027] The method provided in the embodiments of this application is described below:
[0028] See Figure 1 , Figure 1 This is a flowchart illustrating a method provided in an embodiment of this application. The process is applied to an LED display screen. In this embodiment, the LED display screen may include an FPGA, middleware, and N driver ICs. This embodiment deploys a hardware connection method on the LED display screen. Specifically, the hardware connection method may be as follows: the FPGA is connected to the first driver IC among the N driver ICs through the aforementioned middleware, and the last driver IC among the N driver ICs is connected to the FPGA through the aforementioned middleware. When N is greater than 1, the N driver ICs are cascaded through a cascaded link. When N is 1, the single driver IC is both the first and the last driver IC.
[0029] As one example, the aforementioned middleware may be a backplane or a ribbon cable; this embodiment is not specifically limited to these. Figure 2 The structure of an LED display screen is illustrated using the middle component as a backplate and the ribbon cable as an example.
[0030] Based on such Figure 2 The structure of the LED display screen shown is as follows: Figure 1As shown, the process may include the following steps:
[0031] Step 101: In the event of a phase anomaly detection event, a first data signal and a first clock signal associated with the first data signal are sent through the FPGA, so that the first data signal and the first clock signal are transmitted to the first driver IC via the middleware and then transmitted along the cascaded line from the first driver IC to the last driver IC.
[0032] In this embodiment, the detection of a phase anomaly event can be implemented in various ways, such as a power-on event after a power outage, a soft-reboot power-on event, a temperature change event, a timed trigger, an anomaly trigger, or an external command trigger. This embodiment is not specifically limited to these methods. Optionally, the aforementioned temperature change event can be detected based on the aforementioned middleware, such as a temperature sensor deployed on the backplane. Figure 3 An example is shown illustrating the structure of a temperature sensor deployed on the backplane. For instance, each time the temperature sensor detects a 1°C increase in temperature, it is considered a temperature change event.
[0033] In this embodiment, the terms "first data signal" and "first clock signal" are used for ease of description and are not intended to be limiting. Furthermore, the first clock signal associated with the first data signal refers to the clock signal generated by the FPGA's clock generator at the current phase and the current time of sending or receiving the first data signal. Here, obtaining the first data signal includes, for example, generating or receiving the first data signal.
[0034] Optionally, in this embodiment, the pulse width of the first data signal (denoted as the first pulse width) is a set data signal pulse width t. 脉宽 .
[0035] Optionally, to minimize the number of detections, the first pulse width can be a set minimum data signal pulse width t. 最小数据脉宽 The reason is: as long as the minimum data signal pulse width t is used 最小数据脉宽 If the data signal is detected and the LED display's phase is normal, it means the LED display's phase is normal. However, if the first pulse width is not the set minimum data signal pulse width t... 最小数据脉宽 Even if it is subsequently found that the phase of the LED display is normal when tested based on the first data signal, it only means that the phase of the LED display is normal when applied to other data signals with a pulse width greater than or equal to the first pulse width. It does not mean that it is normal when applied to data signals with a pulse width less than the first pulse width. Further testing with data signals with a pulse width less than the first pulse width is required until it is finally detected that the phase of the LED display is normal regardless of which pulse width data signal is used for testing.
[0036] Furthermore, in this embodiment, the pulse width of the first data signal and the pulse width of the first clock signal meet a set requirement so that the hold time and setup time of the first data signal are equal. Here, the setup time of the first data signal refers to the time during which the first data signal to be stored in the register of the driver IC needs to remain stable before the rising edge of the first clock signal arrives. The hold time of the first data signal refers to the time during which the first data signal to be stored in the register of the driver IC needs to remain stable after the rising edge of the first clock signal arrives.
[0037] Based on the definitions of hold time and setup time above, optionally, the pulse width of the first data signal and the pulse width of the first clock signal meet a set requirement, such as the rising edge of the first data signal being at the center of the pulse width of the first clock signal. When the rising edge of the first data signal is at the center of the pulse width of the first clock signal, it indicates that the hold time and setup time of the first data signal are equal.
[0038] Step 102: FPGA receives the second data signal returned by the last driver IC and the second clock signal associated with the second data signal; the second data signal refers to the data signal after the first data signal passes through the driver IC.
[0039] In this embodiment, after receiving a data signal, each driver IC processes the received data signal according to its own configuration. For example, the driver IC may identify the received data signal, adjust the received data signal, and then output it. The output signal will have some phase delay relative to the original received data signal. This embodiment does not specifically limit the way the driver IC processes the data signal.
[0040] As described above, the first data signal is transmitted to the first driver IC. The first driver IC processes the first data signal and outputs it to the second driver IC, and so on. The last driver IC receives the data signal and processes it. After the last driver IC processes the received data signal, this processed data signal is recorded as the second data signal. The last driver IC returns the second data signal and its associated second clock signal to the FPGA. When N is 1, the first driver IC is also the last driver IC, and either the first driver IC or the last driver IC returns the second data signal and its associated second clock signal to the FPGA.
[0041] As an example, the second clock signal associated with the second data signal may be the clock signal of the clock generator of the last driver IC at the current phase and the current time point when the second data signal is sent or received.
[0042] Step 103: By comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal, detect whether the phase of the LED display screen is abnormal.
[0043] In practical applications, setup time and hold time are generally based on the rising edge. Therefore, in order to ensure accuracy, this embodiment can detect whether the phase of the LED display screen is abnormal based on the rising edges of the first data signal and the second data signal, as well as the rising edges of the first clock signal and the second clock signal. Figure 4 One implementation method is illustrated here, but will not be elaborated upon here.
[0044] This concludes the process. Figure 1 The process is shown below.
[0045] pass Figure 1 As can be seen from the process shown, this embodiment improves the original mechanism where the last driver IC does not output by setting the above hardware connection method. In this embodiment, the last driver IC returns the processed data signal to the FPGA, which enables the FPGA to automatically detect the phase anomaly of the LED display screen by means of the data signal and clock signal sent through the hardware connection method and the data signal and clock signal received through the hardware connection method.
[0046] Furthermore, in this embodiment, when performing phase anomaly detection on the LED display screen, execution is based on the detection of a phase anomaly detection event. This phase anomaly detection event can be configured according to actual needs. For example, since factors affecting the phase of the LED display screen generally include hardware components and temperature rise, this embodiment can set the phase anomaly detection event to occur in the initial stage or after the temperature rise. This can save resources when performing phase anomaly detection on the LED display screen and improve resource utilization.
[0047] Step 103 is described below:
[0048] See Figure 4 , Figure 4 A flowchart illustrating the implementation of step 103 in an embodiment of this application. Figure 4 As shown, the process may include the following steps:
[0049] Step 401: Calculate the time difference between the first rising edge of the first data signal and the second data signal.
[0050] For example, the time difference between the first rising edge of the first data signal and the first rising edge of the second data signal is calculated to obtain the first rising edge time difference.
[0051] Step 402: Calculate the time difference between the second rising edge of the first clock signal and the second clock signal.
[0052] For example, the time difference between the first rising edge of the first clock signal and the first rising edge of the second clock signal is calculated to obtain the second rising edge time difference.
[0053] Step 403: Based on the first rising edge time difference, the second rising edge time difference, and the pulse width of the first data signal, detect whether the phase of the LED display screen is abnormal.
[0054] Optionally, step 403 can be implemented as follows: Detecting whether the difference between the time difference of the first rising edge (denoted as Δt1) and the time difference of the second rising edge (denoted as Δt2) is within a certain range. If yes, determine that the phase of the LED display is normal; if no, determine that the phase of the LED display is abnormal. Optionally, in this embodiment, after determining that the phase of the LED display is abnormal, it can be further determined whether the phase abnormality of the LED display is caused by the data signal setup time not meeting the requirements or by the data signal hold time not meeting the requirements. As an example, when the difference between the first rising edge time difference (denoted as Δt1) and the second rising edge time difference (denoted as Δt2) is greater than... It can be assumed that the phase abnormality of the LED display screen is caused by the data signal establishment time not meeting the requirements. When the difference between the first rising edge time difference (denoted as Δt1) and the second rising edge time difference (denoted as Δt2) is less than... If the phase abnormality of the LED display screen is not met, it can be considered that the data signal holding time does not meet the requirements.
[0055] For example, with the above t 脉宽 For t 最小数据脉宽 For example, when When the LED display phase is normal, it indicates that the LED display phase is normal; when When the delay time of the first data signal is too long, the setup time does not meet the requirements, meaning the phase abnormality of the LED display is caused by the setup time of the data signal not meeting the requirements. When the clock signal delay is too long, it indicates that the hold time is not met. In other words, the phase abnormality of the LED display is caused by the data signal not meeting the hold time requirement.
[0056] This concludes the process. Figure 4 The process is shown below.
[0057] pass Figure 4 The process shown enables the detection of whether the phase of the LED display screen is abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal.
[0058] Optionally, in this embodiment, when the phase abnormality of the LED display screen is determined, the phase of the LED display screen can be further adjusted, as detailed in [reference needed]. Figure 5 The process is shown below.
[0059] See Figure 5 , Figure 5 Another flowchart provided for an embodiment of this application. Figure 5 The process shown is executed when a phase anomaly in the LED display screen is detected. For example... Figure 5 As shown, the process may include the following steps:
[0060] Step 501: Adjust the phase of the FPGA's local clock generator from the current value to a value different from the current value.
[0061] Optionally, in step 501, the phase of the FPGA's local clock generator is adjusted from the current value to a value different from the current value. There are many ways to implement this in practice.
[0062] For example, add a preset value (e.g., 1) to the current value of the phase of the local clock generator on the FPGA.
[0063] For example, the phase of the FPGA's local clock generator can be adjusted from its current value to a value different from the current value using a binary classification method. Specifically, the current phase range (e.g., [1, 100]) of the FPGA's local clock generator's current phase value can be determined first. Then, the current phase range is divided into a first phase range and a second phase range, where the phase value in the second phase range is greater than the phase value in the first phase range. If the phase anomaly of the LED display is determined to be caused by the data signal's setup time not meeting the requirements (see the description of step 403), a target phase value is selected from the second phase range. If the phase anomaly of the LED display is determined to be caused by the data signal's hold time not meeting the requirements (see the description of step 403), a target phase value is selected from the first phase range. Then, the phase of the FPGA's local clock generator is adjusted from its current value to the target phase value. Then, step 502 is executed.
[0064] As one embodiment, dividing the current phase range into a first phase range and a second phase range can be achieved by selecting an intermediate value from the current phase range, forming the first phase range from the minimum value of the current phase range to this intermediate value, and using the remainder as the second phase range. Alternatively, in this embodiment, selecting a target phase value from the first or second phase range can be achieved by selecting an intermediate value from either the first or second phase range as the target phase value.
[0065] It should be noted that if the phase of the FPGA's local clock generator is adjusted a certain number of times, an alarm can be output, allowing for external adjustment based on the actual situation. This embodiment is not specifically limited to this. Additionally, if the difference between the phase values of the FPGA's local clock generator before and after adjustment is less than or equal to a set difference range, an alarm can also be output, allowing for external adjustment based on the actual situation. This embodiment is not specifically limited to this either.
[0066] Step 502: Obtain the third data signal and the third clock signal associated with the third data signal generated by the clock generator in the current phase; use the third data signal as the first data signal and the third clock signal as the first clock signal, and return to the step 101 above where the first data signal and the first clock signal associated with the first data signal are sent through the FPGA.
[0067] Optionally, in this embodiment, the third data signal is the same as the first data signal, for example, its pulse width is a set minimum data signal pulse width t. 最小数据脉宽 It should be noted that even if the third data signal is the same as the first data signal, the third clock signal is different from the first clock signal based on the adjustment in step 501.
[0068] In step 502, after using the third data signal as the first data signal and the third clock signal as the first clock signal, the process loops back to step 101 above to ultimately suppress phase abnormalities of the LED display screen by adjusting the phase of the local clock generator of the FPGA.
[0069] This concludes the process. Figure 5 The process is shown below.
[0070] pass Figure 5 The flowchart shown demonstrates how to adjust the phase of the FPGA's local clock generator when an abnormal phase occurs on the LED display screen, in order to eliminate the abnormal phase of the LED display screen.
[0071] The methods provided in the embodiments of this application have been described above. The apparatus provided in the embodiments of this application is described below:
[0072] See Figure 6 , Figure 6 This is a structural diagram of an LED display screen provided in an embodiment of this application. The LED display screen includes an FPGA, middleware, and N driver ICs, where N is greater than or equal to 1. The FPGA is connected to the first driver IC among the N driver ICs through the middleware, and the last driver IC among the N driver ICs is connected to the FPGA through the middleware. When N is greater than 1, the N driver ICs are cascaded through a cascade link.
[0073] like Figure 6 As shown, the LED display screen may include:
[0074] Upon detecting a phase anomaly, a first data signal and a first clock signal associated with the first data signal are sent via the FPGA. This causes the first data signal and the first clock signal to be transmitted via the middleware to the first driver IC and then, starting from the first driver IC, to be transmitted along the cascaded path to the last driver IC. The pulse width of the first data signal is a set pulse width t. 脉宽 The pulse width of the first data signal and the pulse width of the first clock signal meet the set requirements so that the hold time and setup time of the first data signal are equal; when N is 1, the first driver IC is also the last driver IC;
[0075] The FPGA receives a second data signal returned by the last driver IC and a second clock signal associated with the second data signal; the second data signal refers to the data signal after the first data signal passes through the driver IC.
[0076] The phase of the LED display screen is detected to be abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal.
[0077] Optionally, the phase anomaly detection event includes at least one of the following events:
[0078] Power outage and power-on events, soft reboot power-on events, temperature change events, timed triggers, abnormal triggers, and external command triggers.
[0079] Optionally, the set pulse width is the set minimum data signal pulse width t. 最小数据脉宽 ;
[0080] The pulse width t of the first data signal 脉宽 The requirement that the pulse width of the first clock signal meets the set requirement means that the rising edge of the first data signal is at the center of the pulse width of the first clock signal.
[0081] Optionally, detecting whether the phase of the LED display screen is abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal, includes:
[0082] Calculate the time difference between the first rising edge of the first data signal and the second data signal;
[0083] Calculate the time difference between the second rising edge of the first clock signal and the second clock signal;
[0084] Based on the first rise time difference, the second rise time difference, and the pulse width of the first data signal, the phase of the LED display screen is detected to determine whether an abnormality has occurred.
[0085] Optionally, detecting whether the phase of the LED display screen is abnormal based on the first rise time difference, the second rise time difference, and the pulse width of the first data signal includes:
[0086] Detect whether the difference between the time difference of the first rising edge and the time difference of the second rising edge is within the range of... If yes, determine that the phase of the LED display screen is normal; if no, determine that the phase of the LED display screen is abnormal.
[0087] Optionally, when determining a phase anomaly in the LED display screen, the method further includes:
[0088] Adjust the phase of the FPGA's local clock generator from its current value to a value different from the current value;
[0089] Obtain the third data signal and the third clock signal associated with the third data signal generated by the clock generator in the current phase;
[0090] Using the third data signal as the first data signal and the third clock signal as the first clock signal, return to the step of sending the first data signal and the first clock signal associated with the first data signal through the FPGA.
[0091] Optionally, adjusting the phase of the FPGA's local clock generator from its current value to a value different from the current value includes:
[0092] Add a preset value to the current value of the phase of the FPGA's local clock generator; or,
[0093] If the current phase value of the FPGA's local clock generator is determined to be within the current phase range, then the current phase range is divided into a first phase range and a second phase range, where the phase value in the second phase range is greater than the phase value in the first phase range.
[0094] If the phase abnormality of the LED display screen is caused by the data signal establishment time not meeting the requirements, a target phase value is selected from the second phase range. If the phase abnormality of the LED display screen is caused by the data signal holding time not meeting the requirements, a target phase value is selected from the first phase range.
[0095] Adjust the phase of the FPGA's local clock generator from its current value to the target phase value.
[0096] This concludes the process. Figure 6 Structural description of the device shown.
[0097] Correspondingly, embodiments of this application also provide Figure 6 The hardware structure diagram of the device shown is as follows: Figure 7 As shown, the electronic device can be a device implementing the above-described method. Figure 7 As shown, the hardware architecture includes a processor and memory.
[0098] The memory is used to store machine-executable instructions;
[0099] The processor is configured to read and execute machine-executable instructions stored in the memory to implement the method embodiment shown above.
[0100] As one embodiment, the memory can be any electronic, magnetic, optical, or other physical storage device that can contain or store information such as executable instructions, data, etc. For example, the memory can be volatile memory, non-volatile memory, or similar storage media. Specifically, the memory can be RAM (Random Access Memory), flash memory, storage drives (such as hard disk drives), solid-state drives, any type of storage disk (such as optical discs, DVDs, etc.), or similar storage media, or combinations thereof.
[0101] Based on the same inventive concept, this embodiment also provides a computer-readable storage medium. This computer-readable storage medium is used to store a computer program; when executed by a processor, the computer program implements the method embodiment described above.
[0102] Based on the same inventive concept, this embodiment also provides a computer program product, which stores a computer program that, when executed by a processor, implements the method embodiment described above.
[0103] The foregoing has described specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0104] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention filed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0105] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
[0106] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method for detecting phase anomalies in an LED display screen, characterized in that, This method is applied to an LED display screen, which includes an FPGA, middleware, and N driver ICs, where N is greater than or equal to 1. The FPGA is connected to the first driver IC among the N driver ICs through the middleware, and the last driver IC among the N driver ICs is connected to the FPGA through the middleware. When N is greater than 1, the N driver ICs are cascaded through a cascade link. The method includes: Upon detecting a phase anomaly, a first data signal and a first clock signal associated with the first data signal are sent via the FPGA. This causes the first data signal and the first clock signal to be transmitted via the middleware to the first driver IC and then, starting from the first driver IC, to be transmitted along the cascaded path to the last driver IC. The pulse width of the first data signal is a set pulse width t. 脉宽 The pulse width of the first data signal and the pulse width of the first clock signal meet the set requirements so that the hold time and setup time of the first data signal are equal; when N is 1, the first driver IC is also the last driver IC; The FPGA receives a second data signal returned by the last driver IC and a second clock signal associated with the second data signal; the second data signal refers to the data signal after the first data signal passes through the driver IC. The phase of the LED display screen is detected to be abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal.
2. The method according to claim 1, characterized in that, The phase anomaly detection event includes at least one of the following events: Power outage and power-on events, soft reboot power-on events, temperature change events, timed triggers, abnormal triggers, and external command triggers.
3. The method according to claim 1, characterized in that, The set pulse width is the set minimum data signal pulse width t. 最小数据脉宽 ; The pulse width t of the first data signal 脉宽 The requirement that the pulse width of the first clock signal meets the set requirement means that the rising edge of the first data signal is at the center of the pulse width of the first clock signal.
4. The method according to claim 1, characterized in that, The step of detecting whether the phase of the LED display screen is abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal, includes: Calculate the time difference between the first rising edge of the first data signal and the second data signal; Calculate the time difference between the second rising edge of the first clock signal and the second clock signal; Based on the first rise time difference, the second rise time difference, and the pulse width of the first data signal, the phase of the LED display screen is detected to determine whether an abnormality has occurred.
5. The method according to claim 4, characterized in that, The step of detecting whether the phase of the LED display screen is abnormal based on the first rise time difference, the second rise time difference, and the pulse width of the first data signal includes: Detect whether the difference between the time difference of the first rising edge and the time difference of the second rising edge is within the range of... If yes, determine that the phase of the LED display screen is normal; if no, determine that the phase of the LED display screen is abnormal.
6. The method according to any one of claims 1 to 5, characterized in that, When determining a phase anomaly in the LED display screen, the method further includes: Adjust the phase of the FPGA's local clock generator from its current value to a value different from the current value; Obtain the third data signal and the third clock signal associated with the third data signal generated by the clock generator in the current phase; Using the third data signal as the first data signal and the third clock signal as the first clock signal, return to the step of sending the first data signal and the first clock signal associated with the first data signal through the FPGA.
7. The method according to claim 6, characterized in that, The step of adjusting the phase of the FPGA's local clock generator from its current value to a value different from the current value includes: Add a preset value to the current value of the phase of the FPGA's local clock generator; or, If the current phase value of the FPGA's local clock generator is determined to be within the current phase range, then the current phase range is divided into a first phase range and a second phase range, where the phase value in the second phase range is greater than the phase value in the first phase range. If the phase abnormality of the LED display screen is caused by the data signal establishment time not meeting the requirements, a target phase value is selected from the second phase range; if the phase abnormality of the LED display screen is caused by the data signal holding time not meeting the requirements, a target phase value is selected from the first phase range. Adjust the phase of the FPGA's local clock generator from its current value to the target phase value.
8. An LED display screen, characterized in that, The LED display screen includes an FPGA, middleware, and N driver ICs, where N is greater than or equal to 1. The FPGA is connected to the first driver IC among the N driver ICs through the middleware, and the last driver IC among the N driver ICs is connected to the FPGA through the middleware. When N is greater than 1, the N driver ICs are cascaded through a cascade link. Upon detecting a phase anomaly, the FPGA sends a first data signal and a first clock signal associated with the first data signal. This causes the first data signal and the first clock signal to be transmitted via the middleware to the first driver IC and then along the cascaded path from the first driver IC to the last driver IC. The pulse width of the first data signal is a set pulse width t. 脉宽 The pulse width of the first data signal and the pulse width of the first clock signal meet the set requirements so that the hold time and setup time of the first data signal are equal; when N is 1, the first driver IC is also the last driver IC; The FPGA receives a second data signal returned by the last driver IC and a second clock signal associated with the second data signal; the second data signal refers to the data signal after the first data signal passes through the driver IC. The FPGA detects whether the phase of the LED display screen is abnormal by comparing the first data signal and the second data signal, as well as the first clock signal and the second clock signal.
9. An electronic device, characterized in that, Electronic devices include: processors and memory; The memory is used to store machine-executable instructions; The processor is configured to read and execute machine-executable instructions stored in the memory to implement the method executed by the FPGA as described in any one of claims 1 to 7.
10. A computer program product, characterized in that, The computer program product contains a computer program that, when executed by a processor, implements the method described in any one of claims 1 to 7.