A power device and a manufacturing method thereof

Abstract

This invention provides a power device and its fabrication method. The method includes the following steps: providing a semiconductor layer including a cell region and a termination region; forming a masking layer on the semiconductor layer and patterning it to form multiple ion implantation windows, wherein the multiple ion implantation windows are located in the termination region and include a first implantation window and multiple discretely arranged second implantation windows, the first implantation window being located between the cell region and the second implantation windows, and the masking layer being divided into multiple discretely arranged masking islands; performing ion implantation on the semiconductor layer using the patterned masking layer as a mask to form multiple ion implantation regions in the semiconductor layer; and performing annealing to fuse the multiple ion implantation regions to obtain a laterally variable doped termination. This invention performs ring implantation directly around the termination through precise block implantation windows, and performs annealing after implantation, which can form a more curved arc-shaped VLD morphology, improve the concave contact at the junction of the ion implantation regions, and improve the breakdown voltage efficiency of the VLD termination.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit technology and relates to a power device and its fabrication method. Background Technology

[0002] In the field of power electronics, power semiconductor devices are key components, and their characteristics play a crucial role in achieving and improving system performance. One of the most important characteristics of power semiconductor devices is their ability to block high voltages, which mainly relies on a reasonable termination structure. Currently, junction termination protection technologies mainly include field plates (FP), field limiting rings (FLR), junction termination extensions (JTE), and variation of lateral doping (VLD). Among these, the combination of FP and FLR is a commonly used and effective method to improve surface breakdown characteristics, but this combination generally requires a larger size, resulting in a larger chip size. VLD termination, on the other hand, can significantly reduce the termination size and lower the overall device cost, and is widely used in power devices such as MOS and IGBT, exhibiting good reliability.

[0003] Conventional VLD terminations are typically formed by adjusting the size and spacing of the injection windows in the termination region, followed by injection and annealing. Because the spacing between injection windows increases as the injection windows move outwards and the injection windows themselves become smaller, the VLD morphology formed by injection and annealing does not connect well at the termination edge, which leads to reduced termination efficiency.

[0004] Therefore, how to provide a more optimized VLD layout design method to optimize the injection window and improve the voltage withstand efficiency of the VLD terminal has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power device and its manufacturing method, which solves the problem that the VLD morphology is not well connected at the terminal edge in the prior art, resulting in a decrease in terminal withstand voltage efficiency.

[0007] To achieve the above and other related objectives, the present invention provides a method for manufacturing a power device, comprising the following steps:

[0008] A semiconductor layer is provided, the semiconductor layer including a cell region and a terminal region located around the cell region;

[0009] A masking layer is formed on the semiconductor layer, and the masking layer is patterned to form a plurality of ion implantation windows that penetrate the masking layer. The plurality of ion implantation windows are located in the terminal region and include a first implantation window and a plurality of discretely arranged second implantation windows. The first implantation window is located between the cell region and the second implantation window and the masking layer is divided into a plurality of discretely arranged masking islands.

[0010] Ion implantation is performed on the semiconductor layer using the patterned masking layer as a mask to form multiple ion implantation regions in the semiconductor layer;

[0011] Annealing is performed to fuse the multiple ion implantation regions to obtain a lateral variable doping terminal.

[0012] Optionally, the plurality of shielding islands are arranged in at least two columns in the direction from the cell region to the terminal region.

[0013] Optionally, the shielding islands in adjacent columns are staggered.

[0014] Optionally, in two adjacent columns of the shielding islands, the island area of ​​the shielding island closer to the cell region is smaller than the island area of ​​the shielding island farther from the cell region.

[0015] Optionally, the plurality of second injection windows are arranged in at least two columns in the direction from the cell region to the terminal region.

[0016] Optionally, the second injection windows in adjacent columns are staggered.

[0017] Optionally, in two adjacent columns of the second injection windows, the opening area of ​​the second injection window closer to the cell region is larger than the opening area of ​​the second injection window farther away from the cell region.

[0018] Optionally, the shielding island is square or circular, and the second injection window is square or circular.

[0019] Optionally, the power device includes an insulated gate bipolar transistor.

[0020] The present invention also provides a power device, which is manufactured using the power device manufacturing method described in any one of the above claims.

[0021] As described above, in the fabrication method of the power device of the present invention, the first implantation windows near the cell region are connected, and the shielding layer is divided into multiple discretely arranged shielding islands. Multiple second implantation windows far from the cell region are discretely arranged, and the shielding layers between the multiple second implantation windows are connected. The present invention performs ring implantation directly around the terminal periphery through precise block-shaped implantation windows. After implantation, annealing is performed, which can form a more curved arc-shaped VLD morphology, improve the concave contact at the junction of the ion implantation region, and enhance the withstand voltage efficiency of the VLD terminal. The fabrication method of the power device of the present invention is fully compatible with the current VLD terminal power device (e.g., IGBT) fabrication process, requiring no additional steps or layout. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a partial planar layout of an injection window defined by a graphical masking layer in a VLD terminal implementation.

[0023] Figure 2 The diagram shows a partial cross-sectional structure of multiple ion implantation regions obtained by ion implantation into a semiconductor layer using a graphical masking layer as a mask in a VLD terminal implementation.

[0024] Figure 3 The diagram illustrates a lateral variable doping terminal obtained by annealing multiple ion implantation regions to achieve a VLD terminal implementation.

[0025] Figure 4 This is a flowchart illustrating the fabrication process of an IGBT device.

[0026] Figure 5 The diagram shown is a process flow diagram of the method for manufacturing the power device of the present invention.

[0027] Figure 6 The diagram shown is a partial planar layout of the shielding layer as illustrated in Embodiment 1, representing the method for fabricating the power device of the present invention.

[0028] Figure 7 The diagram shown illustrates the method for fabricating the power device of the present invention in Embodiment 1, in which the semiconductor layer is ion implanted and annealed using the patterned masking layer as a mask to obtain a laterally doped terminal.

[0029] Figure 8 The diagram shown is a partial planar layout of the shielding layer after graphical representation of the method for fabricating the power device of the present invention in Embodiment 2.

[0030] Component designation explanation

[0031] 101 Shielding Layer

[0032] 102 ring injection window

[0033] 103 Ion Implantation Region

[0034] 104 Lateral Variable Doping Termination

[0035] Steps S1 to S4

[0036] A Inner Area

[0037] B. Outer Area

[0038] 201 First Injection Window

[0039] 202 Second Injection Window

[0040] 203 Shelter Island

[0041] 204 Shielding layer

[0042] 205 Lateral Variable Doping Termination Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] like Figures 1 to 3 The image shows an implementation of a lateral variable doping terminator, wherein... Figure 1 This is shown as a partial planar layout schematic of the ring injection window 102 defined by a graphical masking layer 101. Figure 2 The diagram shows a partial cross-sectional structure of a semiconductor layer being ion-implanted using a patterned masking layer 101 as a mask to obtain multiple ion-implanted regions 103. Figure 3 The diagram shows a lateral variable doping terminal 104 obtained by fusing multiple ion implantation regions 103 through annealing. In this implementation of the lateral variable doping terminal, the size and spacing of the implantation window are adjusted, generally from the inside out, the implantation window becomes narrower and the shielding layer becomes wider.

[0046] The aforementioned lateral doping termination is highly compatible with the existing mainstream insulated-gate bipolar transistor (IGBT) and MOS fabrication processes. Taking IGBT as an example, the fabrication process flow is as follows: Figure 4 As shown, the process includes the following steps performed sequentially: providing single-crystal material, performing VLD implantation and push-in, performing memory layer implantation and push-in, performing trench etching, performing polysilicon deposition and etching, performing P-type base region implantation and push-in, performing N-doped implantation and push-in, performing dielectric layer deposition, performing photolithography and hole etching, performing metal deposition and etching, performing field cutoff layer implantation and laser annealing, and performing backside implantation and thinning.

[0047] In the aforementioned method of ion implantation and annealing to form a laterally doped terminal by adjusting the size and spacing of the implantation window in the terminal region, the implantation region is strip-shaped, and it gradually narrows from the inside out, with the spacing increasing. After annealing, there is a concave boundary region at the junction of adjacent strip-shaped regions, resulting in poor VLD morphology connection in the peripheral region of the terminal, thereby exacerbating the terminal curvature effect and reducing the breakdown voltage efficiency of the VLD terminal. This invention optimizes the implantation window through an optimized VLD layout design, improving the breakdown voltage efficiency of the VLD terminal. The specific technical solution of this invention is illustrated below through specific embodiments.

[0048] Example 1

[0049] This embodiment provides a method for manufacturing a power device. Please refer to [link / reference]. Figure 5 The diagram shows the process flow of this method, which includes the following steps:

[0050] S1: A semiconductor layer is provided, the semiconductor layer including a cell region and a terminal region located around the cell region;

[0051] S2: A masking layer is formed on the semiconductor layer, and the masking layer is patterned to form a plurality of ion implantation windows that penetrate the masking layer. The plurality of ion implantation windows are located in the terminal region and include a first implantation window and a plurality of discretely arranged second implantation windows. The first implantation window is located between the cell region and the second implantation window and the masking layer is divided into a plurality of discretely arranged masking islands.

[0052] S3: Using the patterned masking layer as a mask, perform ion implantation on the semiconductor layer to form multiple ion implantation regions in the semiconductor layer;

[0053] S4: Perform annealing to fuse the multiple ion implantation regions to obtain a lateral variable doping terminal.

[0054] Specifically, in step S1, the semiconductor layer can be made of a single-crystal material, such as single-crystal silicon. Depending on the type of power device to be manufactured, other suitable semiconductor materials can also be used for the semiconductor layer; this should not unduly limit the scope of protection of the present invention.

[0055] Specifically, in step S2, the masking layer is used to block ion implantation into the masked area of ​​the semiconductor layer. The material of the masking layer includes, but is not limited to, silicon nitride, and it can be deposited on the surface of the semiconductor layer using chemical vapor deposition, physical vapor deposition, or other suitable methods. Methods for patterning the masking layer include photolithography processes such as photolithography and etching.

[0056] For example, please refer to Figure 6 The diagram shows a partial planar layout after the masking layer is graphically rendered. In this embodiment, the terminal area is divided into an inner perimeter region A near the cell region and an outer perimeter region B away from the cell region. The first injection window 201 is located in the inner perimeter region A, and a plurality of second injection windows 202 are located in the outer perimeter region B. The first injection windows 201 are connected, and the masking layer located in the inner perimeter region A is divided into a plurality of separately arranged masking islands 203. The masking layers 204 between the plurality of second injection windows 202 are connected.

[0057] As an example, the shielding island 203 is square, and the second injection window 202 is also square.

[0058] As an example, in the direction from the cell region to the terminal region, i.e., from the inside out, the plurality of shielding islands 203 are arranged in at least two columns, and the plurality of second injection windows 203 are arranged in at least two columns. Figure 6 The arrangement presents a situation where multiple shielding islands 203 are arranged in three columns and multiple second injection windows 203 are arranged in two columns, which is beneficial for better lateral adjustment of the doped region.

[0059] Specifically, each column of masking islands is composed of multiple masking islands, and each column of second injection windows is composed of multiple second injection windows.

[0060] As an example, the two adjacent columns of the shielding islands 203 are staggered, and the two adjacent columns of the second injection windows 202 are staggered, which helps to improve the uniformity of doping.

[0061] As an example, in two adjacent columns of the shielding islands 203, the island area of ​​the shielding island 203 closer to the cell region is smaller than the island area of ​​the shielding island 203 farther from the cell region; in two adjacent columns of the second injection windows 202, the opening area of ​​the second injection window 202 closer to the cell region is larger than the opening area of ​​the second injection window 202 farther from the cell region. That is, from the inside out, the shielding area gradually increases, which is beneficial for the depth of the doped region to gradually become shallower from the inside out.

[0062] For example, please refer to Figure 7 The diagram shows a schematic of ion implantation and annealing of the semiconductor layer using the graphical masking layer as a mask to obtain a lateral variable doping terminal 205. The lateral variable doping terminal 205 has a more curved arc shape, which improves the concave contact at the junction of the ion implantation region and is beneficial to improving the breakdown voltage efficiency of the lateral variable doping terminal.

[0063] Specifically, the fabrication method of the power device in this embodiment is fully compatible with the current fabrication process of VLD terminal power devices, and no additional steps or layout are required.

[0064] As an example, after forming the lateral doped terminal 205, further processes are performed, including memory layer implantation and push-in, trench etching, polysilicon deposition and etching, P-type base region implantation and push-in, N-doped implantation and push-in, dielectric layer deposition, photolithography and hole etching, metal deposition and etching, field stop layer implantation and laser annealing, backside implantation and thinning, and finally an IGBT device is obtained.

[0065] It should be noted that the fabrication method of the power device in this embodiment is applicable not only to IGBTs, but also to other power semiconductor devices.

[0066] The power device fabrication method of this embodiment optimizes the layout of the VLD injection window. The injection windows in the inner area of ​​the terminal region are connected without separation, and the shape is optimized by multiple separately set shielding islands. The outer area of ​​the terminal region uses multiple separately set injection windows, which can make the VLD terminal have a better connection shape.

[0067] It should be noted that the specific layout of the multiple separately arranged shielding islands divided by the first injection window, the specific layout of the multiple separately arranged second injection windows, the size of the shielding islands, and the size of the second injection windows can all be adjusted according to the actual pressure resistance requirements. This can be evaluated through simulation and is not limited to specific adjustments. Figure 6 The situation presented.

[0068] Example 2

[0069] This embodiment uses the same technical solution as Embodiment 1. The difference is that in Embodiment 1, the shielding island 203 and the second injection window 202 are both square, while in this embodiment, the shielding island 203 and the second injection window 202 are both circular.

[0070] Please see Figure 8 This is a partial planar layout diagram presented after the masking layer is graphically rendered in this embodiment.

[0071] Example 3

[0072] This embodiment provides a power device, which may be an insulated gate bipolar transistor or other power semiconductor device, and the power device includes lateral doped terminals. The power device of this embodiment can be fabricated using the power device fabrication method described in Embodiment 1 or Embodiment 2.

[0073] In summary, in the power device fabrication method of the present invention, the first implantation windows near the cell region are connected, and the shielding layer is divided into multiple discretely arranged shielding islands. Multiple second implantation windows far from the cell region are discretely arranged, and the shielding layers between the multiple second implantation windows are connected. The present invention performs ring implantation directly around the terminal periphery through precise block-shaped implantation windows, followed by annealing after implantation. This results in a more curved, arc-shaped VLD morphology, improving the concave contact at the ion implantation region boundary and enhancing the voltage withstand efficiency of the VLD terminal. The power device fabrication method of the present invention is fully compatible with current VLD terminal power device (e.g., IGBT) fabrication processes, requiring no additional steps or layout. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a power device, characterized in that, Includes the following steps: A semiconductor layer is provided, the semiconductor layer including a cell region and a terminal region located around the cell region; A masking layer is formed on the semiconductor layer, and the masking layer is patterned to form a plurality of ion implantation windows penetrating the masking layer. The plurality of ion implantation windows are located in the terminal region and include a first implantation window and a plurality of separately arranged second implantation windows. The first implantation window is located between the cell region and the second implantation windows and divides the masking layer into a plurality of separately arranged masking islands. The first implantation windows are connected. In the direction from the cell region to the terminal region, the plurality of masking islands are arranged in at least two columns. The masking islands in two adjacent columns are staggered. In the two adjacent columns of masking islands, the island area of ​​the masking island closer to the cell region is smaller than the island area of ​​the masking island farther away from the cell region. Ion implantation is performed on the semiconductor layer using the patterned masking layer as a mask to form multiple ion implantation regions in the semiconductor layer; Annealing is performed to fuse the multiple ion implantation regions to obtain a lateral variable doping terminal.

2. The method for manufacturing a power device according to claim 1, characterized in that: In the direction from the cell region to the terminal region, the plurality of second injection windows are arranged in at least two columns.

3. The method for manufacturing a power device according to claim 2, characterized in that: The second injection windows in two adjacent columns are staggered.

4. The method for manufacturing a power device according to claim 2, characterized in that: In two adjacent columns of the second injection windows, the opening area of ​​the second injection window closer to the cell region is larger than the opening area of ​​the second injection window farther away from the cell region.

5. The method for manufacturing a power device according to claim 1, characterized in that: The shielding island is square or circular, and the second injection window is square or circular.

6. The method for manufacturing a power device according to claim 1, characterized in that: The power device includes an insulated gate bipolar transistor.

7. A power device, characterized in that: The power device is manufactured using the power device manufacturing method as described in any one of claims 1-6.

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