Ramp compensation circuit and switching circuit for fixed frequency peak current mode control

Abstract

The fixed-frequency peak current mode control slope compensation circuit and the switching circuit provided by the embodiments of the present disclosure, the current detection module collects the switching node voltage, and outputs a first voltage according to the switching node voltage and the input node voltage during the conduction of the upper power tube, and outputs a second voltage according to the switching node voltage and the ground node voltage during the conduction of the lower power tube; the slope detection module determines a third voltage corresponding to the slope of the change amount of the conduction current of the lower power tube according to the first voltage and the second voltage; the sample and hold module samples the third voltage during the conduction of the lower power tube, holds and outputs a fourth voltage of the third voltage at the time before the conduction of the upper power tube during the conduction of the upper power tube; the slope compensation module generates a slope compensation voltage corresponding to the fourth voltage according to the fourth voltage, and generates a ripple voltage according to the slope compensation voltage and the first voltage; and the duty cycle modulation module generates a duty cycle signal according to the ripple voltage and an error voltage.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology and related technical fields, and more specifically, to a slope compensation circuit and a switching circuit suitable for a fixed frequency peak current mode control. Background Technology

[0002] Power supply design control modes are mainly divided into two categories: current control mode and voltage control mode. Current control mode is widely used because it has advantages such as fast dynamic response, large bandwidth gain, simplified feedback loop design, and easy current sharing in parallel output.

[0003] Peak current control mode is the most common form of current control mode. However, when the power supply PWM duty cycle is greater than 50%, the fixed-frequency peak current control mode will become unstable. Therefore, a slope compensation signal is needed to suppress subharmonic oscillations. If the strength of the slope compensation signal is too small, it cannot meet the system stability requirements under extremely large duty cycles; if the strength of the slope compensation signal is too large, it will affect the transient response of the switching power supply, thereby weakening the load capacity of the switching power supply; if the amplitude of the slope compensation signal is too large, it will cause the peak current control mode to transition to voltage control mode, thus losing the advantages of the current control mode characteristics. The slope of the slope compensation signal is a key factor affecting the slope compensation signal.

[0004] Therefore, based on the problems existing in the prior art, a slope compensation circuit with fixed frequency peak current mode control is proposed. The slope of the added slope compensation can automatically adapt to the changes in input, output and external inductance, and ensure good dynamic response while suppressing subharmonic oscillations. Summary of the Invention

[0005] The embodiments described herein provide a slope compensation circuit and a switching circuit for fixed-frequency peak current mode control, which solves the problems existing in the prior art.

[0006] According to a first aspect of this disclosure, a slope compensation circuit with fixed frequency peak current mode control is provided, comprising: a current detection module, a slope detection module, a sample and hold module, a slope compensation module, and a duty cycle modulation module.

[0007] The current detection module is configured to acquire the switching node voltage, and output a first voltage based on the switching node voltage and the input node voltage during the conduction of the upper power transistor, and output a second voltage based on the switching node voltage and the ground node voltage during the conduction of the lower power transistor.

[0008] The slope detection module is configured to determine a third voltage corresponding to the slope of the change in the conduction current of the lower power transistor when the lower power transistor is turned on, based on the first voltage and the second voltage, and to output zero voltage when the upper power transistor is turned on.

[0009] The sample-and-hold module is configured to sample the third voltage during the conduction of the lower power transistor, and to hold the third voltage at the moment before the upper power transistor is turned on and output the fourth voltage when the upper power transistor is turned on.

[0010] The slope compensation module is configured to generate a slope compensation voltage corresponding to the fourth voltage based on the fourth voltage, and to generate a ripple voltage based on the slope compensation voltage and the first voltage.

[0011] The duty cycle modulation module is configured to generate a duty cycle signal based on the ripple voltage and the error voltage.

[0012] In some embodiments of this disclosure, the slope detection module includes a first switching unit, a second switching unit, and a differentiating unit;

[0013] The first switching unit includes a first switch and a second switch, the second switching unit includes a third switch and a fourth switch, and the differentiating unit includes a first capacitor, a first amplifier, a first resistor and a second capacitor;

[0014] The first terminal of the first switch is electrically connected to the first output terminal of the current detection module. The second terminal of the first switch is electrically connected to the first terminal of the first capacitor and the second terminal of the third switch. The control terminals of the first switch and the second switch are electrically connected to the control terminals of the upper power transistor. The first terminal of the second switch is electrically connected to the second terminal of the first capacitor and the first terminal of the fourth switch. The second terminal of the second switch is electrically connected to the ground node. The first terminal of the third switch is electrically connected to the second output terminal of the current detection module. The control terminals of the third switch and the fourth switch are electrically connected to the control terminals of the lower power transistor. The second terminal of the fourth switch is electrically connected to the first terminal of the first amplifier, the first terminal of the first resistor, and the first terminal of the second capacitor. The second terminal of the first amplifier is electrically connected to the ground node. The third terminal of the first amplifier is electrically connected to the second terminal of the first resistor, the second terminal of the second capacitor, and the sample-and-hold module.

[0015] In some embodiments of this disclosure, the sample-and-hold module includes a fifth switch, a third capacitor, a fourth capacitor, a second resistor, and a second amplifier;

[0016] The first terminal of the fifth switch is electrically connected to the slope detection module. The second terminal of the fifth switch is electrically connected to the first terminal of the third capacitor and the first terminal of the second resistor, respectively. The control terminal of the fifth switch is electrically connected to the control terminal of the lower power transistor. The second terminal of the third capacitor, the second terminal of the fourth capacitor, and the first terminal of the second amplifier are electrically connected to the ground node, respectively. The second terminal of the second resistor is electrically connected to the first terminal of the fourth capacitor and the second terminal of the second amplifier, respectively. The third terminal of the second amplifier is electrically connected to the slope compensation module.

[0017] In some embodiments of this disclosure, the slope compensation module includes a slope compensation unit and a summing unit;

[0018] The slope compensation unit is configured to output a slope compensation voltage corresponding to the fourth voltage when the upper tube is turned on.

[0019] The summing unit is configured to sum the slope compensation voltage with the first voltage to generate a ripple voltage.

[0020] In some embodiments of this disclosure, the slope compensation unit includes a transconductance amplifier, an inverter, a sixth switch, and a fifth capacitor;

[0021] The positive input terminal of the transconductance amplifier is electrically connected to the sample-and-hold module, the inverting input terminal of the transconductance amplifier is electrically connected to the ground node, the current input terminal of the transconductance amplifier is electrically connected to the power supply voltage node, the output terminal of the transconductance amplifier is electrically connected to the first input terminal of the summing unit, the first terminal of the sixth switch, and the first terminal of the fifth capacitor, respectively, the second terminal of the sixth switch and the second terminal of the fifth capacitor are respectively electrically connected to the ground node, the control terminal of the sixth switch is electrically connected to the output terminal of the inverter, and the input terminal of the inverter and the enable terminal of the transconductance amplifier are respectively electrically connected to the control terminal of the lower power transistor.

[0022] In some embodiments of this disclosure, the current detection module includes a first current detection unit and a second current detection unit;

[0023] The first current detection unit includes a seventh switch, a third resistor, a fourth resistor, a fifth resistor, a sixth capacitor, a third amplifier, and a first power supply. The control terminal of the seventh switch is electrically connected to the control terminal of the upper power transistor. The first terminal of the seventh switch is electrically connected to the input node. The second terminal of the seventh switch is electrically connected to the first terminals of the third resistor and the fourth resistor, respectively. The second terminals of the third resistor and the fifth resistor are electrically connected to the switch node, respectively. The second terminal of the fourth resistor is electrically connected to the first terminal of the sixth capacitor and the first terminal of the third amplifier, respectively. The second terminals of the fifth resistor and the sixth capacitor are electrically connected to the second terminal of the third amplifier, respectively. The third terminal of the third amplifier is electrically connected to the slope detection module. The fourth terminal of the third amplifier is electrically connected to the first terminal of the first power supply. The second terminal of the first power supply is electrically connected to the ground node.

[0024] The second current detection unit includes an eighth switch, a sixth resistor, a seventh resistor, an eighth resistor, a seventh capacitor, a fourth amplifier, and a second power supply. The control terminal of the eighth switch is electrically connected to the control terminal of the lower power transistor. The first terminal of the eighth switch is electrically connected to a ground node. The second terminal of the eighth switch is electrically connected to the first terminals of the sixth and seventh resistors, respectively. The second terminals of the sixth and eighth resistors are electrically connected to the switch node, respectively. The second terminal of the seventh resistor is electrically connected to the first terminal of the seventh capacitor and the first terminal of the fourth amplifier, respectively. The second terminals of the eighth resistor and the seventh capacitor are electrically connected to the second terminal of the fourth amplifier, respectively. The third terminal of the fourth amplifier is electrically connected to the slope detection module. The fourth terminal of the fourth amplifier is electrically connected to the first terminal of the second power supply. The second terminal of the second power supply is electrically connected to a ground node.

[0025] In some embodiments of this disclosure, the slope detection module further includes a first delay unit and a second delay unit;

[0026] The first delay unit includes a first delay unit and a first AND gate. The first terminal of the first delay unit is electrically connected to the control terminal of the upper power transistor and the first terminal of the first AND gate, respectively. The output terminal of the first delay unit is electrically connected to the second terminal of the first AND gate, and the output terminal of the first AND gate is electrically connected to the control terminal of the first switch and the control terminal of the second switch, respectively.

[0027] The second delay unit includes a second delay unit and a second AND gate. The first terminal of the second delay unit is electrically connected to the control terminal of the lower power transistor and the first terminal of the second AND gate, respectively. The output terminal of the second delay unit is electrically connected to the second terminal of the second AND gate, and the output terminal of the second AND gate is electrically connected to the control terminal of the third switch and the control terminal of the fourth switch, respectively.

[0028] In some embodiments of this disclosure, the sample-and-hold module further includes a third delay unit and a third AND gate. The first terminal of the third delay unit is electrically connected to the control terminal of the lower power transistor and the first terminal of the third AND gate, respectively. The output terminal of the third delay unit is electrically connected to the second terminal of the third AND gate, and the output terminal of the third AND gate is electrically connected to the control terminal of the fifth switch.

[0029] In some embodiments of this disclosure, a control module and a drive module are also included;

[0030] The control module is configured to generate a pulse width modulation signal based on the clock signal and the duty cycle signal.

[0031] The driving module is configured to generate a switching signal based on the pulse width modulation signal to control the conduction state of the upper power transistor and the lower power transistor.

[0032] According to a second aspect of this disclosure, a switching circuit is provided, including the slope compensation circuit described in any of the first aspects.

[0033] The fixed-frequency peak current mode control slope compensation circuit and switching circuit provided in this disclosure embodiment, by setting a slope detection module in the slope compensation circuit, based on the first and second voltages output by the current detection module, outputs a third voltage corresponding to the slope of the change in the conduction current of the lower power transistor during the conduction period of the lower power transistor, and outputs zero voltage during the conduction period of the upper power transistor. A sample-and-hold module samples the third voltage during the conduction period of the lower power transistor, holds the third voltage during the conduction period of the upper power transistor, and outputs a fourth voltage. The slope compensation module applies the slope compensation voltage corresponding to the fourth voltage to the upper power transistor during the conduction period of the upper power transistor. The first voltage output by the current detection module when the transistor is turned on is compensated and then input to the duty cycle modulation module. Based on the duty cycle modulation module, the on-time of the upper power transistor is modulated and demodulated. Compared with the fixed slope compensation, the problem of excessive or insufficient compensation is avoided, and the subharmonic oscillation caused by disturbance is reduced. In addition, since the slope detection module automatically tracks the slope of the change in the conduction current of the lower power transistor when it is turned on, the subharmonic oscillation will not occur due to insufficient compensation when the circuit output voltage is high. When the circuit output voltage is low, the slope compensation circuit provided in this application has better bandwidth and phase margin compared with the fixed slope compensation circuit. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0035] Figure 1 This is a schematic diagram of a slope compensation circuit with fixed frequency peak current mode control provided in an embodiment of this disclosure;

[0036] Figure 2 This is a schematic diagram of the circuit structure of a slope detection module provided in an embodiment of this disclosure;

[0037] Figure 3 This is a schematic diagram of the circuit structure of a sample-and-hold module provided in an embodiment of this disclosure;

[0038] Figure 4 This is a schematic diagram of the circuit structure of a slope compensation module provided in an embodiment of this disclosure;

[0039] Figure 5 This is a schematic diagram of the circuit structure of a current detection module provided in an embodiment of this disclosure;

[0040] Figure 6 This is a schematic diagram of the circuit structure of another slope detection module provided in an embodiment of this disclosure;

[0041] Figure 7 This is a schematic diagram of the circuit structure of another sample-and-hold module provided in an embodiment of this disclosure;

[0042] Figure 8 This is a schematic diagram of another fixed-frequency peak current mode controlled slope compensation circuit provided in an embodiment of this disclosure;

[0043] Figure 9 This is a timing diagram of a slope compensation circuit with fixed frequency peak current mode control provided in an embodiment of this disclosure. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0046] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled intermediate terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0047] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0048] Based on the problems existing in the prior art, this disclosure provides a slope compensation circuit. Figure 1 This is a schematic diagram of a slope compensation circuit provided in an embodiment of this disclosure, as shown below. Figure 1As shown, the slope compensation circuit includes: a current detection module 10, a slope detection module 20, a sample-and-hold module 30, a slope compensation module 40, and a duty cycle modulation module 50. The current detection module 10 is configured to acquire the switching node voltage and output a first voltage based on the switching node voltage and the input node voltage during the conduction of the upper power transistor, and output a second voltage based on the switching node voltage and the ground node voltage during the conduction of the lower power transistor. The slope detection module 20 is configured to determine a third voltage corresponding to the slope of the change in the conduction current of the lower power transistor based on the second voltage. The sample-and-hold module 30 samples the third voltage during the conduction of the lower transistor, holds the third voltage at the moment before conduction during the conduction of the upper transistor, and outputs a fourth voltage. The slope compensation module 40 is configured to generate a slope compensation voltage corresponding to the fourth voltage, and generate a ripple voltage based on the slope compensation voltage and the first voltage. The duty cycle modulation module 50 is configured to generate a duty cycle signal based on the ripple voltage and the error voltage.

[0049] In existing fixed-frequency buck peak current control DC / DC technology, when the duty cycle is greater than 50%, if the inductor current signal generates a disturbance in the current cycle, this disturbance current will be amplified in the next cycle and generate a secondary slope oscillation. Therefore, slope compensation needs to be added to the inductor signal to suppress the oscillation. The amount of slope compensation is related to the slope of the inductor current drop. Based on the problems existing in the prior art, this application proposes a slope compensation circuit with fixed frequency peak current mode control. By setting a slope detection module 20 in the slope compensation circuit, the slope detection module 20 determines a third voltage corresponding to the slope of the change in the conduction current of the lower power transistor based on the first voltage and the second voltage output by the current detection module 10. The third voltage is sampled or held by the sample-and-hold module 30 and then outputs a fourth voltage. During the conduction period of the upper power transistor 01, the slope compensation voltage corresponding to the fourth voltage is combined with the first voltage to generate a ripple voltage, which is then output to the duty cycle modulation module 50. Based on the duty cycle modulation module 50, the conduction time of the upper power transistor is modulated and demodulated. Compared with the fixed slope slope compensation, the problem of excessive or insufficient compensation is avoided, and the subharmonic oscillation caused by disturbance is reduced. In addition, since the slope detection module automatically tracks the slope of the change in the conduction current of the lower power transistor when it is turned on, the slope compensation circuit provided by this application has better bandwidth and phase margin when the circuit outputs a low voltage compared with the fixed slope compensation circuit.

[0050] Specifically, when the drive signal H_DRV of the upper power transistor is high, the upper power transistor 01 is turned on. The current detection module 10 acquires the switching node voltage VSW and outputs a first voltage V_Rising based on the switching node voltage VSW and the input node voltage VIN. The first voltage V_Rising represents the product of the inductor current (i.e., the upper power transistor's on-state current) and the upper power transistor's on-state resistance during the upper power transistor's on-state period, multiplied by the amplification factor G1. V_Rising = I_Rising × R H_ON ×G1, I_Rising represents the inductor current during the power-on period, R H_ON G1 represents the on-resistance of the upper power transistor, and G2 represents the gain of the amplifier in the first current detection unit of the current detection module 10. When the drive signal L_DRV of the lower power transistor is high, the lower power transistor 02 is turned on. The current detection module 10 acquires the switching node voltage VSW and outputs a second voltage V_Falling based on the switching node voltage VSW and the ground node voltage VGND. The second voltage V_Falling represents the product of the inductor current (i.e., the lower power transistor's on-current) and the lower power transistor's on-resistance during the lower power transistor's conduction period, multiplied by the amplification factor G2. V_Falling = I_Falling × R L_ON ×G2, I_Falling represents the inductor current during the conduction period of the lower power transistor, R L_ON G1 represents the on-resistance of the lower power transistor, and G2 represents the gain of the amplifier in the second current detection unit included in the current detection module 10. That is, when the upper power transistor 01 is turned on, the current detection module 10 converts the on-current (i.e., inductor current) flowing through the upper power transistor 01 into a first voltage V_Rising, which is output to the slope compensation module 40 and the slope detection module 20. When the lower power transistor 02 is turned on, the current (i.e., inductor current) flowing through the lower power transistor 02 into a second voltage V_Falling, which is output to the slope detection module 20.

[0051] The slope detection module 20 determines the third voltage corresponding to the slope of the change in the conduction current of the lower power transistor based on the first voltage V_Rising and the second voltage V_Falling output by the current detection module 10. That is, during the conduction period of the lower power transistor O2, if the change in the inductor current is ΔI, then the slope of the change in the inductor current satisfies: The slope of the second voltage V_Falling satisfies SR V_Falling =SR I_Falling ×R L_ON×G2, after receiving the first voltage V_Rising and the second voltage V_Falling output by the current detection module 10, the slope detection module 20 outputs a third voltage VSRt corresponding to the slope of the change in the power transistor's on-state current. The third voltage VSRt satisfies V_SRt=C1×R1×SR V_Falling During the period when the lower power transistor 02 is turned off, the third voltage VSRt output by the slope detection module 20 satisfies V_SRt=0.

[0052] The sample-and-hold module 30 samples the third voltage V_SRt during the conduction period of the lower power transistor 02, stops sampling during the conduction period of the upper power transistor 01, and holds the V_SRt at the moment before the upper power transistor 01 is turned on. That is, the fourth voltage V_SRo output by the sample-and-hold module 30 satisfies: V_SRo=C1×R1×SR V_Falling At this time, the slope compensation module 40 generates a slope compensation voltage V_Slope corresponding to the fourth voltage V_SRo based on the fourth voltage V_SRo, and adds the slope compensation voltage V_Slope to the first voltage V_Rising to generate a ripple voltage, and outputs the generated ripple voltage to the duty cycle modulation module 50.

[0053] In a specific implementation method Figure 2 This is a schematic diagram of the circuit structure of the slope detection module provided in the embodiments of this disclosure, as shown below. Figure 2 As shown, the slope detection module 20 includes a first switching unit 21, a second switching unit 22, and a differentiating unit 23; the first switching unit 21 includes a first switch S1 and a second switch S2, the second switching unit 22 includes a third switch S3 and a fourth switch S4, and the differentiating unit 23 includes a first capacitor C1, a first amplifier K1, a first resistor R1, and a second capacitor C2; the first terminal of the first switch S1 is electrically connected to the first output terminal of the current detection module, the second terminal of the first switch S1 is electrically connected to the first terminal of the first capacitor C1 and the second terminal of the third switch S3, the control terminals of the first switch S1 and the second switch S2 are electrically connected to the control terminals of the upper power transistor O1, and the first terminal of the second switch S2 is electrically connected to the first output terminal of the current detection module. The second terminal of capacitor C1 is electrically connected to the first terminal of the fourth switch S4. The second terminal of the second switch S2 is electrically connected to the grounding node. The first terminal of the third switch S3 is electrically connected to the second output terminal of the current detection module. The control terminals of the third switch S3 and the fourth switch S4 are electrically connected to the control terminal of the lower power transistor O2. The second terminal of the fourth switch S4 is electrically connected to the first terminal (i.e., the inverting input terminal) of the first amplifier K1, the first terminal of the first resistor R1, and the first terminal of the second capacitor C2, respectively. The second terminal (i.e., the non-inverting input terminal) of the first amplifier K1 is electrically connected to the grounding node. The third terminal of the first amplifier K1 is electrically connected to the second terminal of the first resistor R1, the second terminal of the second capacitor C2, and the sample-and-hold module, respectively.

[0054] Combination Figure 2 When the drive signal H_DRV of the upper power transistor is high, the first switch S1 and the second switch S2 are turned on. The first voltage V_Rising output by the current detection module 10 charges the first capacitor C1 through the first switches S1 and S2. When the drive signal L_DRV of the lower power transistor is high, the second voltage V_Falling output by the current detection module 10 is connected to the first terminal of the first capacitor C1 through the third switch S3. The first capacitor C1, the first amplifier K1, the first resistor R1 and the second capacitor C2 form a differentiating circuit. The first capacitor C1 is connected to the first amplifier K1 through the fourth switch S4. The first amplifier K1 outputs the third voltage V_SRt corresponding to the slope of the change in the conduction current of the lower power transistor. The first resistor R1 and the two capacitors C2 in the differentiating circuit have the function of high-frequency filtering, which is used to weaken the spikes generated by the amplifier K1 output at the time of the alternation of the upper and lower power transistors and suppress high-frequency interference.

[0055] The third voltage output by the slope detection module 20 is: V_SRt=C1×R1×SR V_Falling =C1×R1×SR I_Falling ×R L_ON The voltage V_cap across ×G2 and C1 is determined by the first voltage V_Rising and the second voltage V_Falling output by the current detection module 10.

[0056] In a specific implementation method Figure 3 This is a schematic diagram of the circuit structure of a sample-and-hold module provided in an embodiment of this disclosure, as shown below. Figure 3 As shown, the sample-and-hold module includes a fifth switch S5, a third capacitor C3, a fourth capacitor C4, a second resistor R2, and a second amplifier K2. The first terminal of the fifth switch S5 is electrically connected to the slope detection module. The second terminal of the fifth switch S5 is electrically connected to the first terminal of the third capacitor C3 and the first terminal of the second resistor R2. The control terminal of the fifth switch S5 is electrically connected to the control terminal of the lower power transistor O2. The second terminals of the third capacitor C3, the fourth capacitor C4, and the first terminal (i.e., the inverting input terminal) of the second amplifier K2 are electrically connected to the ground node. The second terminal of the second resistor R2 is electrically connected to the first terminal of the fourth capacitor C4 and the second terminal (i.e., the non-inverting input terminal) of the second amplifier K2. The third terminal of the second amplifier K2 is electrically connected to the slope compensation module.

[0057] like Figure 3As shown, when the drive signal L_DRV of the current power transistor is a high-level signal, the fifth switch S5 is turned on, and the sample-and-hold module 30 outputs the fourth voltage V_SRo = V_SRt. When the drive signal L_DRV of the current power transistor is a low-level signal, the fifth switch S5 is turned off, and the fourth voltage V_SRo output by the sample-and-hold module 30 is the third voltage V_SRt sampled before S5 was turned off.

[0058] That is, the output V_SRo of the sample-and-hold module satisfies the condition that V_SRo = V_SRt when the drive signal H_DRV of the power transistor is a high level signal.

[0059] In a specific implementation method Figure 4 This is a schematic diagram of the circuit structure of a slope compensation module provided in an embodiment of this disclosure, as shown below. Figure 4 As shown, the slope compensation module 40 includes a slope compensation unit 41 and a summing unit 42; the slope compensation unit 41 is configured to output a slope compensation voltage corresponding to the fourth voltage when the upper power transistor is turned on, based on the output of the fourth voltage from the sample-and-hold module; the summing unit 42 is configured to sum the slope compensation voltage with the first voltage to generate a ripple voltage.

[0060] The slope compensation unit 41 includes a transconductance amplifier GM, an inverter NG, a sixth switch S6, and a fifth capacitor C5. The positive input terminal of the transconductance amplifier GM is electrically connected to the sample-and-hold module 30, the inverting input terminal of the transconductance amplifier GM is electrically connected to the ground node, the current input terminal of the transconductance amplifier GM is electrically connected to the power supply voltage node VCC, the output terminal of the transconductance amplifier GM is electrically connected to the first input terminal of the summing unit 42, the first terminal of the sixth switch S6, and the first terminal of the fifth capacitor C5, respectively, the second terminal of the sixth switch S6 and the second terminal of the fifth capacitor C5 are electrically connected to the ground node, the control terminal of the sixth switch S6 is electrically connected to the output terminal of the inverter NG, and the input terminal of the inverter NG and the enable terminal of the transconductance amplifier GM are electrically connected to the control terminal of the lower power transistor 02, respectively.

[0061] Combination Figure 4 When the drive signal H_DRV of the upper power transistor is high, it controls the sixth switch S6 to turn off. The fourth voltage V_SRo input to the slope compensation unit passes through the transconductance amplifier GM and generates a fixed current to charge the fifth capacitor C5. The voltage signal at the first terminal of the fifth capacitor C5 is the slope compensation voltage V_Slope. When the drive signal H_DRV of the upper power transistor is low, it controls the sixth switch S6 to turn on and the transconductance amplifier GM to turn off. At this time, the sixth capacitor C6 discharges, so that the voltage across the sixth capacitor C6 returns to 0 before the next time the drive signal H_DRV of the upper power transistor switches from low to high.

[0062] After the slope compensation unit 41 outputs the slope compensation voltage V_Slope corresponding to the fourth voltage V_SRo, the summing unit 42 sums the slope compensation voltage V_Slope with the first voltage V_Rising output by the current detection module 10 to generate the ripple voltage V_Ramp, and inputs the ripple voltage V_Ramp to the duty cycle modulation module 50. The duty cycle modulation module 50 compares the error voltage V_Comp output by the error amplifier with the ripple voltage V_Ramp to generate the duty cycle signal.

[0063] Since the slope compensation voltage needs to be added to the first voltage during the conduction period of the upper power transistor, the slope of V_Slope needs to be scaled according to the amplification factor of the first current sensing unit. In this example, the slope of the slope compensation is designed to be equal to the slope of the inductor current drop. Therefore, the slope of V_Slope SR V_Slope satisfy: The slope of the slope compensation voltage V_Slope output by the slope compensation unit satisfies therefore, That is to say That is, by adjusting the first capacitor C1, the fifth capacitor C5, the first resistor R1, and the transconductance of the transconductance amplifier, the slope of the ramp compensation voltage is made equal to the slope of the inductor current decrease.

[0064] It should be noted that in the above embodiments, the slope of the ramp compensation is set to be equal to the slope of the inductor current drop, or the slope of the ramp compensation can be set to be equal to the slope of the inductor current drop × 1 / 2. This disclosure does not specifically limit this.

[0065] Based on the above embodiments, Figure 5 This is a schematic diagram of the circuit structure of a current detection module provided in an embodiment of this disclosure, as shown below. Figure 5As shown, the current detection module 10 includes a first current detection unit 11 and a second current detection unit 12. The first current detection unit 11 includes a seventh switch S7, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth capacitor C6, a third amplifier K3, and a first power supply V1. The control terminal of the seventh switch S7 is electrically connected to the control terminal of the upper power transistor O1. The first terminal of the seventh switch S7 is electrically connected to the input node IN. The second terminal of the seventh switch S7 is electrically connected to the first terminals of the third resistor R3 and the fourth resistor R4, respectively. The second terminals of the third resistor R3 and the fifth resistor R5 are electrically connected to the switch node SW, respectively. The second terminal of the fourth resistor R4 is electrically connected to the first terminal of the sixth capacitor C6 and the first terminal (i.e., the positive input terminal) of the third amplifier K3, respectively. The second terminals of the fifth resistor R5 and the sixth capacitor C6 are electrically connected to the second terminal (i.e., the inverted input terminal) of the third amplifier K3, respectively. The third terminal of the third amplifier K3 is electrically connected to the slope detection module. The fourth terminal of the third amplifier K3 is electrically connected to the first terminal of the first power supply V1. The second terminal of power supply V1 is electrically connected to the ground node; the second current detection unit 12 includes an eighth switch S8, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a seventh capacitor C7, a fourth amplifier K4, and a second power supply V2. The control terminal of the eighth switch S8 is electrically connected to the control terminal of the lower power transistor O2. The first terminal of the eighth switch S8 is electrically connected to the ground node GND. The second terminal of the eighth switch S8 is electrically connected to the first terminals of the sixth resistor R6 and the seventh resistor R7, respectively. The second terminals of the sixth resistor R6 and the eighth resistor R8 are electrically connected to the switch node SW, respectively. The second terminal of the seventh resistor R7 is electrically connected to the first terminal of the seventh capacitor C7 and the first terminal (i.e., the positive input terminal) of the fourth amplifier K4, respectively. The second terminals of the eighth resistor R8 and the seventh capacitor C7 are electrically connected to the second terminal (i.e., the inverted input terminal) of the fourth amplifier K4, respectively. The third terminal of the fourth amplifier K4 is electrically connected to the slope detection module. The fourth terminal of the fourth amplifier K4 is electrically connected to the first terminal of the second power supply V2. The second terminal of the second power supply V2 is electrically connected to the ground node.

[0066] When the drive signal H_DRV of the upper power transistor is high, the upper power transistor 01 is turned on, and the first current detection unit 11 is enabled. Switch S7 is turned on, and the input node voltage of input node IN and the switch node voltage of switch node SW are connected to the two ends of resistor R3. After being filtered by the filter composed of the fourth resistor R4, the fifth resistor R5 and the sixth capacitor C6, the signal is sent to the third amplifier K3. After being amplified by the third amplifier K3, the signal is output. The gain of the third amplifier is G1, and the signal output by the third amplifier K3 is V_Rising. The first voltage source V1 provides the DC bias voltage of the third amplifier K3.

[0067] When the drive signal L_DRV of the lower power transistor is high, the lower power transistor 02 is turned on, and the second current detection unit 12 is enabled. Switch S8 is turned on, and the ground node voltage of ground node GND and the switch node voltage of switch node SW are connected to the two ends of resistor R6. After being filtered by the filter composed of the seventh resistor R7, the eighth resistor R8 and the seventh capacitor C7, the signal is sent to the fourth amplifier K4. After being amplified by the fourth amplifier K4, the signal is output. The gain of the fourth amplifier K4 is G2, and the voltage signal output by the fourth amplifier K4 is V_Falling. The second voltage source V2 provides the DC bias voltage of the fourth amplifier K4.

[0068] The gain of the amplifiers in the first current detection unit 11 and the second current detection unit 12 must satisfy the following relationship: G1×R H_ON =G2×R L_ON R H_ON On-resistance of the upper power transistor, R L_ON The on-resistance of the lower power transistor ensures that the voltage across the first capacitor C1 in the slope detection module 20 does not change drastically when the upper and lower power transistors are alternately turned on.

[0069] Based on the above embodiments, Figure 6 This is a schematic diagram of the circuit structure of another slope detection module provided in this embodiment of the present disclosure, as shown below. Figure 6 As shown, the slope detection module also includes a first delay unit and a second delay unit; the first delay unit 24 includes a first delayer D1 and a first AND gate AND1, the first terminal of the first delayer D1 is electrically connected to the control terminal of the upper power transistor O1 and the first terminal of the first AND gate AND1 respectively, the output terminal of the first delayer D1 is electrically connected to the second terminal of the first AND gate AND1, and the output terminal of the first AND gate AND1 is electrically connected to the control terminal of the first switch S1 and the control terminal of the second switch S2 respectively; the second delay unit 25 includes a second delayer D2 and a second AND gate AND2, the first terminal of the second delayer D2 is electrically connected to the control terminal of the lower power transistor O2 and the first terminal of the second AND gate AND2 respectively, the output terminal of the second delayer D2 is electrically connected to the second terminal of the second AND gate AND2, and the output terminal of the second AND gate AND2 is electrically connected to the control terminal of the third switch S3 and the control terminal of the fourth switch S4 respectively.

[0070] like Figure 6As shown, the slope detection module 20 also includes a first delay unit 24 and a second delay unit 25. The first AND gate AND1 receives the drive signal H_DRV of the upper power transistor and the drive signal H_DRV of the upper power transistor after being delayed by the first delay unit D1 for a time t1. After the first delay unit 24 has an internally set shielding time t1 (used to shield the resonant spike current generated by parasitic parameters at the time of the upper power transistor turn-on), it controls the first switch S1 and the second switch S2 to be turned on, so that the first voltage V_Rising output by the first current detection unit 11 is connected to the two ends of the first capacitor C1 through the first switch S1 and the second switch S2. The second AND gate AND2 receives the drive signal L_DRV of the lower power transistor and the drive signal L_DRV of the lower power transistor after being delayed for a time t2 by the second delay unit D2. After the second delay unit 25 has been internally set for a shielding time t2 (used to shield the resonant spike current generated by parasitic parameters at the turn-on time of the lower power transistor), it controls the third switch S3 and the fourth switch S4 to be turned on, so that the second voltage V_Falling output by the second current detection unit 12 is connected to the first terminal of the first capacitor C1 through the third switch S3, and the voltage across the first capacitor C1 is output to the first amplifier K1 through the fourth switch S4.

[0071] Based on the above embodiments, Figure 7 This is a schematic diagram of the circuit structure of another sample-and-hold module provided in an embodiment of this disclosure, as shown below. Figure 7 As shown, the sample-and-hold module also includes a third delay unit D3 and a third AND gate AND3. The first terminal of the third delay unit D3 is electrically connected to the control terminal of the lower power transistor O2 and the first terminal of the third AND gate AND3, respectively. The output terminal of the third delay unit D3 is electrically connected to the second terminal of the third AND gate AND3, and the output terminal of the third AND gate AND3 is electrically connected to the control terminal of the fifth switch S5, respectively.

[0072] The sample-and-hold module also includes a third delay circuit D3 and a third AND gate AND3. The third AND gate AND3 receives the drive signal L_DRV of the lower power transistor and the drive signal L_DRV of the lower power transistor output after a delay of t3 times by the third delay circuit D3. After a shielding time t3, it controls the fifth switch S5 to conduct, thereby sampling or holding the V_SRt output by the first amplifier K1 through the sample-and-hold module. This ensures that when the first amplifier K1 outputs a stable V_SRt, the sample-and-hold module samples or holds the V_SRt. The sampling and holding process is as follows: when the current power transistor's drive signal L_DRV is high, after a shielding time t3, the fifth switch S5 is opened, and the sample-and-hold module 30 outputs the fourth voltage V_SRo = V_SRt. When the current power transistor's drive signal L_DRV is low, the fifth switch S5 is turned off, and the sample-and-hold module 30 outputs the fourth voltage V_SRo, which is the third voltage V_SRt sampled before the fifth switch S5 is turned off. By setting the shielding time, the spike voltage in the V_SRt signal output by the first amplifier K1 is shielded.

[0073] Optional, such as Figure 8 As shown, the ramp compensation circuit also includes a control module 70 and a drive module 80; the control module 70 is configured to generate a pulse width modulation signal based on a clock signal and a duty cycle signal; the drive module 80 is configured to generate a switching signal based on the pulse width modulation signal to control the conduction state of the upper power transistor 01 and the lower power transistor 02.

[0074] Specifically, in combination Figure 9 When the drive signal H_DRV generated by the drive module for the upper power transistor is high, the upper power transistor is turned on. The drive signal H_DRV generated by the drive module enables the first current detection unit, and the first current detection unit outputs V_Rising. The first switch S1 and the second switch S2 of the slope detection module are turned on after an internally set shielding time t1, connecting the V_Rising output by the first current detection unit to the first capacitor C1 through the first switch S1 and the second switch S2. Figure 9V_Cap represents the voltage across the first capacitor C1 (positive terminal). When the drive signal H_DRV of the upper power transistor generated by the drive module is low or high, the first current detection unit is turned off, and the first switch S1 and the second switch S2 of the slope detection module are turned off. At this time, the third switch S1 and the fourth switch S4 are also in the off state, and the voltage in the first capacitor C1 remains unchanged. This stage is in the dead time of the alternation between the power transistor and the lower power transistor. When the drive signal L_DRV of the lower power transistor generated by the drive module is high, the lower power transistor is turned on. The drive signal L_DRV of the lower power transistor generated by the drive module enables the second current detection unit, and the second current detection unit outputs V_Falling. The third switch S3 and the fourth switch S4 of the slope detection module are turned on after the internally set shielding time t2, and the V_Falling output by the second current detection unit is connected to the positive terminal of the first capacitor C1 through the third switch S3. By setting the amplification factor G1 of the first amplifier in the first current detection unit corresponding to the upper power transistor and the amplification factor G2 of the second amplifier in the second current detection unit corresponding to the lower power transistor, the following condition is met: G1 × R H_ON =G2×R L_ON R H_ON On-resistance of the upper power transistor, R L_ON The on-resistance of the lower power transistor ensures that the voltage across the first capacitor C1 in the slope detection module 20 does not change drastically when the upper and lower power transistors are alternately turned on. At this time, the voltage of the first capacitor C1 is the synthesis of V_Rising and V_Falling, i.e., V_Cap. Then, the voltage of the first capacitor C1 is input to the first amplifier K1 through the fourth switch S4, and the third voltage V_SRt is output by the first amplifier K1. When the drive signal L_DRV of the lower power transistor generated by the drive module is high, the sample-and-hold module sends the third voltage V_SRt output by the slope detection module to the filter sampling circuit composed of the fifth switch S5, the second resistor R2, the third capacitor C3 and the fourth capacitor C4 after a shielding time t3, and sends it out through the second amplifier K2 to obtain the fourth voltage V_SRt.

[0075] In addition, such as Figure 8 As shown, the slope compensation circuit also includes an error amplifier module 90. The inverting input of the error amplifier module 90 receives the sampling voltage FB output by the main power module, and the non-inverting input receives the reference voltage Vref. Based on the sampling voltage FB and the reference voltage Vref, the error voltage is output to the duty cycle modulation module.

[0076] Specifically, the error amplifier module includes an operational amplifier EA, a capacitor C0, and a resistor R0; wherein, the inverting input terminal of the operational amplifier is coupled to the sampling voltage node of the main power module, the non-inverting input terminal of the operational amplifier is coupled to the reference voltage node, the output terminal of the operational amplifier is coupled to the first end of the resistor R and the input terminal of the duty cycle modulation module 50, the second end of the resistor R0 is coupled to the first end of the capacitor C0, and the second end of the capacitor C0 is coupled to the ground node.

[0077] The fixed-frequency peak current mode control slope compensation circuit provided in this embodiment includes a slope detection module. Based on the first and second voltages output by the current detection module, the slope detection module outputs a third voltage corresponding to the slope of the change in the conduction current of the lower power transistor during the lower transistor's conduction period, and outputs zero voltage during the upper transistor's conduction period. A sample-and-hold module samples the third voltage during the lower transistor's conduction period, holds the third voltage during the upper transistor's conduction period, and outputs a fourth voltage. The slope compensation module then applies the slope compensation voltage corresponding to this fourth voltage to the upper power transistor during the upper transistor's conduction period. The first voltage output by the current detection module is compensated and then input to the duty cycle modulation module. Based on the duty cycle modulation module, the conduction time of the upper power transistor is modulated and demodulated. Compared with the fixed slope compensation, the problem of excessive or insufficient compensation is avoided, and the subharmonic oscillation caused by disturbance is reduced. In addition, since the slope detection module automatically tracks the slope of the change in the conduction current of the lower power transistor when it is turned on, the subharmonic oscillation will not occur due to insufficient compensation when the circuit output voltage is high. When the circuit output voltage is low, the slope compensation circuit provided in this application has better bandwidth and phase margin compared with the fixed slope compensation circuit.

[0078] Based on the above embodiments, this disclosure also provides a switching circuit, including the slope compensation circuit described in any of the above embodiments, which has the beneficial effects described in any of the above embodiments. This disclosure will not provide specific examples of each of these.

[0079] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0080] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A slope compensation circuit with fixed-frequency peak current mode control, characterized in that, include: Current detection module, slope detection module, sample and hold module, slope compensation module, and duty cycle modulation module; The current detection module is configured to acquire the switching node voltage, and output a first voltage based on the switching node voltage and the input node voltage during the conduction of the upper power transistor, and output a second voltage based on the switching node voltage and the ground node voltage during the conduction of the lower power transistor. The slope detection module is configured to determine a third voltage corresponding to the slope of the change in the conduction current of the lower power transistor based on the first voltage and the second voltage. The sample-and-hold module is configured to sample the third voltage during the conduction of the lower power transistor, hold the third voltage at the moment before the upper power transistor is turned on, and output the fourth voltage during the conduction of the upper power transistor. The slope compensation module is configured to generate a slope compensation voltage corresponding to the fourth voltage based on the fourth voltage, and to generate a ripple voltage based on the slope compensation voltage and the first voltage. The duty cycle modulation module is configured to generate a duty cycle signal based on the ripple voltage and the error voltage.

2. The slope compensation circuit according to claim 1, characterized in that, The slope detection module includes a first switching unit, a second switching unit, and a differentiating unit; The first switching unit includes a first switch and a second switch, the second switching unit includes a third switch and a fourth switch, and the differentiating unit includes a first capacitor, a first amplifier, a first resistor and a second capacitor; The first terminal of the first switch is electrically connected to the first output terminal of the current detection module. The second terminal of the first switch is electrically connected to the first terminal of the first capacitor and the second terminal of the third switch. The control terminals of the first switch and the second switch are electrically connected to the control terminals of the upper power transistor. The first terminal of the second switch is electrically connected to the second terminal of the first capacitor and the first terminal of the fourth switch. The second terminal of the second switch is electrically connected to the ground node. The first terminal of the third switch is electrically connected to the second output terminal of the current detection module. The control terminals of the third switch and the fourth switch are electrically connected to the control terminals of the lower power transistor. The second terminal of the fourth switch is electrically connected to the first terminal of the first amplifier, the first terminal of the first resistor, and the first terminal of the second capacitor. The second terminal of the first amplifier is electrically connected to the ground node. The third terminal of the first amplifier is electrically connected to the second terminal of the first resistor, the second terminal of the second capacitor, and the sample-and-hold module.

3. The slope compensation circuit according to claim 1, characterized in that, The sample-and-hold module includes a fifth switch, a third capacitor, a fourth capacitor, a second resistor, and a second amplifier; The first terminal of the fifth switch is electrically connected to the slope detection module. The second terminal of the fifth switch is electrically connected to the first terminal of the third capacitor and the first terminal of the second resistor, respectively. The control terminal of the fifth switch is electrically connected to the control terminal of the lower power transistor. The second terminal of the third capacitor, the second terminal of the fourth capacitor, and the first terminal of the second amplifier are electrically connected to the ground node, respectively. The second terminal of the second resistor is electrically connected to the first terminal of the fourth capacitor and the second terminal of the second amplifier, respectively. The third terminal of the second amplifier is electrically connected to the slope compensation module.

4. The slope compensation circuit according to claim 1, characterized in that, The slope compensation module includes a slope compensation unit and a summing unit; The slope compensation unit is configured to output a slope compensation voltage corresponding to the fourth voltage when the upper power transistor is turned on. The summing unit is configured to sum the slope compensation voltage with the first voltage to generate a ripple voltage.

5. The slope compensation circuit according to claim 4, characterized in that, The slope compensation unit includes a transconductance amplifier, an inverter, a sixth switch, and a fifth capacitor; The positive input terminal of the transconductance amplifier is electrically connected to the sample-and-hold module, the inverting input terminal of the transconductance amplifier is electrically connected to the ground node, the current input terminal of the transconductance amplifier is electrically connected to the power supply voltage node, the output terminal of the transconductance amplifier is electrically connected to the first input terminal of the summing unit, the first terminal of the sixth switch, and the first terminal of the fifth capacitor, respectively, the second terminal of the sixth switch and the second terminal of the fifth capacitor are respectively electrically connected to the ground node, the control terminal of the sixth switch is electrically connected to the output terminal of the inverter, and the input terminal of the inverter and the enable terminal of the transconductance amplifier are respectively electrically connected to the control terminal of the lower power transistor.

6. The slope compensation circuit according to claim 1, characterized in that, The current detection module includes a first current detection unit and a second current detection unit. The first current detection unit includes a seventh switch, a third resistor, a fourth resistor, a fifth resistor, a sixth capacitor, a third amplifier, and a first power supply. The control terminal of the seventh switch is electrically connected to the control terminal of the upper power transistor. The first terminal of the seventh switch is electrically connected to the input node. The second terminal of the seventh switch is electrically connected to the first terminals of the third resistor and the fourth resistor, respectively. The second terminals of the third resistor and the fifth resistor are electrically connected to the switch node, respectively. The second terminal of the fourth resistor is electrically connected to the first terminal of the sixth capacitor and the first terminal of the third amplifier, respectively. The second terminals of the fifth resistor and the sixth capacitor are electrically connected to the second terminal of the third amplifier, respectively. The third terminal of the third amplifier is electrically connected to the slope detection module. The fourth terminal of the third amplifier is electrically connected to the first terminal of the first power supply. The second terminal of the first power supply is electrically connected to the ground node. The second current detection unit includes an eighth switch, a sixth resistor, a seventh resistor, an eighth resistor, a seventh capacitor, a fourth amplifier, and a second power supply. The control terminal of the eighth switch is electrically connected to the control terminal of the lower power transistor. The first terminal of the eighth switch is electrically connected to a ground node. The second terminal of the eighth switch is electrically connected to the first terminals of the sixth and seventh resistors, respectively. The second terminals of the sixth and eighth resistors are electrically connected to the switch node, respectively. The second terminal of the seventh resistor is electrically connected to the first terminal of the seventh capacitor and the first terminal of the fourth amplifier, respectively. The second terminals of the eighth resistor and the seventh capacitor are electrically connected to the second terminal of the fourth amplifier, respectively. The third terminal of the fourth amplifier is electrically connected to the slope detection module. The fourth terminal of the fourth amplifier is electrically connected to the first terminal of the second power supply. The second terminal of the second power supply is electrically connected to a ground node.

7. The slope compensation circuit according to claim 2, characterized in that, The slope detection module further includes a first delay unit and a second delay unit; The first delay unit includes a first delay unit and a first AND gate. The first terminal of the first delay unit is electrically connected to the control terminal of the upper power transistor and the first terminal of the first AND gate, respectively. The output terminal of the first delay unit is electrically connected to the second terminal of the first AND gate, and the output terminal of the first AND gate is electrically connected to the control terminal of the first switch and the control terminal of the second switch, respectively. The second delay unit includes a second delay unit and a second AND gate. The first terminal of the second delay unit is electrically connected to the control terminal of the lower power transistor and the first terminal of the second AND gate, respectively. The output terminal of the second delay unit is electrically connected to the second terminal of the second AND gate, and the output terminal of the second AND gate is electrically connected to the control terminal of the third switch and the control terminal of the fourth switch, respectively.

8. The slope compensation circuit according to claim 3, characterized in that, The sample-and-hold module further includes a third delay unit and a third AND gate. The first terminal of the third delay unit is electrically connected to the control terminal of the lower power transistor and the first terminal of the third AND gate, respectively. The output terminal of the third delay unit is electrically connected to the second terminal of the third AND gate, and the output terminal of the third AND gate is electrically connected to the control terminal of the fifth switch.

9. The slope compensation circuit according to claim 1, characterized in that, It also includes a control module and a driver module; The control module is configured to generate a pulse width modulation signal based on the clock signal and the duty cycle signal; The driving module is configured to generate a switching signal based on the pulse width modulation signal to control the conduction state of the upper power transistor and the lower power transistor.

10. A switching circuit, characterized in that, Includes the slope compensation circuit as described in any one of claims 1-9.

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