A control method of a totem-pole pfc converter

Abstract

This invention relates to the field of circuit control technology, specifically to a control method for a totem-pole PFC converter, comprising: controlling the operation of the totem-pole PFC converter based on a triangular current mode and obtaining the actual peak current; dynamically searching and locking the turn-off delay time during operation based on the actual peak current using a whale optimization algorithm; and correcting the PWM control signal of the totem-pole PFC converter based on the turn-off delay time. Addressing the problem of reduced control efficiency in existing totem-pole PFC converter circuits due to device turn-on and turn-off delays, this invention introduces a whale optimization algorithm to independently search for and determine the optimal turn-off delay time among the control parameters, and then uses this turn-off delay time to correct the control signal, thereby achieving better control efficiency optimization.

Description

Technical Field

[0001] This invention relates to the field of circuit control technology, specifically to a control method for a totem-pole PFC converter. Background Technology

[0002] Totem-pole PFC rectifiers, with their bridgeless structure, low conduction loss, high power density, and excellent EMI characteristics, are widely used in electric motorcycle on-board converters (OBCs), high-efficiency server power supplies, and energy storage converters, becoming a mainstream research direction for current high-efficiency AC-DC front-end topologies. However, totem-pole PFCs in TCM mode suffer from problems such as large fluctuations in switching frequency with operating conditions and easy degradation of efficiency under light loads. Existing technologies have attempted to introduce new control methods to address these issues.

[0003] For example, patent application CN201910221026.1 discloses a driving device for a totem pole circuit with noise countermeasures and through-current prevention measures. A pulse generation circuit receives logic input signals for the high side and logic input signals for the low side, generates a set signal and a reset signal based on the logic input signals, and generates a control signal based on the logic input signals. A high-side potential detection circuit detects a high-side reference potential; if the high-side potential determination circuit detects a rise in the high-side reference potential during the dead time period, an event signal generation circuit outputs an event signal. If the pulse generation circuit receives an event signal, it regenerates a reset signal and outputs a control signal after a period equal to the dead time in the case where no event signal is generated, from the moment of regeneration.

[0004] For example, patent application CN202411072413.0 discloses a totem-pole PFC drive architecture, electrically connected to a low-frequency bridge arm circuit unit and a high-speed bridge arm circuit unit. The totem-pole PFC drive architecture includes a detection circuit unit, an analog PFC control circuit unit, and a logic drive circuit unit. The detection circuit unit receives an AC signal and outputs an AC positive half-cycle detection signal, an AC negative half-cycle detection signal, and an AC output signal. The analog PFC control circuit unit receives the AC output signal and outputs a PFC drive control signal. The logic drive circuit unit receives the AC positive half-cycle detection signal, the AC negative half-cycle detection signal, and the PFC drive control signal, and outputs a first drive signal and a second drive signal to the low-frequency bridge arm circuit unit according to a truth table to drive the first switch and the second switch.

[0005] However, in practical implementation, this type of technical solution, in triangular current mode, suffers from system delays that prevent its active switching transistors from achieving zero-voltage turn-on across the entire range, thus affecting the converter's efficiency. Furthermore, because the actual parameter values ​​of the components in the PFC circuit often differ from their nominal parameter values, the converter's operating efficiency remains low. Summary of the Invention

[0006] To address the aforementioned problems in the existing technology, a control method for a totem pole PFC converter is provided.

[0007] The specific technical solution is as follows: A control method for a totem-pole PFC converter, applicable to the controller of a totem-pole PFC converter, the control method includes: Step S1: Controlling the operation of the totem-pole PFC converter based on the triangular current mode and obtaining the actual peak current; Step S2: Dynamically searching and locking the turn-off delay time during operation based on the actual peak current using the whale optimization algorithm; Step S3: Correcting the PWM control signal of the totem-pole PFC converter according to the turn-off delay time.

[0008] On the other hand, step S1 includes: step S11: initializing the control parameters and generating a modulated PWM signal corresponding to the totem-pole PFC converter using the initialized control parameters; step S12: performing conduction control on the totem-pole PFC converter based on the modulated PWM signal and acquiring the output voltage; step S13: determining whether the output voltage is stable within the target voltage range; if yes, proceed to step S14; if no, return to step S12 to generate a new modulated PWM signal; step S14: measuring the actual peak current.

[0009] On the other hand, step S2 includes: step S21: setting multiple shutdown delay individuals and initializing their parameters; step S22: calculating the fitness value of each shutdown delay individual based on the actual peak current; step S23: selecting the optimal adapted individual with the smallest fitness based on the fitness value, and generating random numbers and updating the first and second coefficients; step S24: updating the population of shutdown delay individuals according to the update rule matched by the random numbers and the first coefficients; step S25: determining whether the iteration condition is met; if yes, outputting the optimal adapted individual of the last round as the shutdown delay time; if no, returning to step S22.

[0010] On the other hand, in step S22, the process of generating the fitness value includes: ; In the formula, For the first The fitness values ​​mentioned above; This refers to the actual peak current; The desired peak current; The number of samples.

[0011] On the other hand, in step S23, the method for updating the first coefficient and the second coefficient includes: ; In the formula, The first coefficient; This is the second coefficient; r 1 and r 2 is a random parameter in the range [0,1]; a It is a parameter that decreases linearly from 2 to 0 and is used as a distance control factor; This represents the maximum number of iterations. This represents the current iteration number.

[0012] On the other hand, in step S24, the update rule includes a first update rule, which is to update the population using the following method when the random number is greater than 0.5: ; In the formula, For the updated shutdown delay individual; For the corresponding individuals whose shutdown was delayed before the update; The optimal fit individual before the update; The distance between the previously delayed shutdown individual and the optimally fit individual is calculated as follows: D 2=| X * ( t )-X( t )|; It is an empirical constant. The step size.

[0013] On the other hand, in step S24, the update rule includes a second update rule, which is to update the population when the random number is less than 0.5 and the absolute value of the first coefficient is less than 1, using the following method:

[0014] In the formula, For the updated shutdown delay individual; For the corresponding individuals whose shutdown was delayed before the update; The shutdown delay individual is randomly selected from the population before the update; The first coefficient; This is the second coefficient; This is the search step size.

[0015] On the other hand, in step S24, the update rule includes a third update rule, which is to update the population using the following method when the random number is less than 0.5 and the absolute value of the first coefficient is greater than 1: ; In the formula, For the updated shutdown delay individual; For the corresponding individuals whose shutdown was delayed before the update; For the previously mentioned shutdown delay individuals; The first coefficient; This is the second coefficient; To enclose the step size.

[0016] On the other hand, step S3 includes: step S31: determining the initial turn-on time, diode freewheeling time, additional turn-on time, and initial turn-off time based on the target current; step S32: determining the final turn-on time based on the diode freewheeling time, the initial turn-on time, and the turn-off delay time, and determining the final turn-off time based on the initial turn-off time, the additional turn-on time, and the turn-off delay time; step S33: performing control based on the final turn-on time and the final turn-off time.

[0017] A storage medium includes computer instructions that, when executed by a computer device, perform the control method described above.

[0018] The above technical solution has the following advantages or beneficial effects: In response to the problem that the control efficiency of the totem pole PFC converter circuit in the existing technology is easily reduced due to the device turn-on and turn-off delay during the control process, the whale optimization algorithm is introduced to search for and determine the optimal turn-off delay time in the control parameters. Then, the control signal is corrected in combination with the turn-off delay time, thereby achieving a better control efficiency optimization effect. Attached Figure Description

[0019] Embodiments of the invention will be described more fully with reference to the accompanying drawings. However, the drawings are for illustration and explanation only and do not constitute a limitation on the scope of the invention.

[0020] Figure 1 This is an overall schematic diagram of an embodiment of the present invention; Figure 2 This is a schematic diagram of the converter circuit in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the effect of system delay on inductor current when TRV is less than the conduction time in CT mode according to an embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the effect of system delay on inductor current when TRV is greater than the conduction time in CT mode according to an embodiment of the present invention. Figure 5 This is a schematic diagram illustrating the effect of system delay on inductor current when the inductor current decay time is greater than the conduction time in PT mode, according to an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the effect of system delay on inductor current when the inductor current decay time is less than the conduction time in PT mode, according to an embodiment of the present invention. Figure 7 This is a schematic diagram of step S1 in an embodiment of the present invention; Figure 8 This is a schematic diagram of step S2 in an embodiment of the present invention; Figure 9 This is a schematic diagram of step S3 in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0023] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0024] This invention includes: a control method for a totem-pole PFC converter, applicable to a controller for a totem-pole PFC converter. The control method includes: step S1: controlling the operation of the totem-pole PFC converter based on a triangular current mode and obtaining the actual peak current; step S2: dynamically searching and locking the turn-off delay time during operation based on the actual peak current using a whale optimization algorithm; step S3: correcting the PWM control signal of the totem-pole PFC converter based on the turn-off delay time.

[0025] Specifically, to address the issue that the control efficiency of existing totem-pole PFC converter circuits is easily reduced due to device turn-on and turn-off delays during the control process, a whale optimization algorithm is introduced to search for and determine the optimal turn-off delay time among the control parameters. Then, the control signal is modified in combination with the turn-off delay time, thereby achieving a better control efficiency optimization effect.

[0026] Specifically Figure 2 The topology of a totem-pole PFC converter is shown. This circuit contains four power switches, where the first switch S1 and the second switch S2 are high-frequency switches, and the third switch S3 and the fourth switch S4 are power frequency switches. in For the input voltage, C oss1 C oss2 These are the junction capacitances of S1 and S2, respectively. L is the Boost inductor, and i... L For inductor current, C o For the output filter capacitor, U o For the output voltage, R L D is the load resistance. S1 -D S4 These are the body diodes S1-S4, respectively.

[0027] In a totem-pole PFC converter, one operating cycle includes both positive and negative half-cycles. Due to the symmetrical nature of the totem-pole topology, i.e., the operating modes of the positive and negative half-cycles are symmetrical, the following analysis focuses only on the input voltage U. in The operating mode when >0, in which case one switching cycle can be divided into six stages, including: Phase One: In t 0 o'clock S 1. Turn off S 2. Turn on. At this time, the inductor current... i L exist T on_c It increases linearly from zero within the time period. Until... t 1 momentS 1. Turn off S 2. Turn off; Phase Two: Inductors L and two junction capacitances C oss1 , C oss2 Together they form a resonant circuit. From t Starting at moment 1, C oss1 Discharge, C oss2 Charge. Until t At time 2, S 1 drain-source voltage u ds1 Drop to zero, S 2 Drain-source voltage u ds2 Rise to U o , D S1 Conduct and u ds1 Clamped at 0.

[0028] Third stage: The inductor current begins to decrease linearly, and the current flows through... S 1 (If the actual dead time equals) T r1 , S 1 in t Activation time 2. If the actual dead time is greater than... T r1 , D S1 During the remaining dead time, the current will be connected. After the dead time ends, S (1 will be activated) and S 4. Supply power to the load. Until... t At time 3, the inductor current drops to 0.

[0029] Phase Four: When U in ≤ U o / 2, if t 3 moments S 1. Off, inductor L It will be related to two junction capacitances C oss1 , C oss2 The resonance phase V is initiated, and the resonance phase ends. u ds2 It will become zero. S 2. This will enable ZVS.

[0030] Phase 5: Inductors L and two junction capacitances C oss1 , C oss2 Together they form a resonant circuit. From t Starting at time 4, the switching transistor S 1 junction capacitance C oss1 Start charging, switching transistor S 2 junction capacitance C oss2 Start discharging. Until t 5 o'clock, u ds1 Rise to U o , u ds2 Decrease to 0 D S2 Conduct and u ds2 Clamped at 0.

[0031] Phase 6: t 5 moments D S2 When the circuit is turned on, the inductor current increases linearly. t When the inductor current reaches 0 at time 6, the switching cycle ends.

[0032] The above analysis of the operating modes of the TCM totem-pole PFC converter is based on an ideal system. However, in actual control systems, there is a system delay. The following discussion will focus on the positive half-cycle and ignore the current change during the resonance phase, discussing the CT mode and PT mode respectively. Figure 3 and Figure 4 The display shows the changes in inductor current under CT mode, where i L_ref For the desired inductor current, i L_act This represents the actual inductor current. When the inductor current reaches the upper current command (Ucc) value, the active switching transistor... T CT_off The circuit is turned off only after a certain time, during which additional changes occur. Δi CT1 .exist t' At time 1, the synchronous switch did not turn on immediately but waited for a period of time. T CT_on It is only activated afterward. During this period, the body diode will conduct freewheeling current. T CT_onThis will not affect the linear decrease of the inductor current. When the inductor current reaches the low current command (Lcc), the synchronous switch transistor passes through... T CT_off The process of shutting down after a certain time generates additional changes. Δi CT2 .exist t' At time 3, the active switch did not turn on immediately but waited... T CT_on Just turned on (because the resonant time is very short, therefore it is assumed to be contained in [ t' 2, t' [3] Within the time period). As can be seen from the preceding TCM modal analysis, t' Time 3 corresponds to the start of the fourth stage. T RV The body diode of the active switch will conduct for a short period of time, while the active switch will only conduct when the current flows through it. T RV ZVS activation can only be achieved within a specific timeframe. Therefore, when... T RV < T CT_on At this time, the active switching transistor cannot achieve ZVS turn-on, such as Figure 3 As shown. When T RV ≥ T CT_on At this time, an active switching transistor can achieve ZVS turn-on, such as Figure 4 As shown.

[0033] In PT mode, such as Figure 5 , Figure 6 As shown, in t' Before 0, the inductor current increases linearly, until... t' At time 0, the active switch did not turn off immediately, but instead remained off after the PT mode turn-off time. T PT_off The time is only turned off, during which an additional PT mode current delay change is generated. Δi PT1 .exist t' At time 1, the expected current i L_ref With actual current i L_act First current difference Δi ( t' 1) can be represented as: ; In the formula, This is the first current difference. This refers to the shutdown delay time in PT mode. For output voltage, It is a Boost inductor.

[0034] Due to the existence of PT mode opening time T PT_on Synchronization tube in t' At time 1, the circuit does not immediately turn on, but its body diode will conduct freewheeling current, indicating the PT mode turn-on time. T PT_on This will not affect the linear decrease of the inductor current. t' At time 2, the synchronizing tube did not turn off immediately but waited until the PT mode turn-off time had elapsed. T PT_off It was only turned off after a certain time. t' At time 3, the expected current i L_ref With actual current i L_act Second current difference Δi ( t' 3) can be represented as: ; In the formula, For the second current interpolation, Input voltage, For Boost inductors, This is the shutdown time for PT mode.

[0035] exist t' The inductor current decay time required for the inductor current to decrease to 0 at time 3 T' PT_zero for: ; In the formula, The inductor current decay time. For output voltage, Input voltage, This is the shutdown time for PT mode.

[0036] arrive t' At time 3, the synchronizing tube will go through the PT mode conduction time again. T PT_on It was only turned on after that (because the resonance time is very short, it is assumed to be included in [...]). t' 2, t' 3] within the time period). When T' PT_zero > T PT_on At times, such as Figure 5 As shown, the inductor current will... T PT_on It decreases linearly over time until... t'4. When the active switch is turned on, the inductor current begins to increase linearly. Because in t' At time 4, the inductor current has not reached zero, so the active switch cannot achieve zero-voltage turn-on and zero-crossing detection (ZCD) cannot trigger a new switching cycle. However, the valley current in the following switching cycles will gradually approach zero until ZCD triggers a new switching cycle. i L_ref and i L_act Consistent. When T' PT_zero < T PT_on At times, such as Figure 6 As shown, in t' At time 4, the inductor current has reached zero, but T PT_on Time has not yet ended, until t' The active switch only turns on at time 5, but it cannot achieve zero-voltage turn-on. Figure 6 What is presented is also U in The change in inductor current when the input voltage is small U in When the average input current distortion is close to 0, there is almost no distortion, which is the opposite of the CT mode.

[0037] Since the turn-off delay is generally greater than the turn-on delay, and the actual dead time is also greater than the resonant time, the system delays in both modes do not affect the ZVS turn-on of the synchronous switch. As analyzed above, the system delay in CT mode causes zero-crossing distortion of the average input current and prevents the active switch from achieving full-range ZVS turn-on, while the system delay in PT mode only prevents the active switch from achieving full-range ZVS turn-on. Therefore, PT mode can be used to implement TCM modulation, but the effect of system delay still needs to be eliminated.

[0038] To eliminate the effects of turn-off delay, the switching transistor needs to be switched in advance. T PT_off Time-based turn-off. Because the turn-on delay doesn't provide the active switch with sufficient time margin to achieve ZVS turn-on, this can be addressed by increasing | i R | value thus ensuring T RV ≥ T PT_on Inductor current i R It should meet the following requirements: ; because i R The more negative the inductor current, the larger the ripple. i ROnly need to meet the activation delay T PT_on The value is sufficient; In the formula, For inductor current, For output voltage, Input voltage, For PT mode conduction time, For Boost inductors, Z n This is the characteristic impedance.

[0039] Based on the above analysis, the above control method is provided. That is, the output voltage of the whole system is regulated by a voltage single-loop control system. During the initialization phase, the output voltage is collected and combined with the preset control algorithm to adjust the PWM control signals of the first switch S1 to the fourth switch S4 respectively, so that the whole circuit completes the aforementioned positive and negative half-cycle working cycle.

[0040] In the initial stage, variables related to the turn-off delay time are assigned a value of 0, and then a feedback control process based on the output voltage is performed, including the control of the output voltage. U o The sample is detected by hardware circuitry, and after passing through a notch filter, it is compared with the target output voltage. U o_ref Subtraction, error voltage U err The input signal is fed into the PI control module to obtain the output signal. The output signal is then passed through the limiting module and multiplied by the unit sine wave signal output from the PLL phase-locked loop module to obtain the target current. i ref .because i ref ≈ i off / 2, i off Given the inductor current during the first stage mentioned above, the initial conduction time can be obtained. T on_c freewheeling time of the combined diode T RV Initial turn-off time of synchronous switch T off_c Additional conduction time T R and the first dead zone time T r1 Second Dead Zone Time T r2 . T on_c add T RV Subtract the shutdown delay time T PT_offObtain the final on-time of the active switch. T on , T off_c add T R Subtract the shutdown delay time T PT_off Obtain the final turn-off time of the active switch. T off Finally, the PWM control signals corresponding to the first to fourth switching transistors are obtained by using the pre-configured ePWM algorithm inside the controller.

[0041] Subsequently, by combining the actual peak current during actual operation, the current operating status of the converter can be determined. The actual peak current is used as a feedback indicator, and the control parameters based on the turn-off delay time are used as individual particles to perform iterative optimization using the whale optimization algorithm to determine the optimal control efficiency under which turn-off delay time.

[0042] Finally, the turn-off delay time obtained through iteration is substituted back into the previous calculation process to obtain a new PWM control signal for control.

[0043] In one embodiment, such as Figure 7 As shown, step S1 includes: Step S11: Initialize the control parameters and generate a modulated PWM signal corresponding to the totem-pole PFC converter using the initialized control parameters; Step S12: Control the conduction of the totem-pole PFC converter based on the modulated PWM signal and acquire the output voltage; Step S13: Determine whether the output voltage is stable within the target voltage range; if yes, proceed to step S14; if no, return to step S12 to generate a new modulated PWM signal; Step S14: Measure the actual peak current.

[0044] Specifically, to achieve better control performance, in this embodiment, during the initial system startup process, the control parameters are initialized, including setting the turn-off delay time to zero, obtaining the initial control times from a table, and obtaining the desired external input voltage. Then, the initialized control parameters are used to generate a modulated PWM signal corresponding to the totem-pole PFC converter, controlling the first to fourth switching transistors to perform conduction control respectively.

[0045] Subsequently, during the conduction control process, the output voltage is acquired and the aforementioned voltage-based single-loop PWM signal adjustment process is performed. During this adjustment process, the turn-off delay time is kept at zero, and the actual output voltage is obtained through voltage sampling and notch filtering. It is then determined whether the output voltage is stable within the target voltage range.

[0046] When the output voltage stabilizes, the initialization phase is considered complete, and the process switches to measuring the actual peak current to facilitate the subsequent optimization process.

[0047] In one embodiment, such as Figure 8 As shown, step S2 includes: Step S21: Set up multiple turn-off delay individuals and initialize their parameters; Step S22: Calculate the fitness value of each turn-off delay individual based on the actual peak current; Step S23: Filter the individual with the smallest fitness based on the fitness value, and generate random numbers and update the first and second coefficients; Step S24: Update the population of turn-off delay individuals according to the update rule matched by the random numbers and the first coefficient; Step S25: Determine whether the iteration condition is met; if yes, output the optimal fit individual of the last round as the turn-off delay time; if no, return to step S22.

[0048] Specifically, to achieve a better parameter optimization process, in this embodiment, after the circuit enters a steady state, the control parameters are first initialized, including the maximum number of iterations. t max Random parameters r 1. Random parameters r 2. Random Numbers p Empirical constants b Iteration coefficients a Population size (Agents), Individual population T PT_off [Agents], Individual fitness fitness [Agents], First Coefficient Second coefficient And so on. Some of the specific values ​​for the above parameters are set based on empirical or experimental values, while others are calculated using formulas. For example, it is possible to set... t max Set the value to 100, Agents to 30, and b to 1.

[0049] For combinations of multiple parameters, they are treated as several individuals in the whale algorithm, and assigned corresponding values. T PT_off [ i ].

[0050] When the output voltage U o Achieve target output voltage U o_ref At that time, the whale algorithm module begins to run. From the start to the end of the iteration... T PT_off [ i It should be temporarily set to a larger set value to ensure that the inductor current can trigger ZCD by crossing zero.

[0051] When t≤ t maxAt that time, the actual peak current value in n ePWM cycles is collected sequentially. i pk_real And calculate different individuals T PT_off [ i Individual fitness value fitness [ i Because peak current is significantly affected by input voltage, it cannot be sampled over a wide input voltage range. The sampling interval for peak current should be limited to (…). U in_max - Δu , U in_max - Δ u Voltage offset range Δu When it is smaller, ( U o - U in ) / Z n Its changes are relatively small. Z n Characteristic impedance. Individual fitness. fitness [ i [Only subject to] T PT_off [ i The influence of size. After calculating the fitness value of each individual, find the individual with the minimum fitness value and use it as the optimal fit individual for the current iteration. Then generate random numbers. p Update the first coefficient A Second coefficient C Among them, random numbers p Random numbers generated for each newly generated optimally adapted individual in each round p Its value ranges from [0,1].

[0052] according to p and | A The value of | is used to select the corresponding update rule to update the population. T PT_off [Agents], The next iteration begins only after the population update is completed, until the maximum number of iterations is reached. t max This allows us to find the optimal shutdown delay as the shutdown delay time output.

[0053] In one embodiment, step S22, the process of generating the fitness value, includes: ; In the formula, For the first Each fitness value; This represents the actual peak current. The desired peak current; The number of samples.

[0054] In one embodiment, step S23, the method for updating the first coefficient and the second coefficient includes: ; In the formula, The first coefficient; The second coefficient; r 1 and r 2 is a random parameter in the range [0,1]. a It is a parameter that decreases linearly from 2 to 0 and is used as a distance control factor; This represents the maximum number of iterations. This represents the current iteration number.

[0055] In one embodiment, in step S24, the update rule includes a first update rule, which is to update the population using the following method when the random number is greater than 0.5: ; In the formula, For the updated shutdown delay individual; This refers to the individual whose shutdown was delayed before the update. The best-fit individual before the update; The distance between the deactivation-delayed individual and the optimally fit individual before the update is calculated as follows: D 2=| X * ( t )-X( t )|; It is an empirical constant. The step size.

[0056] In one embodiment, in step S24, the update rule includes a second update rule, which is to update the population using the following method when the random number is less than 0.5 and the absolute value of the first coefficient is less than 1:

[0057] In the formula, For the updated shutdown delay individual; This refers to the individual whose shutdown was delayed before the update. A randomly selected individual from the population before the update to delay the shutdown process; The first coefficient; The second coefficient; This is the search step size.

[0058] In one embodiment, in step S24, the update rule includes a third update rule, which is to update the population using the following method when the random number is less than 0.5 and the absolute value of the first coefficient is greater than 1: ; In the formula, For the updated shutdown delay individual; This refers to the individual whose shutdown was delayed before the update. For individuals whose shutdown was delayed before the update; The first coefficient; The second coefficient; To enclose the step size.

[0059] By setting the update rules described above, better control over the search direction can be achieved.

[0060] In one embodiment, such as Figure 9 As shown, step S3 includes: step S31: determining the initial conduction time, diode freewheeling time, additional conduction time, and initial turn-off time based on the target current; step S32: determining the final conduction time based on the diode freewheeling time, initial conduction time, and turn-off delay time, and determining the final turn-off time based on the initial turn-off time, additional conduction time, and turn-off delay time; step S33: performing control based on the final conduction time and final turn-off time.

[0061] Specifically, after iterating over the turn-off delay time, the output voltage is... U o The sample is detected by hardware circuitry, and after passing through a notch filter, it is compared with the target output voltage. U o_ref Subtraction, error voltage U err The input signal is fed into the PI control module to obtain the output signal. The output signal is then passed through the limiting module and multiplied by the unit sine wave signal output from the PLL phase-locked loop module to obtain the target current.i ref .because i ref ≈ i off / 2, i off Given the inductor current during the first stage mentioned above, the initial conduction time can be obtained. T on_c freewheeling time of the combined diode T RV Initial turn-off time of synchronous switch T off_c Additional conduction time T R and the first dead zone time T r1 Second Dead Zone Time T r2 . T on_c add T RV Subtract the shutdown delay time T PT_off Obtain the final on-time of the active switch. T on , T off_c add T R Subtract the shutdown delay time T PT_off Obtain the final turn-off time of the active switch. T off Finally, the PWM control signals corresponding to the first to fourth switching transistors are obtained by using the pre-configured ePWM algorithm inside the controller.

[0062] A storage medium includes computer instructions that, when executed by a computer device, perform the control method described above.

[0063] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A control method for a totem-pole PFC converter, characterized in that, A controller applicable to a totem-pole PFC converter, the control method comprising: step S1: controlling the operation of the totem-pole PFC converter based on a triangular current mode and obtaining the actual peak current; step S2: dynamically searching and locking the turn-off delay time during operation based on the actual peak current using a whale optimization algorithm; step S3: correcting the PWM control signal of the totem-pole PFC converter based on the turn-off delay time.

2. The control method according to claim 1, characterized in that, Step S1 includes: Step S11: Initialize the control parameters and generate a modulated PWM signal corresponding to the totem-pole PFC converter using the initialized control parameters; Step S12: Perform conduction control on the totem-pole PFC converter based on the modulated PWM signal and acquire the output voltage; Step S13: Determine whether the output voltage is stable within the target voltage range; if yes, proceed to step S14; if no, return to step S12 to generate a new modulated PWM signal; Step S14: Measure the actual peak current.

3. The control method according to claim 1, characterized in that, Step S2 includes: Step S21: Setting multiple shutdown delay individuals and initializing their parameters; Step S22: Calculating the fitness value of each shutdown delay individual based on the actual peak current; Step S23: Filtering the optimal adapted individual with the smallest fitness based on the fitness value, and generating random numbers and updating the first and second coefficients; Step S24: Updating the population of shutdown delay individuals according to the update rule matched by the random numbers and the first coefficients; Step S25: Determining whether the iteration condition is met; if yes, outputting the optimal adapted individual of the last round as the shutdown delay time; if no, returning to step S22.

4. The control method according to claim 3, characterized in that, In step S22, the process of generating the fitness value includes: ； In the formula, For the first The fitness values ​​mentioned above; This refers to the actual peak current; The desired peak current; The number of samples.

5. The control method according to claim 3, characterized in that, In step S23, the method for updating the first coefficient and the second coefficient includes: ； In the formula, The first coefficient; This is the second coefficient; r1 and r2 are random parameters in the range [0,1]. 'a' is a parameter that decreases linearly from 2 to 0 and is used as a distance control factor. This represents the maximum number of iterations. This represents the current iteration number.

6. The control method according to claim 3, characterized in that, In step S24, the update rule includes a first update rule, which is to update the population when the random number is greater than 0.5 using the following method: ； In the formula, For the updated shutdown delay individual; For the corresponding individuals whose shutdown was delayed before the update; The optimal fit individual before the update; The distance between the previously delayed shutdown individual and the optimally fit individual is calculated as D2 = |X|. * (t)-X(t)|; It is an empirical constant. The step size.

7. The control method according to claim 3, characterized in that, In step S24, the update rule includes a second update rule, which is to update the population when the random number is less than 0.5 and the absolute value of the first coefficient is less than 1, using the following method: ； In the formula, For the updated shutdown delay individual; For the corresponding individuals whose shutdown was delayed before the update; The shutdown delay individual is randomly selected from the population before the update; The first coefficient; This is the second coefficient; This is the search step size.

8. The control method according to claim 3, characterized in that, In step S24, the update rule includes a third update rule, which is to update the population using the following method when the random number is less than 0.5 and the absolute value of the first coefficient is greater than 1: ； In the formula, For the updated shutdown delay individual; For the corresponding individuals whose shutdown was delayed before the update; For the previously mentioned shutdown delay individuals; The first coefficient; This is the second coefficient; To enclose the step size.

9. The control method according to claim 1, characterized in that, Step S3 includes: Step S31: Determine the initial turn-on time, diode freewheeling time, additional turn-on time, and initial turn-off time based on the target current; Step S32: Determine the final turn-on time based on the diode freewheeling time, the initial turn-on time, and the turn-off delay time, and determine the final turn-off time based on the initial turn-off time, the additional turn-on time, and the turn-off delay time; Step S33: Perform control based on the final turn-on time and the final turn-off time.

10. A storage medium comprising computer instructions, characterized in that, When the computer device executes the computer instructions, it performs the control method as described in any one of claims 1-9.

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