Switching converter system and control circuit

Abstract

This disclosure relates to a system (1400) comprising an input voltage node (1442) configured to provide an input voltage (VIN). The system (1400) also includes a load (R). LOAD A switching converter (1450, 1460) coupled between the input voltage node (1442) and the load (RLOAD). The switching converter (1450, 1460) is configured to provide an output voltage (VOUT) to the load (RLOAD) based on the input voltage (VIN). LOAD The switching converters (1450, 1460) include a gate driver circuitry (1430) and a current-mode control circuitry (1470) coupled to the gate driver circuitry (1430). The current-mode control circuitry (1470) is configured to output control signals to the gate driver circuitry (1430) according to different operating modes, wherein the current-mode control circuitry (1470) is configured to adjust a threshold (I) for switching between discontinuous conduction mode (DCM) and power-saving mode (PSM). PSM *).

Description

Background Technology

[0001] The proliferation of consumer electronics devices and integrated circuit (IC) technology has led to the commoditization of IC products. As new consumer electronics devices are developed and IC technology advances, new IC products are commercialized. One example of an IC product required in consumer electronics devices is the switching converter. Many types of switching converters and output voltage regulation strategies exist. In one example of a switching converter, current-mode control and different operating modes are used to regulate the output voltage to improve the switching converter efficiency under different load conditions. Efforts are underway to further improve the efficiency of switching converters. Summary of the Invention

[0002] According to at least one embodiment of this disclosure, a system includes an input voltage node configured to provide an input voltage. The system also includes a load and a switching converter coupled between the input voltage node and the load. The switching converter is configured to provide an output voltage to the load based on the input voltage. The switching converter includes a gate driver circuitry and current-mode control circuitry coupled to the gate driver circuitry. The current-mode control circuitry is configured to output control signals to the gate driver circuitry according to different operating modes, wherein the current-mode control circuitry is configured to adjust a threshold for switching between discontinuous conduction mode (DCM) and power-saving mode (PSM).

[0003] According to at least one embodiment of this disclosure, a control circuit for a switching converter includes a gate driver circuit system and a current-mode control circuit coupled to the gate driver circuit system. The current-mode control circuit includes an operational amplifier having a reference voltage input and a feedback voltage input. The current-mode control circuit also includes a voltage-to-current converter coupled to the output of the operational amplifier. The current-mode control circuit also includes a clamping circuit coupled to the output of the voltage-to-current converter. The current-mode control circuit also includes a bias circuit coupled to the clamping circuit to provide a lower clamping value, wherein the lower clamping value is adjustable based on the input voltage and output voltage of the switching converter.

[0004] According to at least one embodiment of this disclosure, a switching converter circuit includes a gate driver circuit system and a current-mode control circuit coupled to the gate driver circuit system. The current-mode control circuit is configured to output control signals to the gate driver circuit system according to different operating modes, wherein the current-mode control circuit is configured to adjust a threshold for switching between DCM and PSM. The current-mode control circuit includes a bias circuit configured to adjust the threshold based on the input voltage and the output voltage. The current-mode control circuit also includes a clamping circuit coupled to the bias circuit, wherein the clamping circuit is configured to clamp the input signal at a lower clamping value based on the threshold. Attached Figure Description

[0005] For detailed descriptions of various examples, please refer to the accompanying drawings, in which:

[0006] Figure 1 It is a diagram of switching converters based on some examples;

[0007] Figure 2 It is a graph showing the ripple current as the input and output voltages of the converter change according to different examples;

[0008] Figure 3 This is based on some examples of adjustable power-saving mode thresholds (I PSM *) A schematic diagram of a switching converter that switches to and from Power Saving Mode (PSM);

[0009] Figure 4 It is based on some examples of providing buck converters I PSM A schematic diagram of the bias circuit for *;

[0010] Figure 5 This demonstrates, based on several examples, the ripple current and IT varying according to the input voltage of the buck converter. PSM *The curve graph;

[0011] Figure 6 It is based on some examples of providing boost converters I PSM A schematic diagram of the bias circuit for *;

[0012] Figure 7 This demonstrates, based on several examples, the ripple current and IT varying according to the input voltage of the boost converter. PSM *The curve graph;

[0013] Figure 8A It is based on some examples of providing buck / boost converters I PSM A schematic diagram of the bias circuit for *;

[0014] Figure 8B It is based on some examples for use Figure 8A A schematic diagram of the current source circuit of the bias circuit;

[0015] Figure 9 This demonstrates the ripple current and IT varying with the input voltage of the buck / boost converter, based on several examples. PSM *The curve graph;

[0016] Figure 10 It is based on some examples of providing boost converters I PSM *A schematic diagram of another bias circuit; and

[0017] Figure 11 This demonstrates, based on several examples, the ripple current and IT varying according to the input voltage of the boost converter. PSM *The curve graph;

[0018] Figures 12A to 12C It is to demonstrate, based on some examples, the presence and absence of I PSM Timing diagram of the mode transition of the converter in the case of *;

[0019] Figures 13A to 13C It is to demonstrate, based on some examples, the presence and absence of I PSM *Efficiency curves varying with load current under certain conditions; and

[0020] Figure 14 It is based on the use of I in some examples PSM A diagram of the system. Detailed Implementation

[0021] This document discloses a switching converter topology with an adjustable power-saving mode (PSM) threshold to adjust the transition to and from PSM. In some instances, an adjustable PSM threshold is used in a switching converter having a gate driver circuitry and current-mode control circuitry coupled to the gate driver circuitry. In some instances, the current-mode control circuitry is configured to output control signals to the gate driver circuitry according to different operating modes, wherein the current-mode control circuitry is configured to adjust a threshold (sometimes referred to herein as an adjustable PSM threshold or I) for switching between discontinuous conduction mode (DCM) and power-saving mode (PSM). PSM More specifically, in some instances, the current-mode control circuitry includes a bias circuit configured to adjust the threshold value based on the input and output voltages of the switching converter. The current-mode control circuitry also includes a clamping circuit coupled to the bias circuitry, wherein the clamping circuitry is configured to clamp the input signal at a lower clamping value based on the threshold value.

[0022] In some instances, the input signal to the clamping circuit is based on the output of a first operational amplifier in the current-mode control circuit, wherein the first operational amplifier is configured to compare a reference voltage with a feedback voltage proportional to the output voltage of the switching converter. In some instances, a voltage-to-current converter is used to convert the output of the operational amplifier into the input signal to the clamping circuit. The output of the clamping circuit is clamped at its maximum value based on an upper clamping threshold and at its minimum value based on an adjustable PWM threshold. The output of the clamping circuit is compared with the input voltage of the switching converter by a comparator in the current-mode control circuit. The comparator output, along with a turn-off (TOFF) signal, is used to generate control signals, such as pulse-width modulation (PWM) signals, for the gate driver circuitry. The gate driver circuitry uses the control signals to generate gate drive signals to the switching converter.

[0023] In various instances, adjustable PSM thresholds are used with switching converters corresponding to buck converters, boost converters, or buck / boost converters, which have current-mode control circuitry that uses peak or average current analysis for output voltage regulation. Furthermore, in some instances, the load at the output of the switching converter may be a USB power delivery adapter or a wireless charger. For better understanding, the various adjustable PSM threshold issues and related circuitry and systems are described using the following diagram.

[0024] Figure 1 This is a diagram based on some examples of switching converter 100. In Figure 1 In the middle, the switching converter 100 is a converter with a fixed PSM threshold (I PSM This is not an example of a buck converter with an adjustable PSM threshold. As shown, the switching converter 100 includes a high-side switch (S1) and a low-side switch (S2) between the input voltage (VIN) node 120 and the ground node 122. Between S1 and S2 is a switching node 116, which is coupled to an output inductor (LOUT) between the switching node 116 and the output node 118. Furthermore, an output capacitor (COUT) is coupled between the output node 118 and the ground node 122 to store charge and provide an output voltage (VOUT) at the output node 118. VOUT is available for use by a load (not shown).

[0025] To guide S1 and S2, the switching converter 100 includes various components, including voltage dividers (R1 and R2) configured to provide a feedback voltage (VFB) proportional to VOUT. As shown, VFB and a reference voltage (VREF) are inputs to operational amplifier 102, whose output is a function of VREF-VFB and is provided to voltage / current converter 104. Furthermore, a resistor (R3) and a capacitor (C1) are coupled between the output node 124 of operational amplifier 102 and ground, where R3 and C1 provide compensation to maintain loop stability. The output of voltage / current converter 104 is a current ramp clamped by clamping circuit 106, where I... PSM The lower clamping value of the clamping circuit 106 is controlled, and the upper clamping value of the clamping circuit 106 is controlled by a second threshold (ICLIM). The output from the clamping circuit 106 is a clamped version of the current ramp output from the voltage / current converter 104.

[0026] As shown, the output of clamping circuit 106 is input to comparator 108, which compares the clamping current from clamping circuit 106 with a current ramp (sensed along the VIN-S1 path) output from current sensing circuit 126. The output of comparator 108 is provided to control logic 112, which is configured to provide control signals to gate driver circuitry 114 based on the output of comparator 108 and a TOFF signal. The TOFF signal is provided by off-time circuitry 110.

[0027] exist Figure 1 In this example, the various components used to provide control signals to the gate driver circuitry 114 (e.g., R1, R2, operational amplifier 102, R3, C1, voltage / current converter 104, clamping circuit 106, comparator 108, turn-off time circuit 110, and control logic 112) are part of the current-mode control circuitry. PSM The conversion efficiency between PSM and another mode (e.g., DCM) is affected, resulting in unwanted power consumption, VOUT ripple and / or other problems.

[0028] Figure 2 Figure 200 shows the ripple current variation as the input and output voltages of the converter change according to different examples. In the example of Figure 200, VOUT is set to 10 V, and VIN varies. As shown, the ripple current varies depending on VIN, where VIN values ​​below 10 V correspond to a boost converter scenario, and VIN values ​​at 10 V or higher correspond to a buck converter scenario.

[0029] Figure 3It is based on some instances with adjustable PSM thresholds (I PSM *) A schematic diagram of a switching converter 300 for conversion to and from PSM. As shown, the switching converter 300 includes features for... Figure 1 The switching converter 100 represents many of the same components. Figure 3 Switching converter 300 and Figure 1 The difference between the switching converters 100 lies in the bias circuit 302 included in the switching converter 300, wherein the bias circuit 302 is configured to provide I PSM *To clamping circuit 106. With I PSM * The conversion efficiency between PSM and another mode (e.g., DCM) of the switching converter 300 is compared to that of the switching converter 100 (which uses a fixed I0). PSM Improvements that result in improved power consumption, reduced VOUT ripple, and / or other improvements.

[0030] Figure 4 It is based on some examples of providing buck converters I PSM *The bias circuit 400 (for example, Figure 3 A schematic diagram of the bias circuit 402 is shown. As shown, the bias circuit 400 includes a voltage supply node 420 and a first current source 402 coupled to the voltage supply node 420. The bias circuit 400 also includes a first transistor (Q1) having a first current terminal coupled to the first current source 402 and a second current terminal coupled to a ground node 422. The bias circuit 400 also includes a second current source 404 coupled to the voltage supply node 420. The bias circuit 400 also includes a second transistor (Q2) having a first current terminal coupled to the second current source 404 and a second current terminal coupled to both a first current terminal of Q1 and a control terminal, wherein the control terminal of Q2 is coupled to the first current terminal of Q2. The bias circuit 400 also includes a third current source 406 coupled between the second current terminal of Q2 and the ground node 422.

[0031] exist Figure 4In this example, the bias circuit 400 also includes a third transistor (Q3) having a first current terminal coupled to the voltage supply node 420, a control terminal coupled to the control terminal of Q2, and a second current terminal. The bias circuit 400 also includes a fourth current source 408 coupled between the second current terminal of Q3 and the ground node 422. The bias circuit 400 also includes a fourth transistor (Q4) having a first current terminal, a control terminal coupled to the second current terminal of Q3, and a second current terminal coupled to the ground node 422. The bias circuit also includes a current mirror (composed of...) coupled to the first current terminal of Q4. Figure 4 MP1 and MP2 are formed in the middle), where the output of the current mirror is I. PSM * In some instances, Q1 through Q4 are bipolar junction transistors (BJTs), and MP1 and MP2 are PMOS transistors, such as... Figure 4 The Chinese side indicated that...

[0032] In operation, the bias circuit 400 is configured to be based on the switching converter (e.g., Figure 3 VIN and VOUT adjustment of the switching converter 300 PSM More specifically, when the first current (I1 = VIN / R - VOUT / R) from current source 402 is injected into the collector terminal of Q1, Q1 then generates a base-emitter voltage (VBE1) at node 410 that is approximately equal to VT*ln(I1 / ISAT), where VT is the thermal voltage of the BJT and ISAT is the saturation current of the BJT. When the second current (I2 = VOUT / R) from current source 404 is injected into the collector terminal of Q2, Q2 then generates a base-emitter voltage (VBE2) that is equal to VT*ln(I2 / ISAT). Therefore, the voltage at node 411 is approximately equal to VBE1 + VBE2, which is approximately equal to VT*[ln(I1*I2) / ISAT / ISAT]. When the third current (I3 = VIN / R) is injected into the collector terminal of Q3 by current source 408, Q3 then generates a base-emitter voltage (VBE3) equal to VT*ln(I3 / ISAT). This produces a voltage at node 412 approximately equal to VBE1 + VBE2 - VBE3, which is approximately equal to VT*ln(I1*I2 / I3 / ISAT). The base-emitter voltage of Q4 is VBE4, which is equal to the voltage present at node 412. The collector current of Q4 is determined based on VBE4, such that the collector current of Q4 is approximately equal to ISAT*exp(VBE4 / VT), which is equal to I1*I2 / I3. The collector current of Q4 is used as I with a ratio of 0.75*T*R / L. PSM *The mirror image is projected onto the drain of MP2. Therefore, I PSM* equals VAR*T*R / L*I1*I2 / I3, which is 0.75*T / L*VOUT*(VIN-VOUT) / VIN, where T is the switching converter (e.g., Figure 3 The switching period of the switching converter 300 is given by T, where L is the inductance of the switching converter's LOUT, and VAR is the variance ratio of T and L. In other words, the bias circuit 400 is configured to provide I... PSM *for , where K is a scaling factor (e.g., based on T, L, and the variance of T and L).

[0033] Figure 5 This demonstrates the ripple current and I based on the VIN of the buck converter, according to some examples. PSM *The curve 500. In curve 500, the ripple current (I) RP _CALC) and I PSM *(I PSM *_CALC) represents an expression that increases with VIN, where IRP_CALC is higher than I. PSM *_CALC.

[0034] Figure 6 It is based on some examples of providing boost converters I PSM A schematic diagram of the bias circuit 600 is shown. Figure 6 The bias circuit 600 is similar to Figure 4 The bias circuit 400, except Figure 6 The current sources 602, 604, 606, and 608 in the system provide compared to Figure 4 In addition to the different currents provided by similarly positioned current sources 402, 404, 406, and 408, current source 602 is coupled to voltage supply node 620 and provides a first current (I1 = VOUT / R – VIN / R). Current source 604 is also coupled to voltage supply node 620 and provides a second current (I2 = VIN / R). Current source 606 is coupled between Q2 and ground node 422 and provides a third current (I3 = 2*VIN / R). Current source 608 is coupled between Q3 and ground node 622 and provides a fourth current (I4 = VOUT / R). With the bias circuit 600, The calculation is as follows:

[0035] ,

[0036] Where T is the switching converter (e.g., Figure 3The switching period of the switching converter 300 is given by T, L is the inductance of the switching converter's LOUT, R is a predetermined resistance value (to generate suitable I1 to I3 and ensure that Q1 to Q4 operate in the appropriate region), and VAR is the variance ratio of T and L. In other words, the bias circuit 600 is configured to provide I... PSM *for:

[0037] I PSM * = ,

[0038] Where K is a scaling factor (e.g., based on T, L, and VAR).

[0039] Figure 7 This demonstrates, based on several examples, the ripple current and IT varying according to the input voltage of the boost converter. PSM *The curve 700. In curve 700, the ripple current waveform (I) RP _CALC) and I PSM *Waveform(I) PSM *_CALC) represents an initial value that increases with VIN, then decreases, where IRP_CALC is higher than I... PSM *_CALC.

[0040] Figure 8A It is based on some examples of providing buck / boost converters I PSM A schematic diagram of the bias circuit for * is shown. Figure 8A The bias circuit 800 is similar to Figure 4 The bias circuit 400, except Figure 8A The current sources 802, 804, 806, and 808 provide compared to Figure 4 In addition to the different currents provided by similarly positioned current sources 402, 404, 406, and 408, more specifically, current source 802 is coupled to voltage supply node 820 and provides a first current (I1 = VMAX / R – VMIN / R). Current source 804 is also coupled to voltage supply node 820 and provides a second current (I2 = VMIN / R). Current source 806 is coupled between Q2 and ground node 822 and provides a third current (I3 = 2*VMIN / R). Current source 808 is coupled between Q3 and ground node 822 and provides a fourth current (I4 = VMAX / R). With the bias circuit 800, The calculation is as follows:

[0041]

[0042] Where T is the switching converter (e.g., Figure 3The switching period of the switching converter 300 is given by T, L is the inductance of the switching converter's LOUT, R is a predetermined resistance value (to generate suitable I1 to I3 and ensure that Q1 to Q4 operate in the appropriate region), and VAR is the variance ratio of T and L. In other words, the bias circuit 600 is configured to provide I... PSM *for:

[0043] I PSM * = ,

[0044] Where VMIN is the minimum value of VIN and VOUT, VMAX is the maximum value of VIN and VOUT, and K is a scaling factor (e.g., based on T, L, and VAR).

[0045] Figure 8B It is based on some examples for use Figure 8A A schematic diagram of the current source circuit 830 of the bias circuit 800 is shown. As shown, the current source circuit 830 includes a comparator 832 configured to compare VOUT and VIN. The output of the comparator 832 controls switches (S3 and S4) in an alternating manner (e.g., using an inverter 834 to invert the signal output from the comparator 832). With the current source circuit 830, when VOUT is higher than VIN, the current value (VOUT / R) output from the current source 836 is VMAX / R. Furthermore, when VOUT is higher than VIN, the current value (VIN / R) output from the current source 838 is VMIN / R. On the other hand, when VOUT is less than VIN, the VOUT / R output from the current source 836 is VMIN / R. Furthermore, when VOUT is less than VIN, the VIN / R output from the current source 838 is VMAX / R. Next, by... Figure 8B The MAX / R and VMIN / R values ​​output by the current source circuit 830 in Figure 8 can be used in the bias circuit 800 in Figure 8.

[0046] Figure 9 This demonstrates the ripple current and IT varying with the input voltage of the buck / boost converter, based on several examples. PSM *The curve 900. In curve 900, the ripple current waveform (I) RP _CALC) and I PSM *Waveform(I) PSM *_CALC) indicates that it initially increases with VIN, then decreases during the boost scenario until it reaches its minimum at VIN = VOUT. As VIN continues to increase, I... RP _CALC and I PSM *_CALC increases during buck scenarios, where IRP_CALC is higher than I PSM *_CALC.

[0047] Figure 10 It is based on some examples of providing boost converters I PSM A schematic diagram of another bias circuit 1000. As shown, bias circuit 1000 includes... Figure 4 The Q1 to Q4 and current sources 402, 404, 406 and 408 in the circuit have the same arrangement. The bias circuit 1000 also includes... Figure 4 The voltage supply node 420 and grounding node 422 have the same arrangement as the voltage supply node 1020 and grounding node 1022. Figure 10 In the bias circuit 1000, a bias current (IB) and NMOS devices (MN1, MN2, MN3) are added, where IB is provided by current sources 1010A to 1010C. Figure 10 The arrangement of IB and MN1 to MN3 is used to compensate for the base current.

[0048] Figure 11 This demonstrates the ripple current and I based on the VIN of the buck converter, according to some examples. PSM *The curve 1100. In curve 1100, the ripple current (I RP _CALC) and I PSM *(I PSM *_CALC) represents an expression that increases with VIN, where IRP_CALC is higher than I. PSM *_CALC.

[0049] Figures 12A to 12C It is to demonstrate, based on some examples, the presence and absence of I PSM Timing diagrams 1200, 1210, and 1220 for the mode transition of the switching converter under the condition of *. In Figure 12A In timing diagram 1200, VOUT is adjusted to 5V. Figure 12B In timing diagram 1210, VOUT is adjusted to 9 V. Figure 12C In timing diagram 1220, VOUT is adjusted to 12 V. Figures 12A to 12C In the timing diagrams 1200, 1210, and 1220, VOUT ripple is represented, where VOUT ripple corresponds to the peak-to-peak VOUT in different modes (e.g., PSM, DCM, CCM).

[0050] exist Figures 12A to 12C In the examples, the variance of VOUT in PSM and DCM depends on the PSM control method. However, it should be understood that, with some PSM control methods, VOUT can remain the same in PSM and DCM. Figure 12ATiming diagram 1200 and Figure 13A In the curve graph 1300, when using I PSM *Instead of fixing I PSM At this time, for VOUT=5 V, in PSM, the VOUT ripple is smaller, and the efficiency is slightly lower. Figure 12B Timing diagram 1210 and Figure 13B In Figure 1310, when using I PSM *Instead of fixing I PSM At that time, for VOUT=9 V, in PSM, the VOUT ripple is slightly larger, but the efficiency is higher. Figure 12C Timing diagram 1220 and Figure 13C In graph 1320, when using I PSM *Instead of fixing I PSM At this time, for VOUT=12 V, in PSM, VOUT ripple is slightly larger, but efficiency is higher.

[0051] Figure 14 It is based on the use of I in some examples PSM A diagram of system 1400 is shown. As illustrated, system 1400 includes a switching converter circuit system 1450 and control circuitry 1460 for one or more power switches (e.g., S1 or S2) for switching the switching converter circuit system 1450. Figure 14 In one example, the switching converter circuit system 1450 corresponds to a buck converter topology, where S1 is the high-side switch and S2 is the low-side switch. The switching converter circuit 1450 also includes an output inductor (LOUT) and an output capacitor (COUT). In other examples, the switching converter circuit system 350 may have a boost converter topology, a buck / boost converter topology, or another switching converter topology.

[0052] As shown, S1 and S2 are coupled between battery 1440 (at VIN node 1442) or other power supply configured to provide VIN and ground node 1456. Furthermore, the first terminal of LOUT is coupled to switching node 1452 between S1 and S2. Furthermore, the second terminal of LOUT is coupled to output node 1454. Furthermore, COUT and the load (RLOAD) are coupled in parallel between output node 1454 and ground node 1456. In the first stage (S1 on, S2 off) of the switching converter circuit system 1450, the inductor current (IL) ramps up. In the second stage (S1 off, S2 on), IL ramps down. The timing of the first and second stages is controlled by control circuitry 1460 to regulate VOUT at output node 1454. When VIN supplied by battery 1440 decreases and / or changes with load, control circuit 1460 adjusts the timing of the first and second stages to account for the changes (e.g., by increasing or decreasing the amount of time in the first stage which is subject to certain limitations, such as minimum shutdown time).

[0053] exist Figure 14 In this example, the timing of the first and second stages is based on a current-mode control circuit 1470, which includes... Figure 1 and 3 The various components described herein include those that provide I PSM The bias circuit 302, as described herein, corresponds to the bias circuit 302 in different instances. Figure 4 The bias circuit 400 in the middle Figure 6 The bias circuit 600 in Figure 6, the bias circuit 800 in Figure 8 or Figure 10 The bias circuit in the middle is 1000. With I PSM The current-mode control circuit 1470 adjusts the transition between PSM and DCM, which vary according to VIN and VOUT. The output of the current-mode control circuit 1470 is an on signal (S_ON) provided to the gate driver circuit system 1430, which is configured to provide a high-side drive signal (HG) to S1 and a low-side drive signal (LG) to S2.

[0054] In some instances, the gate driver circuitry 1430 includes a latch 1432 coupled to a driver circuitry 1434. For example, the Q and QN outputs of latch 1432 may be provided to the driver circuitry 1434, which is configured to provide sufficient current to drive S1 and S2. Therefore, when latch 1432 receives S_ON, the gate driver circuitry 1430 directs the switching converter circuitry 1450 to phase 2 (S1 off, S2 on). In some instances, latch 1432 is an SR latch with a set (S) input node and a reset (R) input node, wherein the R input node is configured to receive a turn-off time signal (SHOT) from the on-time timer circuitry 1410.

[0055] In some instances, the system (e.g., Figure 4 The system 1400 in the system includes nodes configured to provide the input voltage VIN (e.g., Figure 14 The system also includes a load (RLOAD) with a variable VOUT range (e.g., 0.8 V to 36 V). In some instances, the RLOAD corresponds to a USB power delivery adapter. In other instances, the RLOAD corresponds to a wireless charger. The system also includes a switching converter coupled between the input voltage node and the load (e.g., ...). Figure 14 The switching converter circuitry 1450 and control circuitry 1460 are configured to provide VOUT to the load based on VIN. The switching converter includes a gate driver circuitry (e.g., Figure 14 The gate driver circuit system 1430 in the middle) and the current mode control circuit coupled to the gate driver circuit system (e.g., Figure 14 The current-mode control circuit 1470 is configured to output control signals (e.g., according to different operating modes, such as CCM, DCM, and PSM, as described herein) based on different operating modes. Figure 14 The S_ON in the diagram is connected to the gate driver circuitry, where the current-mode control circuitry is configured to adjust the threshold (e.g., I_ON in this paper) used for switching between DCM and PSM. PSM *).

[0056] In some instances, the current-mode control circuit 1470 includes a bias circuit (e.g., Figure 3 and 14 The bias circuit 302 in the middle Figure 4 The bias circuit 400 in the middle Figure 6 The bias circuit 600 in Figure 8, the bias circuit 800 in Figure 8, Figure 10The bias circuit 1000 is configured to adjust threshold values ​​based on VIN and VOUT. The current-mode control circuit 1470 also includes clamping circuitry coupled to the bias circuitry (e.g., ...). Figure 3 and 14 The clamping circuit 106 is configured to clamp the input signal at a lower clamping value based on the threshold.

[0057] In some instances, current-mode control circuits also include voltage / current converters (e.g., Figure 3 and 14 The voltage / current converter 104 is coupled to and configured to provide an input signal to the clamping circuit. In some instances, the current-mode control circuit also includes an operational amplifier (e.g., [missing information]) coupled to the voltage / current converter. Figure 3 and 14 The operational amplifier 102 is provided to a voltage-to-current converter, and the output of the operational amplifier is based on a comparison of a reference voltage (VREF) with a feedback voltage (VFB) proportional to the output voltage.

[0058] In some instances, current-mode control circuits also include comparators (e.g., Figure 3 and 14 The comparator 108 in the circuit has: a first input coupled to the output of the clamping circuit; and a second input coupled to a current sensing circuit coupled to the VIN-S1 path (the path from voltage supply node 120 to the high-side switch). In some instances, the current-mode control circuit also includes a turn-off time circuit configured to provide a turn-off signal (TOFF). Figure 3 and 14 The off-time circuit 110 in the circuit. In some instances, the current-mode control circuit also includes control logic coupled to the output of the comparator and the off-time circuit (e.g., Figure 3 and 14 The control logic 112 in the system is coupled to the gate driver circuit system.

[0059] In some instances, the switching converter is a buck converter, where the current-mode control circuitry is configured to adjust a threshold based on the following:

[0060] ,

[0061] Where VOUT is the output voltage, VIN is the input voltage, and K is the scaling factor. In some instances, the switching converter is a boost converter, where the current-mode control circuitry is configured to adjust thresholds based on the following:

[0062] ,

[0063] Where VOUT is the output voltage, VIN is the input voltage, and K is the scaling factor. In some instances, the switching converter is a buck / boost converter, where the current-mode control circuitry is configured to adjust thresholds based on the following:

[0064] ,

[0065] Where VMIN is the minimum value of the input voltage and the output voltage, VMAX is the maximum value of the input voltage and the output voltage, and K is the scaling factor.

[0066] In some instances, the bias circuit includes a voltage supply node (e.g., Figure 4 , 6 Voltage supply nodes 420, 620, 820, or 1020 in 8 and 10), and a first current source coupled to the voltage supply node (e.g., Figure 4 , 6 The current sources 402, 602, 802, or 1002 in 8 and 10). The bias circuit also includes a first transistor (e.g., Figure 4 , 6 Q1 in 8 and 10), the first transistor has a first current terminal coupled to a first current source and has a ground node coupled to a ground node (e.g., Figure 4 , 6 The second current terminal of the grounding nodes 422, 622, 822, or 1022 in 8 and 10. The bias circuit also includes a second current source coupled to the voltage supply node (e.g., Figure 4 , 6 The current sources 404, 604, 804, or 1004 in 8 and 10. The bias circuit also includes a second transistor (e.g., Figure 4 , 6 The second transistor (Q2 in 8 and 10) has a first current terminal coupled to a second current source and a second current terminal coupled to a first current terminal of the first transistor and a control terminal, wherein the control terminal of the second transistor is coupled to the first current terminal of the second transistor. The bias circuit also includes a third current source (e.g., Q2 in 8 and 10) coupled between the second current terminal of Q2 and ground node 422. Figure 4 , 6 Current sources 406, 606, 806, or 1006 in 8 and 10.

[0067] In some instances, the bias circuit also includes a third transistor (e.g., Figure 4 , 6The third transistor (Q3 in 8 and 10) has a first current terminal coupled to the voltage supply node, a control terminal coupled to the control terminal of the second transistor, and a second current terminal. The bias circuit also includes a fourth current source (e.g., Q3 in 8 and 10) coupled between the second current terminal of the third transistor and the ground node. Figure 4 , 6 The current sources 408, 608, 808, or 1008 in 8 and 10. The bias circuit 400 also includes a fourth transistor (e.g., Figure 4 , 6 The fourth transistor (Q4 in 8 and 10) has a first current terminal, a control terminal coupled to the second current terminal of the third transistor, and a second current terminal coupled to a ground node. The bias circuit also includes a current mirror (e.g., from...) coupled to the first current terminal of the fourth transistor. Figure 4 , 6 (Formed by MP1 and MP2 in 8 or 10), where the output of the current mirror is I. PSM * In some instances, the first, second, third, and fourth transistors are BJTs. Furthermore, in some instances, the current mirror is formed by a PMOS transistor, such as... Figure 4 , 6 The numbers 8 and 10 indicate this.

[0068] In the proposed example, an adjustable PSM threshold (I0) is used to track the ripple current for different VIN and VOUT values. PSM * is used to control the transition between PSM and DCM. This allows for a good trade-off between VOUT ripple and efficiency for switching converters with a wide range of VIN and VOUT. The proposed solution is suitable for all current-mode DC / DC converters (e.g., peak current-mode converters, average current-mode converters, buck converters, boost converters, and buck / boost converters).

[0069] Certain terms have been used throughout the description and claims to refer to specific system components. Those skilled in the art will understand that different parties may refer to components by different names. This document does not intend to distinguish components that differ only in name and not in their respective functions or structures. In this disclosure and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be construed as meaning "including but not limited to...".

[0070] The term "coupling" is used throughout this disclosure. This term may encompass connections, communications, or signal paths that achieve a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B via a direct connection, or in a second instance, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not alter the functional relationship between device A and device B such that device B is controlled by device A via control signals generated by device A.

[0071] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once fully understanding the above disclosure, those skilled in the art will become aware of many variations and modifications.

Claims

1. A switching converter system, comprising: Input voltage node; Output node; A switching converter coupled between the input voltage node and the output node, wherein the switching converter is configured to provide an output voltage to the output node based on an input voltage at the input voltage node, and wherein the switching converter includes: Gate driver circuitry; and A current-mode control circuit coupled to the gate driver circuitry and configured to output control signals to the gate driver circuitry according to different operating modes, wherein the current-mode control circuit is configured to adjust a threshold for switching between discontinuous conduction mode (DCM) and power-saving mode (PSM), the current-mode control circuit including a bias circuit configured to adjust the threshold based on the input voltage and the output voltage; and a clamping circuit coupled to the bias circuit, wherein the clamping circuit is configured to clamp the input signal at a lower clamping value based on the threshold.

2. The switching converter system according to claim 1, wherein the current-mode control circuit comprises: A voltage / current converter coupled to the clamping circuit and configured to provide the input signal to the clamping circuit; and An operational amplifier coupled to a voltage / current converter, wherein the output of the operational amplifier is provided to the voltage / current converter, and wherein the output of the operational amplifier is based on a comparison of a reference voltage with a feedback voltage proportional to the output voltage.

3. The switching converter system according to claim 2, wherein the current-mode control circuit further comprises: A comparator has the following characteristics: The first input is coupled to the output of the clamping circuit; and The second input is coupled to a current sensing circuit configured to sense current along the path from the input voltage node to the high-side switch of the switching converter. A turn-off time circuit configured to provide a turn-off signal; and Control logic coupled to the output of the comparator and the off-time circuit, wherein the output of the control logic is coupled to the gate driver circuit system.

4. The switching converter system of claim 1, wherein the switching converter is a buck converter, and wherein the current-mode control circuit is configured to adjust the threshold based on the following: ， Where VOUT is the output voltage, VIN is the input voltage, and K is the scaling factor.

5. The switching converter system of claim 1, wherein the switching converter is a boost converter, and wherein the current-mode control circuit is configured to adjust the threshold based on the following: ， Where VOUT is the output voltage, VIN is the input voltage, and K is the scaling factor.

6. The switching converter system of claim 1, wherein the switching converter is a buck / boost converter, and wherein the current-mode control circuit is configured to adjust the threshold based on the following: ， Where VMIN is the minimum value of the input voltage and the output voltage, VMAX is the maximum value of the input voltage and the output voltage, and K is a scaling factor.

7. The switching converter system according to claim 1, wherein the bias circuit comprises: Voltage supply node; A first current source, which is coupled to the voltage supply node; The first transistor has a first current terminal coupled to the first current source and a second current terminal coupled to a ground node. A second current source is coupled to the voltage supply node; The second transistor has a first current terminal coupled to the second current source and a second current terminal coupled to the first current terminal and a control terminal of the first transistor, wherein the control terminal of the second transistor is coupled to the first current terminal of the second transistor. and A third current source is coupled between the second current terminal of the second transistor and the ground node.

8. The switching converter system of claim 7, wherein the bias circuit further comprises: The third transistor has a first current terminal coupled to the voltage supply node, a control terminal coupled to the control terminal of the second transistor, and a second current terminal; A fourth current source is coupled between the second current terminal of the third transistor and the ground node; The fourth transistor has a first current terminal, a control terminal coupled to the second current terminal of the third transistor, and a second current terminal coupled to the ground node; and A current mirror coupled to the first current terminal of the fourth transistor, wherein the output of the current mirror is the threshold.

9. The switching converter system of claim 1, further comprising a load coupled to the output node, wherein the load comprises a USB power delivery adapter.

10. The switching converter system of claim 1, further comprising a load coupled to the output node, wherein the load comprises a wireless charger.

11. A control circuit for switching converters, the control circuit comprising: Gate driver circuit system; and A current-mode control circuit coupled to the gate driver circuit system, wherein the current-mode control circuit includes: An operational amplifier that has a reference voltage input and a feedback voltage input; A voltage-to-current converter coupled to the output of the operational amplifier; A clamping circuit coupled to the output of the voltage / current converter; A bias circuit coupled to the clamping circuit to provide a lower clamping value, wherein the lower clamping value can be adjusted according to the input voltage and output voltage of the switching converter.

12. The control circuit according to claim 11, wherein the current-mode control circuit further comprises: A comparator has the following characteristics: The first input is coupled to the output of the clamping circuit; and The second input is coupled to the current ramp sensed from the input voltage node to the high-side switching path of the switching converter; and Control logic coupled to the output of the comparator and the off-time circuit, wherein the output of the control logic is coupled to the gate driver circuit system.

13. The control circuit according to claim 11, wherein the bias circuit comprises: Voltage supply node; A first current source, which is coupled to the voltage supply node; The first transistor has a first current terminal coupled to the first current source and a second current terminal coupled to a ground node. A second current source is coupled to the voltage supply node; The second transistor has a first current terminal coupled to the second current source and a second current terminal coupled to the first current terminal and a control terminal of the first transistor, wherein the control terminal of the second transistor is coupled to the first current terminal of the second transistor. and A third current source is coupled between the second current terminal of the second transistor and the ground node.

14. The control circuit according to claim 13, wherein the bias circuit further comprises: The third transistor has a first current terminal coupled to the voltage supply node, a control terminal coupled to the control terminal of the second transistor, and a second current terminal; A fourth current source is coupled between the second current terminal of the third transistor and the ground node; The fourth transistor has a first current terminal, a control terminal coupled to the second current terminal of the third transistor, and a second current terminal coupled to the ground node; and A current mirror coupled to the first current terminal of the fourth transistor, wherein the output of the current mirror is the lower clamping value.

15. A switching converter, comprising: Gate driver circuit system; and A current-mode control circuit coupled to the gate driver circuit system and configured to output control signals to the gate driver circuit system according to different operating modes, wherein the current-mode control circuit is configured to adjust a threshold for switching between discontinuous conduction mode (DCM) and power-saving mode (PSM), wherein the current-mode control circuit includes: A bias circuit configured to adjust the threshold voltage based on the input and output voltages of the switching converter; and A clamping circuit coupled to the bias circuit, wherein the clamping circuit is configured to clamp the input signal at a lower clamping value based on the threshold.

16. The switching converter of claim 15, wherein the current-mode control circuit comprises: A voltage / current converter coupled to the clamping circuit and configured to provide the input signal to the clamping circuit; and An operational amplifier coupled to a voltage / current converter, wherein the output of the operational amplifier is provided to the voltage / current converter, and wherein the output of the operational amplifier is based on a comparison of a reference voltage with a feedback voltage proportional to the output voltage.

17. The switching converter of claim 16, wherein the current-mode control circuit further comprises: A comparator has the following characteristics: The first input is coupled to the output of the clamping circuit; and The second input is coupled to the current ramp sensed from the input voltage node to the high-side switching path of the switching converter; A turn-off time circuit configured to provide a turn-off signal; and Control logic coupled to the output of the comparator and the off-time circuit, wherein the output of the control logic is coupled to the gate driver circuit system.

18. The switching converter of claim 15, wherein the switching converter is a buck converter, and wherein the bias circuit is configured to adjust the threshold based on: ， Where VOUT is the output voltage, VIN is the input voltage, and K is the scaling factor.

19. The switching converter of claim 15, wherein the switching converter is a boost converter, and wherein the bias circuit is configured to adjust the threshold based on: ， Where VOUT is the output voltage, VIN is the input voltage, and K is the scaling factor.

20. The switching converter of claim 15, wherein the switching converter is a buck / boost converter, and wherein the bias circuit is configured to adjust the threshold based on: ， Where VMIN is the minimum value of the input voltage and the output voltage, VMAX is the maximum value of the input voltage and the output voltage, and K is a scaling factor.

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