A signal selection circuit, method and display device of a display panel

Abstract

The present disclosure provides a signal selection circuit, a method and a display device of a display panel, and belongs to the technical field of display. The signal selection circuit of the display panel of the present disclosure, the display panel is divided into N regions, the display panel comprises a plurality of pixel driving circuits and M gate driving circuits for providing M kinds of gate driving signals for the pixel driving circuits; each gate driving circuit comprises N gate driving sub-circuits, and one gate driving sub-circuit is configured to provide one kind of gate driving signal for the pixel driving circuit in one region; M≥2, N≥2, and M and N are both integers; wherein, the signal selection circuit comprises: M frame opening signal lines, one frame opening signal line is configured to provide a frame opening signal for one kind of gate driving circuit; selection sub-circuit, configured to output the frame opening signal written by any frame opening signal line to the gate driving sub-circuit corresponding to the corresponding region of the display panel according to the predetermined order.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a signal selection circuit of a display panel, a method and a display device. BACKGROUND

[0002] The current mature technologies in the display field include liquid crystal (LCD; Liquid Crystal Display) display and active matrix organic electroluminescence diode (OLED; Organic Electroluminescence Display) display. In a complete display system, the general technology of an OLED product is to excite various wavelengths of light spectrum by means of direct recombination of electrons and holes, so as to form a pattern. The display device formed by the OLED technology has a fast response speed, and can maximize the contrast ratio, so the OLED display device is expected to become the mainstream product of the next generation of display.

[0003] Generally, the OLED display device includes a display panel, a gate driving device, a data driver and a timing controller. The display panel includes data lines, gate lines and pixels controlled by the data lines and the gate lines. The general working mode is that when a gate driving signal is provided to the gate lines, a row of pixels is provided with a data voltage of the data lines. The pixels emit light with different brightness according to the size of the data voltage. The gate driving device provides a gate signal to the gate lines, and the gate driving device includes a separate gate driving integrated circuit or a panel gate driving circuit.

[0004] Since the separate gate driving integrated circuit is not conducive to narrow frame and low cost, the panel gate driving circuit is increasingly concerned at present. The traditional panel gate circuit determines the driving mode of the circuit according to the process, such as oxide, low temperature poly-silicon (LTPS; Low Temperature Poly-Silicon) and the like, but the basic principles are similar.

[0005] When the array substrate gate driving integrated (GOA; Gate Driven on Array) sub-area driving is adopted (such as N sub-areas), each sub-area of each group of GOA needs a start signal, and a total of N start signals are needed. In this case, when N is large, too many start signals affect the panel line of gate (PLG; Panel Line of Gate) design and chip on film (COF; Chip on Film) interface pin and other key indicators. SUMMARY

[0006] The present disclosure aims to at least solve one of the technical problems in the prior art, and provides a signal selection circuit of a display panel, a method and a display device.

[0007] In a first aspect, embodiments of this disclosure provide a signal selection circuit for a display panel, the display panel being divided into N zones, the display panel including a plurality of pixel driving circuits, and M types of gate driving circuits providing M types of gate driving signals to the pixel driving circuits; each of the gate driving circuits includes N gate driving sub-circuits, and one of the gate driving sub-circuits is configured to provide a gate driving signal to the pixel driving circuit in one zone; M≥2, N≥2, and M and N are both integers; wherein, the signal selection circuit includes:

[0008] M frame enable signal lines, one of the frame enable signal lines being configured to provide a frame enable signal for one of the gate drive circuits;

[0009] The selection sub-circuit is configured to output the frame enable signal written to any frame enable signal line to the gate drive sub-circuit corresponding to the corresponding area of ​​the display panel in a predetermined order.

[0010] In some examples, the selection sub-circuit includes:

[0011] Control unit and N selection units;

[0012] The control unit is configured to select one of the N selection units to operate;

[0013] The N selection units are configured to correspond one-to-one with the N zones of the display panel, and each selection unit is configured to provide a frame enable signal to the M gate driving circuits corresponding to a zone under the control of the control unit.

[0014] In some examples, the control unit further includes P first logic devices and N second logic devices; any of the selection units includes M third logic devices; the first logic devices are NOT gates, and the second and third logic devices are AND gates; P = [log2 N] + 1;

[0015] Each first logic device has its input terminal connected to a corresponding selection control signal line. Each selection control signal line and the output terminal of each first logic device are connected to the input terminal of the corresponding second logic device, so that the output terminals of N second logic devices output selection control signals in a preset order to control the operation of the corresponding selection unit.

[0016] Each of the third logic devices in any of the selection units is connected to its corresponding frame enable signal line and the output terminal of its corresponding second logic device.

[0017] In some examples, the N second logic devices are AND gates, wherein the number of input bits X of the AND gates is the same as the number P of the selection control signal lines.

[0018] In some examples, the control unit further comprises P first logic devices and N second logic devices; any of the selection units comprises M third logic devices; the first logic devices are NOT gates, the second logic devices are NAND gates, and the third logic devices are NOR gates.

[0019] An input end of each of the first logic devices is connected to a corresponding selection control signal line, and an output end of each of the first logic devices is connected to a corresponding input end of the second logic device, so that the output ends of the N second logic devices output selection control signals in a preset order to control the corresponding selection units to work.

[0020] For each of the third logic devices in any of the selection units, a corresponding frame start signal line is connected to the third logic device, and an output end of the corresponding second logic device is connected to the third logic device.

[0021] In some examples, the N second logic devices are NAND gates, wherein the number of input bits X of the NAND gates is the same as the number P of the selection control signal lines.

[0022] In some examples, M=4, N=4, and P=3. The four regions of the display panel are sequentially arranged from the first region to the fourth region and correspond to the four selection units one by one, and the selection units are respectively referred to as a first selection unit, a second selection unit, a third selection unit, and a fourth selection unit. The number of the selection control signal lines is 3, and the selection control signal lines are respectively referred to as a first selection control signal line, a second selection control signal line, and a third selection control signal line. The four frame start signal lines are respectively referred to as a first frame start signal line, a second frame start signal line, a third frame start signal line, and a fourth frame start signal line. Wherein,

[0023] The three first logic devices in the control unit are all NOT gates, and are respectively referred to as a first NOT gate, a second NOT gate, and a third NOT gate. The four second logic devices in the control unit are all 3-input AND gates, and are respectively referred to as a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate. Any of the selection units comprises four third logic devices, and the third logic devices are all AND gates. In the first selection unit, the four third logic devices are respectively referred to as a fifth AND gate, a sixth AND gate, a seventh AND gate, and an eighth AND gate.

[0024] According to the implementation timing, level signals are input to the frame enable signal line and the selection control signal line. The first input terminal of the first AND gate is connected to the output terminal of the first NOT gate, the second input terminal is connected to the output terminal of the second NOT gate, and the third input terminal is connected to the third selection control signal line. At this time, the output terminal of the first AND gate outputs a high-level signal, and the first frame enable signal line outputs a high-level signal. The first input terminal of the fifth AND gate is connected to the first frame enable signal line, and the second input terminal is connected to the output terminal of the first AND gate. At this time, the output terminal of the fifth AND gate outputs a high-level signal, and so on, providing frame enable signals to the four areas of the display panel respectively.

[0025] Secondly, embodiments of this disclosure also provide a signal selection method for a display panel, applied to the signal selection circuit of the aforementioned display panel; wherein, it includes:

[0026] Determine the number N of the display panel division areas and the number M of the frame enable signal lines;

[0027] The M frame enable signal lines input M types of frame enable signals, and the selection sub-circuit outputs M×N required frame enable signals in a predetermined order to achieve zoned display of the display panel.

[0028] Thirdly, embodiments of this disclosure also provide a display device, which includes the signal selection circuit of the display panel described above.

[0029] In some examples, the display device includes gate lines that provide gate drive signals to pixel drive circuits, with each gate line having an opposite end connected to the gate drive circuit, and each gate drive circuit being electrically connected to a signal selection circuit of the display panel. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the display panel.

[0031] Figure 2 It is a pixel driving circuit.

[0032] Figure 3 for Figure 2 The driving timing diagram of the pixel driving circuit.

[0033] Figure 4 This is another pixel driving circuit according to an embodiment of the present disclosure.

[0034] Figure 5 for Figure 4 The driving timing diagram of the pixel driving circuit.

[0035] Figure 6 This is a schematic diagram of the display panel according to an embodiment of the present disclosure.

[0036] Figure 7a This is a schematic diagram of a 4-zone display panel according to an embodiment of the present disclosure.

[0037] Figure 7b for Figure 7a Enlarged view of Part I.

[0038] Figure 8 for Figure 7a The timing diagram of the drive for the signal selection circuit in the display panel.

[0039] Figure 9 for Figure 7a The timing diagram of the signal selection circuit and the timing diagram of the frame enable signal in the display panel.

[0040] Figure 10 This is a schematic diagram of a 9-zone display panel according to an embodiment of the present disclosure.

[0041] Figure 11 for Figure 10 The timing diagram of the drive for the signal selection circuit in the display panel.

[0042] Figure 12 This is the structure diagram of an X-bit AND gate circuit.

[0043] Figure 13 This is a schematic diagram of the structure of another selection unit according to an embodiment of the present disclosure.

[0044] Figure 14 for Figure 13 A driving timing diagram for a 4-zone display panel applied to an embodiment of this disclosure. Detailed Implementation

[0045] To enable those skilled in the art to better understand the technical solution of this invention / utility model, the invention / utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0047] Figure 1 This is a schematic diagram of the display panel, such as... Figure 1 As shown, exemplarily, the display panel is divided into a display area and a peripheral area surrounding the display area. The display panel includes multiple pixel units arranged in an array in the display area and a gate driving circuit in the peripheral area. Each pixel unit includes only a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The gate driving circuit includes multiple cascaded shift register units (gate driving sub-circuits), each gate driving sub-circuit providing a gate driving signal to the pixel driving circuits located in the same row.

[0048] Specifically, Figure 2 As a pixel driving circuit, such as Figure 2 As shown, exemplarily, the pixel driving circuit includes a switching transistor T1, a first reset transistor T2, a second reset transistor T3, a driving transistor T4, a light-emitting control transistor T5, and a first storage capacitor C. st Second storage capacitor C el The signal lines are: Data line, Reference signal line, Initialization signal line, Vinit, First power supply signal line, Vcc, and Second power supply signal line, Vcath. The source of switching transistor T1 is electrically connected to the Data line, and the drain of switching transistor T1 is connected to the first storage capacitor C. st First plate C st1 The drain of the first reset transistor T2 is electrically connected to the gate of the driving transistor T4, and the gate of the switching transistor T1 is electrically connected to the fourth control line S4. The source of the first reset transistor T2 is electrically connected to the reference signal line Vref, and the drain of the first reset transistor T2 is electrically connected to the first storage capacitor C. st First plate C st1, the drain of the switch transistor T1 and the gate of the drive transistor T4 are electrically connected, and the gate of the first reset transistor T2 is electrically connected with the third control line S3. The drain of the first reset transistor T2, the first plate C st of the first storage capacitor C st1 , the connection node between the drain of the switch transistor T1 and the gate of the drive transistor T4 is N1. The source of the second reset transistor T3 is electrically connected with the initialization signal line Vinit, and the drain of the second reset transistor T3 is electrically connected with the drain of the light emitting control transistor T5 and the source of the drive transistor T4 respectively. The second plate C st of the first storage capacitor C st2 , the first plate C el of the second storage capacitor C el1 , the first electrode (i.e. anode) of the light emitting device EL and the drain of the drive transistor T4 are electrically connected, and the gate of the second reset transistor T3 is electrically connected with the second control line S2. The connection node between the drain of the second reset transistor T3, the source of the drive transistor T4 and the drain of the light emitting control transistor T5 is N2. The source of the drive transistor T4 is electrically connected with the drain of the light emitting control transistor T5, and the drain of the drive transistor T4 is electrically connected with the first electrode (i.e. anode) of the light emitting device EL, the second plate C st of the first storage capacitor C st2 , the first plate C el of the second storage capacitor C el1 and the drain of the second reset transistor T3 are electrically connected, and the gate of the drive transistor T4 is electrically connected with the drain of the switch transistor T1, the first plate C st of the first storage capacitor C st1 and the drain of the first reset transistor T2 respectively. The source of the light emitting control transistor T5 is electrically connected with the first power signal line Vcc, the drain of the light emitting control transistor T5 is electrically connected with the source of the drive transistor T4, and the gate of the light emitting control transistor T5 is electrically connected with the first control line S1. The first electrode (i.e. anode) of the light emitting device EL is electrically connected with the drain of the drive transistor T4, the second plate C st of the first storage capacitor C st2 and the first plate C el of the second storage capacitor C el1 respectively, and the second electrode (i.e. cathode) of the light emitting device EL is electrically connected with the second plate C el of the second storage capacitor C el2 and the second power signal line Vcath respectively. By Figure 2It can be seen that for a pixel driving circuit, four gate driving lines, i.e., the first control line S1, the second control line S2, the third control line S3 and the fourth control line S4, are required to provide the light emitting control signal for the light emitting control transistor T5, the initialization signal for the second reset transistor T3, the reset signal for the first reset transistor T2 and the switching control signal for the switching transistor T1. In order to facilitate wiring, the gate of the switching transistor T1 of the pixel driving circuit located in the same row is connected to the same first control line S1, the gate of the first reset transistor T2 is connected to the same third control line S3, the gate of the second reset transistor T3 is connected to the same second control line S2, and the gate of the switching transistor T1 is connected to the same fourth control line S4. One gate driving sub-circuit of one gate driving circuit provides one control signal line, i.e., the gate of the switching transistor T1 of the pixel driving circuit located in the same row is connected to the same fourth control line S4, the gate of the first reset transistor T2 is connected to the same third control line S3, the gate of the second reset transistor T3 is connected to the same second control line S2, and the gate of the switching transistor T1 is connected to the same first control line S1. Figure 7a As shown in the display panel, four gate driving circuits are required to provide the gate driving signal for each gate driving sub-circuit, so as to provide the gate driving signal for the pixel driving circuit located in the same row. For any gate driving circuit, the signal output end of the gate driving sub-circuit at the current stage is connected to the signal output end of the gate driving sub-circuit at the next stage, so as to realize the cascade of the multi-stage gate driving sub-circuit. The signal output end of the gate driving sub-circuit at the first stage is connected to the frame opening signal line, and the frame opening signal line is connected to the printed circuit board, so as to input the frame opening signal provided by the printed circuit board to the signal input end of the gate driving sub-circuit at the first stage through the frame opening signal line.

[0049] The inventor finds that with the continuous increase of the size of the display panel, the display panel partition driving can make the control of the display panel more flexible. In this case, each partition of the display panel requires a group of four gate driving circuits. If the display panel is divided into four areas, 16 gate driving circuits are required, i.e., 16 frame opening signal lines are required. Correspondingly, the number of ports of the printed circuit board needs to meet the requirement of the number of frame opening signal lines, thus greatly increasing the cost.

[0050] Based on the above technical problem, the technical scheme is provided in the embodiments of the present disclosure. The signal selection circuit of the display panel can be applied to the pixel driving circuit after the display panel is divided into N areas, so as to reduce the number of starting signals, thereby controlling the N partition independent starting through fewer signals, which has great application value. Wherein, the number of M frame opening signal lines is determined according to the number of gate driving signals required by the pixel driving circuit, so as to provide the gate driving signal for each gate driving circuit. The M kinds of frame opening signals of the M frame opening signal lines are input into the selection sub-circuit, and the MxN required frame opening signals are output in a predetermined order through the selection sub-circuit, so as to realize the partition display of the display panel.

[0051] The signal selection circuit of the display panel according to the embodiments of the present disclosure is described below in combination with the accompanying drawings and specific embodiments.

[0052] The signal selection circuit of the display panel according to the embodiments of the present disclosure can make the start signal more concise when the display panel adopts a partition design. Figure 6 A schematic diagram of the display panel according to the embodiments of the present disclosure is shown in FIG. 1. Figure 6 As shown in FIG. 1, the display panel is divided into N regions, and the display panel includes a plurality of pixel driving circuits and M gate driving circuits for providing M kinds of gate driving signals for the pixel driving circuits. Each gate driving circuit includes N gate driving sub-circuits, and one gate driving sub-circuit is configured to provide one kind of gate driving signal for the pixel driving circuits in one region. M≥2, N≥2, and M and N are both integers. The signal selection circuit according to the embodiments of the present disclosure includes M frame start signal lines and a selection sub-circuit. Each of the M frame start signal lines is configured to provide a frame start signal for one kind of gate driving circuit. The selection sub-circuit is configured to output the frame start signal written by any frame start signal line to the gate driving sub-circuit corresponding to the corresponding region of the display panel in a predetermined order.

[0053] Since the selection sub-circuit is added to the signal selection circuit of the display panel according to the embodiments of the present disclosure, the frame start signal input to the gate driving sub-circuit corresponding to the corresponding region of the display panel can be selected, thereby completing the partition display. At the same time, the selection sub-circuit simplifies the number of signals, thereby reducing the number of signal access ports of the display panel, and further realizing the narrow-frame design of the display panel and reducing the manufacturing cost.

[0054] It should be noted that the selection sub-circuit can only realize that the frame start signal written by any frame start signal line is output to the gate driving sub-circuit corresponding to the corresponding region of the display panel in a predetermined order, and the internal specific selection function is not limited.

[0055] In some examples, the selection sub-circuit includes a control unit and N selection units. The control unit is configured to select one of the N selection units to work. The N selection units are arranged in one-to-one correspondence with the N regions of the display panel. One selection unit is configured to provide the frame start signal for the M gate driving circuits corresponding to one region respectively under the control of the control unit. Since the control unit can select one of the N selection units to work, and the N selection units are arranged in one-to-one correspondence with the N regions of the display panel, the display of each partition of the display panel can be accurately controlled, thereby realizing the insertion of a local high-frequency frame in the display, and further applied to intelligent display.

[0056] Further, the control unit further comprises P first logic devices and N second logic devices; any selection unit comprises M third logic devices; the first logic device is a NOT gate, and the second logic device and the third logic device are AND gates; P=[log2 N]+1.

[0057] It should be noted that, since there is a case that all partitions of the display panel are not written with signals, i.e., the logical level is zero, P=[log2 N]+1, and [log2 N] represents an integer not exceeding log2 N.

[0058] The input end of each first logic device is connected with a corresponding selection control signal line, so as to obtain the inverted signal of each selection control signal; each selection control signal line and the output end of each first logic device are connected with the input end of a corresponding second logic device, so that the output ends of the N second logic devices output the selection control signals in a preset order, so as to control the operation of the corresponding selection unit. For each third logic device in any selection unit, a corresponding frame opening signal line and the output end of a corresponding second logic device are connected, so that the partition display of the display panel is realized.

[0059] Among them, the N second logic devices are AND gates, the input bit number X of the AND gate is the same as the number P of the selection control signal lines, so that the logical AND function of the selection control signal can be realized. The implementation method of the AND gate includes using CMOS tube, NMOS tube, PMOS tube and diode to realize, etc. Figure 12 The structure diagram of an X-bit AND gate circuit is as follows: Figure 12As shown, the AND gate circuit used in the embodiment of the present disclosure is a CMOS AND gate circuit. The CMOS AND gate circuit is composed of a CMOS NAND gate and a CMOS inverter, and NMOS and PMOS transistors appear in pairs in the circuit and are complementary in operation, thereby forming the CMOS AND gate circuit. When an X-bit input AND gate is needed, X pairs of CMOS transistors are needed, that is, the number of input bits can be changed by increasing or decreasing the number of CMOS transistors. The X-input CMOS AND gate circuit is composed of an X-input CMOS NAND gate circuit and an inverter, wherein the X-input NAND gate includes X series-connected N-channel enhancement-mode MOS transistors and X parallel-connected P-channel enhancement-mode MOS transistors, and the inverter is composed of an N transistor and a P transistor. The output of the X-input NAND gate is the input of the inverter, and each of the inputs A, B, …, X is connected to the gate of an N-channel and a P-channel MOS transistor. The output terminal F is the output terminal of the inverter. When only one of the input terminals A, B, …, X is at a low level, the NAND gate part will make the NMOS transistor connected thereto cut off and the PMOS transistor connected thereto conduct, so that the input of the inverter is at a high level. When the input of the inverter is at a high level, the NMOS transistor of the inverter is turned on and the PMOS transistor is cut off, so that the output of the inverter, that is, the F terminal, outputs a low level. Only when A, B, …, X are all at a high level, the X series-connected NMOS transistors of the NAND gate part are all turned on, the X parallel-connected PMOS transistors are all cut off, the output is at a low level, and then the PMOS transistor of the inverter part is turned on and the NMOS transistor is cut off, so that the output terminal Q outputs a high level, thereby realizing the function of the X-input AND gate.

[0060] In some examples, without changing the partition design of the present disclosure, the control unit further comprises P first logic devices and N second logic devices; any selection unit comprises M third logic devices; the first logic device is a NOT gate, the second logic device is a NAND gate, and the third logic device is a NOR gate.

[0061] The input terminal of each first logic device is connected to a corresponding selection control signal line, thereby obtaining the inverted signal of each selection control signal. Each selection control signal line and the output terminal of each first logic device are connected to the input terminal of a corresponding second logic device, so that the output terminals of the N second logic devices output the selection control signals in a predetermined order to control the operation of the corresponding selection unit.

[0062] For each third logic device in any selection unit, a corresponding frame-on signal line and the output terminal of a corresponding second logic device are connected, thereby realizing the partition display of the display panel.

[0063] In this example, the N second logic devices are changed from AND gates to NAND gates, and the third logic device is changed from an AND gate to a NOR gate, but the change of the gate circuit does not affect the function implementation of the signal selection circuit of the display panel of the present disclosure, wherein the input bit number X of the NAND gate is the same as the number P of the selection control signal lines.

[0064] It should be noted that in this example, referring to Figure 12 , the AND gate is less than the NAND gate by the inverter composed of PMOS and NMOS, that is, the NAND gate is easier to implement than the AND gate in the CMOS gate circuit, thereby simplifying the internal basic circuit of the present disclosure, and further optimizing the architecture of the present disclosure.

[0065] In the field of display technology, pixel driving circuits applied to display panels need different numbers of gate driving signals according to their functions. Figure 2 A pixel driving circuit is provided, as shown in Figure 2 , the pixel driving circuit comprises a switch transistor T1, a first reset transistor T2, a second reset transistor T3, a driving transistor T4, a light-emitting control transistor T5, a first storage capacitor C st and a second storage capacitor C el , a data line Data, a reference signal line Vref, an initialization signal line Vinit, a first power signal line Vcc and a second power signal line Vcath.

[0066] It should be noted that the transistors used in the pixel driving circuit of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the source and drain are turned on when a low-level signal is input to the gate; when an N-type transistor is used, the source and drain are turned on when a high-level signal is input to the gate. As shown in Figure 2 , all the transistors in the pixel driving circuit are N-type transistors except for the light-emitting control transistor T5 which is a P-type transistor.

[0067] Specifically, the source of the switch transistor T1 is electrically connected with the data line Data, the drain of the switch transistor T1 is electrically connected with the first plate C st of the first storage capacitor C st1 , the drain of the first reset transistor T2 and the gate of the driving transistor T4, and the gate of the switch transistor T1 is electrically connected with the fourth control line S4. Specifically, the switch transistor T1 is configured to be turned on when the fourth control line S4 writes a working level, to transmit the data voltage signal written by the data line Data to the gate of the driving transistor T4, and to store the data voltage signal through the first storage capacitor C st .

[0068] The source of the first reset transistor T2 is electrically connected to the reference signal line Vref, and the drain of the first reset transistor T2 is connected to the first storage capacitor C. st First plate C st1 The drain of switching transistor T1 and the gate of driving transistor T4 are electrically connected, and the gate of first reset transistor T2 is electrically connected to the third control line S3. The drain of first reset transistor T2 and the first storage capacitor C... st First plate C st1 The connection node between the drain of switching transistor T1 and the gate of driving transistor T4 is N1. Specifically, the first reset transistor T2 is configured to turn on when the working level is written to the third control line S3, and output the first reset signal written to the reference signal line Vref to the connection node N1.

[0069] The source of the second reset transistor T3 is electrically connected to the initialization signal line Vinit, and the drain of the second reset transistor T3 is electrically connected to the drain of the light-emitting control transistor T5 and the source of the driving transistor T4, respectively. The first storage capacitor C... st The second plate C st2 Second storage capacitor C el First plate C el1 The first electrode (anode) of the light-emitting device EL is electrically connected to the drain of the driving transistor T4, and the gate of the second reset transistor T3 is electrically connected to the second control line S2. The connection node between the drain of the second reset transistor T3, the source of the driving transistor T4, and the drain of the light-emitting control transistor T5 is N2. Specifically, the second reset transistor T3 is configured to turn on when the working level is written to the second control line S2, transmitting the second reset signal written by the initialization signal line Vinit to the connection node N2.

[0070] The source of the driving transistor T4 is electrically connected to the drain of the light-emitting control transistor T5. The drain of the driving transistor T4 is connected to the first electrode (i.e., the anode) of the light-emitting device EL and the first storage capacitor C, respectively. st The second plate C st2 Second storage capacitor C el First plate C el1 The drain of the second reset transistor T3 is electrically connected, and the gate of the driving transistor T4 is connected to the drain of the switching transistor T1 and the first storage capacitor C, respectively. st First plate C st1 The drain of the first reset transistor T2 is electrically connected. Specifically, the driving transistor T4 is configured to provide a driving current to the first electrode (i.e., the anode) of the light-emitting device EL when it is turned on, thereby driving the light-emitting device EL to emit light.

[0071] The source of the light-emitting control transistor T5 is electrically connected with the first power signal line Vcc, the drain of the light-emitting control transistor T5 is electrically connected with the source of the driving transistor T4, and the gate of the light-emitting control transistor T5 is electrically connected with the first control line S1. Specifically, the light-emitting control transistor T5 is configured to, in the case of being turned on, transmit the first power voltage input by the first power signal line Vcc to the source of the driving transistor T4.

[0072] The first electrode (i.e. anode) of the light-emitting device EL is electrically connected with the drain of the driving transistor T4, the second plate C st of the first storage capacitor C st2 and the first plate C el of the second storage capacitor C el1 respectively, and the second electrode (i.e. cathode) of the light-emitting device EL is electrically connected with the second plate C el of the second storage capacitor C el2 and the second power signal line Vcath respectively.

[0073] The first power signal line Vcc is a voltage source to output a constant first power voltage, and the first power voltage is a positive voltage; and the second power signal line Vcath can be a voltage source to output a constant second power voltage, and the second power voltage is a negative voltage, etc. For example, the second power signal line Vcath is grounded.

[0074] Figure 3 The driving timing diagram of the pixel driving circuit of Figure 2 is shown in Figure 3 , wherein S1 represents the first control line of the light-emitting control transistor T5, S2 represents the second control line of the second reset transistor T3, S3 represents the third control line of the first reset transistor T2, and S4 represents the fourth control line of the switch transistor T1.

[0075] As shown in Figure 3As shown in the driving timing, in the t01-t02 period, S1, S2, S3, and S4 are low, at this time, the light emitting control transistor T5 in the pixel driving circuit receives the first power voltage provided by the first power signal line Vcc. In the t02-t03 period, S1 and S2 are high, and S3 and S4 are low, the second reset transistor T3 in the pixel driving circuit receives the second reset signal written by the initialization signal line Vinit, and the voltage of the N2 connection node is Vinit. In the t03-t04 period, S1, S2, and S3 are high, and S4 is low, the first reset transistor T2 receives the first reset signal written by the reference signal line Vref, and the voltage of the N1 connection node is Vref; at this time, the first reset transistor T2 in the pixel driving circuit continuously receives the first reset signal written by the reference signal line Vref, and the voltage of the N1 connection node is continuously Vref. In the t04-t05 period, S1, S2, S3, and S4 are low, at this time, the light emitting control transistor T5 in the pixel driving circuit receives the first power voltage provided by the first power signal line Vcc. In the t05-t06 period, S1, S2, and S3 are low, and S4 is high, at this time, the switch transistor T1 in the pixel driving circuit can realize the connection conduction between the driving transistor T4 and the data line Data, and receive the data voltage signal written by the data line Data, and at the same time, the data voltage signal is transmitted to the gate of the driving transistor T4; at the same time, the driving transistor T4 is turned on under the control of the stored data signal, so that the gate and the drain of the driving transistor T4 are connected, and the driving transistor T4 is in a self-saturation state, at this time, the first node N1 is written with the data signal and the threshold voltage of the driving transistor T4, realizing the compensation of the threshold voltage of the driving transistor T4; the light emitting control transistor T5 in the pixel driving circuit receives the first power voltage provided by the first power signal line Vcc, and provides a driving current for the driving transistor T4, and the driving transistor T4 controls the driving current flowing from the first power signal line Vcc to the light emitting device EL according to the voltage stored in the storage capacitor Cst. st

[0076] Figure 4 For another pixel driving circuit of the embodiment of the present disclosure, the pixel driving circuit Figure 5 For Figure 4 the driving timing diagram of the pixel driving circuit; as Figure 4 and Figure 5 shown, the pixel driving is realized by a 5T1C (5 transistors and 1 capacitor) structure. It should be noted that, Figure 4 the pixel driving circuit shown in Figure 2 is a variation of the pixel driving circuit shown in Figure 2 , and the light emitting principle is similar to that of the pixel driving circuit shown in .

[0077] The two pixel driving circuits above both need four gate driving signals, and the corresponding two timing diagrams can be implemented in the embodiments of the present disclosure. For the convenience of description, the pixel driving circuit and the corresponding timing shown in Figure 2 and Figure 3 are taken as examples, and the following will be described in combination with specific examples.

[0078] The first example, Figure 7a is a schematic diagram of a 4-partition display panel according to an embodiment of the present disclosure, Figure 7b is Figure 7a is a zoomed-in view of part I in Figure 8 is Figure 7a is a driving timing diagram of the signal selection circuit in the display panel of Figure 9 is Figure 7a is a driving timing diagram of the signal selection circuit in the display panel of and a timing diagram of the frame start signal; where A', B', C' are signals obtained by inverters from A, B, C, as shown in Figure 7a , 7b , 8 and 9, in the signal selection circuit of the display panel, M = 4, N = 4, P = 3, the four partitions of the display panel are arranged in order from the first to the fourth and correspond to the four selection units one by one, and the selection units are respectively referred to as the first selection unit, the second selection unit, the third selection unit and the fourth selection unit; the number of selection control signal lines is 3, and they are respectively referred to as the first selection control signal line A, the second selection control signal line B and the third selection control signal line C; the four frame start signal lines correspond to the gate driving circuits of the control signals in the pixel circuit, and they are respectively referred to as the first frame start signal line S1, the second frame start signal line S2, the third frame start signal line S3 and the fourth frame start signal line S4; refer to Figure 3 , where the first frame start signal line S1, the second frame start signal line S2, the third frame start signal line S3 and the fourth frame start signal line S4 correspond to the first control line S1, the second control line S2, the third control line S3 and the fourth control line S4 in the pixel driving circuit.

[0079] The three first logic devices in the control unit are all NOT gates, and they are respectively referred to as the first NOT gate, the second NOT gate and the third NOT gate; the four second logic devices in the control unit are all 3-input AND gates, and they are respectively referred to as the first AND gate, the second AND gate, the third AND gate and the fourth AND gate; any selection unit includes four third logic devices, and the third logic devices are all AND gates, where the four third logic devices in the first selection unit are respectively referred to as the fifth AND gate, the sixth AND gate, the seventh AND gate and the eighth AND gate.

[0080] Specifically, in the first selection unit, the output end of the first AND gate is connected to the second input end of the fifth AND gate, the sixth AND gate, the seventh AND gate and the eighth AND gate respectively, the first frame start signal line S1 is connected to the first input end of the fifth AND gate, the second frame start signal line S2 is connected to the first input end of the sixth AND gate, the third frame start signal line S3 is connected to the first input end of the seventh AND gate, and the fourth frame start signal line S4 is connected to the first input end of the eighth AND gate. For any selection unit, the connection is made according to the above connection relationship.

[0081] The level signals are input to the frame start signal lines and the selection control signal lines according to the implementation timing, wherein the first input end of the first AND gate is connected to the output end of the first NOT gate, the second input end is connected to the output end of the second NOT gate, and the third input end is connected to the third selection control signal line C, at this time, the output end of the first AND gate outputs a high level signal, and the first frame start signal line S1 outputs a high level signal; the first input end of the fifth AND gate is connected to the first frame start signal line S1, and the second input end is connected to the output end of the first AND gate, at this time, the output end of the fifth AND gate outputs a high level signal, and so on, thereby providing the four areas of the display panel with frame start signals respectively.

[0082] A second example, Figure 10 A schematic diagram of a 9-zone display panel according to an embodiment of the present disclosure, Figure 11 A schematic diagram of a 9-zone display panel according to an embodiment of the present disclosure, Figure 10 A driving timing diagram of the signal selection circuit in the display panel; as shown in Figure 10 and Figure 11 In the signal selection circuit of the display panel, M=4, N=9, and P=4, the nine areas of the display panel are arranged in order from the first to the ninth and correspond to the nine selection units one by one, and the selection units are respectively referred to as the first selection unit, the second selection unit, the third selection unit, the fourth selection unit, the fifth selection unit, the sixth selection unit, the seventh selection unit, the eighth selection unit and the ninth selection unit; the number of selection control signal lines is four, and they are respectively referred to as the first selection control signal line A, the second selection control signal line B, the third selection control signal line C and the fourth selection control signal line D; the four frame start signal lines are respectively referred to as the first frame start signal line S1, the second frame start signal line S2, the third frame start signal line S3 and the fourth frame start signal line S4; refer to Figure 3 , wherein the first frame start signal line S1, the second frame start signal line S2, the third frame start signal line S3 and the fourth frame start signal line S4 correspond to the first control line S1, the second control line S2, the third control line S3 and the fourth control line S4 in the pixel driving circuit respectively.

[0083] The four first logic devices in the control unit are all NOT gates, and are respectively referred to as a first NOT gate, a second NOT gate, a third NOT gate and a fourth NOT gate; the nine second logic devices in the control unit are all 4-input AND gates, and are respectively referred to as a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate and a ninth AND gate; any selection unit includes four third logic devices, and the third logic devices are all AND gates, wherein the four third logic devices in the first selection unit are respectively referred to as a tenth AND gate, an eleventh AND gate, a twelfth AND gate and a thirteenth AND gate.

[0084] Specifically, in the first selection unit, the output terminals of the first AND gate are connected to the second input terminals of the tenth AND gate, the eleventh AND gate, the twelfth AND gate and the thirteenth AND gate respectively, the first frame start signal line S1 is connected to the first input terminal of the tenth AND gate, the second frame start signal line S2 is connected to the first input terminal of the eleventh AND gate, the third frame start signal line S3 is connected to the first input terminal of the twelfth AND gate, and the fourth frame start signal line S4 is connected to the first input terminal of the thirteenth AND gate. For any selection unit, the connection is performed according to the above connection relationship.

[0085] The level signals are input to the frame start signal lines and the selection control signal lines according to the implementation timing, wherein the first input terminal of the first AND gate is connected to the output terminal of the first NOT gate, the second input terminal is connected to the output terminal of the second NOT gate, the third input terminal is connected to the output terminal of the third NOT gate, and the fourth input terminal is connected to the fourth selection control signal line D, at this time, the output terminal of the first AND gate outputs a high level signal, and the first frame start signal line S1 outputs a high level signal; the first input terminal of the tenth AND gate is connected to the first frame start signal line S1, and the second input terminal is connected to the output terminal of the first AND gate, at this time, the output terminal of the tenth AND gate outputs a high level signal, and the other tenth AND gates are connected in the same way, thereby providing the nine areas of the display panel with frame start signals respectively.

[0086] A third example, Figure 13 A structural schematic diagram of another selection unit of the embodiment of the present disclosure, Figure 14 A structural schematic diagram of another selection unit of the embodiment of the present disclosure, Figure 13 A driving timing diagram of a 4-partition display panel applied to the embodiment of the present disclosure; as Figure 13 And Figure 14 As shown in the signal selection circuit of the display panel, M=4, N=4, P=3, the four areas of the display panel are arranged in sequence from the first to the fourth and correspond to the four selection units one by one, and the selection units are respectively referred to as a first selection unit, a second selection unit, a third selection unit and a fourth selection unit; the number of selection control signal lines is 3, and they are respectively referred to as a first selection control signal line A, a second selection control signal line B and a third selection control signal line C; the four frame start signal lines are respectively referred to as a first frame start signal line S1, a second frame start signal line S2, a third frame start signal line S3 and a fourth frame start signal line S4;Figure 3 The first frame start signal line S1, the second frame start signal line S2, the third frame start signal line S3, and the fourth frame start signal line S4 correspond to the first control line S1, the second control line S2, the third control line S3, and the fourth control line S4 in the pixel driving circuit, respectively.

[0087] The three first logic devices in the control unit are all NAND gates, and are referred to as a first NAND gate, a second NAND gate, and a third NAND gate, respectively; the four second logic devices in the control unit are all 3-input NAND gates, and are referred to as a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate, respectively; any selection unit includes four third logic devices, and the third logic devices are all NOR gates, wherein the four third logic devices in the first selection unit are referred to as a fifth NOR gate, a sixth NOR gate, a seventh NOR gate, and an eighth NOR gate, respectively.

[0088] Specifically, in the first selection unit, the output ends of the first NAND gate are connected to the second input ends of the fifth NOR gate, the sixth NOR gate, the seventh NOR gate, and the eighth NOR gate, respectively; the first input end of the fifth NOR gate is connected to the first frame start signal line S1, the first input end of the sixth NOR gate is connected to the second frame start signal line S2, the first input end of the seventh NOR gate is connected to the third frame start signal line S3, and the first input end of the eighth NOR gate is connected to the fourth frame start signal line S4. For any selection unit, the connection is performed according to the above connection relationship.

[0089] The level signals are input to the frame start signal lines and the selection control signal lines according to the implementation timing, wherein the first input end of the first NAND gate is connected to the output end of the first NAND gate, the second input end is connected to the output end of the second NAND gate, and the third input end is connected to the third selection control signal line C; at this time, the output end of the first NAND gate outputs a low-level signal, and the first frame start signal line S1 outputs a low-level signal; the first input end of the fifth NAND gate is connected to the first frame start signal line S1, and the second input end is connected to the output end of the first NAND gate; at this time, the output end of the fifth NAND gate outputs a high-level signal; and the same applies to the other NAND gates, so as to provide the frame start signals to the four areas of the display panel, respectively.

[0090] It should be noted that, in this embodiment, the NAND gate is used instead of the NAND gate in the CMOS gate circuit, which is easier to implement, so that the second logic device is changed to the NAND gate, the internal basic circuit of the display panel is simplified, the architecture of the display panel is optimized, and the manufacturing cost is reduced.

[0091] The display panel signal selection method provided in the embodiment of the display panel signal selection circuit, and the display panel signal selection method comprises the following steps: determining the number N of the divided areas of the display panel and the number M of the frame start signal lines; inputting M kinds of frame start signals to the M frame start signal lines; and outputting MxN required frame start signals in a predetermined order through the selection sub-circuit, so as to realize the display of the divided areas of the display panel.

[0092] The display device also includes the signal selection circuit of the display panel.

[0093] In some examples, the pixel driving circuit in the display panel of the display device includes the gate driving circuit on both sides of the gate line, i.e., for a row of gate lines, there is a GOA unit on both the left and right sides to charge the row of gate lines. In this case, the left and right GOA circuit designs are completely symmetrical, and the display panel is driven on both sides. In this display panel, the signal selection circuit of the present disclosure is arranged according to the GOA two-side partitioning, i.e., the signal selection circuit is included on both sides of the display panel.

[0094] It should be noted that for a small-size display panel, the load of the gate line is small, and a GOA unit can be added on only one side for one-side driving. Similarly, in this display panel, the signal selection circuit of the present disclosure is arranged according to the GOA one-side partitioning, i.e., the signal selection circuit is included on both sides of the display panel.

[0095] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered to be within the protection scope of the present application.

Claims

1. A signal selection circuit for a display panel, the display panel being divided into N zones, the display panel including a plurality of pixel driving circuits, and M types of gate driving circuits providing M types of gate driving signals to the pixel driving circuits; each of the gate driving circuits including N gate driving sub-circuits, and one of the gate driving sub-circuits being configured to provide a gate driving signal to the pixel driving circuit in one zone; M≥2, N≥2, and M and N are both integers; where, The signal selection circuit includes: M frame enable signal lines, one of the frame enable signal lines being configured to provide a frame enable signal for one of the gate drive circuits; The selection sub-circuit is configured to output the frame enable signal written to any frame enable signal line to the gate drive sub-circuit corresponding to the corresponding area of ​​the display panel in a predetermined order. The selection sub-circuit includes: a control unit and N selection units; The control unit is configured to select one of the N selection units to operate; N selection units are set one-to-one with N areas of the display panel, and one selection unit is configured to provide a frame enable signal for M types of gate driving circuits corresponding to one area under the control of the control unit. The control unit includes P first logic devices and N second logic devices; each selection unit includes M third logic devices; P = [log2 N] + 1; the input terminal of each first logic device is connected to its corresponding selection control signal line, and each selection control signal line and the output terminal of each first logic device are connected to the input terminal of the corresponding second logic device, so that the output terminals of the N second logic devices output selection control signals in a preset order to control the operation of the corresponding selection unit; Each of the third logic devices in any of the selection units is connected to its corresponding frame enable signal line and the output terminal of its corresponding second logic device.

2. The signal selection circuit for the display panel according to claim 1, wherein, The first logic device is a NOT gate, and the second and third logic devices are both AND gates.

3. In the signal selection circuit of the display panel according to claim 2, the N second logic devices are AND gates, wherein, The number of input bits X of the AND gate is the same as the number of selection control signal lines P.

4. The signal selection circuit for the display panel according to claim 1, wherein, The first logic device is a NOT gate, the second logic device is a NAND gate, and the third logic device is a NOR gate.

5. The signal selection circuit for the display panel according to claim 4, wherein the N second logic devices are NAND gates, wherein, The number of input bits X of the NAND gate is the same as the number of selection control signal lines P.

6. The signal selection circuit of the display panel according to claim 1, wherein M=4, N=4, P=3, the four areas of the display panel are arranged sequentially from the first to the fourth and correspond one-to-one with the four selection units, the selection units being referred to as the first selection unit, the second selection unit, the third selection unit, and the fourth selection unit; the number of selection control signal lines is three, and they are referred to as the first selection control signal line, the second selection control signal line, and the third selection control signal line; the four frame enable signal lines are referred to as the first frame enable signal line, the second frame enable signal line, the third frame enable signal line, and the fourth frame enable signal line; wherein, The three first logic devices in the control unit are all NOT gates, and are respectively referred to as the first NOT gate, the second NOT gate, and the third NOT gate; the four second logic devices in the control unit are all 3-input AND gates, and are respectively referred to as the first AND gate, the second AND gate, the third AND gate, and the fourth AND gate; any selection unit includes four third logic devices, all of which are AND gates, wherein the four third logic devices in the first selection unit are respectively referred to as the fifth AND gate, the sixth AND gate, the seventh AND gate, and the eighth AND gate; According to the implementation timing, level signals are input to the frame enable signal line and the selection control signal line. The first input terminal of the first AND gate is connected to the output terminal of the first NOT gate, the second input terminal is connected to the output terminal of the second NOT gate, and the third input terminal is connected to the third selection control signal line. At this time, the output terminal of the first AND gate outputs a high-level signal, and the first frame enable signal line outputs a high-level signal. The first input terminal of the fifth AND gate is connected to the first frame enable signal line, and the second input terminal is connected to the output terminal of the first AND gate. At this time, the output terminal of the fifth AND gate outputs a high-level signal, and so on, providing frame enable signals to the four areas of the display panel respectively.

7. A signal selection method for a display panel, applied to the signal selection circuit of the display panel according to any one of claims 1-6; wherein, include: Determine the number N of the display panel division areas and the number M of the frame enable signal lines; The M frame enable signal lines input M types of frame enable signals, and the selection sub-circuit outputs M×N required frame enable signals in a predetermined order to achieve zoned display of the display panel.

8. A display device comprising a signal selection circuit for a display panel according to any one of claims 1-6.

9. The display device according to claim 8, wherein, The display device includes gate lines that provide gate driving signals to pixel driving circuits, each gate line having its opposite end connected to a gate driving circuit, and each gate driving circuit being electrically connected to a signal selection circuit of the display panel.

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