Display driving circuit and display device

Abstract

The display driving circuit comprises two gate driving circuits; each gate driving circuit comprises a plurality of driving circuits; each driving circuit comprises N clock signal terminals, N output sub-circuits and N driving signal output terminals; N is an integer greater than or equal to 2; the N output sub-circuits share a first pull-up node; the i-th driving signal output terminal of one driving circuit is electrically connected with the i+j-th driving signal output terminal of another driving circuit, i and j are positive integers, i is a positive integer less than or equal to N, j is a positive integer less than or equal to N, and i+j is less than or equal to N. According to the display driving circuit, the i-th driving signal output terminal of one driving circuit in the two driving circuits is electrically connected with the i+j-th driving signal output terminal of another driving circuit, which are complementary to each other, so that the driving ability of the driving signals received by the gate lines is substantially the same.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display driving circuit and a display device. Background Technology

[0002] The related display product designs all adopt a double-sided symmetrical GOA (Gate On Array) model design, which makes it difficult to achieve narrow bezels. For full-screen displays and products with increasingly stringent bezel requirements, the wiring space is severely limited, making it difficult to meet the product requirements of high resolution and high refresh rate. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a display driving circuit including two gate driving circuits, the two gate driving circuits being respectively disposed on opposite sides of the display panel; the gate driving circuit includes a plurality of cascaded driving circuits.

[0004] The driving circuit includes N clock signal terminals, N output sub-circuits, and N driving signal output terminals; N is an integer greater than or equal to 2; the N output sub-circuits share a first pull-up node;

[0005] The nth output sub-circuit is used to control the output of the nth drive signal through the nth drive signal output terminal under the control of the potential of the first pull-up node, according to the nth clock signal provided by the nth clock signal terminal; n is a positive integer less than or equal to N;

[0006] The i-th drive signal output terminal of one of the two drive circuits is electrically connected to the i+j-th drive signal output terminal of the other drive circuit. i and j are both positive integers, i is a positive integer less than or equal to N, j is a positive integer less than or equal to N, and i+j is a positive integer less than or equal to N.

[0007] When the potential of the i-th clock signal provided by the i-th clock signal terminal among the N clock signal terminals changes from an invalid level to an active level, the potential of the first pull-up node is a first voltage value; when the potential of the (i+j)-th clock signal provided by the (i+j)-th clock signal terminal among the N clock signal terminals changes from an invalid level to an active level, the potential of the first pull-up node is a second voltage value; the first voltage value and the second voltage value are not equal.

[0008] The time period during which the potential of the i-th clock signal remains at an effective level and the time period during which the potential of the (i+j)-th clock signal remains at an effective level at least partially overlap.

[0009] The time point at which the potential of the i-th clock signal changes from an active level to an inactive level is different from the time point at which the potential of the (i+j)-th clock signal changes from an active level to an inactive level.

[0010] Optionally, when the potential of the i-th clock signal changes from an active level to an inactive level, the potential of the first pull-up node is a third voltage value; when the potential of the (i+j)-th clock signal changes from an active level to an inactive level, the potential of the first pull-up node is a fourth voltage value.

[0011] The third voltage value is not equal to the fourth voltage value.

[0012] Optionally, when the potential of the i-th clock signal changes from an invalid level to an effective level, the potential of the first pull-up node rises by a first potential height within a first time period.

[0013] When the potential of the (i+j)th clock signal changes from an invalid level to an effective level, the potential of the first pull-up node rises by a second potential height within the second time period.

[0014] The first potential height is not equal to the second potential height, and / or the first time is not equal to the second time.

[0015] Optionally, when the potential of the i-th clock signal changes from an active level to an inactive level, the potential of the first pull-up node drops by a third potential height within the third time period;

[0016] When the potential of the (i+j)th clock signal changes from an active level to an inactive level, the potential of the first pull-up node drops by a fourth potential height during the fourth time period.

[0017] The third potential height is not equal to the fourth potential height, and / or the third time is not equal to the fourth time.

[0018] Optionally, the driving circuit includes a capacitor disposed between the a-th driving signal terminal and the first pull-up node, wherein the first time is less than the second time, and the first potential height is less than the second potential height; a is an even number, a is a positive integer; or;

[0019] The driving circuit includes a capacitor disposed between the b-th driving signal terminal and the first pull-up node, wherein the first time is greater than the second time, and the first potential height is greater than the second potential height; b is an odd number and b is a positive integer.

[0020] Optionally, the driving circuit includes a capacitor disposed between the a-th driving signal terminal and the first pull-up node, the third time is less than the fourth time, and the third potential height is greater than the fourth potential height; a is an even number, a is a positive integer; or;

[0021] The driving circuit includes a capacitor disposed between the b-th driving signal terminal and the first pull-up node, the third time is greater than the fourth time, and the third potential height is less than the fourth potential height; b is an odd number and b is a positive integer.

[0022] Optionally, the driving circuit further includes a first input sub-circuit, a first pull-down sub-circuit, a first pull-down node control sub-circuit, and N output reset sub-circuits; the N output reset sub-circuits multiplex the first pull-down node;

[0023] The first input sub-circuit is used to control the potential of the first pull-up node under the control of the first input signal provided at the first input terminal;

[0024] The first pull-down sub-circuit is electrically connected to the first pull-up node, the first pull-down node, the first reset terminal, and the first voltage terminal, respectively, and is used to control the connection between the first pull-up node and the first voltage terminal under the control of the potential of the first pull-down node, and to control the connection between the first pull-up node and the first voltage terminal under the control of the first reset signal provided by the first reset terminal.

[0025] The first pull-down node control sub-circuit is electrically connected to the first control voltage terminal, the first pull-up node, the first pull-down node, and the first voltage terminal, respectively, and is used to control the potential of the first pull-down node according to the first voltage signal provided by the first voltage terminal under the control of the first control voltage provided by the first control voltage terminal and the potential of the first pull-up node.

[0026] The nth output reset circuit is electrically connected to the first pull-down node, the second voltage terminal, and the nth drive signal output terminal, respectively, and is used to control the connection between the nth drive signal output terminal and the second voltage terminal under the control of the potential of the first pull-down node.

[0027] Optionally, the driving circuit further includes a first carry signal output terminal and a first carry output sub-circuit;

[0028] The first carry output sub-circuit is electrically connected to the first pull-up node, the first carry signal output terminal, and the first carry clock signal terminal, respectively, and is used to control the connection between the first carry signal output terminal and the first carry clock signal terminal under the control of the potential of the first pull-up node.

[0029] Optionally, the driving circuit further includes a first carry-reset sub-circuit;

[0030] The first carry reset sub-circuit is electrically connected to the first pull-down node, the first carry signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the first carry signal output terminal and the first voltage terminal under the control of the potential of the first pull-down node.

[0031] Optionally, the first input sub-circuit is electrically connected to the first input terminal, the first input voltage terminal, and the first pull-up node, respectively, and is used to control the connection between the first pull-up node and the first input voltage terminal under the control of the first input signal provided by the first input terminal;

[0032] The first input terminal is the first carry signal output terminal of the adjacent upper-level driving circuit;

[0033] The first input voltage terminal is the first carry signal output terminal of the adjacent upper-level driving circuit, the c-th driving signal output terminal of the adjacent upper-level driving circuit, or the third voltage terminal; c is a positive integer less than or equal to N.

[0034] Optionally, the first carry clock signal terminal is the c-th clock signal terminal among the N clock signal terminals;

[0035] The first pull-down sub-circuit is also electrically connected to the first input voltage terminal, and is used to control the connection between the first pull-down node and the first voltage terminal under the control of the first input voltage provided by the first input voltage terminal;

[0036] The first input sub-circuit is also electrically connected to the frame reset terminal and is also used to control the connection between the first pull-up node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

[0037] Optionally, the driving circuit further includes N capacitors;

[0038] The first terminal of the nth capacitor among the N capacitors is electrically connected to the first pull-up node, and the second terminal of the nth capacitor among the N capacitors is electrically connected to the nth drive signal output terminal.

[0039] Optionally, the first input sub-circuit includes a first transistor, the first pull-down sub-circuit includes a second transistor and a third transistor, and the first pull-down node control sub-circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0040] The control electrode of the first transistor is electrically connected to the first input terminal, the first electrode of the first transistor is electrically connected to the first input voltage terminal, and the second electrode of the first transistor is electrically connected to the first pull-up node.

[0041] The control terminal of the second transistor is electrically connected to the first reset terminal, the first terminal of the second transistor is electrically connected to the first pull-up node, and the second terminal of the second transistor is electrically connected to the first voltage terminal.

[0042] The control electrode of the third transistor is electrically connected to the first pull-down node, the first electrode of the third transistor is electrically connected to the first pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal.

[0043] The control electrode and the first electrode of the fourth transistor are both electrically connected to the first control voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first pull-down control node.

[0044] The control electrode of the fifth transistor is electrically connected to the first pull-down control node, the first electrode of the fifth transistor is electrically connected to the first control voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first pull-down node.

[0045] The control electrode of the sixth transistor is electrically connected to the first pull-up node, the first electrode of the sixth transistor is electrically connected to the first pull-down node, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0046] The control electrode of the seventh transistor is electrically connected to the first pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down control node, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal.

[0047] Optionally, the first pull-down sub-circuit includes an eighth transistor, and the first input sub-circuit further includes a ninth transistor;

[0048] The control electrode of the eighth transistor is electrically connected to the first input voltage terminal, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first voltage terminal.

[0049] The control electrode of the ninth transistor is electrically connected to the frame reset terminal, the first electrode of the ninth transistor is electrically connected to the first pull-up node, and the second electrode of the ninth transistor is electrically connected to the first voltage terminal.

[0050] Optionally, the nth output sub-circuit includes the nth output transistor;

[0051] The control terminal of the nth output transistor is electrically connected to the first pull-up node, the first terminal of the nth output transistor is electrically connected to the nth clock signal terminal, and the second terminal of the nth output transistor is electrically connected to the nth drive signal output terminal.

[0052] The first carry output sub-circuit includes a first carry output transistor;

[0053] The control terminal of the first carry output transistor is electrically connected to the first pull-up node, the first terminal of the first carry output transistor is electrically connected to the first carry clock signal terminal, and the second terminal of the first carry output transistor is electrically connected to the first carry signal output terminal.

[0054] The nth output reset sub-circuit includes the nth output reset transistor;

[0055] The control electrode of the nth output reset transistor is electrically connected to the first pull-down node, the first electrode of the nth output reset transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth output reset transistor is electrically connected to the second voltage terminal.

[0056] Optionally, the first carry reset sub-circuit includes a first carry reset transistor;

[0057] The control electrode of the first carry reset transistor is electrically connected to the first pull-down node, the first electrode of the first carry reset transistor is electrically connected to the first carry signal output terminal, and the second electrode of the first carry reset transistor is electrically connected to the first voltage terminal.

[0058] Optionally, the driving circuit further includes a first on / off control sub-circuit;

[0059] The first on / off control sub-circuit is electrically connected to the touch enable terminal, the first connection node, and the first pull-up node, respectively, and is used to control the connection or disconnection between the first connection node and the first pull-up node under the control of the touch enable signal provided by the touch enable terminal.

[0060] Optionally, the first on / off control sub-circuit includes a first on / off control transistor;

[0061] The control electrode of the first on / off control transistor is electrically connected to the touch enable terminal, the first electrode of the first on / off control transistor is connected to the first pull-up node, and the second electrode of the first on / off control transistor is electrically connected to the first connection node.

[0062] Optionally, the driving circuit further includes a first output capacitor;

[0063] The first end of the first output capacitor is electrically connected to the pull-up node circuit, and the second end of the first output capacitor is electrically connected to one of the N drive signal output terminals.

[0064] Optionally, the driving circuit further includes M clock signal terminals, M output sub-circuits, a second carry output sub-circuit, M driving signal output terminals, and a second carry signal output terminal; the M output sub-circuits share a second pull-up node;

[0065] The N+m output sub-circuit is used to output the N+m drive signal through the N+m drive signal output terminal under the control of the potential of the second pull-up node, according to the N+m clock signal provided by the N+m clock signal terminal, where m is a positive integer less than or equal to M and M is a positive integer greater than or equal to 2.

[0066] The second carry output sub-circuit is electrically connected to the second pull-up node, the second carry signal output terminal, and the second carry clock signal terminal, respectively, and is used to control the connection between the second carry signal output terminal and the second carry clock signal terminal under the control of the potential of the second pull-up node.

[0067] Optionally, the driving circuit further includes M capacitors;

[0068] The first terminal of the m-th capacitor among the M capacitors is electrically connected to the second pull-up node, and the second terminal of the m-th capacitor among the M capacitors is electrically connected to the N+m-th drive signal output terminal.

[0069] Optionally, the driving circuit further includes a second input sub-circuit, a second pull-down sub-circuit, a second pull-down node control sub-circuit, and M output reset sub-circuits; the M output reset sub-circuits multiplex the second pull-down node;

[0070] The second input sub-circuit is used to control the potential of the second pull-up node under the control of the second input signal provided at the second input terminal;

[0071] The second pull-down sub-circuit is electrically connected to the second pull-up node, the second pull-down node, the second reset terminal, and the first voltage terminal, respectively. It is used to control the connection between the second pull-up node and the first voltage terminal under the control of the potential of the second pull-down node, and to control the connection between the second pull-up node and the first voltage terminal under the control of the second reset signal provided by the second reset terminal.

[0072] The second pull-down node control sub-circuit is electrically connected to the second control voltage terminal, the second pull-up node, the second pull-down node and the first voltage terminal respectively, and is used to control the potential of the second pull-down node according to the first voltage signal provided by the first voltage terminal under the control of the second control voltage provided by the second control voltage terminal and the potential of the second pull-up node;

[0073] The N+m output reset sub-circuit is electrically connected to the second pull-down node, the second voltage terminal, and the N+m drive signal output terminal, respectively, and is used to control the connection between the N+m drive signal output terminal and the second voltage terminal under the control of the potential of the second pull-down node.

[0074] Optionally, the driving circuit further includes a second carry reset circuit;

[0075] The second carry reset sub-circuit is electrically connected to the second pull-down node, the second carry signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the second carry signal output terminal and the first voltage terminal under the control of the potential of the second pull-down node.

[0076] Optionally, the second input sub-circuit is electrically connected to the second input terminal, the second input voltage terminal, and the second pull-up node, respectively, and is used to control the connection between the second pull-up node and the second input voltage terminal under the control of the second input signal provided by the second input terminal;

[0077] The second input terminal is the second carry signal output terminal of the adjacent upper-level driving circuit;

[0078] The second input voltage terminal is the second carry signal output terminal of the adjacent upper-level driving circuit, the d-th driving signal output terminal of the adjacent upper-level driving circuit, or the third voltage terminal; d is a positive integer less than or equal to M.

[0079] Optionally, the second carry clock signal terminal is the d-th clock signal terminal among the M clock signal terminals;

[0080] The second pull-down sub-circuit is also electrically connected to the second input voltage terminal, and is used to control the connection between the second pull-down node and the first voltage terminal under the control of the second input voltage provided by the second input voltage terminal;

[0081] The second input sub-circuit is also electrically connected to the frame reset terminal and is also used to control the connection between the second pull-up node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

[0082] Optionally, the driving circuit further includes M capacitors;

[0083] The first terminal of the m-th capacitor among the M capacitors is electrically connected to the second pull-up node, and the second terminal of the m-th capacitor among the M capacitors is electrically connected to the N+m-th drive signal output terminal.

[0084] Optionally, the first pull-down sub-circuit may further include a tenth transistor;

[0085] The control electrode of the tenth transistor is electrically connected to the second pull-down node, the first electrode of the tenth transistor is electrically connected to the first pull-up node, and the second electrode of the tenth transistor is electrically connected to the first voltage terminal.

[0086] The first pull-down node control sub-circuit also includes an eleventh transistor;

[0087] The control electrode of the eleventh transistor is electrically connected to the second pull-up node, the first electrode of the eleventh transistor is electrically connected to the first pull-down control node, and the second electrode of the eleventh transistor is electrically connected to the first voltage terminal.

[0088] Optionally, the nth output reset sub-circuit may further include an nth reset transistor;

[0089] The control electrode of the nth reset transistor is electrically connected to the second pull-down node, the first electrode of the nth reset transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth reset transistor is electrically connected to the second voltage terminal.

[0090] Optionally, the first carry reset sub-circuit may further include a second carry reset transistor;

[0091] The control electrode of the second carry reset transistor is electrically connected to the second pull-down node, the first electrode of the second carry reset transistor is electrically connected to the first carry signal output terminal, and the second electrode of the second carry reset transistor is electrically connected to the first voltage terminal.

[0092] Optionally, the second pull-down sub-circuit includes a twelfth transistor;

[0093] The control electrode of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the second pull-up node, and the second electrode of the twelfth transistor is electrically connected to the first voltage terminal.

[0094] The second pull-down node control sub-circuit includes a thirteenth transistor;

[0095] The control electrode of the thirteenth transistor is electrically connected to the first pull-up node, the first electrode of the thirteenth transistor is electrically connected to the second pull-down control node, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal.

[0096] Optionally, the (N+m)th output reset sub-circuit includes the (N+m)th reset transistor;

[0097] The control electrode of the N+m reset transistor is electrically connected to the first pull-down node, the first electrode of the N+m reset transistor is electrically connected to the N+m drive signal output terminal, and the second electrode of the N+m reset transistor is electrically connected to the second voltage terminal.

[0098] Optionally, the second carry reset sub-circuit includes a third carry reset transistor and a fourth carry reset transistor;

[0099] The control electrode of the third carry reset transistor is electrically connected to the second pull-down node, the first electrode of the third carry reset transistor is electrically connected to the second carry signal output terminal, and the second electrode of the third carry reset transistor is electrically connected to the first voltage terminal.

[0100] The control electrode of the fourth carry reset transistor is electrically connected to the first pull-down node, the first electrode of the fourth carry reset transistor is electrically connected to the second carry signal output terminal, and the second electrode of the fourth carry reset transistor is electrically connected to the first voltage terminal.

[0101] Optionally, the driving circuit further includes a second on / off control sub-circuit;

[0102] The second on / off control sub-circuit is electrically connected to the touch enable terminal, the second connection node, and the second pull-up node, respectively, and is used to control the connection or disconnection between the second connection node and the second pull-up node under the control of the touch enable signal provided by the touch enable terminal.

[0103] Optionally, the second on / off control sub-circuit includes a second on / off control transistor;

[0104] The control electrode of the second on / off control transistor is electrically connected to the touch enable terminal, the first electrode of the second on / off control transistor is connected to the second pull-up node, and the second electrode of the second on / off control transistor is electrically connected to the second connection node.

[0105] Optionally, the display driving circuit described in at least one embodiment of this disclosure includes a second output capacitor;

[0106] The first end of the second output capacitor is electrically connected to the second pull-up node, and the second end of the second output capacitor is electrically connected to one of the drive signal output terminals of the M drive signal output terminals.

[0107] In a second aspect, embodiments of this disclosure provide a display device including the display driving circuit described above.

[0108] Optionally, the display device described in at least one embodiment of this disclosure further includes multiple rows of gate lines, multiple columns of data lines, and multiple rows and columns of pixel circuits;

[0109] The pixel circuit includes a display control transistor and pixel electrodes;

[0110] The gate of the display control transistor is electrically connected to the gate line, the first electrode of the display control transistor is electrically connected to the data line, and the second electrode of the display control transistor is electrically connected to the pixel electrode.

[0111] The pixel electrode has multiple slits; the angle between the slit directions of two pixel electrodes in the same pixel electrode group is greater than 90 degrees and less than 180 degrees.

[0112] The pixel electrode group is a pixel electrode group disposed in the display area formed by adjacent row grid lines and adjacent column data lines.

[0113] Optionally, two rows of gate lines are provided between two adjacent rows of pixel electrodes;

[0114] The gate of one of the two transistors electrically connected to the same column of data lines is electrically connected to one of the gate lines in the two rows of gate lines, and the gate of the other transistor of the two transistors electrically connected to the same column of data lines is electrically connected to the other gate line in the two rows of gate lines.

[0115] The width of the conductive connection portion between two transistors electrically connected to the same column of data lines and that column of data lines along the first direction is greater than the minimum width of the data lines along the first direction.

[0116] The first direction is the extension direction of the gate line.

[0117] Optionally, the display device described in at least one embodiment of this disclosure further includes multiple rows and columns of common electrodes;

[0118] Adjacent rows of common electrodes are electrically connected by jumper wires, which are disposed on the same layer as the pixel electrodes.

[0119] Optionally, the pixel electrodes corresponding to both ends of the jumper wire have a clearance portion.

[0120] Optionally, at the intersection of the jumper wire and the gate wire, the linewidth of the gate wire is less than the maximum linewidth of the gate wire. Attached Figure Description

[0121] Figure 1 These are waveforms of the first and second clock signals.

[0122] Figure 2 This is a waveform diagram of the potential of the first pull-up node;

[0123] Figure 3 This is a structural diagram of at least one embodiment of the driving circuit in the display driving circuit described in this disclosure;

[0124] Figure 4 This is a structural diagram of at least one embodiment of the driving circuit;

[0125] Figure 5 This is a structural diagram of at least one embodiment of the driving circuit;

[0126] Figure 6 This is a structural diagram of at least one embodiment of the driving circuit;

[0127] Figure 7 This is a structural diagram of at least one embodiment of the driving circuit;

[0128] Figure 8 This is a circuit diagram of at least one embodiment of the driving circuit;

[0129] Figure 9 yes Figure 8 The timing diagram of at least one embodiment of the driving circuit shown;

[0130] Figure 10 This is a circuit diagram of at least one embodiment of the driving circuit;

[0131] Figure 11 This is a public announcement Figure 10 The waveform diagram of the potential of the first pull-up node PU1 when at least one embodiment of the driving circuit shown is in operation;

[0132] Figure 12 This is a circuit diagram of at least one embodiment of the driving circuit;

[0133] Figure 13 This is a circuit diagram of at least one embodiment of the driving circuit;

[0134] Figure 14 This is a circuit diagram of at least one embodiment of the driving circuit;

[0135] Figure 15 This is a circuit diagram of at least one embodiment of the driving circuit;

[0136] Figure 16 This is a circuit diagram of at least one embodiment of the driving circuit;

[0137] Figure 17 This is a circuit diagram of at least one embodiment of the driving circuit;

[0138] Figure 18 This is a circuit diagram of at least one embodiment of the driving circuit;

[0139] Figure 19 This is a circuit diagram of at least one embodiment of the driving circuit;

[0140] Figure 20 This is a circuit diagram of at least one embodiment of the driving circuit;

[0141] Figure 21 This is a circuit diagram of at least one embodiment of the driving circuit;

[0142] Figure 22 This is a circuit diagram of at least one embodiment of the driving circuit;

[0143] Figure 23 This is a circuit diagram of at least one embodiment of the driving circuit;

[0144] Figure 24 This is a circuit diagram of at least one embodiment of the driving circuit;

[0145] Figure 25 This is a circuit diagram of at least one embodiment of the driving circuit;

[0146] Figure 26 yes Figure 25 The timing diagram of at least one embodiment of the driving circuit shown;

[0147] Figure 27 This is a circuit diagram of at least one embodiment of the driving circuit;

[0148] Figure 28 This is a circuit diagram of at least one embodiment of the driving circuit;

[0149] Figure 29 This is a structural diagram of the display driving circuit according to at least one embodiment of the present disclosure;

[0150] Figure 30 It shows the waveforms of ten clock signals;

[0151] Figure 31 This is a structural diagram of the display driving circuit according to at least one embodiment of the present disclosure;

[0152] Figure 32 This is a structural diagram of a portion of the display driving circuit described in at least one embodiment of this disclosure;

[0153] Figure 33 This is a structural diagram of a portion of the display driving circuit described in at least one embodiment of this disclosure;

[0154] Figure 34 This is a structural diagram of the display substrate in the display device according to at least one embodiment of the present disclosure;

[0155] Figure 35A , Figure 35B and Figure 35C Is Figure 34 The layout diagram of the display substrate including each pixel circuit is shown in at least one embodiment.

[0156] Figure 36 yes Figure 35BThe layout diagram of the common electrode, the gate of each display control transistor, and each gate line;

[0157] Figure 37 yes Figure 35B The layout diagram of the data lines, the source of each display control transistor, the drain of each display control transistor, and the active layer of each display control transistor.

[0158] Figure 38 yes Figure 35B The layout diagram of the pixel electrodes and jumpers. Detailed Implementation

[0159] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0160] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0161] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0162] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0163] The display driving circuit described in this embodiment includes two gate driving circuits, which are respectively disposed on opposite sides of the display panel; the gate driving circuit includes multiple cascaded driving circuits.

[0164] The driving circuit includes N clock signal terminals, N output sub-circuits, and N driving signal output terminals; N is an integer greater than or equal to 2; the N output sub-circuits share a first pull-up node;

[0165] The nth output sub-circuit is used to control the output of the nth drive signal through the nth drive signal output terminal under the control of the potential of the first pull-up node, according to the nth clock signal provided by the nth clock signal terminal; n is a positive integer less than or equal to N;

[0166] The i-th drive signal output terminal of one of the two drive circuits is electrically connected to the i+j-th drive signal output terminal of the other drive circuit. i and j are both positive integers, i is a positive integer less than or equal to N, j is a positive integer less than or equal to N, and i+j is a positive integer less than or equal to N.

[0167] When the potential of the i-th clock signal provided by the i-th clock signal terminal among the N clock signal terminals changes from an invalid level to an active level, the potential of the first pull-up node is a first voltage value; when the potential of the (i+j)-th clock signal provided by the (i+j)-th clock signal terminal among the N clock signal terminals changes from an invalid level to an active level, the potential of the first pull-up node is a second voltage value; the first voltage value and the second voltage value are not equal.

[0168] The time period during which the potential of the i-th clock signal remains at an effective level and the time period during which the potential of the (i+j)-th clock signal remains at an effective level at least partially overlap.

[0169] The time point at which the potential of the i-th clock signal changes from an active level to an inactive level is different from the time point at which the potential of the (i+j)-th clock signal changes from an active level to an inactive level.

[0170] In the display driving circuit described in the embodiments of this disclosure, the driving capabilities of the driving signals output by different driving signal output terminals of the same driving circuit are different. The i-th driving signal output terminal of one of the two driving circuits is electrically connected to the i+j-th driving signal output terminal of the other driving circuit in the two driving circuits to form a complement, so that the driving capability of the driving signal received by each row of gate lines (the left end of the gate line can be electrically connected to the i-th driving signal output terminal, for example, and the right end of the gate line can be electrically connected to the i+j-th driving signal output terminal, for example) is approximately the same, thereby improving the display quality of the display screen.

[0171] In at least one embodiment of this disclosure, the N output sub-circuits share a first pull-up node, thereby reducing the number of transistors controlling the potential of the pull-up node, which is beneficial for achieving a narrow bezel.

[0172] In at least one embodiment of this disclosure, when the transistor controlled by the drive signal is an n-type transistor, the effective level can be a high level and the ineffective level can be a low level; or, when the transistor controlled by the drive signal is a p-type transistor, the effective level can be a low level and the ineffective level can be a high level.

[0173] However, this is not the only limit.

[0174] In at least one embodiment of this disclosure, the ratio between the first voltage value and the second voltage value can be greater than or equal to 0.4 and less than or equal to 1. For example, the ratio between the first voltage value and the second voltage value can be 0.5, 0.52, 0.55, 0.57, 0.6, 0.65, 0.62, 0.67, 0.7, 0.72, 0.75 or 0.8, 0.82, 0.85, 0.9, 0.92, 0.95, etc., but is not limited thereto.

[0175] In at least one embodiment of this disclosure, the gate driving circuits disposed on opposite sides of the display panel may have identical structures. The first gate driving circuit may be disposed on the first side of the display panel, and the second gate driving circuit may be disposed on the second side of the display panel. The first side and the second side may be opposite sides. In this case, the (i+j)th clock signal may be the (i+j)th clock signal among the N clock signals input to the first gate driving circuit, or it may be the (i+j)th clock signal among the N clock signals input to the second gate driving circuit.

[0176] Optionally, the first side can be the left side and the second side can be the right side, but this is not a limitation.

[0177] In at least one embodiment of this disclosure, N equals 2 as an example. However, in actual operation, N can also be any integer greater than 2, such as 3, 4, 5, etc.

[0178] In at least one embodiment of this disclosure, when the potential of the i-th clock signal changes from an active level to an inactive level, the potential of the first pull-up node is a third voltage value; when the potential of the (i+j)-th clock signal changes from an active level to an inactive level, the potential of the first pull-up node is a fourth voltage value.

[0179] The third voltage value is not equal to the fourth voltage value.

[0180] Optionally, the ratio between the fourth voltage value and the third voltage value can be greater than or equal to 0.4 and less than or equal to 1. For example, the ratio between the fourth voltage value and the third voltage value can be 0.5, 0.55, 0.6, 0.65 or 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, but is not limited thereto.

[0181] In at least one embodiment of this disclosure, when the potential of the i-th clock signal jumps from an invalid level to an effective level, the potential of the first pull-up node rises by a first potential height within a first time period.

[0182] When the potential of the (i+j)th clock signal changes from an invalid level to an effective level, the potential of the first pull-up node rises by a second potential height within the second time period.

[0183] The first potential height is not equal to the second potential height, and / or the first time is not equal to the second time.

[0184] Optionally, the ratio between the second potential height and the first potential height can be greater than or equal to 0.5 and less than or equal to 4. For example, the ratio between the second potential height and the first potential height can be 0.5, 1, 1.5, 2, 2.4, 2.8, 3, 3.2, 3.6 or 4.

[0185] Optionally, the ratio between the second time and the first time can be greater than or equal to 1 and less than or equal to 4. For example, the ratio between the second time and the first time can be 1.2, 1.4, 1.6, 2, 2.4, 2.5, 2.6, or 3, 3.4, 3.6, 3.8, etc., but is not limited thereto.

[0186] In at least one embodiment of this disclosure, when the potential of the i-th clock signal jumps from an active level to an inactive level, the potential of the first pull-up node drops by a third potential height within a third time period;

[0187] When the potential of the (i+j)th clock signal changes from an active level to an inactive level, the potential of the first pull-up node drops by a fourth potential height within the fourth time period.

[0188] The third potential height is not equal to the fourth potential height, and / or the third time is not equal to the fourth time.

[0189] Optionally, the ratio between the fourth potential height and the third potential height can be greater than or equal to 0.4 and less than or equal to 1.5. For example, the ratio between the fourth potential height and the third potential height can be 0.4, 0.6, 0.89, 0.7, 0.8, 0.9, 1, 1.2, 1.3, 1.4 or 1.5, but is not limited thereto.

[0190] Optionally, the ratio between the fourth time and the third time can be greater than or equal to 1 and less than or equal to 5. For example, the ratio between the fourth time and the third time can be 1.5, 1.8, 2, 2.4, 2.8, 3, 3.2, 3.6, 3.8 or 4, 4.8, etc., but is not limited thereto.

[0191] In at least one embodiment of this disclosure, the driving circuit includes a capacitor disposed between the a-th driving signal terminal and the first pull-up node, wherein the first time is less than the second time, and the first potential height is less than the second potential height; a is an even number, a is a positive integer; or;

[0192] The driving circuit includes a capacitor disposed between the b-th driving signal terminal and the first pull-up node, wherein the first time is greater than the second time, and the first potential height is greater than the second potential height; b is an odd number and b is a positive integer.

[0193] In practical implementation, the capacitor can be placed between the even-numbered drive signal output terminal and the first pull-up node to reduce the pull-down effect on the potential of the first pull-up node when the odd-numbered row drive signal output terminal is pulled down; or,

[0194] The capacitor can be placed between the odd-numbered drive signal output terminal and the first pull-up node to reduce the pull-down effect on the potential of the first pull-up node when the odd-numbered drive signal output terminal is pulled down.

[0195] Optionally, the driving circuit includes a capacitor disposed between the a-th driving signal terminal and the first pull-up node, the third time is less than the fourth time, and the third potential height is greater than the fourth potential height; a is an even number, a is a positive integer; or;

[0196] The driving circuit includes a capacitor disposed between the b-th driving signal terminal and the first pull-up node, the third time is greater than the fourth time, and the third potential height is less than the fourth potential height; b is an odd number and b is a positive integer.

[0197] In at least one embodiment of this disclosure, the driving circuit further includes a first input sub-circuit, a first pull-down sub-circuit, a first pull-down node control sub-circuit, and N output reset sub-circuits; the N output reset sub-circuits multiplex the first pull-down node;

[0198] The first input sub-circuit is used to control the potential of the first pull-up node under the control of the first input signal provided at the first input terminal;

[0199] The first pull-down sub-circuit is electrically connected to the first pull-up node, the first pull-down node, the first reset terminal, and the first voltage terminal, respectively, and is used to control the connection between the first pull-up node and the first voltage terminal under the control of the potential of the first pull-down node, and to control the connection between the first pull-up node and the first voltage terminal under the control of the first reset signal provided by the first reset terminal.

[0200] The first pull-down node control sub-circuit is electrically connected to the first control voltage terminal, the first pull-up node, the first pull-down node, and the first voltage terminal, respectively, and is used to control the potential of the first pull-down node according to the first voltage signal provided by the first voltage terminal under the control of the first control voltage provided by the first control voltage terminal and the potential of the first pull-up node.

[0201] The nth output reset circuit is electrically connected to the first pull-down node, the second voltage terminal, and the nth drive signal output terminal, respectively, and is used to control the connection between the nth drive signal output terminal and the second voltage terminal under the control of the potential of the first pull-down node.

[0202] In at least one embodiment of this disclosure, the N output reset sub-circuits reuse the first pull-down node to reduce the number of transistors controlling the potential of the pull-down node, which is beneficial for achieving a narrow bezel.

[0203] In at least one embodiment of this disclosure, the first drive signal output terminal of one of the two drive circuits is electrically connected to the second drive signal output terminal of the other drive circuit; both the one drive circuit and the other drive circuit are connected to the first clock signal terminal and the second clock signal terminal.

[0204] like Figure 2 As shown, when the potential of the first clock signal provided by the first clock signal terminal K1 changes from low level to high level, the potential of the first pull-up node PU1 is the first voltage value Vb1; when the potential of the second clock signal provided by the second clock signal terminal K2 changes from low level to high level, the potential of the first pull-up node PU1 is the second voltage value Vb2; the first voltage value Vb1 and the second voltage value Vb2 are not equal.

[0205] like Figure 1As shown, the time period during which the potential of the first clock signal remains high and the time period during which the potential of the second clock signal remains high at least partially overlap; the time point at which the potential of the first clock signal transitions from high to low is different from the time point at which the potential of the second clock signal transitions from high to low.

[0206] exist Figure 2 In the diagram, time t1 is the first time, time t2 is the second time, time t3 is the third time, and time t4 is the fourth time.

[0207] The following describes the display driving circuit of at least one embodiment of this disclosure, taking N equal to 2 as an example.

[0208] like Figure 3 As shown, in at least one embodiment of this disclosure, the driving circuit includes a first clock signal terminal K1, a second clock signal terminal K2, a first output sub-circuit 111, a second output sub-circuit 112, a first driving signal output terminal G1, and a second driving signal output terminal G2.

[0209] The first output sub-circuit 111 and the second output sub-circuit 112 share the first pull-up node PU1;

[0210] The first output sub-circuit 111 is electrically connected to the first pull-up node PU1, the first clock signal terminal K1, and the first drive signal output terminal G1, respectively. It is used to control the output of the first drive signal through the first drive signal output terminal G1 according to the first clock signal provided by the first clock signal terminal K1 under the control of the potential of the first pull-up node PU1.

[0211] The second output sub-circuit 112 is electrically connected to the first pull-up node PU1, the second clock signal terminal K2, and the second drive signal output terminal G2, respectively. It is used to control the output of the second drive signal through the second drive signal output terminal G2 according to the second clock signal provided by the second clock signal terminal K2 under the control of the potential of the first pull-up node PU1.

[0212] The driving circuit further includes a first input sub-circuit 12, a first pull-down sub-circuit 13, a first pull-down node control sub-circuit 14, a first output reset sub-circuit 151, and a second output reset sub-circuit 152; the first output reset sub-circuit 151 and the second output reset sub-circuit 152 multiplex the first pull-down node PD1;

[0213] The first input sub-circuit 12 is electrically connected to the first input terminal I1 and the first pull-up node PU1 respectively, and is used to control the potential of the first pull-up node PU1 under the control of the first input signal provided by the first input terminal I1;

[0214] The first pull-down sub-circuit 13 is electrically connected to the first pull-up node PU1, the first pull-down node PD1, the first reset terminal R1 and the first voltage terminal V1 respectively. It is used to control the connection between the first pull-up node PU1 and the first voltage terminal V1 under the control of the potential of the first pull-down node PD1, and to control the connection between the first pull-up node PU1 and the first voltage terminal V1 under the control of the first reset signal provided by the first reset terminal R1.

[0215] The first pull-down node control sub-circuit 14 is electrically connected to the first control voltage terminal VDDO, the first pull-up node PU1, the first pull-down node PD1 and the first voltage terminal V1 respectively, and is used to control the potential of the first pull-down node PD1 according to the first voltage signal provided by the first voltage terminal V1 under the control of the first control voltage provided by the first control voltage terminal VDDO and the potential of the first pull-up node PU1.

[0216] The first output reset sub-circuit 151 is electrically connected to the first pull-down node PD1, the second voltage terminal V2 and the first drive signal output terminal G1 respectively, and is used to control the connection between the first drive signal output terminal G1 and the second voltage terminal V2 under the control of the potential of the first pull-down node PD1.

[0217] The second output reset sub-circuit 152 is electrically connected to the first pull-down node PD1, the second voltage terminal V2, and the second drive signal output terminal G2, respectively, and is used to control the connection between the second drive signal output terminal G2 and the second voltage terminal V2 under the control of the potential of the first pull-down node PD1.

[0218] Optionally, the first voltage terminal can be a first low voltage terminal, and the second voltage terminal can be a second low voltage terminal. Optionally, the voltage value of the first low voltage signal provided by the first low voltage terminal is lower than the voltage value of the second low voltage signal provided by the second low voltage terminal, but this is not a limitation.

[0219] In at least one embodiment of this disclosure, the driving circuit further includes a first carry signal output terminal and a first carry output sub-circuit;

[0220] The first carry output sub-circuit is electrically connected to the first pull-up node, the first carry signal output terminal, and the first carry clock signal terminal, respectively, and is used to control the connection between the first carry signal output terminal and the first carry clock signal terminal under the control of the potential of the first pull-up node.

[0221] In a specific implementation, the first carry output sub-circuit is used to control the first carry signal output terminal to output the first carry signal, and the first carry signal output terminal can be used for cascading.

[0222] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first carry signal output terminal Co1 and a first carry output sub-circuit 41;

[0223] The first carry output sub-circuit 41 is electrically connected to the first pull-up node PU1, the first carry signal output terminal Co1, and the first carry clock signal terminal Kc1, respectively, and is used to control the first carry signal output terminal Co1 to be electrically connected to the first carry clock signal terminal Kc1 under the control of the potential of the first pull-up node PU1.

[0224] In at least one embodiment of this disclosure, the first carry clock signal terminal Kc1 may be different from the clock signal terminals among the N clock signal terminals. That is, an independent carry clock signal terminal is used for carry, so that carry can be independently controlled.

[0225] Optionally, the driving circuit further includes a first carry-reset sub-circuit;

[0226] The first carry reset sub-circuit is electrically connected to the first pull-down node, the first carry signal output terminal, and the first voltage terminal, respectively. It is used to control the connection between the first carry signal output terminal and the first voltage terminal under the control of the potential of the first pull-down node, so as to reset the potential of the first carry signal output by the first carry signal output terminal.

[0227] like Figure 5 As shown, in Figure 4 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first carry-reset sub-circuit 51;

[0228] The first carry reset sub-circuit 51 is electrically connected to the first pull-down node PD1, the first carry signal output terminal Co1, and the first voltage terminal V1, respectively. It is used to control the connection between the first carry signal output terminal Co1 and the first voltage terminal V1 under the control of the potential of the first pull-down node PD1, so as to reset the potential of the first carry signal output by the first carry signal output terminal Co1.

[0229] In at least one embodiment of this disclosure, the first input sub-circuit is electrically connected to the first input terminal, the first input voltage terminal, and the first pull-up node, respectively, and is used to control the connection between the first pull-up node and the first input voltage terminal under the control of the first input signal provided by the first input terminal;

[0230] The first input terminal is the first carry signal output terminal of the adjacent upper-level driving circuit;

[0231] The first input voltage terminal is the first carry signal output terminal of the adjacent upper-level driving circuit, the c-th driving signal output terminal of the adjacent upper-level driving circuit, or the third voltage terminal; c is a positive integer less than or equal to N. It should be noted that the adjacent upper level here can refer to the adjacent previous level, or several levels, such as two, three, four, five, etc., which are not limited here.

[0232] In a specific implementation, the first input terminal can be the first carry signal output terminal of the adjacent upper-level driving circuit, and the first input voltage terminal can be the first carry signal output terminal of the adjacent upper-level driving circuit, the c-th driving signal output terminal of the adjacent upper-level driving circuit, or the third voltage terminal.

[0233] like Figure 6 As shown, in Figure 5 Based on at least one embodiment of the driving circuit shown, the first input sub-circuit 12 is electrically connected to the first input terminal I1, the first input voltage terminal VI1 and the first pull-up node PU1, respectively, and is used to control the connection between the first pull-up node PU1 and the first input voltage terminal VI1 under the control of the first input signal provided by the first input terminal I1.

[0234] Optionally, the first carry clock signal terminal is the c-th clock signal terminal among the N clock signal terminals; that is, one of the N clock signal terminals can be reused as the first carry clock signal terminal.

[0235] The first input voltage terminal is either the first carry signal output terminal of the adjacent upper-level driving circuit or the c-th driving signal output terminal included in the adjacent upper-level driving circuit.

[0236] In at least one embodiment of this disclosure, the first carry clock signal terminal can be one of the N clock signal terminals. In this case, the first input voltage terminal can be the first carry signal output terminal of the adjacent upper-level driving circuit or the c-th driving signal output terminal included in the adjacent upper-level driving circuit.

[0237] In at least one embodiment of this disclosure, the first pull-down sub-circuit may also be electrically connected to the first input voltage terminal, for controlling the connection between the first pull-down node and the first voltage terminal under the control of the first input voltage provided by the first input voltage terminal;

[0238] The first input sub-circuit can also be electrically connected to the frame reset terminal, and is also used to control the connection between the first pull-up node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal.

[0239] like Figure 7 As shown, in Figure 6Based on at least one embodiment of the driving circuit shown, the first pull-down sub-circuit 13 can also be electrically connected to the first input voltage terminal VI1, and is used to control the connection between the first pull-down node PD1 and the first voltage terminal V1 under the control of the first input voltage provided by the first input voltage terminal VI1, so as to reset the potential of the first pull-down node PD1.

[0240] The first input sub-circuit 12 can also be electrically connected to the frame reset terminal TR, and is also used to control the connection between the first pull-up node PU1 and the first voltage terminal V1 under the control of the frame reset signal provided by the frame reset terminal TR, so as to reset the potential of the first pull-up node PU1.

[0241] The display driving circuit described in at least one embodiment of this disclosure may further include N capacitors;

[0242] The first terminal of the nth capacitor among the N capacitors is electrically connected to the first pull-up node, and the second terminal of the nth capacitor among the N capacitors is electrically connected to the nth drive signal output terminal.

[0243] In at least one embodiment of this disclosure, the display driving circuit may further include N capacitors, with one capacitor provided at each driving signal output terminal and the first pull-up node.

[0244] Optionally, the first input sub-circuit includes a first transistor, the first pull-down sub-circuit includes a second transistor and a third transistor, and the first pull-down node control sub-circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0245] The control electrode of the first transistor is electrically connected to the first input terminal, the first electrode of the first transistor is electrically connected to the first input voltage terminal, and the second electrode of the first transistor is electrically connected to the first pull-up node.

[0246] The control terminal of the second transistor is electrically connected to the first reset terminal, the first terminal of the second transistor is electrically connected to the first pull-up node, and the second terminal of the second transistor is electrically connected to the first voltage terminal.

[0247] The control electrode of the third transistor is electrically connected to the first pull-down node, the first electrode of the third transistor is electrically connected to the first pull-up node, and the second electrode of the third transistor is electrically connected to the first voltage terminal.

[0248] The control electrode and the first electrode of the fourth transistor are both electrically connected to the first control voltage terminal, and the second electrode of the fourth transistor is electrically connected to the first pull-down control node.

[0249] The control electrode of the fifth transistor is electrically connected to the first pull-down control node, the first electrode of the fifth transistor is electrically connected to the first control voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first pull-down node.

[0250] The control electrode of the sixth transistor is electrically connected to the first pull-up node, the first electrode of the sixth transistor is electrically connected to the first pull-down node, and the second electrode of the sixth transistor is electrically connected to the first voltage terminal.

[0251] The control electrode of the seventh transistor is electrically connected to the first pull-up node, the first electrode of the seventh transistor is electrically connected to the first pull-down control node, and the second electrode of the seventh transistor is electrically connected to the first voltage terminal.

[0252] Optionally, the first pull-down sub-circuit includes an eighth transistor, and the first input sub-circuit further includes a ninth transistor;

[0253] The control electrode of the eighth transistor is electrically connected to the first input voltage terminal, the first electrode of the eighth transistor is electrically connected to the first pull-down node, and the second electrode of the eighth transistor is electrically connected to the first voltage terminal.

[0254] The control electrode of the ninth transistor is electrically connected to the frame reset terminal, the first electrode of the ninth transistor is electrically connected to the first pull-up node, and the second electrode of the ninth transistor is electrically connected to the first voltage terminal.

[0255] Optionally, the nth output sub-circuit includes the nth output transistor;

[0256] The control terminal of the nth output transistor is electrically connected to the first pull-up node, the first terminal of the nth output transistor is electrically connected to the nth clock signal terminal, and the second terminal of the nth output transistor is electrically connected to the nth drive signal output terminal.

[0257] The first carry output sub-circuit includes a first carry output transistor;

[0258] The control terminal of the first carry output transistor is electrically connected to the first pull-up node, the first terminal of the first carry output transistor is electrically connected to the first carry clock signal terminal, and the second terminal of the first carry output transistor is electrically connected to the first carry signal output terminal.

[0259] The nth output reset sub-circuit includes the nth output reset transistor;

[0260] The control electrode of the nth output reset transistor is electrically connected to the first pull-down node, the first electrode of the nth output reset transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth output reset transistor is electrically connected to the second voltage terminal.

[0261] Optionally, the first carry reset sub-circuit includes a first carry reset transistor;

[0262] The control electrode of the first carry reset transistor is electrically connected to the first pull-down node, the first electrode of the first carry reset transistor is electrically connected to the first carry signal output terminal, and the second electrode of the first carry reset transistor is electrically connected to the first voltage terminal.

[0263] like Figure 8 As shown, in Figure 7 Based on at least one embodiment of the driving circuit shown,

[0264] The first input sub-circuit 12 includes a first transistor M1; the first pull-down sub-circuit 13 includes a second transistor M2 and a third transistor M3; the first pull-down node control sub-circuit 14 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; the driving circuit also includes a first capacitor C1 and a second capacitor C2.

[0265] The gate of the first transistor M1 is electrically connected to the first input terminal I1, the source of the first transistor M1 is electrically connected to the first input voltage terminal VI1, and the drain of the first transistor M1 is electrically connected to the first pull-up node PU1.

[0266] The gate of the second transistor M2 is electrically connected to the first reset terminal R1, the source of the second transistor M2 is electrically connected to the first pull-up node PU1, and the drain of the second transistor M2 is electrically connected to the first low voltage terminal LVSS.

[0267] The gate of the third transistor M3 is electrically connected to the first pull-down node PD1, the source of the third transistor M3 is electrically connected to the first pull-up node PU1, and the drain of the third transistor M3 is electrically connected to the first low-voltage terminal LVSS.

[0268] The gate and source of the fourth transistor M4 are both electrically connected to the first control voltage terminal VDDO, and the drain of the fourth transistor M4 is electrically connected to the first pull-down control node.

[0269] The gate of the fifth transistor M5 is electrically connected to the first pull-down control node, the source of the fifth transistor M5 is electrically connected to the first control voltage terminal VDDO, and the drain of the fifth transistor M5 is electrically connected to the first pull-down node PD1.

[0270] The gate of the sixth transistor M6 is electrically connected to the first pull-up node PU1, the source of the sixth transistor M6 is electrically connected to the first pull-down node PD1, and the drain of the sixth transistor M6 is electrically connected to the first low voltage terminal LVSS.

[0271] The gate of the seventh transistor M7 is electrically connected to the first pull-up node PU1, the source of the seventh transistor M7 is electrically connected to the first pull-down control node, and the drain of the seventh transistor M7 is electrically connected to the first low voltage terminal LVSS.

[0272] The first pull-down sub-circuit 13 includes an eighth transistor M8, and the first input sub-circuit 12 also includes a ninth transistor M9;

[0273] The gate of the eighth transistor M8 is electrically connected to the first input voltage terminal VI1, the source of the eighth transistor M8 is electrically connected to the first pull-down node PD1, and the drain of the eighth transistor M8 is electrically connected to the first low voltage terminal LVSS.

[0274] The gate of the ninth transistor M9 is electrically connected to the frame reset terminal TR, the source of the ninth transistor M9 is electrically connected to the first pull-up node PU1, and the drain of the ninth transistor M9 is electrically connected to the first low voltage terminal LVSS.

[0275] The first output sub-circuit 111 includes a first output transistor MO1; the second output sub-circuit 112 includes a second output transistor MO2;

[0276] The gate of the first output transistor MO1 is electrically connected to the first pull-up node PU1, the source of the first output transistor MO1 is electrically connected to the first clock signal terminal K1, and the drain of the first output transistor MO1 is electrically connected to the first drive signal output terminal G1.

[0277] The gate of the second output transistor MO2 is electrically connected to the first pull-up node PU1, the source of the second output transistor MO2 is electrically connected to the second clock signal terminal K2, and the drain of the second output transistor MO2 is electrically connected to the second drive signal output terminal G2.

[0278] The first carry output sub-circuit 41 includes a first carry output transistor MC1;

[0279] The gate of the first carry output transistor MC1 is electrically connected to the first pull-up node PU1, the source of the first carry output transistor MC1 is electrically connected to the first carry clock signal terminal KC1, and the drain of the first carry output transistor MC1 is electrically connected to the first carry signal output terminal Co1.

[0280] The first output reset sub-circuit 151 includes a first output reset transistor MF1; the second output reset circuit 152 includes a second output reset transistor MF2;

[0281] The gate of the first output reset transistor MF1 is electrically connected to the first pull-down node PD1, the source of the first output reset transistor MF1 is electrically connected to the first drive signal output terminal G1, and the drain of the first output reset transistor MF1 is electrically connected to the second low voltage terminal VSS.

[0282] The gate of the second output reset transistor MF2 is electrically connected to the first pull-down node PD1, the source of the second output reset transistor MF2 is electrically connected to the second drive signal output terminal G2, and the drain of the second output reset transistor MF2 is electrically connected to the second low voltage terminal VSS.

[0283] The first carry reset sub-circuit 51 includes a first carry reset transistor MR1;

[0284] The gate of the first carry reset transistor MR1 is electrically connected to the first pull-down node PD1, the source of the first carry reset transistor MR1 is electrically connected to the first carry signal output terminal Co1, and the drain of the first carry reset transistor MR1 is electrically connected to the first low voltage terminal LVSS.

[0285] The first terminal of the first capacitor C1 is electrically connected to the first pull-up node PU1, and the second terminal of the first capacitor C1 is electrically connected to the first drive signal output terminal G1.

[0286] The first end of the second capacitor C2 is electrically connected to the first pull-up node PU1, and the second end of the second capacitor C2 is electrically connected to the second drive signal output terminal G2.

[0287] exist Figure 8 In at least one embodiment of the driving circuit shown, all transistors may be n-type transistors, but are not limited thereto.

[0288] exist Figure 8 In at least one embodiment of the driving circuit shown, the gate and source of the first transistor M1 may be connected to different signals, but this is not a limitation; in actual operation, the gate and source of the first transistor M1 may also be connected to the same signal.

[0289] In at least one embodiment of this disclosure, the first input terminal I1 can be the first carry signal output terminal of an adjacent upper-level driving circuit;

[0290] According to one specific embodiment, the first input voltage terminal VI1 can be the first drive signal output terminal of the adjacent upper-level drive circuit.

[0291] According to another specific embodiment, the first input voltage terminal VI1 can be a high voltage terminal;

[0292] According to another specific embodiment, the first input voltage terminal VI1 can be the first carry signal output terminal of the adjacent upper-level driving circuit.

[0293] The optional term "adjacent parent level" can be the adjacent parent level or several adjacent parent levels; there is no limitation here.

[0294] In at least one embodiment of this disclosure, when the first input terminal I1 is the first carry signal output terminal of the adjacent upper-level driving circuit and the first input voltage terminal VI1 is the first drive signal output terminal of the adjacent upper-level driving circuit, the low voltage value of the signal provided by the first carry signal output terminal of the adjacent upper-level driving circuit can be controlled to be a volts and the low voltage value of the signal provided by the first drive signal output terminal of the adjacent upper-level driving circuit can be controlled to be b volts. a can be set to be less than b, so that when both the gate and the source of M1 are connected to the low voltage signal, the gate-source voltage of M1 is negative, thereby reducing the leakage current of M1.

[0295] In at least one embodiment of this disclosure, when the first input voltage terminal VI1 can be a high voltage terminal, during the time period when the potential of the first pull-up node PU1 is kept at a high level, the leakage current of M1 can continuously charge the capacitor to achieve a compensation effect.

[0296] In at least one embodiment of this disclosure, when the first input voltage terminal VI1 is the first carry signal output terminal of the adjacent upper-level driving circuit, the gate of M1 and the source of M1 can be electrically connected to each other.

[0297] Figure 9 This is a public announcement Figure 8 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0298] This disclosure is as follows Figure 8 When at least one embodiment of the driving circuit shown is in operation, I1 is electrically connected to the first carry signal output terminal of the adjacent upper-level driving circuit, and VI1 is electrically connected to the first drive signal output terminal of the adjacent upper-level driving circuit.

[0299] When I1 provides a high voltage signal, M1 turns on to pull up the potential of PU1 to a high voltage. At this time, K1, K2 and KC1 all provide low voltage signals, so G1, G2 and Co1 all output low voltage signals. M4 turns on, and M6 and M7 also turn on to control the potential of PD1 to a low voltage. The transistors whose gates are electrically connected to PD1 are all turned off.

[0300] Subsequently, the potential of the first clock signal provided by K1 jumps from low level to high level, and the potential of PU1 is adjusted to a higher potential. Within the first time t1, the potential of the first pull-up node PU1 rises to a first potential height, and the potential of the first pull-up node PU1 becomes the first voltage value Vb1.

[0301] Subsequently, the potential of the second clock signal provided by K2 jumps from low level to high level, and the potential of PU1 rises to a higher potential. During the second time t2, the potential of the first pull-up node PU1 rises to a second potential height, and the potential of the first pull-up node PU1 becomes the second voltage value Vb2.

[0302] Afterwards, the potential of the first clock signal provided by K1 jumps from high level to low level, and the potential of PU1 is lowered to a lower potential. During the third time t3, the potential of the first pull-up node PU1 drops by the third potential height, and the potential of the first pull-up node PU1 becomes the third voltage value Vb3.

[0303] Afterwards, the potential of the second clock signal provided by K2 jumps from high level to low level, and the potential of PU1 is lowered to a lower potential. During the fourth time t4, the potential of the first pull-up node PU1 drops by the fourth potential height, and the potential of the first pull-up node PU1 becomes the fourth voltage value Vb4. At this time, the potential of the first pull-up node PU1 can be low level.

[0304] When the potential of PU1 is high, MO1, MO2 and MC1 are turned on, G1 is connected to K1, G2 is connected to K2, Co1 is connected to KC1, G1 outputs the corresponding first drive signal, G2 outputs the corresponding second drive signal, and Co1 outputs the corresponding first carry signal.

[0305] When the potential of PU1 is low, M4 is turned on, M6 and M7 are turned off, the potential of the first pull-down control node is high, M5 is turned on, the potential of PD1 is high, MF1, MF2 and MR1 are turned on, and G1, G2 and Co1 all output low level.

[0306] exist Figure 8 In at least one embodiment of the driving circuit shown, a first capacitor C1 is provided between PU1 and G1, and a second capacitor C2 is provided between PU1 and G2.

[0307] In actual operation, a capacitor can be set only between PU1 and G2, or only between PU1 and G1.

[0308] Figure 10 At least one embodiment of the driving circuit shown is Figure 8 The difference in at least one embodiment of the driving circuit shown is that: no capacitor is provided between PU1 and G1; and a first output capacitor C01 is provided between PU1 and G2.

[0309] This disclosure is as follows Figure 10 When at least one embodiment of the driving circuit shown is in operation, I1 is electrically connected to the first carry signal output terminal of the adjacent upper-level driving circuit, and VI1 is electrically connected to the first drive signal output terminal of the adjacent upper-level driving circuit.

[0310] When I1 provides a high voltage signal, M1 is turned on, such as... Figure 11 As shown, the potential of PU1 is pulled up to a high voltage. At this time, K1, K2 and KC1 all provide low voltage signals, so G1, G2 and Co1 all output low voltage signals. M4 is turned on, and M6 and M7 are also turned on to control the potential of PD1 to a low voltage. The transistors whose gates are electrically connected to PD1 are all turned off.

[0311] Then, the potential of the first clock signal provided by K1 changes from low to high, as follows: Figure 11 As shown, the potential of PU1 is raised to a higher potential. Within the first time t1, the potential of the first pull-up node PU1 rises by a first potential height Vg1, and the potential of the first pull-up node PU1 becomes a first voltage value Vb1.

[0312] Then, the potential of the second clock signal provided by K2 jumps from low level to high level, such as... Figure 11 As shown, the potential of PU1 is raised to a higher potential. During the second time t2, the potential of the first pull-up node PU1 rises to a second potential height Vg2, and the potential of the first pull-up node PU1 becomes the second voltage value Vb2.

[0313] Then, the potential of the first clock signal provided by K1 changes from high level to low level, such as... Figure 11 As shown, the potential of PU1 is lowered to a lower potential. During the third time t3, the potential of the first pull-up node PU1 drops by the third potential height Vg3, and the potential of the first pull-up node PU1 becomes the third voltage value Vb3.

[0314] Then, the potential of the second clock signal provided by K2 changes from high to low, as follows: Figure 11As shown, the potential of PU1 is lowered to a lower potential. During the fourth time t4, the potential of the first pull-up node PU1 drops by the fourth potential height Vg4, and the potential of the first pull-up node PU1 becomes the fourth voltage value Vb4. At this time, the potential of the first pull-up node PU1 can be low level.

[0315] When the potential of PU1 is high, MO1, MO2 and MC1 are turned on, G1 is connected to K1, G2 is connected to K2, Co1 is connected to KC1, G1 outputs the corresponding first drive signal, G2 outputs the corresponding second drive signal, and Co1 outputs the corresponding first carry signal.

[0316] When the potential of PU1 is low, M4 is turned on, M6 and M7 are turned off, the potential of the first pull-down control node is high, M5 is turned on, the potential of PD1 is high, MF1, MF2 and MR1 are turned on, and G1, G2 and Co1 all output low level.

[0317] This disclosure is as follows Figure 10 In at least one embodiment of the driving circuit shown, when in operation, t1 can be greater than or equal to 2us and less than or equal to 6us, t2 can be greater than or equal to 5us and less than or equal to 14us, t3 can be greater than or equal to 2us and less than or equal to 6us, and t4 can be greater than or equal to 5us and less than or equal to 14us.

[0318] Vb1 can be greater than or equal to 18V and less than or equal to 30V, Vb2 can be greater than or equal to 30V and less than or equal to 36V, Vb3 can be greater than or equal to 18V and less than or equal to 30V, and Vb4 can be greater than or equal to 13V and less than or equal to 20V;

[0319] Vg1 can be greater than or equal to 2V and less than or equal to 12V, Vg2 can be greater than or equal to 6V and less than or equal to 18V, Vg3 can be greater than or equal to 6V and less than or equal to 18V, and Vg4 can be greater than or equal to 2V and less than or equal to 17V;

[0320] However, this is not the only limit.

[0321] In at least one embodiment of this disclosure, the first potential height Vg1 may be less than the second potential height Vg2, and the third potential height Vg3 may be greater than the fourth potential height Vg4; or;

[0322] The first potential height Vg1 can be greater than the second potential height Vg2, and the third potential height Vg3 can be less than the fourth potential height Vg4; or...

[0323] The first potential height Vg1 can be equal to the second potential height Vg2, and the third potential height Vg3 can be equal to the fourth potential height Vg4.

[0324] In at least one embodiment of this disclosure, the first time t1 may be less than the second time t2, and the third time t3 may be less than the fourth time t4; or,

[0325] The first time t1 can be less than the second time t2, and the third time t3 can be less than the fourth time t4; or...

[0326] The first time t1 can be greater than the second time t2, and the third time t3 can be greater than the fourth time t4; or...

[0327] The first time t1 can be equal to the second time t2, and the third time t3 can be equal to the fourth time t4.

[0328] In at least one embodiment of this disclosure, the ratio between the first voltage value Vb1 and the second voltage value Vb2 can be greater than or equal to 0.5 and less than or equal to 0.9;

[0329] The ratio between the fourth voltage value Vb4 and the third voltage value Vb3 can be greater than or equal to 0.4 and less than or equal to 0.9;

[0330] However, this is not the only limit.

[0331] In at least one embodiment of this disclosure, the driving circuit further includes a first on / off control sub-circuit;

[0332] The first on / off control sub-circuit is electrically connected to the touch enable terminal, the first connection node, and the first pull-up node, respectively, and is used to control the connection or disconnection between the first connection node and the first pull-up node under the control of the touch enable signal provided by the touch enable terminal.

[0333] Optionally, the first on / off control sub-circuit includes a first on / off control transistor;

[0334] The control electrode of the first on / off control transistor is electrically connected to the touch enable terminal, the first electrode of the first on / off control transistor is connected to the first pull-up node, and the second electrode of the first on / off control transistor is electrically connected to the first connection node.

[0335] like Figure 12 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first on / off control sub-circuit 121; the first on / off control sub-circuit includes a first on / off control transistor MK1;

[0336] The gate of the first on / off control transistor MK1 is electrically connected to the touch enable terminal TE, the source of the first on / off control transistor MK1 is connected to the first pull-up node PU1, and the second terminal of the first on / off control transistor is electrically connected to the first connection node.

[0337] The drain of the first transistor M1 is electrically connected to the first connection node.

[0338] exist Figure 8 Based on at least one embodiment of the driving circuit shown, Figure 12 At least one embodiment of the driving circuit shown includes a first on / off control transistor MK1;

[0339] During the normal display phase, TE provides a high-level signal, MK1 is turned on, ensuring that PU1 is charged and its charge is maintained;

[0340] During the touch phase, TE provides a low-level signal, MK1 is turned off, the number of transistors that the leakage current of PU1 needs to pass through increases, the leakage current is smaller, and the voltage holding capability of PU1 is stronger.

[0341] exist Figure 8 , Figure 10 , Figure 12 In at least one embodiment of the driving circuit shown, the source of the first carry output transistor MC1 is electrically connected to the first carry clock signal terminal KC1, the source of the first output transistor MO1 is electrically connected to the first clock signal terminal K1, and the source of the second output transistor MO2 is electrically connected to the second clock signal terminal K2; KC1, K1, and K2 are different clock signal terminals.

[0342] The gate driving circuit including the aforementioned driving circuit can control a predetermined stage driving circuit to output a corresponding driving signal, or it can control multiple stages of driving circuits including the gate driving circuit to sequentially output corresponding driving signals.

[0343] In at least one embodiment of this disclosure, the source of the first carry output transistor may also be electrically connected to the first clock signal terminal or the second clock signal terminal, but is not limited thereto.

[0344] Figure 13 At least one embodiment of the driving circuit shown is Figure 12 The difference in at least one embodiment of the driving circuit shown is that the source of the first carry output transistor MC1 is electrically connected to the first clock signal terminal K1.

[0345] exist Figure 13 In at least one embodiment of the driving circuit shown, the two output sub-circuits share the first pull-up node PU1, so the number of carry signal output terminals is halved. The first carry signal is output together with the odd-level driving signal, which can increase the size of M1 and M2 to improve the charging and discharging capability of the first pull-up node PU1.

[0346] The display driving circuit described in at least one embodiment of this disclosure may further include a first output capacitor;

[0347] The first end of the first output capacitor is electrically connected to the pull-up node circuit, and the second end of the first output capacitor is electrically connected to one of the N drive signal output terminals.

[0348] In at least one embodiment of this disclosure, the driving circuit further includes M clock signal terminals, M output sub-circuits, a second carry output sub-circuit, M driving signal output terminals, and a second carry signal output terminal; the M output sub-circuits share a second pull-up node;

[0349] The N+m output sub-circuit is used to output the N+m drive signal through the N+m drive signal output terminal under the control of the potential of the second pull-up node, according to the N+m clock signal provided by the N+m clock signal terminal, where m is a positive integer less than or equal to M and M is a positive integer greater than or equal to 2.

[0350] The second carry output sub-circuit is electrically connected to the second pull-up node, the second carry signal output terminal, and the second carry clock signal terminal, respectively, and is used to control the connection between the second carry signal output terminal and the second carry clock signal terminal under the control of the potential of the second pull-up node.

[0351] In a specific implementation, the driving circuit may further include M driving signal output terminals and a second carry signal output terminal, as well as M output sub-circuits that control the M driving signal output terminals respectively, and a second carry output sub-circuit that controls the second carry signal output terminal. The M output sub-circuits share a second pull-up node.

[0352] The following explanation uses M equal to 2 as an example, but in practice, M can also be an integer greater than 2.

[0353] like Figure 14 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown, the at least one embodiment of the driving circuit further includes a third clock signal terminal K3, a fourth clock signal terminal K4, a third output sub-circuit 113, a fourth output sub-circuit 114, a second carry output sub-circuit 42, a third driving signal output terminal G3, a fourth driving signal output terminal G4, and a second carry signal output terminal Co2; the third output sub-circuit 113 and the fourth output sub-circuit 114 share a second pull-up node PU2;

[0354] The third output sub-circuit 113 is electrically connected to the second pull-up node PU2, the third clock signal terminal K3 and the third drive signal output terminal G3 respectively, and is used to control the connection between the third drive signal output terminal G3 and the third clock signal terminal K3 under the control of the potential of the second pull-up node PU2.

[0355] The fourth output sub-circuit 114 is electrically connected to the second pull-up node PU2, the fourth clock signal terminal K4 and the fourth drive signal output terminal G4 respectively, and is used to control the connection between the fourth drive signal output terminal G4 and the fourth clock signal terminal K4 under the control of the potential of the second pull-up node PU2.

[0356] The second carry output sub-circuit 42 is electrically connected to the second pull-up node PU2, the second carry signal output terminal Co2, and the second carry clock signal terminal KC2, respectively, and is used to control the connection between the second carry signal output terminal Co2 and the second carry clock signal terminal KC2 under the control of the potential of the second pull-up node PU2.

[0357] In at least one embodiment of this disclosure, the driving circuit may further include M capacitors;

[0358] The first terminal of the m-th capacitor among the M capacitors is electrically connected to the second pull-up node, and the second terminal of the m-th capacitor among the M capacitors is electrically connected to the N+m-th drive signal output terminal.

[0359] In at least one embodiment of this disclosure, the driving circuit further includes a second input sub-circuit, a second pull-down sub-circuit, a second pull-down node control sub-circuit, and M output reset sub-circuits; the M output reset sub-circuits multiplex the second pull-down node;

[0360] The second input sub-circuit is used to control the potential of the second pull-up node under the control of the second input signal provided at the second input terminal;

[0361] The second pull-down sub-circuit is electrically connected to the second pull-up node, the second pull-down node, the second reset terminal, and the first voltage terminal, respectively. It is used to control the connection between the second pull-up node and the first voltage terminal under the control of the potential of the second pull-down node, and to control the connection between the second pull-up node and the first voltage terminal under the control of the second reset signal provided by the second reset terminal.

[0362] The second pull-down node control sub-circuit is electrically connected to the second control voltage terminal, the second pull-up node, the second pull-down node and the first voltage terminal respectively, and is used to control the potential of the second pull-down node according to the first voltage signal provided by the first voltage terminal under the control of the second control voltage provided by the second control voltage terminal and the potential of the second pull-up node;

[0363] The N+m output reset sub-circuit is electrically connected to the second pull-down node, the second voltage terminal, and the N+m drive signal output terminal, respectively, and is used to control the connection between the N+m drive signal output terminal and the second voltage terminal under the control of the potential of the second pull-down node.

[0364] like Figure 15 As shown, in Figure 14 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a second input sub-circuit 61, a second pull-down sub-circuit 62, a second pull-down node control sub-circuit 63, a third output reset sub-circuit 153, and a fourth output reset sub-circuit 154; the third output reset sub-circuit 153 and the fourth output reset sub-circuit 154 multiplex the second pull-down node PD2;

[0365] The second input sub-circuit 61 is electrically connected to the second input terminal I2 and the second pull-up node PU2, respectively, and is used to control the potential of the second pull-up node PU2 under the control of the second input signal provided by the second input terminal I2;

[0366] The second pull-down sub-circuit 62 is electrically connected to the second pull-up node PU2, the second pull-down node PD2, the second reset terminal R2, and the first low voltage terminal LVSS, respectively. It is used to control the connection between the second pull-up node PU2 and the first low voltage terminal LVSS under the control of the potential of the second pull-down node PD2, and to control the connection between the second pull-up node PU2 and the first low voltage terminal LVSS under the control of the second reset signal provided by the second reset terminal R2.

[0367] The second pull-down node control sub-circuit 63 is electrically connected to the second control voltage terminal VDDE, the second pull-up node PU2, the second pull-down node PD2 and the first low voltage terminal LVSS, respectively. It is used to control the potential of the second pull-down node PD2 according to the first low voltage signal provided by the first low voltage terminal LVSS under the control of the second control voltage provided by the second control voltage terminal VDDE and the potential of the second pull-up node PU2.

[0368] The third output reset sub-circuit 153 is electrically connected to the second pull-down node PD2, the second low voltage terminal VSS and the third drive signal output terminal G3 respectively, and is used to control the connection between the third drive signal output terminal G3 and the second low voltage terminal VSS under the control of the potential of the second pull-down node PD2.

[0369] The fourth output reset sub-circuit 154 is electrically connected to the second pull-down node PD2, the second low voltage terminal VSS and the fourth drive signal output terminal G4 respectively, and is used to control the connection between the fourth drive signal output terminal G4 and the second low voltage terminal VSS under the control of the potential of the second pull-down node PD2.

[0370] In at least one embodiment of this disclosure, the driving circuit further includes a second carry-reset sub-circuit;

[0371] The second carry reset sub-circuit is electrically connected to the second pull-down node, the second carry signal output terminal, and the first voltage terminal, respectively, and is used to control the connection between the second carry signal output terminal and the first voltage terminal under the control of the potential of the second pull-down node.

[0372] like Figure 16 As shown, in Figure 15 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a second carry-reset sub-circuit 52;

[0373] The second carry reset sub-circuit 52 is electrically connected to the second pull-down node PD2, the second carry signal output terminal Co2, and the first low voltage terminal LVSS, respectively, and is used to control the connection between the second carry signal output terminal Co2 and the first low voltage terminal LVSS under the control of the potential of the second pull-down node PD2.

[0374] In at least one embodiment of this disclosure, the second input sub-circuit is electrically connected to the second input terminal, the second input voltage terminal, and the second pull-up node, respectively, and is used to control the connection between the second pull-up node and the second input voltage terminal under the control of the second input signal provided by the second input terminal;

[0375] The second input terminal can be the second carry signal output terminal of the adjacent upper-level driving circuit;

[0376] The second input voltage terminal can be the second carry signal output terminal of the adjacent upper-level driving circuit, the d-th driving signal output terminal of the adjacent upper-level driving circuit, or the third voltage terminal; d is a positive integer less than or equal to M.

[0377] like Figure 17 As shown, in Figure 16 Based on at least one embodiment of the driving circuit shown, the second input sub-circuit 61 is also electrically connected to the second input voltage terminal VI2, and is used to control the connection between the second pull-up node PU2 and the second input voltage terminal VI2 under the control of the second input signal provided by the second input terminal I2.

[0378] In at least one embodiment of this disclosure, the second input terminal may be the second carry signal output terminal of the adjacent previous stage driving circuit, and the second input voltage terminal may be the same voltage terminal as the second input terminal; or, the second input voltage terminal may be a different voltage terminal from the second input terminal.

[0379] When the second input voltage terminal can be a different voltage terminal from the second input terminal.

[0380] The second input voltage terminal can be either the first drive signal output terminal of the adjacent previous stage drive circuit or the second drive signal output terminal of the adjacent previous stage drive circuit; or,

[0381] The second input voltage terminal can be a high voltage terminal;

[0382] However, this is not the only limit.

[0383] Optionally, the second carry clock signal terminal is the d-th clock signal terminal among the M clock signal terminals.

[0384] In practice, the second carry clock signal terminal can also be one of the M clock signal terminals to reduce the number of clock signal terminals used.

[0385] In at least one embodiment of this disclosure, the second pull-down sub-circuit is also electrically connected to the second input voltage terminal, and is used to control the connection between the second pull-down node and the first voltage terminal under the control of the second input voltage provided by the second input voltage terminal, so as to control the potential of the second pull-down node;

[0386] The second input sub-circuit is also electrically connected to the frame reset terminal and is also used to control the connection between the second pull-up node and the first voltage terminal under the control of the frame reset signal provided by the frame reset terminal, so as to reset the potential of the second pull-up node.

[0387] like Figure 18 As shown, in Figure 17 Based on at least one embodiment of the driving circuit shown, the second pull-down sub-circuit 62 is also electrically connected to the second input voltage terminal VI2, and is used to control the connection between the second pull-down node PD2 and the first low voltage terminal LVSS under the control of the second input voltage provided by the second input voltage terminal VI2;

[0388] The second input sub-circuit 61 is also electrically connected to the frame reset terminal TR, and is also used to control the connection between the second pull-up node PU2 and the first low voltage terminal LVSS under the control of the frame reset signal provided by the frame reset terminal TR, so as to reset the potential of the second pull-up node PU2.

[0389] In at least one embodiment of this disclosure, the driving circuit may further include M capacitors;

[0390] The first terminal of the m-th capacitor among the M capacitors is electrically connected to the second pull-up node, and the second terminal of the m-th capacitor among the M capacitors is electrically connected to the N+m-th drive signal output terminal.

[0391] In a specific implementation, the driving circuit may further include M capacitors, the first ends of which are all electrically connected to the second pull-up node, and the second ends of which are respectively electrically connected to M driving signal output terminals.

[0392] Optionally, the first pull-down sub-circuit may further include a tenth transistor;

[0393] The control electrode of the tenth transistor is electrically connected to the second pull-down node, the first electrode of the tenth transistor is electrically connected to the first pull-up node, and the second electrode of the tenth transistor is electrically connected to the first voltage terminal.

[0394] The first pull-down node control sub-circuit also includes an eleventh transistor;

[0395] The control electrode of the eleventh transistor is electrically connected to the second pull-up node, the first electrode of the eleventh transistor is electrically connected to the first pull-down control node, and the second electrode of the eleventh transistor is electrically connected to the first voltage terminal.

[0396] Optionally, the nth output reset sub-circuit may further include an nth reset transistor;

[0397] The control electrode of the nth reset transistor is electrically connected to the second pull-down node, the first electrode of the nth reset transistor is electrically connected to the nth drive signal output terminal, and the second electrode of the nth reset transistor is electrically connected to the second voltage terminal.

[0398] In at least one embodiment of this disclosure, the first carry reset sub-circuit may further include a second carry reset transistor;

[0399] The control electrode of the second carry reset transistor is electrically connected to the second pull-down node, the first electrode of the second carry reset transistor is electrically connected to the first carry signal output terminal, and the second electrode of the second carry reset transistor is electrically connected to the first voltage terminal.

[0400] like Figure 19 As shown, in Figure 10 Based on at least one embodiment of the driving circuit shown, the first pull-down sub-circuit 13 further includes a tenth transistor M10;

[0401] The gate of the tenth transistor M10 is electrically connected to the second pull-down node PD2, the source of the tenth transistor M10 is electrically connected to the first pull-up node PU1, and the drain of the tenth transistor M10 is electrically connected to the first low voltage terminal LVSS.

[0402] The first pull-down node control sub-circuit 14 also includes an eleventh transistor M11;

[0403] The gate of the eleventh transistor M11 is electrically connected to the second pull-up node PU2, the source of the eleventh transistor M11 is electrically connected to the first pull-down control node, and the drain of the eleventh transistor M11 is electrically connected to the first low voltage terminal LVSS.

[0404] The first output reset sub-circuit further includes a first reset transistor MW1; the second output reset sub-circuit further includes a second reset transistor MW2;

[0405] The gate of the first reset transistor MW1 is electrically connected to the second pull-down node PD2, the source of the first reset transistor is electrically connected to the first drive signal output terminal G1, and the drain of the nth reset transistor MW1 is electrically connected to the second low voltage terminal VSS.

[0406] The gate of the second reset transistor MW2 is electrically connected to the second pull-down node PD2, the source of the second reset transistor MW2 is electrically connected to the second drive signal output terminal G2, and the drain of the second reset transistor MW2 is electrically connected to the second low voltage terminal VSS.

[0407] The first carry reset sub-circuit 51 may further include a second carry reset transistor MR2;

[0408] The gate of the second carry reset transistor MR2 is electrically connected to the second pull-down node PD2, the source of the second carry reset transistor MR2 is electrically connected to the first carry signal output terminal Co1, and the drain of the second carry reset transistor MR2 is electrically connected to the first low voltage terminal LVSS.

[0409] Figure 20 At least one embodiment of the driving circuit shown is Figure 19 The difference in at least one embodiment of the driving circuit shown is that the source of the first carry output transistor MC1 is electrically connected to the first clock signal terminal K1.

[0410] In at least one embodiment of this disclosure, the second pull-down sub-circuit may include a twelfth transistor;

[0411] The control electrode of the twelfth transistor is electrically connected to the first pull-down node, the first electrode of the twelfth transistor is electrically connected to the second pull-up node, and the second electrode of the twelfth transistor is electrically connected to the first voltage terminal.

[0412] The second pull-down node control sub-circuit includes a thirteenth transistor;

[0413] The control electrode of the thirteenth transistor is electrically connected to the first pull-up node, the first electrode of the thirteenth transistor is electrically connected to the second pull-down control node, and the second electrode of the thirteenth transistor is electrically connected to the first voltage terminal.

[0414] Optionally, the (N+m)th output reset sub-circuit includes the (N+m)th reset transistor;

[0415] The control electrode of the N+m reset transistor is electrically connected to the first pull-down node, the first electrode of the N+m reset transistor is electrically connected to the N+m drive signal output terminal, and the second electrode of the N+m reset transistor is electrically connected to the second voltage terminal.

[0416] Optionally, the second carry reset sub-circuit includes a third carry reset transistor and a fourth carry reset transistor;

[0417] The control electrode of the third carry reset transistor is electrically connected to the second pull-down node, the first electrode of the third carry reset transistor is electrically connected to the second carry signal output terminal, and the second electrode of the third carry reset transistor is electrically connected to the first voltage terminal.

[0418] The control electrode of the fourth carry reset transistor is electrically connected to the first pull-down node, the first electrode of the fourth carry reset transistor is electrically connected to the second carry signal output terminal, and the second electrode of the fourth carry reset transistor is electrically connected to the first voltage terminal.

[0419] Optionally, the second input sub-circuit includes a fourteenth transistor, the second pull-down sub-circuit includes a fifteenth transistor and a sixteenth transistor; the second pull-down node control sub-circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor.

[0420] The control electrode of the fourteenth transistor is electrically connected to the second input terminal, the first electrode of the fourteenth transistor is electrically connected to the second input voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the second pull-up node.

[0421] The control terminal of the fifteenth transistor is electrically connected to the second reset terminal, the first terminal of the fifteenth transistor is electrically connected to the second pull-up node, and the second terminal of the fifteenth transistor is electrically connected to the first voltage terminal.

[0422] The control electrode of the sixteenth transistor is electrically connected to the second pull-down node, the first electrode of the sixteenth transistor is electrically connected to the second pull-up node, and the second electrode of the sixteenth transistor is electrically connected to the first voltage terminal.

[0423] The control electrode and the first electrode of the seventeenth transistor are both electrically connected to the second control voltage terminal, and the second electrode of the seventeenth transistor is electrically connected to the second pull-down control node;

[0424] The control electrode of the eighteenth transistor is electrically connected to the second pull-down control node, the first electrode of the eighteenth transistor is electrically connected to the second control voltage terminal, and the second electrode of the eighteenth transistor is electrically connected to the second pull-down node;

[0425] The control electrode of the nineteenth transistor is electrically connected to the second pull-up node, the first electrode of the nineteenth transistor is electrically connected to the second pull-down node, and the second electrode of the nineteenth transistor is electrically connected to the first voltage terminal.

[0426] The control terminal of the twentieth transistor is electrically connected to the second pull-up node, the first terminal of the twentieth transistor is electrically connected to the second pull-down control node, and the second terminal of the twentieth transistor is electrically connected to the first voltage terminal.

[0427] Optionally, the second pull-down sub-circuit includes a twenty-first transistor, and the second input sub-circuit further includes a twenty-second transistor;

[0428] The control terminal of the 21st transistor is electrically connected to the first input voltage terminal, the first terminal of the 21st transistor is electrically connected to the second pull-down node, and the second terminal of the 21st transistor is electrically connected to the first voltage terminal.

[0429] The control terminal of the 22nd transistor is electrically connected to the frame reset terminal, the first terminal of the 22nd transistor is electrically connected to the second pull-up node, and the second terminal of the 22nd transistor is electrically connected to the first voltage terminal.

[0430] Optionally, the second pull-down node control sub-circuit may further include a twenty-third transistor and a twenty-fourth transistor;

[0431] The control electrode of the 23rd transistor is electrically connected to the second pull-up node, the first electrode of the 23rd transistor is electrically connected to the first pull-down node, and the second electrode of the 23rd transistor is electrically connected to the first voltage terminal.

[0432] The control terminal of the 24th transistor is electrically connected to the second pull-up node, the first terminal of the 24th transistor is electrically connected to the second pull-down node, and the second terminal of the 24th transistor is electrically connected to the first voltage terminal.

[0433] Optionally, the N+m output sub-circuit includes the N+m output transistor;

[0434] The control terminal of the N+m output transistor is electrically connected to the second pull-up node, the first terminal of the N+m output transistor is electrically connected to the N+m clock signal terminal, and the second terminal of the N+m output transistor is electrically connected to the N+m drive signal output terminal.

[0435] The second carry output sub-circuit includes a second carry output transistor;

[0436] The control terminal of the second carry output transistor is electrically connected to the second pull-up node, the first terminal of the second carry output transistor is electrically connected to the second carry clock signal terminal, and the second terminal of the second carry output transistor is electrically connected to the second carry signal output terminal.

[0437] The N+m output reset sub-circuit includes the N+m output reset transistor;

[0438] The control electrode of the N+m output reset transistor is electrically connected to the second pull-down node, the first electrode of the N+m output reset transistor is electrically connected to the N+m drive signal output terminal, and the second electrode of the N+m output reset transistor is electrically connected to the second voltage terminal.

[0439] like Figure 21 As shown, in Figure 19 Based on at least one embodiment of the driving circuit shown, the second pull-down sub-circuit 62 may include a twelfth transistor M12; the driving circuit also includes a third capacitor C3 and a fourth capacitor C4;

[0440] The gate of the twelfth transistor M12 is electrically connected to the first pull-down node PD1, the source of the twelfth transistor M12 is electrically connected to the second pull-up node PU2, and the drain of the twelfth transistor M12 is electrically connected to the first low voltage terminal LVSS.

[0441] The second pull-down node control sub-circuit 63 includes a thirteenth transistor M13;

[0442] The gate of the thirteenth transistor M13 is electrically connected to the first pull-up node PU1, the source of the thirteenth transistor M13 is electrically connected to the second pull-down control node, and the second terminal of the thirteenth transistor M13 is electrically connected to the first low voltage terminal LVSS.

[0443] The third output reset circuit includes a third reset transistor MW3; the fourth output reset circuit includes a fourth reset transistor MW4;

[0444] The gate of the third reset transistor MW3 is electrically connected to the first pull-down node PD1, the source of the third reset transistor MW3 is electrically connected to the third drive signal output terminal G3, and the drain of the third reset transistor MW3 is electrically connected to the second low voltage terminal VSS.

[0445] The gate of the fourth reset transistor MW4 is electrically connected to the first pull-down node PD1, the source of the fourth reset transistor MW4 is electrically connected to the fourth drive signal output terminal G4, and the drain of the fourth reset transistor MW4 is electrically connected to the second low voltage terminal VSS.

[0446] The second carry reset sub-circuit 52 includes a third carry reset transistor MR3 and a fourth carry reset transistor MR4;

[0447] The gate of the third carry reset transistor MR3 is electrically connected to the second pull-down node PD2, the source of the third carry reset transistor MR3 is electrically connected to the second carry signal output terminal Co2, and the drain of the third carry reset transistor MR3 is electrically connected to the first low voltage terminal LVSS.

[0448] The gate of the fourth carry reset transistor MR4 is electrically connected to the first pull-down node PD1, the source of the fourth carry reset transistor MR4 is electrically connected to the second carry signal output terminal Co2, and the drain of the fourth carry reset transistor MR4 is electrically connected to the first low voltage terminal LVSS.

[0449] The second input sub-circuit 61 includes the fourteenth transistor M14, the second pull-down sub-circuit 62 includes the fifteenth transistor M15 and the sixteenth transistor M16; the second pull-down node control sub-circuit 63 includes the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, and the twentieth transistor M20.

[0450] The gate of the fourteenth transistor M14 is electrically connected to the second input terminal I2, the source of the fourteenth transistor M14 is electrically connected to the second input voltage terminal VI2, and the drain of the fourteenth transistor M14 is electrically connected to the second pull-up node PU2.

[0451] The gate of the fifteenth transistor M15 is electrically connected to the second reset terminal R2, the source of the fifteenth transistor M15 is electrically connected to the second pull-up node PU2, and the drain of the fifteenth transistor M15 is electrically connected to the first low voltage terminal LVSS.

[0452] The gate of the sixteenth transistor M16 is electrically connected to the second pull-down node PD2, the source of the sixteenth transistor M16 is electrically connected to the second pull-up node PU2, and the drain of the sixteenth transistor M16 is electrically connected to the first low voltage terminal LVSS.

[0453] The gate and source of the seventeenth transistor M17 are both electrically connected to the second control voltage terminal VDDE, and the drain of the seventeenth transistor M17 is electrically connected to the second pull-down control node.

[0454] The gate of the eighteenth transistor M18 is electrically connected to the second pull-down control node, the source of the eighteenth transistor M18 is electrically connected to the second control voltage terminal VDDE, and the drain of the eighteenth transistor M18 is electrically connected to the second pull-down node PD2.

[0455] The gate of the nineteenth transistor M19 is electrically connected to the second pull-up node PU2, the source of the nineteenth transistor M19 is electrically connected to the second pull-down node PD2, and the drain of the nineteenth transistor M19 is electrically connected to the first low voltage terminal LVSS.

[0456] The gate of the twentieth transistor M20 is electrically connected to the second pull-up node PU2, the source of the twentieth transistor M20 is electrically connected to the second pull-down control node, and the drain of the twentieth transistor M20 is electrically connected to the first low voltage terminal LVSS.

[0457] The second pull-down sub-circuit 62 includes a twenty-first transistor M21, and the second input sub-circuit 61 also includes a twenty-second transistor M22;

[0458] The gate of the 21st transistor M21 is electrically connected to the first input voltage terminal VI1, the source of the 21st transistor M21 is electrically connected to the second pull-down node PD2, and the drain of the 21st transistor M21 is electrically connected to the first low voltage terminal LVSS.

[0459] The gate of the twentieth transistor M22 is electrically connected to the frame reset terminal TR, the source of the twentieth transistor M22 is electrically connected to the second pull-up node PU2, and the drain of the twentieth transistor M22 is electrically connected to the first low voltage terminal LVSS.

[0460] The third output sub-circuit 113 includes a third output transistor MO3; the fourth output sub-circuit 114 includes a fourth output transistor MO4;

[0461] The gate of the third output transistor MO3 is electrically connected to the second pull-up node PU2, the source of the third output transistor MO3 is electrically connected to the third clock signal terminal K3, and the drain of the third output transistor MO3 is electrically connected to the third drive signal output terminal G3.

[0462] The gate of the fourth output transistor MO4 is electrically connected to the second pull-up node PU2, the source of the fourth output transistor MO4 is electrically connected to the fourth clock signal terminal K4, and the drain of the fourth output transistor MO4 is electrically connected to the fourth drive signal output terminal G4.

[0463] The second carry output sub-circuit 42 includes a second carry output transistor MC2;

[0464] The gate of the second carry output transistor MC2 is electrically connected to the second pull-up node PU2, the source of the second carry output transistor MC2 is electrically connected to the second carry clock signal terminal Kc2, and the drain of the second carry output transistor MC2 is electrically connected to the second carry signal output terminal Co2.

[0465] The third output reset circuit includes a third output reset transistor MF3; the fourth output reset circuit includes a fourth output reset transistor MF4.

[0466] The gate of the third output reset transistor MF3 is electrically connected to the second pull-down node PD2, the source of the third output reset transistor MF3 is electrically connected to the third drive signal output terminal G3, and the drain of the third output reset transistor MF3 is electrically connected to the second low voltage terminal VSS.

[0467] The gate of the fourth output reset transistor MF4 is electrically connected to the second pull-down node PD2, the source of the fourth output reset transistor MF4 is electrically connected to the fourth drive signal output terminal G4, and the drain of the fourth output reset transistor MF4 is electrically connected to the second low voltage terminal VSS.

[0468] The first end of the third capacitor C3 is electrically connected to the second pull-up node PU2, and the second end of the third capacitor C3 is electrically connected to the third drive signal output terminal G3.

[0469] The first end of the fourth capacitor C4 is electrically connected to the second pull-up node PU2, and the second end of the fourth capacitor C4 is electrically connected to the fourth drive signal output terminal G4.

[0470] Figure 22 At least one embodiment of the driving circuit shown is Figure 21 The difference in at least one embodiment of the driving circuit shown is that the first pull-down node control sub-circuit 14 further includes a twenty-third transistor M23, and the second pull-down node control sub-circuit 63 further includes a twenty-fourth transistor M24.

[0471] The gate of the 23rd transistor M23 is electrically connected to the second pull-up node PU2, the source of the 23rd transistor M23 is electrically connected to the first pull-down node PD1, and the drain of the 23rd transistor M23 is electrically connected to the first low voltage terminal LVSS.

[0472] The gate of the 24th transistor M24 is electrically connected to the first pull-up node PU1, the source of the 24th transistor M24 is electrically connected to the second pull-down node PD2, and the drain of the 24th transistor M24 is electrically connected to the first low-voltage terminal LVSS.

[0473] Figure 22 At least one embodiment of the driving circuit shown adds a twenty-third transistor M23 and a twenty-fourth transistor M24. The second pull-up node PU2 pulls down the potential of the first pull-down node PD1, and the first pull-up node PU1 pulls down the potential of the second pull-down node PD2. This is used to reduce the noise of the first pull-down node PD1 after the first pull-up node PU1 has reduced noise and the second pull-up node PU2 has not been reset, and to reduce the noise of the second pull-down node PD2 after the first pull-up node PU1 has been lifted and the second pull-up node PU2 has not been lifted.

[0474] Figure 23 At least one embodiment of the driving circuit shown is Figure 22 The difference in at least one embodiment of the driving circuit shown is that the source of the first carry output transistor MC1 is electrically connected to the first clock signal terminal K1, and the source of the second carry output transistor MC2 is electrically connected to the third clock signal terminal K3.

[0475] Figure 24 At least one embodiment of the driving circuit shown is Figure 23 The difference in at least one embodiment of the driving circuit shown is that no capacitor is provided between the second pull-up node PU2 and the third driving signal output terminal G3;

[0476] A second output capacitor C02 is provided between the second pull-up node PU2 and the fourth drive signal output terminal G4.

[0477] In at least one embodiment of this disclosure, the driving circuit may further include a second on / off control sub-circuit;

[0478] The second on / off control sub-circuit is electrically connected to the touch enable terminal, the second connection node, and the second pull-up node, respectively, and is used to control the connection or disconnection between the second connection node and the second pull-up node under the control of the touch enable signal provided by the touch enable terminal.

[0479] Optionally, the second on / off control sub-circuit includes a second on / off control transistor;

[0480] The control electrode of the second on / off control transistor is electrically connected to the touch enable terminal, the first electrode of the second on / off control transistor is connected to the second pull-up node, and the second electrode of the second on / off control transistor is electrically connected to the second connection node.

[0481] like Figure 25 As shown, in Figure 24 Based on at least one embodiment of the driving circuit shown, the driving circuit further includes a first on / off control sub-circuit and a second on / off control sub-circuit.

[0482] The first on / off sub-circuit includes a first on / off control transistor MK1;

[0483] The second on / off control sub-circuit includes a second on / off control transistor MK2;

[0484] The gate of the first on / off control transistor MK1 is electrically connected to the touch enable terminal TE, the source of the first on / off control transistor MK1 is connected to the first pull-up node PU1, and the second terminal of the first on / off control transistor is electrically connected to the first connection node.

[0485] The drain of the first transistor M1 is electrically connected to the first connection node;

[0486] The gate of the second on / off control transistor MK2 is electrically connected to the touch enable terminal TE, the source of the second on / off control transistor MK2 is electrically connected to the second pull-up node PU2, and the drain of the second on / off control transistor MK2 is electrically connected to the second connection node.

[0487] The second connection node is electrically connected to the drain of the fourteenth transistor M14.

[0488] exist Figure 25 At least one embodiment of the driving circuit shown includes a first on / off control transistor MK1 and a second on / off control transistor MK2.

[0489] During the normal display phase, TE provides a high-level signal, MK1 and MK2 are turned on, ensuring that PU1 and PU2 are charged and their charge is maintained;

[0490] During the touch phase, TE provides a low-level signal, MK1 and MK2 are turned off, the number of transistors that the leakage current of PU1 and PU2 needs to pass through increases, the leakage current is smaller, and the voltage holding capability of PU2 is stronger.

[0491] Figure 26 yes Figure 25 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0492] The display driving circuit described in at least one embodiment of this disclosure may further include a second output capacitor;

[0493] The first end of the second output capacitor is electrically connected to the second pull-up node, and the second end of the second output capacitor is electrically connected to one of the drive signal output terminals of the M drive signal output terminals.

[0494] Figure 27 At least one embodiment of the driving circuit shown is Figure 25 The difference in at least one embodiment of the driving circuit shown is that MR1, MR2, MR3 and MR4 are not provided to reduce the GOA (Gate On Array) layout. Considering that the parasitic capacitance of the carry signal output terminal is small and the coupling pull noise is small, and at the same time, the pull-down node is used to reduce the noise of the pull-up node, which can eliminate the rise of the pull-up node potential caused by the noise of the carry signal output terminal.

[0495] Figure 28 At least one embodiment of the driving circuit shown is Figure 24 The difference in at least one embodiment of the driving circuit shown is that the gate and source of M1 are both electrically connected to the first input terminal I1.

[0496] Both the gate and source of M14 are electrically connected to the second input terminal I2.

[0497] In at least one embodiment of this disclosure, since the four drive signal output terminals share a set of noise reduction units, the noise reduction load is relatively large. Therefore, it is necessary to increase the channel width of the fourth transistor M4, the channel width of the fifth transistor M5, the channel width of the seventeenth transistor M17, and the channel width of the eighteenth transistor M18 to improve the noise reduction capability.

[0498] In at least one embodiment of this disclosure, the width of the channel of M4 and the width of the channel of M17 can be greater than 50 μm. For example, the width of the channel of M4 and the width of the channel of M17 can be 60 μm, 80 μm, 90 μm or 100 μm, but are not limited thereto.

[0499] The width of the channel for M5 and the width of the channel for M18 can be greater than 500um. For example, the width of the channel for M5 and the width of the channel for M18 can be 550um, 600um, 700um, 800um or 900um, but are not limited to this.

[0500] In at least one embodiment of this disclosure, the width of the channel of M1 can be greater than 1500um, for example, it can be 1600um, 1800um, 2000um or 2200um;

[0501] The width of the M2 channel can be greater than 800um, for example, it can be 800um, 900um, 1000um or 1200um;

[0502] The width of the channel for M3, M10, M12 and M16 can be greater than 700um, for example, it can be 700um, 800um, 900um, 1000um or 1100um.

[0503] The width of the channel of each output reset transistor and the width of the channel of each reset transistor can be greater than 700um, for example, it can be 700um, 800um, 900um, 1000um or 1100um.

[0504] The channel width of each carry-reset transistor can be greater than 320um, for example, it can be 340um, 360um or 400um;

[0505] However, this is not the only limit.

[0506] like Figure 29 As shown, the display driving circuit includes a first gate driving circuit and a second gate driving circuit.

[0507] The first gate driving circuit is located on the left side of the display panel, and the second gate driving circuit is located on the right side of the display panel;

[0508] The first gate driving circuit includes multiple cascaded first driving circuits, and the second gate driving circuit includes multiple cascaded second driving circuits.

[0509] The structure of the first driving circuit can be the same as that of the second driving circuit;

[0510] exist Figure 29 In the diagram, S11 is the first-stage first driving circuit, S12 is the second-stage first driving circuit, S13 is the third-stage first driving circuit, S14 is the fourth-stage first driving circuit, and S15 is the fifth-stage first driving circuit.

[0511] S21 is the first-stage second driving circuit, S22 is the second-stage second driving circuit, S23 is the third-stage second driving circuit, S24 is the fourth-stage second driving circuit, and S25 is the fifth-stage second driving circuit.

[0512] The first drive signal output terminal of S12 and the second drive signal output terminal of S22 are electrically connected; the first drive signal output terminal of S12 is electrically connected to the first row gate line GT1.

[0513] The second drive signal output terminal of S12 is electrically connected to the third drive signal output terminal of S22; the second drive signal output terminal of S12 is electrically connected to the second row gate line GT2.

[0514] The third drive signal output terminal of S12 is electrically connected to the fourth drive signal output terminal of S22; the third drive signal output terminal of S12 is electrically connected to the third row gate line GT3.

[0515] The fourth drive signal output terminal of S12 is electrically connected to the first drive signal output terminal of S23; the fourth drive signal output terminal of S12 is electrically connected to the fourth row gate line GT4.

[0516] The first drive signal output terminal of S13 and the second drive signal output terminal of S23 are electrically connected; the first drive signal output terminal of S13 is electrically connected to the fifth row gate line GT5.

[0517] The second drive signal output terminal of S13 and the third drive signal output terminal of S23 are electrically connected; the second drive signal output terminal of S13 is electrically connected to the sixth row gate line GT6.

[0518] The third drive signal output terminal of S13 and the fourth drive signal output terminal of S23 are electrically connected; the third drive signal output terminal of S13 is electrically connected to the seventh row gate line GT7.

[0519] The fourth drive signal output terminal of S13 is electrically connected to the first drive signal output terminal of S24; the fourth drive signal output terminal of S13 is electrically connected to the eighth row of gate lines GT8.

[0520] The first drive signal output terminal of S14 and the second drive signal output terminal of S24 are electrically connected; the first drive signal output terminal of S14 is electrically connected to the ninth row of gate lines GT9.

[0521] The second drive signal output terminal of S14 and the third drive signal output terminal of S24 are electrically connected; the second drive signal output terminal of S14 is electrically connected to the tenth row gate line GT10.

[0522] The third drive signal output terminal of S14 and the fourth drive signal output terminal of S24 are electrically connected; the third drive signal output terminal of S14 is electrically connected to the eleventh row gate line GT11.

[0523] The fourth drive signal output terminal of S14 is electrically connected to the first drive signal output terminal of S25; the fourth drive signal output terminal of S14 is electrically connected to the twelfth row gate line GT12.

[0524] The first drive signal output terminal of S15 and the second drive signal output terminal of S25 are electrically connected; the first drive signal output terminal of S15 is electrically connected to the thirteenth row gate line GT13.

[0525] The second drive signal output terminal of S15 and the third drive signal output terminal of S25 are electrically connected; the second drive signal output terminal of S15 is electrically connected to the fourteenth row gate line GT14.

[0526] The third drive signal output terminal of S15 and the fourth drive signal output terminal of S25 are electrically connected; the third drive signal output terminal of S15 is electrically connected to the fifteenth row gate line GT15.

[0527] The fourth drive signal output terminal of S15 is electrically connected to the sixteenth row of gate lines GT16;

[0528] The first driving signal output terminal of S11 is electrically connected to the first row pseudo-pixel circuit DU1, the second driving signal output terminal of S11 is electrically connected to the second row pseudo-pixel circuit DU2, the third driving signal output terminal of S11 is electrically connected to the third row pseudo-pixel circuit DU3, and the fourth driving signal output terminal of S11 is electrically connected to the fourth row pseudo-pixel circuit DU4.

[0529] The first drive signal output terminal of S21 is electrically connected to the first row pseudo pixel circuit DU0.

[0530] The second drive signal output terminal of S21 is electrically connected to the first row pseudo pixel circuit DU1, the third drive signal output terminal of S21 is electrically connected to the second row pseudo pixel circuit DU2, the fourth drive signal output terminal of S21 is electrically connected to the third row pseudo pixel circuit DU3, and the first drive signal output terminal of S22 is electrically connected to the fourth row pseudo pixel circuit DU4.

[0531] exist Figure 29 In the diagram, CLK1 is the first clock signal, CLK2 is the second clock signal, CLK3 is the third clock signal, CLK4 is the fourth clock signal, CLK5 is the fifth clock signal, CLK6 is the sixth clock signal, CLK7 is the seventh clock signal, CLK8 is the eighth clock signal, CLK9 is the ninth clock signal, and CLK10 is the tenth clock signal.

[0532] The clock signal labeled CLKC1 is the first carry clock signal, CLKC2 is the second carry clock signal, CLKC3 is the third carry clock signal, CLKC4 is the fourth carry clock signal, CLKC5 is the fifth carry clock signal, CLKC6 is the sixth carry clock signal, CLKC7 is the seventh carry clock signal, CLKC8 is the eighth carry clock signal, CLKC9 is the ninth carry clock signal, and CLKC10 is the tenth carry clock signal.

[0533] The terminal labeled STV is the start signal terminal.

[0534] exist Figure 29In at least one embodiment shown, in the first driving circuit and the second driving circuit, the first terminal of the first carry output transistor is electrically connected to the first carry clock signal terminal, and the first terminal of the second carry output transistor is electrically connected to the second carry clock signal terminal.

[0535] This disclosure is as follows Figure 29 At least one embodiment of the display driving circuit shown can output odd and even level driving signals separately when in operation, and has HSR (high-frequency repetition) function. (See reference...) Figure 29 and Figure 22 The circuit in this case can realize the display function of any row or at least a portion of the row. Compared with displaying the entire screen, it can reduce display power consumption. For example, for displaying any row or at least a portion of the row, the cascading relationship can be ensured by outputting a continuous carry clock signal to the carry clock signal terminal. As for the clock signals connecting the first clock signal terminal K1, the second clock signal terminal K2, or other rows of G1 and G2, it is only necessary to provide a valid clock signal to the corresponding display row. For example, when displaying the entire screen, the clock signal timing reference is... Figure 30 When displaying any row, a partial row, an odd row, or an even row, the clock signal can be set to an invalid level when the corresponding row does not need to be displayed.

[0536] In this disclosure Figure 29 In at least one embodiment of the display driving circuit shown, the carry clock signal and the clock signal used for output are independent of each other, so that in the case of normal cascading, by providing only a portion of the clock signal used for output, the corresponding driving signal can be output from a portion of the driving signal output terminal of the driving circuit.

[0537] Figure 30 This is a waveform diagram of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7, the eighth clock signal CLK8, the ninth clock signal CLK9, and the tenth clock signal CLK10.

[0538] like Figure 31 As shown, the display driving circuit includes a first gate driving circuit and a second gate driving circuit.

[0539] The first gate driving circuit is located on the left side of the display panel, and the second gate driving circuit is located on the right side of the display panel;

[0540] The first gate driving circuit includes multiple cascaded first driving circuits, and the second gate driving circuit includes multiple cascaded second driving circuits.

[0541] The structure of the first driving circuit can be the same as that of the second driving circuit;

[0542] exist Figure 31 In the diagram, S11 is the first-stage first driving circuit, S12 is the second-stage first driving circuit, S13 is the third-stage first driving circuit, S14 is the fourth-stage first driving circuit, and S15 is the fifth-stage first driving circuit.

[0543] S21 is the first-stage second driving circuit, S22 is the second-stage second driving circuit, S23 is the third-stage second driving circuit, S24 is the fourth-stage second driving circuit, and S25 is the fifth-stage second driving circuit.

[0544] The first drive signal output terminal of S12 and the second drive signal output terminal of S22 are electrically connected; the first drive signal output terminal of S12 is electrically connected to the first row gate line GT1.

[0545] The second drive signal output terminal of S12 is electrically connected to the third drive signal output terminal of S22; the second drive signal output terminal of S12 is electrically connected to the second row gate line GT2.

[0546] The third drive signal output terminal of S12 is electrically connected to the fourth drive signal output terminal of S22; the third drive signal output terminal of S12 is electrically connected to the third row gate line GT3.

[0547] The fourth drive signal output terminal of S12 is electrically connected to the first drive signal output terminal of S23; the fourth drive signal output terminal of S12 is electrically connected to the fourth row gate line GT4.

[0548] The first drive signal output terminal of S13 and the second drive signal output terminal of S23 are electrically connected; the first drive signal output terminal of S13 is electrically connected to the fifth row gate line GT5.

[0549] The second drive signal output terminal of S13 and the third drive signal output terminal of S23 are electrically connected; the second drive signal output terminal of S13 is electrically connected to the sixth row gate line GT6.

[0550] The third drive signal output terminal of S13 and the fourth drive signal output terminal of S23 are electrically connected; the third drive signal output terminal of S13 is electrically connected to the seventh row gate line GT7.

[0551] The fourth drive signal output terminal of S13 is electrically connected to the first drive signal output terminal of S24; the fourth drive signal output terminal of S13 is electrically connected to the eighth row of gate lines GT8.

[0552] The first drive signal output terminal of S14 and the second drive signal output terminal of S24 are electrically connected; the first drive signal output terminal of S14 is electrically connected to the ninth row of gate lines GT9.

[0553] The second drive signal output terminal of S14 and the third drive signal output terminal of S24 are electrically connected; the second drive signal output terminal of S14 is electrically connected to the tenth row gate line GT10.

[0554] The third drive signal output terminal of S14 and the fourth drive signal output terminal of S24 are electrically connected; the third drive signal output terminal of S14 is electrically connected to the eleventh row gate line GT11.

[0555] The fourth drive signal output terminal of S14 is electrically connected to the first drive signal output terminal of S25; the fourth drive signal output terminal of S14 is electrically connected to the twelfth row gate line GT12.

[0556] The first drive signal output terminal of S15 and the second drive signal output terminal of S25 are electrically connected; the first drive signal output terminal of S15 is electrically connected to the thirteenth row gate line GT13.

[0557] The second drive signal output terminal of S15 and the third drive signal output terminal of S25 are electrically connected; the second drive signal output terminal of S15 is electrically connected to the fourteenth row gate line GT14.

[0558] The third drive signal output terminal of S15 and the fourth drive signal output terminal of S25 are electrically connected; the third drive signal output terminal of S15 is electrically connected to the fifteenth row gate line GT15.

[0559] The fourth drive signal output terminal of S15 is electrically connected to the sixteenth row of gate lines GT16;

[0560] The first driving signal output terminal of S11 is electrically connected to the first row pseudo-pixel circuit DU1, the second driving signal output terminal of S11 is electrically connected to the second row pseudo-pixel circuit DU2, the third driving signal output terminal of S11 is electrically connected to the third row pseudo-pixel circuit DU3, and the fourth driving signal output terminal of S11 is electrically connected to the fourth row pseudo-pixel circuit DU4.

[0561] The first drive signal output terminal of S21 is electrically connected to the first row pseudo pixel circuit DU0.

[0562] The second drive signal output terminal of S21 is electrically connected to the first row pseudo pixel circuit DU1, the third drive signal output terminal of S21 is electrically connected to the second row pseudo pixel circuit DU2, the fourth drive signal output terminal of S21 is electrically connected to the third row pseudo pixel circuit DU3, and the first drive signal output terminal of S22 is electrically connected to the fourth row pseudo pixel circuit DU4.

[0563] exist Figure 31In the diagram, CLK1 is the first clock signal, CLK2 is the second clock signal, CLK3 is the third clock signal, CLK4 is the fourth clock signal, CLK5 is the fifth clock signal, CLK6 is the sixth clock signal, CLK7 is the seventh clock signal, CLK8 is the eighth clock signal, CLK9 is the ninth clock signal, and CLK10 is the tenth clock signal.

[0564] The terminal labeled STV is the start signal terminal.

[0565] exist Figure 31 In at least one embodiment shown, in the first driving circuit and the second driving circuit, the first terminal of the first carry output transistor and the first terminal of the first output transistor are connected to the same clock signal, and the first terminal of the second carry output transistor and the first terminal of the second output transistor are connected to the same clock signal, so as to reduce the number of clock signal lines used and facilitate the realization of a narrow bezel.

[0566] like Figure 32 and Figure 33 As shown, taking a display device with 4320 rows of gate lines as an example, the first driving circuit of the first gate driving circuit and the second driving circuit of the second gate driving circuit are cascaded in a staggered manner.

[0567] exist Figure 32 In the diagram, S11 is the first stage first driving circuit included in the first gate driving circuit, S12 is the second stage first driving circuit included in the first gate driving circuit, S13 is the third stage first driving circuit included in the first gate driving circuit, and S14 is the fourth stage first driving circuit included in the first gate driving circuit.

[0568] S21 is the first stage second driving circuit included in the second gate driving circuit, S22 is the second stage second driving circuit included in the second gate driving circuit, S23 is the third stage second driving circuit included in the second gate driving circuit, and S24 is the fourth stage second driving circuit included in the second gate driving circuit.

[0569] exist Figure 32 and Figure 33In the diagram, STV is the start signal terminal, CLK1 is the first clock signal, CLK2 is the second clock signal, CLK3 is the third clock signal, CLK4 is the fourth clock signal, CLK5 is the fifth clock signal, CLK6 is the sixth clock signal, CLK7 is the seventh clock signal, CLK8 is the eighth clock signal, CLK9 is the ninth clock signal, and CLK10 is the tenth clock signal.

[0570] like Figure 32 As shown, the second drive signal output terminal of S12 is electrically connected to the first drive signal output terminal of S22, and both the second drive signal output terminal of S12 and the first drive signal output terminal of S22 are electrically connected to the 4320th row gate line GT4320.

[0571] The third drive signal output terminal of S12 is electrically connected to the second drive signal output terminal of S22, and both the third drive signal output terminal of S12 and the second drive signal output terminal of S22 are electrically connected to the 4319th row gate line GT4319.

[0572] The fourth drive signal output terminal of S12 is electrically connected to the third drive signal output terminal of S22, and both the fourth drive signal output terminal of S12 and the third drive signal output terminal of S22 are electrically connected to the 4318th row gate line GT4318.

[0573] The first drive signal output terminal of S13 is electrically connected to the fourth drive signal output terminal of S22, and both the first drive signal output terminal of S13 and the fourth drive signal output terminal of S22 are electrically connected to the 4317th row gate line GT4317.

[0574] The second drive signal output terminal of S13 is electrically connected to the first drive signal output terminal of S23. Both the second drive signal output terminal of S13 and the first drive signal output terminal of S23 are electrically connected to the 4316th row gate line GT4316.

[0575] The third drive signal output terminal of S13 is electrically connected to the second drive signal output terminal of S23, and both the third drive signal output terminal of S13 and the second drive signal output terminal of S23 are electrically connected to the 4315th row gate line GT4315.

[0576] The fourth drive signal output terminal of S13 is electrically connected to the third drive signal output terminal of S23. Both the fourth drive signal output terminal of S13 and the third drive signal output terminal of S23 are electrically connected to the 4314th row gate line GT4314.

[0577] The first drive signal output terminal of S14 is electrically connected to the fourth drive signal output terminal of S23, and both the first drive signal output terminal of S14 and the fourth drive signal output terminal of S23 are electrically connected to the 4313th row gate line GT4313.

[0578] The second drive signal output terminal of S14 is electrically connected to the first drive signal output terminal of S24, and both the second drive signal output terminal of S14 and the first drive signal output terminal of S24 are electrically connected to the 4312th row gate line GT4312.

[0579] The third drive signal output terminal of S14 is electrically connected to the second drive signal output terminal of S24, and both the third drive signal output terminal of S14 and the second drive signal output terminal of S24 are electrically connected to the 4311th row gate line GT4311.

[0580] The fourth drive signal output terminal of S14 is electrically connected to the third drive signal output terminal of S24, and both the fourth drive signal output terminal of S14 and the third drive signal output terminal of S24 are electrically connected to the 4310th row gate line GT4310.

[0581] exist Figure 33 In the diagram, S11081 is the first driving circuit of the 1081st stage, and S21081 is the second driving circuit of the 1081st stage.

[0582] The circuit labeled DM11 is the first-stage first virtual drive circuit, the circuit labeled DM12 is the second-stage first virtual drive circuit, and the circuit labeled DM13 is the third-stage first virtual drive circuit.

[0583] The circuit labeled DM21 is the first-stage second virtual drive circuit, the circuit labeled DM22 is the second-stage second virtual drive circuit, and the circuit labeled DM23 is the third-stage second virtual drive circuit.

[0584] The first drive signal output terminal of S11081 is electrically connected to the fifth row gate line GT5;

[0585] The second drive signal output terminal of S11081 is electrically connected to the first drive signal output terminal of S21081; the second drive signal output terminal of S11081 is electrically connected to the fourth row gate line GT4.

[0586] The third drive signal output terminal of S11081 is electrically connected to the second drive signal output terminal of S21081; the third drive signal output terminal of S11081 is electrically connected to the third row gate line GT3.

[0587] The fourth drive signal output terminal of S11081 is electrically connected to the first drive signal output terminal of S21081; the fourth drive signal output terminal of S11081 is electrically connected to the second row gate line GT2.

[0588] The first drive signal output terminal of DM11 is electrically connected to the first row of gate lines GT1.

[0589] The display device described in this embodiment includes the display driving circuit described above.

[0590] The display device described in at least one embodiment of this disclosure may further include multiple rows of gate lines, multiple columns of data lines, and multiple rows and columns of pixel circuits;

[0591] The pixel circuit includes a display control transistor and pixel electrodes;

[0592] The gate of the display control transistor is electrically connected to the gate line, the first electrode of the display control transistor is electrically connected to the data line, and the second electrode of the display control transistor is electrically connected to the pixel electrode.

[0593] The pixel electrode has multiple slits; the angle between the slit directions of two pixel electrodes in the same pixel electrode group is greater than 90 degrees and less than 180 degrees.

[0594] The pixel electrode group is a pixel electrode group disposed in the display area formed by adjacent row grid lines and adjacent column data lines.

[0595] In at least one embodiment of this disclosure, the domains of two pixel electrodes included in the same pixel electrode group are opposite, which can improve color shift.

[0596] In at least one embodiment of this disclosure, the two rows of gate lines between two adjacent rows of pixel circuits are electrically connected to the two driving signal output terminals included in the driving circuit, or the two rows of gate lines disposed on the upper and lower sides of a row of pixel circuits are electrically connected to the two driving signal output terminals included in the driving circuit.

[0597] like Figure 34As shown, the display device according to at least one embodiment of this disclosure includes a first row of gate lines GT1, a second row of gate lines GT2, a third row of gate lines GT3, a fourth row of gate lines GT4, a fifth row of gate lines GT5, a sixth row of gate lines GT6, a first column of data lines D1, a second column of data lines D2, a third column of data lines D3, a fourth column of data lines D4, a fifth column of data lines D5, a sixth column of data lines D6, a first row of first column of pixel circuits, a first row of second column of pixel circuits, a first row of third column of pixel circuits, a first row of fourth column of pixel circuits, a first row of fifth column of pixel circuits, and a first... The pixel circuits in the sixth column of the first row, the seventh column of the first row, the eighth column of the first row, the ninth column of the first row, the tenth column of the first row, the eleventh column of the first row, the twelfth column of the first row, the first column of the second row, the second column of the second row, the third column of the second row, the fourth column of the second row, the fifth column of the second row, the sixth column of the second row, the seventh column of the second row, the eighth column of the second row, the ninth column of the second row, and the tenth column of the second row.

[0598] The first row and first column pixel circuit includes a first row and first column pixel electrode P11 and a first row and first column display control transistor T11;

[0599] The gate of T11 is electrically connected to GT2, the source of T11 is electrically connected to D1, and the drain of T11 is electrically connected to P11.

[0600] The first row and two column pixel circuit includes a first row and second column pixel electrode P12 and a first row and second column display control transistor T12;

[0601] The gate of T12 is electrically connected to GT3, the source of T12 is electrically connected to D1, and the drain of T12 is electrically connected to P12.

[0602] The first row and third column pixel circuit includes a first row and third column pixel electrode P13 and a first row and third column display control transistor T13;

[0603] The gate of T13 is electrically connected to GT2, the source of T13 is electrically connected to D2, and the drain of T13 is electrically connected to P13.

[0604] The first row and fourth column pixel circuit includes a first row and fourth column pixel electrode P14 and a first row and fourth column display control transistor T14;

[0605] The gate of T14 is electrically connected to GT3, the source of T14 is electrically connected to D2, and the drain of T14 is electrically connected to P14.

[0606] The first row and fifth column pixel circuit includes the first row and fifth column pixel electrode P15 and the first row and fifth column display control transistor T15;

[0607] The gate of T15 is electrically connected to GT2, the source of T15 is electrically connected to D3, and the drain of T15 is electrically connected to P15.

[0608] The pixel circuit in the first row and sixth column includes a pixel electrode P16 in the first row and sixth column and a display control transistor T16 in the first row and sixth column.

[0609] The gate of T16 is electrically connected to GT3, the source of T16 is electrically connected to D3, and the drain of T16 is electrically connected to P16.

[0610] The first row and seventh column pixel circuit includes the first row and seventh column pixel electrode P17 and the first row and seventh column display control transistor T17;

[0611] The gate of T17 is electrically connected to GT2, the source of T17 is electrically connected to D4, and the drain of T17 is electrically connected to P17.

[0612] The first row and eighth column pixel circuit includes the first row and eighth column pixel electrode P18 and the first row and eighth column display control transistor T18;

[0613] The gate of T18 is electrically connected to GT3, the source of T18 is electrically connected to D4, and the drain of T18 is electrically connected to P18.

[0614] The pixel circuit in the first row and ninth column includes a pixel electrode P19 in the first row and ninth column and a display control transistor T19 in the first row and ninth column.

[0615] The gate of T19 is electrically connected to GT2, the source of T19 is electrically connected to D5, and the drain of T19 is electrically connected to P19.

[0616] The first row and tenth column pixel circuit includes a first row and tenth column pixel electrode P110 and a first row and tenth column display control transistor T110;

[0617] The gate of T110 is electrically connected to GT3, the source of T110 is electrically connected to D5, and the drain of T110 is electrically connected to P110.

[0618] The second row, first column pixel circuit includes the second row, first column pixel electrode P21 and the second row, first column display control transistor T21;

[0619] The gate of T21 is electrically connected to GT4, the source of T21 is electrically connected to D2, and the drain of T21 is electrically connected to P21.

[0620] The second row and two column pixel circuit includes the second row and second column pixel electrode P22 and the second row and second column display control transistor T22;

[0621] The gate of T22 is electrically connected to GT5, the source of T22 is electrically connected to D2, and the drain of T22 is electrically connected to P22.

[0622] The second row and third column pixel circuit includes the second row and third column pixel electrode P23 and the second row and third column display control transistor T23;

[0623] The gate of T23 is electrically connected to GT4, the source of T23 is electrically connected to D3, and the drain of T23 is electrically connected to P23.

[0624] The second row and fourth column pixel circuit includes the second row and fourth column pixel electrode P24 and the second row and fourth column display control transistor T24;

[0625] The gate of T24 is electrically connected to GT5, the source of T24 is electrically connected to D3, and the drain of T24 is electrically connected to P24.

[0626] The second row and fifth column pixel circuit includes the second row and fifth column pixel electrode P25 and the second row and fifth column display control transistor T25;

[0627] The gate of T25 is electrically connected to GT4, the source of T25 is electrically connected to D4, and the drain of T25 is electrically connected to P25.

[0628] The second row and sixth column pixel circuit includes the second row and sixth column pixel electrode P26 and the second row and sixth column display control transistor T26;

[0629] The gate of T26 is electrically connected to GT5, the source of T26 is electrically connected to D4, and the drain of T26 is electrically connected to P26.

[0630] The second row and seventh column pixel circuit includes the second row and seventh column pixel electrode P27 and the second row and seventh column display control transistor T27;

[0631] The gate of T27 is electrically connected to GT4, the source of T27 is electrically connected to D5, and the drain of T27 is electrically connected to P27.

[0632] The second row and eighth column pixel circuit includes the second row and eighth column pixel electrode P28 and the second row and eighth column display control transistor T28;

[0633] The gate of T28 is electrically connected to GT5, the source of T28 is electrically connected to D5, and the drain of T28 is electrically connected to P28.

[0634] The second row and ninth column pixel circuit includes the second row and ninth column pixel electrode P29 and the second row and ninth column display control transistor T29;

[0635] The gate of T29 is electrically connected to GT4, the source of T29 is electrically connected to D6, and the drain of T29 is electrically connected to P29.

[0636] The second row and tenth column pixel circuit includes the second row and tenth column pixel electrode P210 and the second row and tenth column display control transistor T210;

[0637] The gate of T210 is electrically connected to GT5, the source of T210 is electrically connected to D6, and the drain of T210 is electrically connected to P210.

[0638] In at least one embodiment of this disclosure, the first drive signal output terminal G1 of the drive circuit can be connected to... Figure 34 GT1 is electrically connected in the circuit, and the second drive signal output terminal G2 of the drive circuit can be connected to... Figure 34 GT2 is electrically connected in the circuit, and the third drive signal output terminal G3 of the drive circuit can be connected to... Figure 34 GT3 is electrically connected in the circuit, and the fourth drive signal output terminal G4 of the drive circuit can be connected to... Figure 34 GT4 electrical connection in; or,

[0639] The driving circuit includes a first driving signal output terminal G1 that can be connected to... Figure 34 GT2 is electrically connected in the middle, and the second drive signal output terminal G2 of the drive circuit can be connected to... Figure 34 The GT3 in the circuit is electrically connected, and the third drive signal output terminal G3 of the drive circuit can be connected to... Figure 34 The GT4 in the circuit is electrically connected, and the fourth drive signal output terminal G4 of the drive circuit can be connected to... Figure 34 GT5 electrical connection in the middle;

[0640] However, this is not the only limit.

[0641] exist Figure 34 In at least one embodiment shown, P11 and P12 form a pixel electrode group, P13 and P14 form a pixel electrode group, P15 and P16 form a pixel electrode group, P17 and P18 form a pixel electrode group, P19 and P110 form a pixel electrode group, P21 and P22 form a pixel electrode group, P23 and P24 form a pixel electrode group, P25 and P26 form a pixel electrode group, P27 and P28 form a pixel electrode group, and P29 and P210 form a pixel electrode group.

[0642] In at least one embodiment of this disclosure, two rows of gate lines are provided between two adjacent rows of pixel electrodes;

[0643] The gate of one of the two transistors electrically connected to the same column of data lines is electrically connected to one of the gate lines in the two rows of gate lines, and the gate of the other transistor of the two transistors electrically connected to the same column of data lines is electrically connected to the other gate line in the two rows of gate lines.

[0644] The width of the conductive connection portion between two transistors electrically connected to the same column of data lines and that column of data lines along the first direction is greater than the minimum width of the data lines along the first direction.

[0645] The first direction is the extension direction of the gate line.

[0646] Optionally, the first direction can be horizontal, but is not limited to this.

[0647] The display device described in at least one embodiment of this disclosure may further include multiple rows and columns of common electrodes;

[0648] Adjacent rows of common electrodes are electrically connected by jumper wires, which are disposed on the same layer as the pixel electrodes.

[0649] In at least one embodiment of this disclosure, the pixel electrodes corresponding to both ends of the jumper wire have avoidance portions.

[0650] Optionally, at the intersection of the jumper wire and the gate wire, the linewidth of the gate wire is less than the maximum linewidth of the gate wire.

[0651] like Figure 36 As shown, in at least one embodiment of this disclosure, the gate lines are designed as zigzag lines, and the two gate lines located between two adjacent rows of pixel circuits are designed to be approximately axially symmetrical, so that the blank area between two adjacent gate lines can just be used to set the wider part of the data line.

[0652] Figure 35A , Figure 35B and Figure 35C Is Figure 34 The diagram shown is a layout of a display substrate including pixel circuits in at least one embodiment.

[0653] Figure 36 yes Figure 35B The layout diagram of the common electrode, the gate of each display control transistor, and each gate line;

[0654] Figure 37 yes Figure 35B The layout diagram of the data lines, the source of each display control transistor, the drain of each display control transistor, and the active layer of each display control transistor.

[0655] Figure 38 yes Figure 35B The layout diagram of the pixel electrodes and jumpers.

[0656] exist Figure 35C In the diagram, D2 is the second data line, T13 is the first row and third column display control transistor, Y1 is the first extension line, and P14 is the first row and fourth column pixel electrode.

[0657] like Figure 35C As shown, the source of T13 is electrically connected to the pixel electrode P14 in the first row and fourth column through the first extension line Y1.

[0658] like Figures 35A-38 As shown, the common electrode is a plate-shaped electrode, which can be located on the same layer as the gate and gate line of each display control transistor. The pixel electrode can be disposed on the side of the common electrode away from the substrate. It should be noted that in this case, the common electrode can also be disposed on the side of the pixel electrode away from the substrate, that is, the pixel electrode is below and the common electrode is above. In this case, the common electrode is designed with a slot. This is not limited here. In this case, the semiconductor layer of the transistor can be an amorphous silicon semiconductor layer, a low-temperature polycrystalline silicon semiconductor layer, or an oxide semiconductor layer, etc., which is not limited here.

[0659] exist Figure 37 In the diagram, the electrode labeled D23 is the drain of T23, the electrode labeled S23 is the source of T23, the electrode labeled D16 is the drain of T16, and the electrode labeled S16 is the source of T16.

[0660] like Figure 37 As shown, L1 is the conductive connection between T13, T22 and D2. The width of L1 in the horizontal direction is greater than the minimum width of D2 in the horizontal direction, so that the spacer (PS) pillar can be placed against the conductive connection to support the display panel. Optionally, the PS pillar can be placed on the color filter substrate or on the array substrate.

[0661] exist Figure 36 In the diagram, CM11 is the first common electrode in the first row and first column; CM12 is the first common electrode in the second row and second column; CM13 is the first common electrode in the third row and first column; CM14 is the first common electrode in the fourth row and first column; CM15 is the first common electrode in the fifth row and first column; CM16 is the first common electrode in the sixth row and first column; CM17 is the first common electrode in the seventh row and first column; CM18 is the first common electrode in the eighth row and first column; CM19 is the first common electrode in the ninth row and first column; and CM110 is the first common electrode in the tenth row and first column.

[0662] The electrode labeled CM21 is the common electrode in the first column of the second row; the electrode labeled CM22 is the common electrode in the second column of the second row; the electrode labeled CM23 is the common electrode in the third column of the second row; the electrode labeled CM24 is the common electrode in the fourth column of the second row; the electrode labeled CM25 is the common electrode in the fifth column of the second row; the electrode labeled CM26 is the common electrode in the sixth column of the second row; the electrode labeled CM27 is the common electrode in the seventh column of the second row; the electrode labeled CM28 is the common electrode in the eighth column of the second row; the electrode labeled CM29 is the common electrode in the ninth column of the second row; and the electrode labeled CM210 is the common electrode in the tenth column of the second row.

[0663] like Figure 36 and Figure 35B As shown, GT1 is the first row of gate lines, GT2 is the second row of gate lines, GT3 is the third row of gate lines, GT4 is the fourth row of gate lines, GT5 is the fifth row of gate lines, and GT6 is the sixth row of gate lines.

[0664] In at least one embodiment of this disclosure, CM11, CM12, CM13, CM14, CM15, CM16, CM17, CM18, CM19 and CM110 are electrically connected to each other to form a strip-shaped common electrode;

[0665] CM21, CM22, CM23, CM24, CM25, CM26, CM27, CM28, CM29 and CM210 are electrically connected to each other to form a strip-shaped common electrode.

[0666] exist Figure 35B In the diagram, the transistor labeled T16 is the display control transistor in the first row and sixth column, and the transistor labeled T23 is the display control transistor in the second row and third column.

[0667] exist Figure 37 and Figure 35B In the diagram, D1 is the first data line, D2 is the second data line, D3 is the third data line, D4 ​​is the fourth data line, D5 is the fifth data line, and D6 is the sixth data line.

[0668] exist Figure 38 and Figure 35BIn the diagram, the pixel electrode labeled P11 is the first row and first column; the pixel electrode labeled P12 is the first row and second column; the pixel electrode labeled P13 is the first row and third column; the pixel electrode labeled P14 is the first row and fourth column; the pixel electrode labeled P15 is the first row and fifth column; the pixel electrode labeled P16 is the first row and sixth column; the pixel electrode labeled P17 is the first row and seventh column; the pixel electrode labeled P18 is the first row and eighth column; the pixel electrode labeled P19 is the first row and ninth column; and the pixel electrode labeled P110 is the first row and tenth column.

[0669] The pixel electrode labeled P21 is the first pixel electrode in the second row; the pixel electrode labeled P22 is the second pixel electrode in the second row; the pixel electrode labeled P23 is the third pixel electrode in the second row; the pixel electrode labeled P24 is the fourth pixel electrode in the second row; the pixel electrode labeled P25 is the fifth pixel electrode in the second row; the pixel electrode labeled P26 is the sixth pixel electrode in the second row; the pixel electrode labeled P27 is the seventh pixel electrode in the second row; the pixel electrode labeled P28 is the eighth pixel electrode in the second row; the pixel electrode labeled P29 is the ninth pixel electrode in the second row; and the pixel electrode labeled P210 is the tenth pixel electrode in the second row.

[0670] The first jumper wire, labeled KX1, is located on the same layer as each pixel electrode.

[0671] KX1 is used for electrical connections of CM15, CM16, CM25 and CM26.

[0672] like Figure 38 As shown, the upper end of KX1 corresponds to P15 and P16, and P15 and P16 have a first clearance portion B1 for setting KX1;

[0673] The lower end of KX1 corresponds to P25 and P26, and P25 and P26 have a second clearance portion B2 for setting KX1.

[0674] In at least one embodiment of this disclosure, P11, P12, P21 and P22 are considered as a unit. P21 can be rotated 180 degrees in the horizontal direction, and P22 can also be rotated 180 degrees in the horizontal direction, so that the domains of P11 and P22 are the same, and the domains of P12 and P21 are the same.

[0675] P13, P14, P23 and P24 are considered as a unit. P23 ​​can be rotated 180 degrees horizontally, and P24 can also be rotated 180 degrees horizontally, so that the domains of P13 are the same as the domains of P24, and the domains of P14 are the same as the domains of P23.

[0676] P15, P16, P25 and P26 are considered as a unit. P25 can be rotated 180 degrees horizontally, and P26 can also be rotated 180 degrees horizontally, so that the domains of P15 are the same as the domains of P26, and the domains of P16 are the same as the domains of P25.

[0677] P17, P18, P27 and P28 are considered as a unit. P27 can be rotated 180 degrees horizontally, and P28 can also be rotated 180 degrees horizontally, so that the domains of P17 are the same as the domains of P28, and the domains of P18 are the same as the domains of P27.

[0678] P19, P110, P29, and P210 are considered as a unit. P29 can be rotated 180 degrees horizontally, and P210 can also be rotated 180 degrees horizontally, so that the domains of P19 are the same as the domains of P210, and the domains of P110 are the same as the domains of P29.

[0679] In practice, each pixel electrode can be provided with a clearance portion, and it is not limited to the pixel electrode corresponding to the jumper having a clearance portion.

[0680] like Figures 35A-38 As shown, at the intersection of the first jumper line KX1 and the third row of gate lines GT3, the line width of the third row of gate lines GT3 is smaller than the maximum line width of the third row of gate lines GT3. This setting can reduce the parasitic capacitance formed by the overlap between the jumper line and the gate line.

[0681] At the intersection of the first jumper line KX1 and the fourth row of gate lines GT4, the line width of the fourth row of gate lines GT4 is less than the maximum line width of the fourth row of gate lines GT4.

[0682] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0683] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display driving circuit, comprising two gate driving circuits arranged at opposite sides of a display panel respectively, wherein each of the gate driving circuits comprises a plurality of cascaded driving circuits; each of the driving circuits comprises N clock signal terminals, N output sub-circuits and N driving signal output terminals, N is an integer greater than or equal to 2, the N output sub-circuits share a first pull-up node; an nth output sub-circuit is configured to control an nth driving signal output through an nth driving signal output terminal under the control of a potential of the first pull-up node according to an nth clock signal provided by an nth clock signal terminal; n is a positive integer less than or equal to N; an ith driving signal output terminal of one of the two driving circuits is electrically connected to an ith+j driving signal output terminal of the other of the two driving circuits, i and j are positive integers, i is a positive integer less than or equal to N, j is a positive integer less than or equal to N, and i+j is a positive integer less than or equal to N; when a potential of an ith clock signal provided by an ith clock signal terminal of the N clock signal terminals jumps from an invalid level to a valid level, a potential of the first pull-up node is a first voltage value; when a potential of an ith+j clock signal provided by an ith+j clock signal terminal of the N clock signal terminals jumps from an invalid level to a valid level, the potential of the first pull-up node is a second voltage value; the first voltage value is not equal to the second voltage value; a time period during which the potential of the ith clock signal is continuously at the valid level at least partially overlaps with a time period during which the potential of the ith+j clock signal is continuously at the valid level; a time point at which the potential of the ith clock signal jumps from the valid level to the invalid level is different from a time point at which the potential of the ith+j clock signal jumps from the valid level to the invalid level; the driving circuit further comprises M clock signal terminals, M output sub-circuits, a second carry output sub-circuit, M driving signal output terminals and a second carry signal output terminal, the M output sub-circuits share a second pull-up node; an Nth+m output sub-circuit is configured to output an Nth+m driving signal through an Nth+m driving signal output terminal under the control of a potential of the second pull-up node according to an Nth+m clock signal provided by an Nth+m clock signal terminal, m is a positive integer less than or equal to M, and M is a positive integer greater than or equal to 2; the second carry output sub-circuit is electrically connected to the second pull-up node, the second carry signal output terminal and a second carry clock signal terminal respectively, and is configured to control the second carry signal output terminal and the second carry clock signal terminal to be in communication under the control of the potential of the second pull-up node; when the potential of the ith clock signal jumps from the valid level to the invalid level, a potential of the first pull-up node is a third voltage value; when the potential of the ith+j clock signal jumps from the valid level to the invalid level, a potential of the first pull-up node is a fourth voltage value; and the third voltage value is not equal to the fourth voltage value. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 2. The display drive circuit of claim 1, wherein, ​ ​ ​ 3. The display drive circuit of claim 1, wherein, When the potential of the i-th clock signal jumps from the invalid level to the valid level, the potential of the first pull-up node rises by a first potential height within a first time; When the potential of the i+j-th clock signal changes from the invalid level to the valid level, the potential of the first pull-up node rises by a second potential height within a second time; The first potential height is not equal to the second potential height, and / or the first time is not equal to the second time.

4. The display drive circuit of claim 1, wherein, When the potential of the i-th clock signal jumps from the valid level to the invalid level, the potential of the first pull-up node falls by a third potential height within a third time; When the potential of the i+j-th clock signal changes from the valid level to the invalid level, the potential of the first pull-up node falls by a fourth potential height within a fourth time; The third potential height is not equal to the fourth potential height, and / or the third time is not equal to the fourth time.

5. The display drive circuit of claim 3, wherein, The driving circuit comprises a capacitor arranged between the a-th driving signal end and the first pull-up node, the first time is less than the second time, and the first potential height is less than the second potential height; a is an even number, and a is a positive integer; or The driving circuit comprises a capacitor arranged between the b-th driving signal end and the first pull-up node, the first time is greater than the second time, and the first potential height is greater than the second potential height; b is an odd number, and b is a positive integer. The driving circuit comprises a capacitor arranged between the a-th driving signal end and the first pull-up node, the third time is less than the fourth time, and the third potential height is greater than the fourth potential height; a is an even number, and a is a positive integer; or 6. The display drive circuit of claim 4, wherein, The driving circuit comprises a capacitor arranged between the b-th driving signal end and the first pull-up node, the third time is greater than the fourth time, and the third potential height is less than the fourth potential height; b is an odd number, and b is a positive integer. The driving circuit further comprises a first input sub-circuit, a first pull-down sub-circuit, a first pull-down node control sub-circuit, and N output reset sub-circuits; the N output reset sub-circuits share the first pull-down node; 7. The display drive circuit of claim 1, wherein, The first input sub-circuit is configured to control the potential of the first pull-up node under the control of a first input signal provided by a first input end; The first pull-down sub-circuit is electrically connected with the first pull-up node, the first pull-down node, a first reset end, and a first voltage end respectively, and is configured to control the first pull-up node to be in communication with the first voltage end under the control of the potential of the first pull-down node, and control the first pull-up node to be in communication with the first voltage end under the control of a first reset signal provided by the first reset end; The first pull-down node control sub-circuit is electrically connected with a first control voltage end, the first pull-up node, the first pull-down node, and the first voltage end respectively, and is configured to control the potential of the first pull-down node according to a first voltage signal provided by the first voltage end under the control of a first control voltage provided by the first control voltage end and the potential of the first pull-up node. ​ The nth output reset sub-circuit is electrically connected with the first pull-down node, the second voltage terminal and the nth drive signal output terminal, and is used for controlling the communication between the nth drive signal output terminal and the second voltage terminal under the control of the potential of the first pull-down node.

8. The display drive circuit of claim 7, wherein, The drive circuit further comprises a first carry signal output terminal and a first carry output sub-circuit; The first carry output sub-circuit is electrically connected with the first pull-up node, the first carry signal output terminal and a first carry clock signal terminal, and is used for controlling the communication between the first carry signal output terminal and the first carry clock signal terminal under the control of the potential of the first pull-up node.

9. The display drive circuit of claim 8, wherein, The drive circuit further comprises a first carry reset sub-circuit; The first carry reset sub-circuit is electrically connected with the first pull-down node, the first carry signal output terminal and a first voltage terminal, and is used for controlling the communication between the first carry signal output terminal and the first voltage terminal under the control of the potential of the first pull-down node.

10. The display drive circuit of claim 8, wherein, The first input sub-circuit is electrically connected with the first input terminal, a first input voltage terminal and the first pull-up node, and is used for controlling the communication between the first pull-up node and the first input voltage terminal under the control of a first input signal provided by the first input terminal; The first input terminal is a first carry signal output terminal of an adjacent upper-level drive circuit; The first input voltage terminal is a first carry signal output terminal of an adjacent upper-level drive circuit, a cth drive signal output terminal included in the adjacent upper-level drive circuit or a third voltage terminal; c is a positive integer less than or equal to N.

11. The display drive circuit of claim 10, wherein, The first carry clock signal terminal is a cth clock signal terminal of the N clock signal terminals; The first pull-down sub-circuit is further electrically connected with the first input voltage terminal, and is used for controlling the communication between the first pull-down node and the first voltage terminal under the control of a first input voltage provided by the first input voltage terminal; The first input sub-circuit is further electrically connected with a frame reset terminal, and is used for controlling the communication between the first pull-up node and the first voltage terminal under the control of a frame reset signal provided by the frame reset terminal.

12. The display drive circuit of claim 1, wherein, The drive circuit further comprises N capacitors; A first end of an nth capacitor of the N capacitors is electrically connected with the first pull-up node, and a second end of the nth capacitor is electrically connected with the nth drive signal output terminal.

13. The display drive circuit of claim 10, wherein, The first input sub-circuit comprises a first transistor, the first pull-down sub-circuit comprises a second transistor and a third transistor, and the first pull-down node control sub-circuit comprises a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; A control pole of the first transistor is electrically connected with the first input terminal, a first pole of the first transistor is electrically connected with the first input voltage terminal, and a second pole of the first transistor is electrically connected with the first pull-up node; A control pole of the second transistor is electrically connected with the first reset terminal, a first pole of the second transistor is electrically connected with the first pull-up node, and a second pole of the second transistor is electrically connected with the first voltage terminal; The control electrode of the third transistor is electrically connected with the first pull-down node, the first electrode of the third transistor is electrically connected with the first pull-up node, and the second electrode of the third transistor is electrically connected with the first voltage terminal; The control electrode of the fourth transistor and the first electrode of the fourth transistor are electrically connected with the first control voltage terminal, and the second electrode of the fourth transistor is electrically connected with the first pull-down control node; The control electrode of the fifth transistor is electrically connected with the first pull-down control node, the first electrode of the fifth transistor is electrically connected with the first control voltage terminal, and the second electrode of the fifth transistor is electrically connected with the first pull-down node; The control electrode of the sixth transistor is electrically connected with the first pull-up node, the first electrode of the sixth transistor is electrically connected with the first pull-down node, and the second electrode of the sixth transistor is electrically connected with the first voltage terminal; The control electrode of the seventh transistor is electrically connected with the first pull-up node, the first electrode of the seventh transistor is electrically connected with the first pull-down control node, and the second electrode of the seventh transistor is electrically connected with the first voltage terminal.

14. The display drive circuit of claim 11, wherein, The first pull-down sub-circuit comprises an eighth transistor, and the first input sub-circuit further comprises a ninth transistor; The control electrode of the eighth transistor is electrically connected with the first input voltage terminal, the first electrode of the eighth transistor is electrically connected with the first pull-down node, and the second electrode of the eighth transistor is electrically connected with the first voltage terminal; The control electrode of the ninth transistor is electrically connected with the frame reset terminal, the first electrode of the ninth transistor is electrically connected with the first pull-up node, and the second electrode of the ninth transistor is electrically connected with the first voltage terminal.

15. The display drive circuit of claim 13, wherein, The nth output sub-circuit comprises an nth output transistor; The control electrode of the nth output transistor is electrically connected with the first pull-up node, the first electrode of the nth output transistor is electrically connected with an nth clock signal terminal, and the second electrode of the nth output transistor is electrically connected with an nth drive signal output terminal; The first carry output sub-circuit comprises a first carry output transistor; The control electrode of the first carry output transistor is electrically connected with the first pull-up node, the first electrode of the first carry output transistor is electrically connected with the first carry clock signal terminal, and the second electrode of the first carry output transistor is electrically connected with the first carry signal output terminal; The nth output reset sub-circuit comprises an nth output reset transistor; The control electrode of the nth output reset transistor is electrically connected with the first pull-down node, the first electrode of the nth output reset transistor is electrically connected with the nth drive signal output terminal, and the second electrode of the nth output reset transistor is electrically connected with the second voltage terminal.

16. The display driver circuit of claim 9, wherein, The first carry reset sub-circuit comprises a first carry reset transistor; The control electrode of the first carry reset transistor is electrically connected with the first pull-down node, the first electrode of the first carry reset transistor is electrically connected with the first carry signal output terminal, and the second electrode of the first carry reset transistor is electrically connected with the first voltage terminal.

17. The display driver circuit of claim 15, wherein, The drive circuit further comprises a first on-off control sub-circuit; The first on-off control sub-circuit is electrically connected with a touch enable end, a first connection node and the first pull-up node, and is configured to control the first connection node and the first pull-up node to be connected or disconnected under the control of a touch enable signal provided by the touch enable end.

18. The display driver circuit of claim 17, wherein, The first on-off control sub-circuit comprises a first on-off control transistor. The control electrode of the first on-off control transistor is electrically connected with the touch enable end, the first electrode of the first on-off control transistor is connected with the first pull-up node, and the second electrode of the first on-off control transistor is electrically connected with the first connection node.

19. The display driver circuit of claim 1, wherein, The driving circuit further comprises a first output capacitor. The first end of the first output capacitor is electrically connected with the pull-up node circuit, and the second end of the first output capacitor is electrically connected with one of the N driving signal output ends.

20. The display driver circuit of claim 1, wherein, The driving circuit further comprises M capacitors. The first end of the mth capacitor in the M capacitors is electrically connected with the second pull-up node, and the second end of the mth capacitor in the M capacitors is electrically connected with the N+mth driving signal output end.

21. The display driver circuit of claim 1, wherein, The driving circuit further comprises a second input sub-circuit, a second pull-down sub-circuit, a second pull-down node control sub-circuit and M output reset sub-circuits; the M output reset sub-circuits share a second pull-down node; The second input sub-circuit is configured to control the potential of the second pull-up node under the control of a second input signal provided by a second input end; The second pull-down sub-circuit is electrically connected with the second pull-up node, the second pull-down node, a second reset end and a first voltage end, respectively, and is configured to control the second pull-up node and the first voltage end to be connected under the control of the potential of the second pull-down node, and control the second pull-up node and the first voltage end to be connected under the control of a second reset signal provided by the second reset end; The second pull-down node control sub-circuit is electrically connected with a second control voltage end, the second pull-up node, the second pull-down node and the first voltage end, respectively, and is configured to control the potential of the second pull-down node according to a first voltage signal provided by the first voltage end under the control of a second control voltage provided by the second control voltage end and the potential of the second pull-up node; The N+mth output reset sub-circuit is electrically connected with the second pull-down node, a second voltage end and the N+mth driving signal output end, respectively, and is configured to control the N+mth driving signal output end and the second voltage end to be connected under the control of the potential of the second pull-down node.

22. The display driver circuit of claim 21, wherein, The driving circuit further comprises a second carry reset sub-circuit; The second carry reset sub-circuit is electrically connected with the second pull-down node, the second carry signal output end and the first voltage end, respectively, and is configured to control the second carry signal output end and the first voltage end to be connected under the control of the potential of the second pull-down node.

23. The display driver circuit of claim 21, wherein, The second input sub-circuit is electrically connected with the second input end, the second input voltage end and the second pull-up node, and is configured to control the second pull-up node to be in communication with the second input voltage end under the control of a second input signal provided by the second input end. The second input end is a second carry signal output end of an adjacent upper-level driving circuit. The second input voltage end is a second carry signal output end of an adjacent upper-level driving circuit, a dth driving signal output end included in the adjacent upper-level driving circuit, or a third voltage end; d is a positive integer less than or equal to M.

24. The display driver circuit of claim 23, wherein, The second carry clock signal end is a dth clock signal end of the M clock signal ends. The second pull-down sub-circuit is further electrically connected with the second input voltage end, and is configured to control the second pull-down node to be in communication with the first voltage end under the control of a second input voltage provided by the second input voltage end. The second input sub-circuit is further electrically connected with a frame reset end, and is further configured to control the second pull-up node to be in communication with the first voltage end under the control of a frame reset signal provided by the frame reset end.

25. The display driver circuit of claim 1, wherein, The driving circuit further comprises M capacitors. A first end of an mth capacitor of the M capacitors is electrically connected with the second pull-up node, and a second end of the mth capacitor of the M capacitors is electrically connected with the N+mth driving signal output end.

26. The display driver circuit of claim 14, wherein, The first pull-down sub-circuit further comprises a tenth transistor. A control pole of the tenth transistor is electrically connected with the second pull-down node, a first pole of the tenth transistor is electrically connected with the first pull-up node, and a second pole of the tenth transistor is electrically connected with the first voltage end. The first pull-down node control sub-circuit further comprises an eleventh transistor. A control pole of the eleventh transistor is electrically connected with the second pull-up node, a first pole of the eleventh transistor is electrically connected with the first pull-down control node, and a second pole of the eleventh transistor is electrically connected with the first voltage end.

27. The display driver circuit of claim 15, wherein, The nth output reset sub-circuit further comprises an nth reset transistor. A control pole of the nth reset transistor is electrically connected with the second pull-down node, a first pole of the nth reset transistor is electrically connected with the nth driving signal output end, and a second pole of the nth reset transistor is electrically connected with the second voltage end.

28. The display driver circuit of claim 16, wherein, The first carry reset sub-circuit further comprises a second carry reset transistor. A control pole of the second carry reset transistor is electrically connected with the second pull-down node, a first pole of the second carry reset transistor is electrically connected with the first carry signal output end, and a second pole of the second carry reset transistor is electrically connected with the first voltage end.

29. The display driver circuit of claim 21, wherein, The second pull-down sub-circuit comprises a twelfth transistor. A control pole of the twelfth transistor is electrically connected with the first pull-down node, a first pole of the twelfth transistor is electrically connected with the second pull-up node, and a second pole of the twelfth transistor is electrically connected with the first voltage end. The second pull-down node control sub-circuit comprises a thirteenth transistor. The control electrode of the thirteenth transistor is electrically connected with the first pull-up node, the first electrode of the thirteenth transistor is electrically connected with the second pull-down control node, and the second electrode of the thirteenth transistor is electrically connected with the first voltage terminal.

30. The display driver circuit of claim 21, wherein, The N+m output reset sub-circuit comprises an N+m reset transistor. The control electrode of the N+m reset transistor is electrically connected with the first pull-down node, the first electrode of the N+m reset transistor is electrically connected with the N+m driving signal output terminal, and the second electrode of the N+m reset transistor is electrically connected with the second voltage terminal.

31. The display driver circuit of claim 22, wherein, The second carry reset sub-circuit comprises a third carry reset transistor and a fourth carry reset transistor. The control electrode of the third carry reset transistor is electrically connected with the second pull-down node, the first electrode of the third carry reset transistor is electrically connected with the second carry signal output terminal, and the second electrode of the third carry reset transistor is electrically connected with the first voltage terminal. The control electrode of the fourth carry reset transistor is electrically connected with the first pull-down node, the first electrode of the fourth carry reset transistor is electrically connected with the second carry signal output terminal, and the second electrode of the fourth carry reset transistor is electrically connected with the first voltage terminal.

32. The display driver circuit of claim 21, wherein, The driving circuit further comprises a second on-off control sub-circuit. The second on-off control sub-circuit is electrically connected with the touch enable terminal, the second connection node and the second pull-up node respectively, and is used for controlling the second connection node and the second pull-up node to be in communication or disconnected under the control of a touch enable signal provided by the touch enable terminal.

33. The display driver circuit of claim 32, wherein, The second on-off control sub-circuit comprises a second on-off control transistor. The control electrode of the second on-off control transistor is electrically connected with the touch enable terminal, the first electrode of the second on-off control transistor is connected with the second pull-up node, and the second electrode of the second on-off control transistor is electrically connected with the second connection node.

34. The display driver circuit of claim 1, wherein, A second output capacitor is included. The first end of the second output capacitor is electrically connected with the second pull-up node, and the second end of the second output capacitor is electrically connected with one of the M driving signal output terminals.

35. A display device comprising the display driving circuit according to any one of claims 1 to 34.

36. The display device of claim 35, wherein, A plurality of gate lines, a plurality of data lines and a plurality of rows and columns of pixel circuits are further included. The pixel circuit comprises a display control transistor and a pixel electrode. The gate electrode of the display control transistor is electrically connected with the gate line, the first electrode of the display control transistor is electrically connected with the data line, and the second electrode of the display control transistor is electrically connected with the pixel electrode. The pixel electrode is provided with a plurality of slits, and the included angle between the slit directions of two pixel electrodes in the same pixel electrode group is greater than 90 degrees and less than 180 degrees. The pixel electrode group is a pixel electrode group arranged in a display region formed by adjacent rows of gate lines and adjacent columns of data lines.

37. The display device of claim 36, wherein, Two rows of gate lines are arranged between two rows of adjacent pixel electrodes. The gate of one of the two transistors electrically connected with the same column data line is electrically connected with one of the two gate lines, and the gate of the other of the two transistors electrically connected with the same column data line is electrically connected with the other of the two gate lines; The width of the conductive connection part between the two transistors electrically connected with the same column data line and the column data line in the first direction is greater than the minimum width of the data line in the first direction; The first direction is the extension direction of the gate line.

38. A display device as claimed in claim 36 or 37, wherein, Further comprising a plurality of rows of common electrodes and a plurality of columns of common electrodes; The two adjacent rows of common electrodes are electrically connected through a cross-over line, and the cross-over line is arranged in the same layer as the pixel electrode.

39. The display device of claim 38, wherein, The corresponding pixel electrodes at both ends of the cross-over line have a avoiding part.

40. The display device of claim 38, wherein, The line width of the gate line at the overlapping position of the cross-over line and the gate line is less than the maximum line width of the gate line.

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