Memory array and method of making the same, memory, electronic device

Abstract

The embodiment of the application discloses a kind of storage array and its preparation method, memory, electronic equipment, it is related to semiconductor technical field.Storage array includes: substrate and storage cell subarray.Storage cell subarray includes: laminated structure, first channel layer, first gate dielectric layer and first gate.Laminated structure includes conductive layer and storage function layer, conductive layer includes conductive block, between adjacent two conductive blocks, storage function layer is arranged, and adjacent two conductive blocks and storage function layer form storage cell.First channel layer corresponds with storage cell, at least part of first channel layer is located on the side wall of laminated structure, and is in contact with adjacent two conductive blocks in storage cell and storage function layer.Adjacent two conductive blocks and first channel layer, first gate dielectric layer, first gate form first transistor.Storage array is 3D architecture, and first transistor is vertical channel structure field effect transistor, it is convenient to increase the quantity of storage cell and first transistor, improve storage density.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] With the continuous evolution of integrated circuit technology, the number of transistors per unit area on chips in various electronic products (such as computers and mobile phones) is constantly increasing, leading to continuous optimization of the performance of electronic products. Taking chip memory as an example, as the number of transistors per unit area increases, the storage density of chip memory also continues to grow, thereby meeting people's data processing needs in the information age.

[0003] However, due to the differences in the structure and manufacturing process of the logic units in the chip processor and the memory units in the chip memory, there is a gap in the degree of performance improvement between the two. That is, the storage density of the chip memory cannot keep up with the computing speed of the chip processor, resulting in the "memory wall" phenomenon, which limits the overall performance of the system including the chip processor and the chip memory. Summary of the Invention

[0004] This application provides a storage array and its fabrication method, a memory, and an electronic device for improving storage density.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a memory array is provided, comprising: a substrate and a plurality of memory cell subarrays located on the substrate. The memory cell subarrays include: a stacked structure, a first channel layer, a first gate dielectric layer, and a first gate. The stacked structure includes multiple conductive layers and a plurality of memory functional layers stacked along a first direction. The conductive layers include a plurality of conductive blocks spaced apart along a second direction, with a memory functional layer disposed between adjacent conductive blocks. Two adjacent conductive blocks and the memory functional layer between them form a memory cell. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate. The first channel layer corresponds to a memory cell, and at least a portion of the first channel layer is located on the sidewall of the stacked structure and is in contact with two adjacent conductive blocks and the memory functional layer in the memory cell. The first gate dielectric layer covers the first channel layer. The first gate is located on the side of the first gate dielectric layer away from the first channel layer. Two adjacent conductive blocks, the first channel layer, the first gate dielectric layer, and the first gate form a first transistor.

[0007] Some embodiments of this application provide a memory array in which a storage functional layer is disposed between two adjacent conductive blocks to form a memory cell for storing data. The two adjacent conductive blocks, the first channel layer, the first gate dielectric layer, and the first gate in this memory cell constitute a first transistor. This first transistor is used to change the state of the storage functional layer in the corresponding memory cell, thereby achieving data storage. Embodiments of this application stack conductive layers comprising multiple conductive blocks and storage functional layers to form a stacked structure. The first channel layer, the first gate dielectric layer, and the first gate in the first transistor are disposed on the sidewalls of the stacked structure, making the memory array have a 3D architecture. This facilitates increasing the number of memory cells per unit area, thereby increasing the storage density of the memory array. Furthermore, the first transistor in this application is a vertical channel field-effect transistor (VDT). VDTs have a relatively small projected area on the substrate, which allows for the placement of more first transistors on the substrate, further improving the storage density of the memory array.

[0008] In the first possible implementation, two adjacent conductive blocks in the memory cell are located on the same conductive layer. Along the second direction, the memory functional layer in the memory cell is located between two adjacent conductive blocks. This allows for the simultaneous fabrication of two conductive blocks in each memory cell in a single patterning process, simplifying the fabrication process of the memory array. Furthermore, a sufficient contact area between the memory functional layer and the conductive blocks is enough for the memory cell to possess the required functions, which helps reduce the alignment requirements between the conductive blocks and the memory functional layer within the same memory cell, thus reducing the fabrication difficulty of the memory array.

[0009] In one possible implementation of the first aspect, conductive blocks and storage functional layers are alternately arranged along the second direction within the same conductive layer. Two adjacent storage cells on the same layer can share a conductive block and be electrically connected to each other through this shared block. This simplifies the structure of multiple storage cells on the same layer (or in the same row), increases the integration density of multiple storage cells on the same layer, and facilitates the placement of a larger number of storage cells within the same conductive layer, thereby further improving the integration density, storage capacity, and storage density of the storage array.

[0010] In one possible implementation of the first aspect, the stacked structure further includes multiple first insulating layers. Along the first direction, multiple conductive layers and multiple first insulating layers are alternately arranged. By providing the first insulating layers, adjacent conductive layers can be separated, forming an insulating barrier between them to prevent short circuits and ensure good electrical performance of the storage array.

[0011] In one possible implementation of the first aspect, two adjacent conductive blocks in the memory cell are located in two adjacent conductive layers, and the orthographic projections of the two adjacent conductive blocks on the substrate overlap. Along the first direction, the memory functional layer in the memory cell is located between two adjacent conductive blocks. This helps to increase the contact area between the memory functional layer and the adjacent conductive blocks, thereby improving the performance of the memory cell.

[0012] In one possible implementation of the first aspect, among two adjacent conductive layers, the conductive block located in one conductive layer is called the first conductive block, and the conductive block located in the other conductive layer is called the second conductive block. In the orthographic projection of the two adjacent conductive layers onto the substrate, along the second direction, multiple first conductive blocks and multiple second conductive blocks are alternately arranged. Along the first direction, one first conductive block and two second conductive blocks overlap, and one first conductive block overlaps with two storage functional layers. Thus, two adjacent conductive layers and multiple storage functional layers located between them constitute a row of storage cells. Multiple storage cells in this row are arranged sequentially along the second direction, and adjacent storage cells in this row share a first conductive block or a second conductive block, and are electrically connected to each other through the shared conductive block. By sharing the first conductive block or the second conductive block, the orthographic projection area of ​​the first conductive block or the shared second conductive block on the substrate can be increased, which helps reduce the fabrication difficulty of the conductive layer, and thus helps reduce the fabrication difficulty of the storage array.

[0013] In one possible implementation of the first aspect, the stacked structure further includes multiple first insulating blocks. Within the same conductive layer, multiple conductive blocks and multiple first insulating blocks are alternately arranged along the second direction. By setting the first insulating blocks, adjacent conductive blocks in the same conductive layer can be separated, forming an insulating barrier between the two adjacent conductive blocks to prevent short circuits and ensure good electrical performance of the storage array.

[0014] In one possible implementation of the first aspect, the memory cell subarray includes multiple rows of memory cells, each row comprising multiple memory cells arranged along a second direction. The stacked structure also includes multiple layers of second insulating layers located between adjacent rows of memory cells. By providing the second insulating layers, adjacent rows of memory cells can be separated, forming an insulating barrier between them to prevent short circuits and ensure good electrical performance of the memory array.

[0015] In one possible implementation of the first aspect, the memory cell subarray includes multiple rows of memory cells, each row comprising multiple memory cells arranged along a second direction. The stacked structure also includes multiple second insulating blocks, with the storage functional layers of multiple memory cells and the multiple second insulating blocks alternately arranged within the same row of memory cells. Alternatively, the storage functional layers of multiple memory cells within the same row of memory cells are connected and form a single structure. By setting multiple second insulating blocks, adjacent storage functional layers located on the same conductive layer can be separated, facilitating clearer definition of the memory cells. By connecting the storage functional layers of multiple memory cells within the same row of memory cells and forming a single structure, etching of the storage functional layers of multiple memory cells within the same row of memory cells can be avoided, effectively reducing the number of photomask passes, simplifying the fabrication process of the storage functional layers, and consequently simplifying the fabrication process of the memory array and reducing costs.

[0016] In one possible implementation of the first aspect, the memory cell subarray includes multiple columns of memory cells, each column comprising multiple memory cells stacked along a first direction. Within the same column, the orthographic projections of the storage functional layers of any two memory cells onto the substrate at least partially overlap. This improves the regularity of the arrangement of memory cells in each memory cell subarray, thereby improving the regularity of the arrangement of the first transistors corresponding to each memory cell, and reducing the wiring and fabrication difficulty of the memory array.

[0017] In a possible implementation of the first aspect, multiple stacked structures are arranged sequentially along a third direction, which is parallel to the substrate and perpendicular to the second direction. The stacked structures have opposing first and second sidewalls. The multiple stacked structures include at least one pair of stacked structures, each pair comprising an adjacent first and second stacked structure. The first sidewall of the first stacked structure is located on a side away from the second stacked structure, and the second sidewall of the second stacked structure is located on a side away from the first stacked structure. The first channel layer, first gate dielectric layer, and first gate of the first transistor corresponding to a memory cell in the first stacked structure are located on the first sidewall of the first stacked structure, and the first channel layer, first gate dielectric layer, and first gate of the first transistor corresponding to a memory cell in the second stacked structure are located on the second sidewall of the second stacked structure.

[0018] In a possible implementation of the first aspect, the stacked structure has opposing first and second sidewalls. In the first transistor corresponding to a memory cell in the stacked structure, a portion of the first channel layer, a portion of the first gate dielectric layer, and a portion of the first gate are located on the first sidewall, while another portion of the first channel layer, another portion of the first gate dielectric layer, and another portion of the first gate are located on the second sidewall. This is equivalent to each first transistor including two conductive channels, which increases the effective channel width and effectively increases the read speed of the memory array.

[0019] In a possible implementation of the first aspect, the memory cell subarray includes multiple columns of memory cells, each column comprising multiple memory cells arranged sequentially along a first direction. Along the first and second directions, the first channel layers of adjacent first transistors are spaced apart. The first gate dielectric layers of multiple first transistors corresponding to the same column of memory cells are connected and located on the sidewalls of the stacked structure. The first gates of multiple first transistors corresponding to the same column of memory cells are connected and located on the sidewalls of the stacked structure. By separating the first channel layers of adjacent first transistors, short circuits between different first transistors through the first channel layers can be avoided, ensuring good electrical performance of each first transistor. By connecting the first gate dielectric layers of multiple first transistors corresponding to the same column of memory cells, the first gate dielectric layers of these multiple first transistors can be integrated into a single structure. By connecting the first gates of multiple first transistors corresponding to the same column of memory cells, the first gates of these multiple first transistors can be integrated into a single structure, which helps to reduce the difficulty of fabricating the first transistors and the memory array. Furthermore, after the first gates of multiple first transistors corresponding to the same column of memory cells are connected, the first gates of these multiple first transistors can be electrically connected to the same word line, which helps to reduce the number of word lines and simplify the structure of the memory array.

[0020] In one possible implementation of the first aspect, in the first transistor furthest from the substrate along the first direction, the first channel layer, the first gate dielectric layer, and the first gate also cover the top wall of the stacked structure. This avoids etching the portions of the first channel layer, the first gate dielectric layer, and the first gate covering the top wall of the stacked structure during the fabrication of the first transistor furthest from the substrate along the first direction, thus reducing the difficulty of fabricating the first transistor and the memory array.

[0021] In one possible implementation of the first aspect, in the first transistor corresponding to each memory cell, the cross-sectional patterns of the first channel layer, the first gate dielectric layer, and the first gate are annular along a first direction and a third direction. The first channel layer surrounds the memory cell, the first gate dielectric layer surrounds the first channel layer, and the first gate surrounds the first gate dielectric layer. The third direction is parallel to the substrate and perpendicular to the second direction. This makes the structure of each first transistor an all-gate structure, effectively increasing the overlap area of ​​the first gate and the first channel layer, thereby effectively improving the control capability of the first gate on the first channel layer and improving the performance of the first transistor and the memory array.

[0022] In a possible implementation of the first aspect, the memory cell subarray includes multiple columns of memory cells, each column comprising multiple memory cells stacked along a first direction. The first gates of multiple first transistors corresponding to the same column of memory cells are connected and located between the sidewalls of the stacked structure and two adjacent first gate dielectric layers. This allows the first gates of the multiple first transistors to be electrically connected to the same word line, which helps reduce the number of word lines and simplifies the structure of the memory array.

[0023] In one possible implementation of the first aspect, at least two memory cell subarrays are arranged sequentially along the second direction, and at least two memory cell subarrays are arranged sequentially along the third direction. The third direction is parallel to the substrate and perpendicular to the second direction. This allows for increased storage density of the memory array while avoiding an increase in the thickness of the memory array.

[0024] In one possible implementation of the first aspect, at least two memory cell subarrays are arranged sequentially along a first direction. The memory array also includes an encapsulation layer located between two adjacent memory cell subarrays along the first direction. By arranging the memory cell subarrays along the first direction, the storage density of the memory array can be increased while space utilization is improved and the area of ​​the memory array can be reduced. The encapsulation layer can separate two adjacent memory cell subarrays along the first direction, improving the structural stability of the upper-layer memory cell subarray.

[0025] In a possible implementation of the first aspect, the memory cell subarray includes multiple rows of memory cells, each row comprising multiple memory cells arranged along a second direction. The memory cell subarray further includes multiple second transistors located at the ends of a row of memory cells, arranged in a column along a first direction; each second transistor includes a second source, a second drain, a second channel layer, a second gate dielectric layer, and a second gate. Two adjacent conductive blocks at the ends of a row of memory cells respectively form a second source and a second drain, with a third insulating block disposed between the second source and the second drain. At least a portion of the second channel layer is located on the sidewall of the stacked structure and is in contact with the second source, the second drain, and the third insulating block. The second gate dielectric layer covers the second channel layer. The second gate is located on the side of the second gate dielectric layer away from the second channel layer. By providing the second transistors, the operation of a specific row of memory cells in the memory cell subarray can be selectively controlled. When the first gates of the first transistors corresponding to the memory cells in the same column are connected and form an integral structure, interference between different rows of memory cells can be avoided, ensuring the normal operation of the memory array. In addition, the second transistor is a vertical channel field-effect transistor, which has a smaller projected area on the substrate, thus avoiding affecting the storage density of the memory array.

[0026] In one possible implementation of the first aspect, the storage functional layer includes a ferroelectric material layer, a resistive switching material layer, or a phase change material layer. When the storage functional layer is a ferroelectric material layer, the storage array is a ferroelectric memory array. When the storage functional layer is a resistive switching material layer, the storage array is a resistive switching memory array. When the storage functional layer is a phase change material layer, the storage array is a phase change memory array.

[0027] In a second aspect, a method for fabricating a memory array is provided, the method comprising: providing a substrate; forming an initial stacked structure on the substrate, forming a first channel layer, a first gate dielectric layer, and a first gate. The initial stacked structure includes multiple conductive layers and multiple memory functional layers stacked along a first direction; the conductive layers include multiple conductive blocks spaced apart sequentially along a second direction, with a memory functional layer disposed between adjacent conductive blocks, and the adjacent conductive blocks and the memory functional layer located between the adjacent conductive blocks forming a memory cell. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate. The first channel layer corresponds to a memory cell, and at least a portion of the first channel layer is located on the sidewall of the initial stacked structure and is in contact with two adjacent conductive blocks and the memory functional layer in the memory cell. The first gate dielectric layer covers the first channel layer. The first gate is located on the side of the first gate dielectric layer away from the first channel layer. Two adjacent conductive blocks, the first channel layer, the first gate dielectric layer, and the first gate form a first transistor.

[0028] In a possible implementation of the second aspect, forming an initial stacked structure on a substrate includes: alternately forming a first composite layer and a first sacrificial layer on the substrate. Forming the first composite layer includes: forming a first conductive thin film; etching the first conductive thin film to form a plurality of conductive blocks spaced apart sequentially along a second direction, thereby obtaining a conductive layer. A storage functional layer is formed between two adjacent conductive blocks, wherein two adjacent conductive blocks in the same storage cell are located in the conductive layer of the first composite layer.

[0029] In a possible implementation of the second aspect, forming a first channel layer, a first gate dielectric layer, and a first gate includes: forming a channel film that at least covers the sidewalls of the initial stacked structure; forming a gate dielectric film that covers the channel film; forming a gate film that covers the gate dielectric film; etching the gate film, the gate dielectric film, and the channel film to form an initial gate, an initial gate dielectric layer, and an initial channel layer extending along a first direction; removing a first sacrificial layer through the sidewalls of the initial stacked structure not covered by the initial gate, the initial gate dielectric layer, and the initial channel layer to form a first gap; and etching the initial channel layer through the first gap to remove the portion of the initial channel layer opposite to the first gap.

[0030] In a possible implementation of the second aspect, the initial gate, initial gate dielectric layer, and initial channel layer are all located at least on two opposing sidewalls of the initial stacked structure. Before removing the first sacrificial layer via the portion of the sidewalls of the initial stacked structure not covered by the initial gate, initial gate dielectric layer, and initial channel layer, the method further includes: etching at least the initial stacked structure along a first direction and along a second direction to form a first initial stacked structure and a second initial stacked structure disposed opposite to each other, wherein the initial gate, initial gate dielectric layer, and initial channel layer are all divided into two parts, with one part of each located on the sidewall of the first initial stacked structure and the other part located on the sidewall of the second initial stacked structure.

[0031] In a possible implementation of the second aspect, after forming the first channel layer, the first gate dielectric layer and the first gate, the fabrication method further includes: filling the first gap with insulating material to form a first insulating layer.

[0032] In a possible implementation of the second aspect, the initial gate, the initial gate dielectric layer, and the initial channel layer are all located on at least two opposite sidewalls of the initial stacked structure; after etching the initial channel layer through the first gap, a first channel pattern is obtained. The method of forming a first channel layer, a first gate dielectric layer, and a first gate further includes: etching an initial gate dielectric layer through a first gap to remove the portion of the initial gate dielectric layer opposite to the first gap, forming a first gate dielectric pattern; depositing material of the first channel layer within the first gap to form a second channel pattern, the first channel pattern and the second channel pattern forming the first channel layer; the cross-sectional pattern of the first channel layer is annular along a first direction and along a third direction, the first channel layer surrounding the memory cell, the third direction being parallel to the substrate and perpendicular to the second direction; depositing material of the first gate dielectric layer within the first gap to form a second gate dielectric pattern, the first gate dielectric pattern and the second gate dielectric pattern forming the first gate dielectric layer; the cross-sectional pattern of the first gate dielectric layer is annular along the first direction and along a third direction, the first gate dielectric layer surrounding the first channel layer; depositing material of the first gate within the first gap to form a first gate pattern, the portions of the first gate pattern and the initial gate located on opposite sides of the same memory cell forming the first gate; the cross-sectional pattern of the first gate is annular along the first direction and along a third direction, the first gate surrounding the first gate dielectric layer.

[0033] In a possible implementation of the second aspect, forming an initial stacked structure on a substrate includes: alternately forming a second composite layer and a second sacrificial layer on the substrate. Forming the second composite layer includes: forming a second conductive thin film; etching the second conductive thin film to form a plurality of conductive blocks spaced apart sequentially along a second direction to obtain a conductive layer; forming a storage functional layer on the plurality of conductive blocks; forming a third conductive thin film on the storage functional layer; etching the third conductive thin film to form a plurality of conductive blocks spaced apart sequentially along the second direction to obtain a conductive layer; along a first direction, two adjacent conductive blocks in the same storage cell are respectively located in two adjacent conductive layers in the second composite layer, and the orthographic projections of the two adjacent conductive blocks on the substrate overlap.

[0034] In a possible implementation of the second aspect, forming a storage functional layer on a plurality of conductive blocks includes: forming a plurality of second insulating blocks spaced apart sequentially along a second direction on the plurality of conductive blocks; forming a storage functional layer between two adjacent second insulating blocks, wherein the plurality of storage functional layers are spaced apart sequentially along the second direction. In two adjacent conductive layers of the second composite layer, a conductive block located in one conductive layer is a first conductive block, and a conductive block located in the other conductive layer is a second conductive block. In the orthographic projection of the two adjacent conductive layers onto the substrate, along the second direction, a plurality of first conductive blocks and a plurality of second conductive blocks are alternately arranged; along the first direction, one first conductive block and two second conductive blocks overlap, and one first conductive block and two storage functional layers overlap.

[0035] In a possible implementation of the second aspect, forming a first channel layer, a first gate dielectric layer, and a first gate includes: forming a channel film that at least covers the sidewalls of an initial stacked structure; forming a gate dielectric film that covers the channel film; forming a gate film that covers the gate dielectric film; etching the gate film, the gate dielectric film, and the channel film to form an initial gate, an initial gate dielectric layer, and an initial channel layer extending along a first direction; removing a second sacrificial layer through the sidewalls of the initial stacked structure not covered by the initial gate, the initial gate dielectric layer, and the initial channel layer to form a second gap; etching the initial channel layer through the second gap to remove the portion of the initial channel layer opposite to the second gap to form a plurality of first channel layers spaced apart in the first direction; and filling the second gap with an insulating material to form a second insulating layer.

[0036] Thirdly, a memory is provided, comprising: a controller, and a memory array as described in any of the embodiments of the first aspect.

[0037] Fourthly, an electronic device is provided, comprising: a processor, and a memory as described in any embodiment of the third aspect. The memory is used to store data generated by the processor.

[0038] The technical effects of the storage array fabrication method in the second aspect, the memory in the third aspect, and the electronic device in the fourth aspect can be found in the technical effects of different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0039] Figure 1a This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0040] Figure 1b A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0041] Figure 2 This is a schematic diagram of the structure of an array cell in a ferroelectric memory array provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0044] Figure 5a This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0045] Figure 5b for Figure 5a The front view of the storage array shown;

[0046] Figure 5c for Figure 5a A cross-sectional view of the storage array shown along the second direction and the third direction;

[0047] Figure 5d for Figure 5a A cross-sectional view of the storage array shown along a first direction and a third direction;

[0048] Figure 6 This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0049] Figure 7 An equivalent circuit diagram of a storage array provided in an embodiment of this application;

[0050] Figure 8a This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0051] Figure 8b for Figure 8a The front view of the storage array shown;

[0052] Figure 8c for Figure 8aA cross-sectional view of the storage array shown along the second direction and the third direction;

[0053] Figure 8d for Figure 8a A cross-sectional view of the storage array shown along a first direction and a third direction;

[0054] Figure 9a This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0055] Figure 9b for Figure 9a The front view of the storage array shown;

[0056] Figure 9c for Figure 9a A cross-sectional view of the storage array shown along the second direction and the third direction;

[0057] Figure 9d for Figure 9a A cross-sectional view of the storage array shown along a first direction and a third direction;

[0058] Figure 10a This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0059] Figure 10b for Figure 10a The front view of the storage array shown;

[0060] Figure 10c for Figure 10a A cross-sectional view of the storage array shown along the second direction and the third direction;

[0061] Figure 10d for Figure 10a A cross-sectional view of the storage array shown along a first direction and a third direction;

[0062] Figure 11a This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0063] Figure 11b for Figure 11a The front view of the storage array shown;

[0064] Figure 11c for Figure 11a A cross-sectional view of the storage array shown along the second direction and the third direction;

[0065] Figure 11d for Figure 11a A cross-sectional view of the storage array shown along a first direction and a third direction;

[0066] Figure 12a This is a schematic diagram of another storage array structure provided in an embodiment of this application;

[0067] Figure 12b for Figure 12a The front view of the storage array shown;

[0068] Figure 12c for Figure 12a A cross-sectional view of the storage array shown along the second direction and the third direction;

[0069] Figure 12d for Figure 12a A cross-sectional view of the storage array shown along a first direction and a third direction;

[0070] Figure 13 A flowchart illustrating a method for fabricating a storage array, as provided in an embodiment of this application;

[0071] Figures 14a to 14k A flowchart illustrating the fabrication process of a storage array provided in this application embodiment;

[0072] Figures 15a-15d This is a flowchart illustrating the fabrication process of another storage array provided in an embodiment of this application;

[0073] Figures 16a-16e This is a flowchart illustrating the fabrication process of another storage array provided in an embodiment of this application;

[0074] Figures 17a to 17g This is a flowchart illustrating the fabrication process of another storage array provided in an embodiment of this application;

[0075] Figures 18a-18d This is a flowchart illustrating the fabrication process of another storage array provided in an embodiment of this application. Detailed Implementation

[0076] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0077] In the description of this application, unless otherwise stated, "multiple" means two or more. "At least one" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0078] "AND / OR" describes the relationship between related objects, indicating that there can be three relationships. For example, A AND / OR B can mean: A alone, A and B simultaneously, or B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "OR" relationship.

[0079] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner for ease of understanding.

[0080] In this application embodiment, "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings. In the accompanying drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the drawings do not reflect the actual dimensional proportions.

[0081] This application describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown in this application, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0082] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0083] This application provides an electronic device. The electronic device can be a mobile phone, tablet, television, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, as well as cellular phone, personal digital assistant (PDA), augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, smart wearable device (e.g., smartwatch, smart bracelet), in-vehicle device, smart home device, and / or smart city device. This application does not impose any special limitations on the specific type of the electronic device.

[0084] Figure 1a This is a schematic diagram of the architecture of an electronic device provided as an example of an embodiment of this application. Figure 1a As shown, the electronic device 1000 includes components such as a memory 500, a processor 200, an input device 300, and an output device 400. Those skilled in the art will understand that... Figure 1a The structure of the electronic device shown does not constitute a limitation on the electronic device 100, which may include, for example... Figure 1a The components shown may have more or fewer components, or may be combined as follows: Figure 1a Some of the components shown, or those that can be combined with, for example Figure 1a The component arrangements shown are different.

[0085] The memory 500 is used to store software programs and modules. The memory 500 mainly includes a program storage area and a data storage area. The program storage area can store the operating system, application programs required for at least one function (such as sound playback, image playback, etc.), etc.; the data storage area can store data created based on the use of the electronic device (such as audio data, image data, phonebook, etc.). Furthermore, the memory 500 includes external memory 510 and internal memory 520. Data stored in the external memory 510 and internal memory 520 can be transferred between each other. External memory 510 includes, for example, a hard disk, USB flash drive, floppy disk, etc. Internal memory 520 includes, for example, static random access memory (SRAM), dynamic random access memory (DRAM), read-only memory, etc.

[0086] The processor 200 is the control center of the aforementioned electronic device 1000. It connects to various parts of the electronic device 1000 via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 500, and by calling data stored in the memory 500, it performs various functions and processes data of the electronic device 1000, thereby providing overall monitoring of the electronic device 1000. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, or other application-specific integrated circuits (ASICs). Figure 1a Taking processor 200 as an example (CPU), the CPU may include an arithmetic logic unit (ALU) 210 and a control unit 220. The ALU 210 retrieves data stored in the internal memory 520, processes the data, and typically sends the processed result back to the internal memory 520. The control unit 220 can control the ALU 210 to process the data, and can also control the external memory 510 and the internal memory 520 to store or retrieve data. The memory 500 can store data generated by the processor 200.

[0087] Input device 300 is used to receive input digital or character information and generate key signal inputs related to user settings and function control of electronic device 1000. For example, input device 300 may include a touchscreen and other input devices. A touchscreen, also known as a touch panel, can collect touch operations performed by the user on or near the touchscreen (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touchscreen) and drive corresponding connected devices according to a pre-set program. Optionally, the touchscreen may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, transmitting the signal to the touch controller. The touch controller receives touch information from the touch detection device, converts it into touch point coordinates, sends it to processor 200, and can receive and execute commands from processor 200. Furthermore, touchscreens can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. Other input devices may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control buttons, power switch buttons, etc.), trackballs, mice, and joysticks. The controller 220 in the processor 200 can also control the input device 300 to receive or not receive input signals. Furthermore, the input digital or character information received by the input device 300, as well as the key signal inputs related to user settings and function control of the electronic device, can be stored in the internal memory 520.

[0088] Output device 400 is used to output signals corresponding to data input by input device 300 and stored in internal memory 520. For example, output device 400 outputs audio signals or video signals. The controller 220 in the processor 200 can also control output device 400 to output signals or not output signals.

[0089] It should be noted that, Figure 1a The thick arrows in the diagram are used to indicate data transmission, and the direction of the thick arrow indicates the direction of data transmission. For example, a one-way arrow between input device 300 and internal memory 520 indicates that data received by input device 300 is transmitted to internal memory 520. As another example, a two-way arrow between arithmetic unit 210 and internal memory 520 indicates that data stored in internal memory 520 can be transmitted to arithmetic unit 210, and data processed by arithmetic unit 210 can be transmitted to internal memory 520. Figure 1a The thin arrows in the diagram indicate components that the controller 220 can control. For example, the controller 220 can control external memory 510, internal memory 520, arithmetic unit 210, input device 300, and output device 400.

[0090] Optional, such as Figure 1aThe electronic device 1000 shown may also include various sensors, such as gyroscope sensors, hygrometer sensors, infrared sensors, magnetometer sensors, etc., which will not be described in detail here. Optionally, the electronic device 1000 may also include wireless fidelity (WiFi) modules, Bluetooth modules, etc., which will not be described in detail here.

[0091] It is understood that the memory provided in this application embodiment can be used as the memory 500 in the above-described electronic device 1000. For example, the memory provided in this application embodiment can be used as the external memory 510 in the above-described memory 500, or it can be used as the internal memory 520 in the above-described memory 500.

[0092] The memories provided in this application include, but are not limited to, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), or phase change memory (PCM). Ferroelectric random access memory can be simply referred to as ferroelectric memory, and resistive random access memory can be simply referred to as resistive random access memory.

[0093] In some examples, such as Figure 1b As shown, the memory 500 includes a controller 600 and a memory array 100. The controller 600 and the memory array 100 can be configured independently or integrated together. The number of memory arrays 100 can be one or more. Figure 1b The diagram shows four storage arrays 100.

[0094] For example, controller 600 may be coupled to storage array 100 and used to control storage array 100 to store data. For instance, controller 600 may manage data stored in storage array 100 and communicate with external devices (e.g., a host). Furthermore, controller 600 may also control the operation of storage array 100, such as read or write operations. Of course, controller 600 may perform any other suitable functions, not limited to the two examples given.

[0095] For example, the memory cells provided in the embodiments of this application all include: two adjacent conductive blocks, and a storage functional layer disposed between the two conductive blocks. The two conductive blocks are disposed opposite each other along the stacking direction of the two conductive blocks and the storage functional layer. The storage functional layer includes, but is not limited to, a ferroelectric material layer, a resistive switching material layer, or a phase change material layer. When the storage functional layer is a ferroelectric material layer, the memory is a ferroelectric memory. When the storage functional layer is a resistive switching material layer, the memory is a resistive switching memory. When the storage functional layer is a phase change material layer, the memory is a phase change memory.

[0096] The principles of data storage for the various types of memory described above are basically similar. For example, the two conductive blocks in the memory cell can be used as two electrodes. By forming an electric field between the two conductive blocks, the state of the storage functional layer can be changed. By utilizing the change in the state of the storage functional layer, data storage can be achieved.

[0097] Taking a ferroelectric material layer as the storage functional layer and a ferroelectric memory as an example, the ferroelectric material layer comprises ferroelectric materials and can serve as an insulating medium, enabling the two electrodes in the storage cell and the ferroelectric material layer to form a ferroelectric capacitor. Ferroelectric memory utilizes the characteristic that ferroelectric materials can spontaneously polarize, and that their polarization state can be reoriented under the influence of an external electric field, to store data.

[0098] For example, the two conductive blocks mentioned above are the first conductive block and the second conductive block, respectively. When a positive voltage is applied to the first conductive block and a negative voltage is applied to the second conductive block, an electric field is formed between the first and second conductive blocks. Under the influence of this electric field, the polarity of the ferroelectric material in the ferroelectric layer points towards the first conductive block. When a negative voltage is applied to the first conductive block and a positive voltage is applied to the second conductive block, an electric field is formed between the first and second conductive blocks. Under the influence of this electric field, the polarity of the ferroelectric material in the ferroelectric layer points towards the second conductive block.

[0099] Specifically, when an electric field is applied to a ferroelectric material, its central atoms remain in a low-energy state along with the electric field. Conversely, when an electric field is reversed and applied to the same ferroelectric material, its central atoms move in the direction of the electric field within the crystal and remain in another low-energy state. A large number of central atoms move and couple within the crystal unit cell to form ferroelectric domains. Under the influence of an electric field, these ferroelectric domains generate polarization charges (also known as flipped charges).

[0100] Ferroelectric domains exhibit higher flip charges when flipped under an electric field, while ferroelectric domains exhibit lower flip charges when not flipped under an electric field. This binary stable state of ferroelectric materials allows them to be used as memory. By utilizing the different directions of residual polarization, applying an electric field in the same direction will produce different flip charges, which can be used to store data "0" and "1".

[0101] When an electric field is applied to a ferroelectric crystal, the central atom moves in the direction of the electric field within the crystal. As the atom moves, it passes through an energy barrier, causing charge breakdown. After the electric field is removed, the central atom can maintain its position and polarization state. Therefore, ferroelectric memory formed using ferroelectric materials has the characteristic of non-volatility, meaning that the stored data will not be lost when the power is off.

[0102] Ferroelectric memories (FEs), as a type of non-volatile memory, offer advantages such as high speed, high density, low power consumption, and radiation resistance. Specifically, FEs can perform write operations at bus speeds, with virtually no write latency during data transmission. They impose no limitations on the amount of data transferred or write latency, allowing the system to complete a write operation on the entire chip memory instantaneously. In other words, FEs have extremely fast read and write speeds. Furthermore, because they use ferroelectric capacitors as the storage medium, FE write operations only need to be performed under the operating voltage. Therefore, the operating current and quiescent current of FEs are very low, resulting in very low power consumption.

[0103] For example, a ferroelectric memory includes multiple array cells arranged in an array, and the structure of the array cells mainly includes, for example, Figure 2 The four structures shown.

[0104] Figure 2 Example (a) in the text provides a transistor Tr and a ferroelectric capacitor C. Figure 2 In (a), the ferroelectric capacitor C is electrically connected to the gate of the transistor Tr. During the operation of the ferroelectric memory, the gate voltage of the transistor Tr can be adjusted by controlling the flipping of the ferroelectric domains in the ferroelectric capacitor C, and the storage state of the ferroelectric memory can be determined by detecting the current of the transistor Tr. Therefore, Figure 2 The structure shown in (a) can also be called a 1T1C current sensing structure.

[0105] Figure 2 Example (b) exemplifies a transistor Tr and n ferroelectric capacitors C connected in parallel, where n ≥ 2 and n is an integer. Figure 2In (b), each ferroelectric capacitor C is electrically connected to the gate of transistor Tr. During the operation of the ferroelectric memory, one ferroelectric capacitor C can be selected from the multiple parallel ferroelectric capacitors C. Then, the gate voltage of transistor Tr is controlled by the flipping of the ferroelectric domains in the selected ferroelectric capacitor C. The storage state of the selected ferroelectric capacitor C is determined by detecting the current of transistor Tr, that is, the storage state of the ferroelectric memory is determined. Therefore, Figure 2 The structure shown in (b) can also be called the 1TnC current sensing structure.

[0106] Figure 2 Example (c) in the example provides a transistor Tr and a ferroelectric capacitor C. Figure 2 In (c), the ferroelectric capacitor C is electrically connected to the source or drain of the transistor Tr. During the operation of the ferroelectric memory, the storage state of the ferroelectric capacitor C can be determined by detecting the direction of the current in the transistor Tr, that is, the storage state of the ferroelectric memory itself. Therefore, Figure 2 The structure shown in (c) can also be called a 1T1C charge sensing structure, which can be understood, for example, as replacing the capacitor in a traditional 1T1C DRAM with a ferroelectric capacitor.

[0107] Figure 2 Example (d) in the example gives a transistor Tr and n ferroelectric capacitors C connected in parallel. Figure 2 In (d), each ferroelectric capacitor C is electrically connected to the source of transistor Tr, or all are electrically connected to the drain of transistor Tr. During the operation of the ferroelectric memory, one ferroelectric capacitor C can be selected from the multiple parallel ferroelectric capacitors C. Then, the storage state of the selected ferroelectric capacitor C can be determined by detecting the current direction of transistor Tr, that is, the storage state of the ferroelectric memory. Therefore, Figure 2 The structure shown in (c) can also be called the 1TnC charge sensing structure.

[0108] Since each ferroelectric capacitor C can be used to store 1 bit of data, each of the above 1TnC structure array units can store n bits of data, which is beneficial for realizing high-density storage based on ferroelectric memory.

[0109] The ferroelectric memories described above typically exhibit a 2D architecture, or planar architecture, with the transistor Tr being a horizontally channeled transistor. Limited by the fabrication process of ferroelectric memories, it is difficult to further increase their storage density. For example, due to limitations in the precision of photolithography, the area of ​​the transistor Tr and ferroelectric capacitor C in a ferroelectric memory cannot be significantly reduced. This makes it difficult to place more transistors Tr and ferroelectric capacitors C per unit area, thus hindering the improvement of the storage density of ferroelectric memories.

[0110] Based on this, embodiments of this application provide a storage array with a 3D architecture. For example... Figure 3 and Figure 4 As shown, the storage array 100 includes a substrate 1 and a plurality of storage cell subarrays 2 located on the substrate 1. The storage cell subarrays 2 are used to store data.

[0111] The arrangement of the aforementioned multiple memory cell subarrays 2 includes various methods, which can be selected and set according to actual needs. Among them, the memory array 100 has a first direction Z, a second direction X, and a third direction Y. The first direction Z is perpendicular to the substrate 1, the second direction X is parallel to the substrate 1, and the third direction Y is parallel to the substrate 1, and the second direction X and the third direction Y are perpendicular to each other.

[0112] In some examples, such as Figure 3 As shown, at least two storage cell subarrays 2 are arranged sequentially along the second direction X, and at least two storage cell subarrays 2 are arranged sequentially along the third direction Y. That is, the multiple storage cell subarrays 2 in the storage array 100 are arranged in an array, with multiple rows and columns. Or, the multiple storage cell subarrays 2 in the storage array 100 include multiple columns of storage cell subarrays 2 arranged along the second direction X, and each column of storage cell subarrays 2 includes multiple storage cell subarrays 2 arranged along the third direction Y.

[0113] For example, Figure 3 The diagram illustrates twelve storage cell subarrays 2, which are arranged in three columns along the second direction X. Each column of storage cell subarrays 2 includes four storage cell subarrays 2 arranged along the third direction Y.

[0114] This allows for increasing the size and storage density of the storage array 100 while avoiding increasing its thickness.

[0115] In other examples, such as Figure 4As shown, at least two storage cell subarrays 2 are arranged sequentially along the second direction X, at least two storage cell subarrays 2 are arranged sequentially along the third direction Y, and at least two storage cell subarrays 2 are arranged sequentially along the first direction Z. That is, the multiple storage cell subarrays 2 in the storage array 100 are not only arranged in an array in the plane, but also arranged in a layered manner in the first direction Z. Alternatively, the multiple storage cell subarrays 2 in the storage array 100 are arranged along the first direction Z to form a multi-layer storage cell subarray 2, and the multiple storage cell subarrays 2 in each layer of storage cell subarray 2 include multiple columns of storage cell subarrays 2 arranged along the second direction X, and each column of storage cell subarray 2 includes multiple storage cell subarrays 2 arranged along the third direction Y.

[0116] For example, Figure 4 The diagram illustrates twenty-four storage cell subarrays 2, which are arranged in two layers along the first direction Z, with each layer containing twelve storage cell subarrays 2. For each layer of storage cell subarrays 2, these twelve storage cell subarrays 2 are arranged in three columns along the second direction X, with each column containing four storage cell subarrays 2 arranged along the third direction Y.

[0117] For example, the storage array 100 further includes an encapsulation layer 7 located between two adjacent storage cell subarrays 2 along the first direction Z. The encapsulation layer 7 can separate two adjacent storage cell subarrays 2 along the first direction Z, thereby improving the structural stability of the upper storage cell subarray 2. Figure 4 Only a partial structure of the encapsulation layer 7 is shown; the overall structure of the encapsulation layer 7 is not limited.

[0118] This allows for increased storage array size and storage density while improving space utilization and reducing the area of ​​storage array 100.

[0119] Figure 5a The diagram illustrates the structure of a memory cell subarray 2. Each memory cell subarray 2 includes a stacked structure 21, a first channel layer 22, a first gate dielectric layer 23, and a first gate 24. The number of first channel layers 22, first gate dielectric layers 23, and first gates 24 are all multiple.

[0120] For example, the material of the first channel layer 22 includes, but is not limited to, semiconductor materials and metal oxide materials. For instance, the material of the first channel layer 22 includes, but is not limited to, silicon-based semiconductor materials such as Si, poly-Si (p-Si, polycrystalline silicon), and amorphous-Si (a-Si, amorphous silicon), or metal oxide materials such as In2O3 (indium oxide), ZnO (zinc oxide), Ga2O3 (gallium oxide), ITO (indium tin oxide), and TiO2 (titanium dioxide), multi-component compound materials such as In-Ga-Zn-O (IGZO, indium gallium zinc oxide) and In-Sn-Zn-O (ISZO, indium tin zinc oxide), or two-dimensional semiconductor materials such as graphene, MoS2 (molybdenum disulfide), and black phosphorus, or any combination thereof. The material of the first gate dielectric layer 23 includes, but is not limited to, insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium oxide), and Si3N4 (silicon nitride), or any combination thereof. The structure of the first gate dielectric layer 23 is a single-layer structure, a multilayer structure, or a multilayer structure composed of combined materials. The material of the first gate 24 includes metallic materials or other conductive materials. For example, the material of the first gate 24 includes conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver), or any combination thereof.

[0121] In some examples, such as Figure 5a and Figure 5b As shown, the above-mentioned stacked structure 21 includes multiple conductive layers 211 stacked along the first direction Z.

[0122] The material of the conductive layer 211 includes metallic materials or other conductive materials. For example, the material of the conductive layer 211 includes conductive materials such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), Al, Cu, Ru, Ag, or any combination thereof.

[0123] In the aforementioned stacked structure 21, the thickness of each conductive layer 211 can be the same or different, and can be set according to actual needs. Furthermore, in the manufacturing process of the stacked structure 21, different numbers of stacked layers correspond to different stacking heights. For example, the number of film layers stacked in the stacked structure 21 can be dozens or even hundreds (e.g., 32, 64, or 128 layers). The more film layers included in the stacked structure 21, the higher the integration level and the larger the storage capacity of the storage array 100. The specific number of stacked layers and stacking height of the stacked structure 21 can be designed according to actual storage requirements or fabrication process conditions; this application does not impose any limitations on this.

[0124] For example, each conductive layer 211 includes a plurality of conductive blocks 211a spaced apart along the second direction X. The plurality of conductive blocks 211a are arranged sequentially along the second direction X in a row. For example, in each conductive layer 211, there is a certain distance between two adjacent conductive blocks 211a, and they are insulated from each other.

[0125] In some examples, such as Figures 5b-5d As shown, the above-mentioned stacked structure 21 also includes multiple storage function layers 212. Each storage function layer 212 is, for example, block-shaped. A storage function layer 212 is disposed between two adjacent conductive blocks 211a, and the two adjacent conductive blocks 211a and the storage function layer 212 located between the two adjacent conductive blocks 211a form a storage cell MC.

[0126] By forming an electric field between two conductive blocks 211a in each storage cell MC, the state of the storage function layer 212 located between the two conductive blocks 211a can be changed, and data storage can be achieved by utilizing the change in the state of the storage function layer 212.

[0127] For example, one memory cell MC is used to store one bit of data. The multiple conductive layers 211 and multiple storage functional layers 212 in each stacked structure 21 can constitute multiple memory cells MC, thus each stacked structure 21 can store multiple bits of data. The multiple memory cells MC in each stacked structure 21 are arranged sequentially in the second direction X and stacked in the first direction Z to form a 3D architecture. Compared to a planar architecture (or 2D architecture), this is advantageous in increasing the number of memory cells MC per unit area, thereby increasing the storage density of the storage array 100.

[0128] For example, the stacked structure 21 has two opposing sidewalls A, namely a first sidewall A1 and a second sidewall A2. The sidewalls A of the stacked structure 21 are, for example, perpendicular to the plane containing the substrate 1. Alternatively, considering the influence of the fabrication process, there may be a certain angle between the sidewalls A of the stacked structure 21 and the plane containing the substrate 1. In this case, the sidewalls A of the stacked structure 21 can be considered approximately perpendicular to the plane containing the substrate 1. That is, the third direction Y is perpendicular or approximately perpendicular to the sidewalls A.

[0129] For example, the conductive block 211a and the storage layer 212 have the same or approximately the same dimensions in the third direction Y. The sides of the conductive block 211a and the storage layer 212 that are perpendicular or approximately perpendicular to the third direction Y form part of the sidewall A of the stacked structure 21.

[0130] In some examples, at least a portion of the first channel layer 22 is located on the sidewall A of the stacked structure 21, the first gate dielectric layer 23 covers the first channel layer 22, and the first gate 24 is located on the side of the first gate dielectric layer 23 away from the first channel layer 22. That is, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 are stacked sequentially in a third direction Y away from the sidewall A. The first gate dielectric layer 23 separates the first gate 24 from the first channel layer 22 to form electrical isolation, preventing contact between the first gate 24 and the first channel layer 22. At the same time, it separates the first gate 24 from the conductive block 211a in the stacked structure 21 to prevent short circuit between the first gate 24 and the conductive block 211a.

[0131] Wherein, "at least a portion of the first channel layer 22 is located on the sidewall A of the laminated structure 21" includes, but is not limited to: a portion of the first channel layer 22 is located on one sidewall A (e.g., the first sidewall A1) of the laminated structure 21, and another portion is located on another sidewall A (e.g., the second sidewall A2) of the laminated structure 21; or, the entire first channel layer 22 is located on one sidewall A (e.g., the first sidewall A1) of the laminated structure 21. The first channel layer 22 is, for example, in a vertical structure.

[0132] In some examples, the first channel layer 22 described above is configured corresponding to a memory cell MC. For example, one first channel layer 22 is configured for each memory cell MC. Figure 5c As shown, the first channel layer 22 is in contact with two adjacent conductive blocks 211a and the storage function layer 212 in its corresponding memory cell MC. An ohmic contact (or electrical contact) is formed between the first channel layer 22 and the two adjacent conductive blocks 211a. The two adjacent conductive blocks 211a, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 form the first transistor T1.

[0133] In each memory cell MC, two adjacent conductive blocks 211a can serve as either two electrodes or as the source and drain of their corresponding first transistor T1, allowing the memory cell MC and the corresponding first transistor T1 to be connected in parallel. During data storage in the memory cell MC, for example, the first transistor T1 corresponding to that memory cell MC can be turned off, and then voltages can be applied to the two conductive blocks 211a in the memory cell MC to prevent them from forming a conductive path through the first channel layer 22. This allows an electric field to be formed between the two conductive blocks 211a, changing the state of the storage function layer 212 and achieving data storage.

[0134] The memory cell MC and its corresponding first transistor T1 share the two adjacent conductive blocks 211a, which helps to simplify the structure of the stacked structure 21, reduce the positive projection area of ​​the stacked structure 21 on the substrate 1, and thus facilitate the setting of more stacked structures 21 or memory cell subarrays 2 on the substrate 1, thereby increasing the storage density of the memory array 100.

[0135] Based on the positional relationship between the first gate 24 and the first channel layer 22 in the first transistor T1, the structure of the first transistor T1 forms a transistor structure with a vertical channel. Therefore, the first transistor T1 can be called a vertical channel field-effect transistor (FET). Compared with a horizontal channel transistor, the first transistor T1 has a smaller projected area on the substrate 1, which is beneficial for setting more first transistors T1 and stacked structures 21 on the substrate 1, and is conducive to further improving the storage density of the storage array 100.

[0136] Therefore, in some embodiments of this application, the storage array 100 has a storage function layer 212 disposed between two adjacent conductive blocks 211a to form a storage cell MC for storing data. The two adjacent conductive blocks 211a, the first channel layer 22, the first gate dielectric layer 23 and the first gate 24 in the storage cell MC form a first transistor T1, so as to use the first transistor T1 to change the state of the storage function layer 212 in the corresponding storage cell MC to realize data storage.

[0137] This embodiment of the application stacks a conductive layer including multiple conductive blocks 211a and a storage functional layer 212 to form a stacked structure 21, and places the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of the first transistor T1 on the sidewall A of the stacked structure 21, so that the memory array 100 has an overall 3D architecture. This is beneficial for increasing the number of memory cells MC per unit area, thereby increasing the storage density of the memory array 100.

[0138] Furthermore, the first transistor T1 in this application is a vertical channel field-effect transistor. The projected area of ​​the vertical channel field-effect transistor on the substrate 1 is relatively small, which is beneficial to setting more first transistors T1 on the substrate 1 and further improving the storage density of the storage array 100.

[0139] The aforementioned storage array 100 can be applied to back end of line (BEOL) processes, which helps to increase the storage area and achieve a large-capacity non-volatile storage array through stacking.

[0140] In some embodiments, such as Figure 6As shown, the aforementioned storage cell subarray 2 includes multiple rows of storage cells MC, and each row of storage cells MC includes multiple storage cells MC arranged along the second direction X. Adjacent storage cells MC in the same row are electrically connected. Figure 7 The equivalent circuit diagram shown illustrates a row of memory cells MC and the first transistor T1 corresponding to that row of memory cells MC.

[0141] For example, such as Figure 5c and Figure 6 As shown, the electrical connection between two adjacent memory cells MC is as follows: a conductive block 211a in one memory cell MC is electrically connected to a conductive block 211a in another memory cell MC. Since the two conductive blocks 211a in the memory cell MC can serve as the source and drain of the first transistor T1 corresponding to that memory cell MC, the electrical connection between two adjacent memory cells MC in the same row can also be understood as the electrical connection between the two first transistors T1 corresponding to those two adjacent memory cells MC, that is, the source of one first transistor T1 and the drain of the other first transistor T1 are electrically connected.

[0142] Thus, each row of storage cell MC and the first transistor T1 corresponding to that row of storage cell MC are arranged in an island chain cell structure, and the storage array 100 is arranged in an island chain structure.

[0143] In some examples, the first gate 24 of each first transistor T1 is electrically connected to a word line WL, one of the source and drain of the first transistor T1 is electrically connected to a plate line PL (e.g., a direct or indirect connection), and the other of the source and drain of the first transistor T1 is electrically connected to a bit line BL (e.g., a direct or indirect connection). Figure 7 The equivalent circuit diagram shown illustrates n+1 first transistors T1. From right to left, the first gates 24 of these n+1 first transistors T1 are sequentially electrically connected to word lines WL0, WL1, ..., WLn. The leftmost first transistor T1 is directly electrically connected to the board line PL, while the remaining first transistors T1 are indirectly electrically connected to the board line PL (i.e., connected via the left-hand first transistor T1). Each first transistor T1 is indirectly connected to the bit line BL, with the rightmost first transistor T1 connected to the bit line BL via a second transistor T2. The structure of the second transistor T2 can be found in the description below and will not be repeated here.

[0144] The working principle of the above chain cell structure is as follows: In the "standby" state, each word line WL transmits a high-potential electrical signal to the first transistor T1 to control the first transistor T1 to turn on. The selection signal line BS transmits a high-potential electrical signal to the second transistor T2 to control the second transistor T2 to turn on. Then, both the board line PL and the bit line BL transmit a low-potential electrical signal Vss, so that the storage functional layer 212 in each memory cell MC is in the same state (for example, if the storage functional layer 212 is a ferroelectric material layer, it can make each ferroelectric capacitor in the same polarization state). During the "write" process, the word line WL electrically connected to the first transistor T1 corresponding to the selected memory cell MC transmits a low-potential electrical signal to control the first transistor T1 to turn off. The remaining first transistors T1 and second transistors T2 are in the on state. The board line PL transmits a high-potential electrical signal Vdd, and the bit line BL still transmits a low-potential electrical signal Vss, so that the storage functional layer 212 in the selected memory cell MC changes (for example, if the storage functional layer 212 is a ferroelectric material layer, it can make each ferroelectric capacitor in the same polarization state). In the case of a ferroelectric material layer, the polarization direction of the selected ferroelectric capacitor is reversed, while the unselected memory cell MC maintains its original state (for example, when the storage function layer 212 is a ferroelectric material layer, the unselected ferroelectric capacitor maintains its original polarization state), thus realizing data writing; during the "read" process, the word line WL electrically connected to the first transistor T1 corresponding to the selected memory cell MC transmits a low-potential electrical signal to control the first transistor T1 to turn off, while the remaining first transistors T1 and second transistors T2 are on. In the power-on state, the board line PL transmits a negative high-level electrical signal (-Vdd), while the bit line BL still transmits a low-level electrical signal Vss. This causes a change in the storage function layer 212 in the selected memory cell MC (for example, if the storage function layer 212 is a ferroelectric material layer, this causes the polarization direction of the selected ferroelectric capacitor to reverse). Meanwhile, the unselected memory cells MC maintain their original state (for example, if the storage function layer 212 is a ferroelectric material layer, the unselected ferroelectric capacitor maintains its original polarization state), thus enabling data reading.

[0145] In some embodiments of this application, the positional relationship between two adjacent conductive blocks 211a and the storage functional layer 212 in the same storage cell MC includes various types, which can be selected and set according to actual needs, and this application does not limit this.

[0146] In some possible embodiments, such as Figures 5a-5c and Figures 8a to 10dAs shown, two adjacent conductive blocks 211a in the same storage cell MC are located on the same conductive layer 211. That is, two conductive blocks 211a in the same storage cell MC are arranged on the same layer; conductive blocks 211a in different storage cells MC in the same row of storage cells MC are also arranged on the same layer.

[0147] For example, along the second direction X, the storage function layer 212 in the same storage cell MC is located between the two adjacent conductive blocks 211a, and the storage function layer 212 is also located on the same layer as the two adjacent conductive blocks 211a. Along the second direction X, the two adjacent conductive blocks 211a are located on opposite sides of the storage function layer 212, and both are in contact with the storage function layer 212.

[0148] Here, the "same-layer configuration" mentioned in this application refers to a layer structure formed by using the same film deposition process to form a film layer with a specific pattern, and then forming a layer structure using the same mask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In this way, two conductive blocks 211a in each memory cell MC can be fabricated simultaneously in a single patterning process, which helps to simplify the fabrication process of the memory cell subarray 2 and the memory array 100.

[0149] Furthermore, the contact area between the storage functional layer 212 and the conductive blocks 211a located on opposite sides of it within the same storage cell MC is not limited in this embodiment. That is, the contact area between the storage functional layer 212 and the conductive blocks 211a located on opposite sides of it within the same storage cell MC can be large or small; a certain contact area is sufficient for the storage cell MC to possess the required functions. This helps reduce the alignment accuracy between the conductive blocks 211a and the storage functional layer 212 within the same storage cell MC, and reduces the fabrication difficulty of the storage cell subarray 2 and the storage array 100.

[0150] In some examples, such as Figure 8c , Figure 9c and Figure 10c As shown, in the same conductive layer 211, conductive blocks 211a and storage function layers 212 are alternately arranged along the second direction X. Among the multiple conductive blocks 211a located in the same conductive layer 211, a storage function layer 212 is disposed between any two adjacent conductive blocks 211a. Two adjacent memory cells MC located in the same layer can share a conductive block 211a and be electrically connected to each other through the shared conductive block 211a. Alternatively, it can be understood that the two first transistors T1 corresponding to two adjacent memory cells MC located in the same layer share a source or drain.

[0151] by Figure 9c Taking the structure shown as an example, the conductive layer 211 includes a first conductive block 211a-1, a second conductive block 211a-2, and a third conductive block 211a-3 arranged sequentially along the second direction X. A first storage function layer 212-1 is disposed between the first conductive block 211a-1 and the second conductive block 211a-2, and a second storage function layer 212-2 is disposed between the second conductive block 211a-2 and the third conductive block 211a-3. That is, along the second direction X, the first conductive block 211a-1, the first storage function layer 212-1, the second conductive block 211a-2, the second storage function layer 212-2, and the third conductive block 211a-3 are arranged sequentially. The first conductive block 211a-1, the first storage functional layer 212-1, and the second conductive block 211a-2 form the first storage unit MC-1. The second conductive block 211a-2, the second storage functional layer 212-2, and the third conductive block 211a-3 form the second storage unit MC-2. The first storage unit MC-1 and the second storage unit MC-2 share the second conductive block 211a-2 and are electrically connected through the second conductive block 211a-2.

[0152] This helps to simplify the structure of multiple memory cells MC located on the same layer (or in the same row), improve the integration of multiple memory cells MC located on the same layer, and facilitate the setting of more memory cells MC in the same conductive layer 211, thereby further improving the integration density, storage capacity and storage density of the storage array 100.

[0153] In some examples, such as Figure 8b , Figure 9b and Figure 10b As shown, the stacked structure 21 also includes multiple layers of first insulating layers 213. Along the first direction Z, multiple conductive layers 211 and multiple layers of first insulating layers 213 are alternately arranged. A first insulating layer 213 is disposed between any two adjacent conductive layers 211, and a conductive layer 211 is disposed between any two adjacent first insulating layers 213.

[0154] For example, the material of the first insulating layer 213 includes, but is not limited to, insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, and the structure of the first insulating layer 213 is a single-layer structure, a multilayer structure, or a multilayer structure composed of combined materials.

[0155] By setting the first insulating layer 213, the two adjacent conductive layers 211 can be separated, forming an insulating isolation (or electrical isolation) between the two adjacent conductive layers 211, so as to avoid short circuits between the two adjacent conductive layers 211 and ensure that the storage array 100 has good electrical performance.

[0156] In other possible embodiments, such as Figures 11a to 12d As shown, two adjacent conductive blocks 211a in the same storage cell MC are located in two adjacent conductive layers 211. Along the first direction Z, the storage function layer 212 in the storage cell MC is located between the two adjacent conductive blocks 211a. That is, two adjacent conductive blocks 211a in the same storage cell MC are located in different conductive layers 211, and the storage function layer 212 is also located in a different layer from the two adjacent conductive blocks 211a. Along the first direction Z, in the same storage cell MC, one conductive block 211a, the storage function layer 212, and another conductive block 211a are arranged in sequence, with the lower surface of the storage function layer 212 in contact with one conductive block 211a and the upper surface of the storage function layer 212 in contact with the other conductive block 211a.

[0157] For example, the orthographic projections of two adjacent conductive blocks 211a in the same storage cell MC onto the substrate 1 overlap. These two adjacent conductive blocks 211a are staggered. In the first direction Z, the two adjacent conductive blocks 211a partially overlap. Since the storage functional layer 212 is located between these two adjacent conductive blocks 211a, the storage functional layer 212 and the two adjacent conductive blocks 211a partially overlap in the first direction Z, and the overlapping portion serves to store data.

[0158] The above arrangement helps to increase the contact area between the storage function layer 212 and the adjacent conductive block 211a, thereby improving the performance of the storage cell MC.

[0159] In some examples, such as Figure 11b As shown, in the same storage cell MC, among two adjacent conductive blocks 211a, the conductive block 211a located in one of the two adjacent conductive layers 211 is the first conductive block 211a-1, and the conductive block 211a located in the other conductive layer 211 is the second conductive block 211a-2.

[0160] In the orthographic projection of the two adjacent conductive layers 211 onto the substrate 1, along the second direction X, a plurality of first conductive blocks 211a-1 and a plurality of second conductive blocks 211a-2 are alternately arranged. That is, a second conductive block 211a-2 is arranged between any two adjacent first conductive blocks 211a-1, and a first conductive block 211a-1 is arranged between any two adjacent second conductive blocks 211a-2.

[0161] Along the first direction Z, a first conductive block 211a-1 and two second conductive blocks 211a-2 overlap, and a first conductive block 211a-1 overlaps with two storage functional layers 212. At this time, the first conductive block 211a-1, the two second conductive blocks 211a-2 overlapping with it, and the two storage functional layers 212 overlapping with it form two memory cells MC arranged sequentially along the second direction X. These two memory cells MC share the first conductive block 211a-1 and are electrically connected to each other through it. Alternatively, it can be understood that the two first transistors T1 corresponding to the two memory cells MC share a single source or drain.

[0162] Alternatively, along the first direction Z, one second conductive block 211a-2 and two first conductive blocks 211a-1 overlap, and one second conductive block 211a-2 overlaps with two storage functional layers 212. In this case, the second conductive block 211a-2, the two first conductive blocks 211a-1 overlapping with it, and the two storage functional layers 212 overlapping with it form two memory cells MC arranged sequentially along the second direction X. These two memory cells MC share the second conductive block 211a-2 and are electrically connected to each other through it. Alternatively, it can be understood that the two first transistors T1 corresponding to the two memory cells MC share a single source or drain.

[0163] Thus, two adjacent conductive layers 211 and multiple storage functional layers 212 located between them constitute a row of storage cells MC. The multiple storage cells MC in this row are arranged sequentially along the second direction X. In this row of storage cells MC, adjacent storage cells MC share a first conductive block 211a-1 or a second conductive block 211a-2, and are electrically connected to each other through the shared conductive block. By sharing the first conductive block 211a-1 or the second conductive block 211a-2, the projected area of ​​the first conductive block 211a-1 or the shared second conductive block 211a-2 on the substrate 1 can be increased, which helps reduce the fabrication difficulty of the conductive layer 211, and consequently reduces the fabrication difficulty of the storage array 100.

[0164] Moreover, the two first transistors T1 corresponding to the two memory cells MC share a source or drain, which increases the overlap area between the first gate 24 and the source, and the overlap area between the first gate 24 and the drain, which is beneficial to achieving ohmic contact between the source or drain and the first channel layer 22.

[0165] In some examples, such as Figure 11b , Figure 11c , Figure 12b and Figure 12c As shown, the stacked structure 21 also includes a plurality of first insulating blocks 214. In the same conductive layer 211, along the second direction X, a plurality of conductive blocks 211a and a plurality of first insulating blocks 214 are alternately arranged.

[0166] Each conductive layer 211 is provided with a plurality of first insulating blocks 214. The plurality of first insulating blocks 214 and the plurality of conductive blocks 211a in the conductive layer 211 are arranged sequentially along the second direction X. A conductive block 211a is provided between any two adjacent first insulating blocks 214, and a first insulating block 214 is provided between any two adjacent conductive blocks 211a.

[0167] For example, the material of the first insulating block 214 includes, but is not limited to, insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, and the structure of the first insulating block 214 is a single-layer structure, a multilayer structure, or a multilayer structure composed of combined materials.

[0168] By setting the first insulating block 214, two adjacent conductive blocks 211a in the same conductive layer 211 can be separated, forming an insulating isolation (or electrical isolation) between the two adjacent conductive blocks 211a, so as to avoid short circuit between the two adjacent conductive blocks 211a and ensure that the storage array 100 has good electrical performance.

[0169] In some examples, such as Figure 11b and Figure 12b As shown, the stacked structure 21 also includes multiple layers of second insulating layers 215, which are located between two adjacent rows of memory cells MC. Along the first direction Z, multiple rows of memory cells MC and multiple layers of second insulating layers 215 are alternately arranged. A second insulating layer 215 is disposed between any two adjacent rows of memory cells MC, and a row of memory cells MC is disposed between any two adjacent layers of second insulating layers 215.

[0170] Since two adjacent conductive layers 211 and a plurality of storage functional layers 212 located between the two adjacent conductive layers 211 constitute a row of storage cells MC, a second insulating layer 215 is provided between every two conductive layers 211.

[0171] For example, the material of the second insulating layer 215 includes, but is not limited to, insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, and the structure of the second insulating layer 215 is a single-layer structure, a multilayer structure, or a multilayer structure composed of combined materials.

[0172] By setting the second insulating layer 215, adjacent rows of memory cells MC can be separated, forming an insulating isolation (or electrical isolation) between adjacent rows of memory cells MC, so as to avoid short circuits between adjacent rows of memory cells MC and ensure that the memory array 100 has good electrical performance.

[0173] Within the same row of storage units (MCs), there are multiple ways to configure the storage function layer (MC), which can be selected according to actual needs.

[0174] For example, such as Figure 11b and Figure 11c As shown, the stacked structure 21 also includes multiple second insulating blocks 216. In the same row of memory cells MC, the storage function layers 212 and multiple second insulating blocks 216 of multiple memory cells MC are alternately arranged. At this time, each storage function layer 212 is block-shaped.

[0175] For multiple storage function layers 212 and multiple second insulating blocks 216 located on the same conductive layer 211, the multiple storage function layers 212 and multiple second insulating blocks 216 are arranged sequentially along the second direction X. A storage function layer 212 is disposed between any two adjacent second insulating blocks 216, and a second insulating block 216 is disposed between any two adjacent storage function layers 212.

[0176] Optionally, the material of the second insulating block 216 includes, but is not limited to, insulating materials such as SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, Si3N4, or any combination thereof, and the structure of the second insulating block 216 is a single-layer structure, a multilayer structure, or a multilayer structure composed of combined materials.

[0177] By setting the second insulating block 216, two adjacent storage function layers 212 located on the same conductive layer 211 can be separated, making it easier to define the storage cell MC more clearly.

[0178] For example, such as Figures 12a-12c As shown, in the same row of storage cells MC, the storage function layers 212 of multiple storage cells MC are connected and form a single structure. That is, the storage function layers 212 of multiple storage cells MC in the same row of storage cells MC are arranged on the same layer, and the storage function layers 212 of two adjacent storage cells MC are continuous and unbroken. At this time, each storage function layer 212 is strip-shaped and extends along the second direction X.

[0179] This avoids etching the storage function layer 212 of multiple storage cells MC in the same row of storage cells MC, effectively reducing the number of photomask operations, simplifying the fabrication process of the storage function layer 212, and further simplifying the fabrication process of the storage cell subarray 2 and the storage array 100, thus reducing costs.

[0180] In some embodiments, such as Figure 8b , Figure 9b , Figure 10b , Figure 11b and Figure 12b As shown, the aforementioned memory cell subarray 2 includes multiple columns of memory cells MC, each column of memory cells MC including multiple memory cells MC stacked along the first direction Z. Adjacent memory cells MC in the same column are electrically insulated (or electrically isolated). Within the same column of memory cells MC, the orthographic projections of the storage functional layers 212 of any two memory cells MC onto the substrate 1 at least partially overlap.

[0181] For example, the orthographic projections of the storage function layers 212 of the two storage cells MC on the substrate 1 overlap and are somewhat misaligned; or, the orthographic projections of the storage function layers 212 of the two storage cells MC on the substrate 1 coincide; or, in the storage function layers 212 of the two storage cells MC, the orthographic projection of one on the substrate 1 is located within the orthographic projection range of the other on the substrate 1.

[0182] By adopting the above configuration, the memory cells MC in each memory cell subarray 2 are arranged in multiple rows and columns, which helps to improve the regularity of the arrangement of memory cells MC in each memory cell subarray 2, and further helps to improve the regularity of the arrangement of the first transistor T1 corresponding to each memory cell MC, and reduces the wiring difficulty and fabrication difficulty of memory cell subarray 2 and memory array 100.

[0183] In some embodiments of this application, the first transistor T1 corresponding to each memory cell MC is configured in various ways, and can be selected according to actual needs. This application does not limit this configuration.

[0184] In some possible embodiments, at least one first channel layer 22 of the first transistor T1 is located on one sidewall A or both sidewalls A2 of the stacked structure 21.

[0185] In some examples, such as Figure 5c As shown, the first channel layer 22 of the first transistor T1 is located on a sidewall A (e.g., the first sidewall A1) of the stacked structure 21. The first gate dielectric layer 23 and the first gate 24 of the first transistor T1 are also located on the sidewall A, and the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 are arranged sequentially along a direction away from the sidewall A. The first channel layer 22 is in contact with one side of the conductive block 211a in the corresponding memory cell MC and one side of the memory functional layer 212.

[0186] This helps to improve the regularity of the arrangement of each first transistor T1 and reduces the wiring and fabrication difficulty of the memory cell subarray 2 and the memory array 100.

[0187] Here, the location of the first transistor T1 in each memory cell subarray 2 can be varied.

[0188] For example, in the same memory cell subarray 2, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of each first transistor T1 are located on the same sidewall A (e.g., the first sidewall A1) of the stacked structure 21.

[0189] For example, in different memory cell subarrays 2, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of each first transistor T1 are all located on the first sidewall A1 (or the second sidewall A2) of the corresponding stacked structure 21. Alternatively, in different memory cell subarrays 2, in a portion of the memory cell subarrays 2, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of each first transistor T1 are all located on the first sidewall A1 (or the second sidewall A2) of the corresponding stacked structure 21, while in another portion of the memory cell subarrays 2, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of each first transistor T1 are all located on the second sidewall A2 (or the first sidewall A1) of the corresponding stacked structure 21.

[0190] Optionally, such as Figure 8a , Figure 8c and Figure 8d As shown, multiple stacked structures 21 are arranged sequentially along a third direction Y. These multiple stacked structures 21 include at least one stacked structure pair, and each stacked structure pair includes two adjacent stacked structures 21. The two adjacent stacked structures 21 included in the stacked structure pair are a first stacked structure 21-1 and a second stacked structure 21-2, respectively. The first sidewall A1 of the first stacked structure 21-1 is located on the side away from the second stacked structure 21-2, and the second sidewall A2 of the second stacked structure 21-2 is located on the side away from the first stacked structure 21-1. Accordingly, the second sidewall A2 of the first stacked structure 21-1 and the first sidewall A1 of the second stacked structure 21-2 are arranged opposite to each other.

[0191] The first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of the first transistor T1 corresponding to the memory cell MC in the first stacked structure 21-1 are located on the first sidewall A1 of the first stacked structure 21-1, and the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of the first transistor T1 corresponding to the memory cell MC in the second stacked structure 21-2 are located on the second sidewall A2 of the second stacked structure 21-2.

[0192] For example, the first stacked structure 21-1 and the second stacked structure 21-2 are symmetrically arranged. The first channel layer 22, the first gate dielectric layer 23 and the first gate 24 of each first transistor T1 located on the first sidewall A1 of the first stacked structure 21-1 are symmetrically arranged with the first channel layer 22, the first gate dielectric layer 23 and the first gate 24 of each first transistor T1 located on the second sidewall A2 of the second stacked structure 21-2.

[0193] In other examples, such as Figure 9a , Figure 9c and Figure 9d As shown, in the first transistor T1, a portion of the first channel layer 22, a portion of the first gate dielectric layer 23, and a portion of the first gate 24 are located on the first sidewall A1 of the stacked structure 21, while another portion of the first channel layer 22, another portion of the first gate dielectric layer 23, and another portion of the first gate 24 are located on the second sidewall A2 of the stacked structure 21. That is, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of each first transistor T1 are each divided into two parts, located on the first sidewall A1 and the second sidewall A2 of the stacked structure 21, respectively.

[0194] The first channel layer 22 of each first transistor T1 is in contact with two opposite sides of the memory cell MC (including the two sides of the conductive block 211a and the two sides of the memory function layer 212). This is equivalent to each first transistor T1 having two conductive channels, which increases the effective channel width and can effectively increase the read speed of the memory array 100.

[0195] In some other examples, such as Figure 8b and Figure 9b As shown, along the first direction Z and the second direction X, the first channel layers 22 of two adjacent first transistors T1 are separated from each other. That is, the first channel layers 22 of different first transistors T1 are independent and unconnected. This avoids short circuits between different first transistors T1 through the first channel layers 22, ensuring good electrical performance of each first transistor T1.

[0196] The first gate dielectric layers 23 of a plurality of first transistors T1 corresponding to the same column of memory cells MC are connected and located on the sidewall A of the stacked structure 21. The first gates 24 of a plurality of first transistors T1 corresponding to the same column of memory cells MC are connected and located on the sidewall A of the stacked structure 21. For example, along the first direction Z, the first gate dielectric layers 23 of two adjacent first transistors T1 are interconnected and form a single structure, and the interconnected portion is in contact with the sidewall A of the stacked structure 21. The first gates 24 of two adjacent first transistors T1 are interconnected and form a single structure, and the interconnected portion is located on the surface of the first gate dielectric layer 23 away from the stacked structure 21.

[0197] By connecting the first gate dielectric layers 23 of multiple first transistors T1 corresponding to the same column of memory cells MC, the first gate dielectric layers 23 of the multiple first transistors T1 can be integrated into a single structure and form a vertical structure. Similarly, by connecting the first gates 24 of the multiple first transistors T1 corresponding to the same column of memory cells MC, the first gates 24 of the multiple first transistors T1 can be integrated into a single structure and form a vertical structure. This avoids etching the first gate dielectric layers 23 or the first gates 24 of the multiple first transistors T1 corresponding to the same column of memory cells MC, which helps to reduce the difficulty of fabricating the first transistors T1 and the memory array 100. Moreover, after connecting the first gates 24 of the multiple first transistors T1 corresponding to the same column of memory cells MC, the first gates 24 of the multiple first transistors T1 can be electrically connected to the same word line WL, which helps to reduce the number of word lines WL and simplify the structure of the memory array 100.

[0198] In some of the examples above, such as Figure 8a and Figure 9a As shown, in the first transistor T1, which is furthest from the substrate 1 along the first direction Z, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 also cover the top wall B of the stacked structure 21. The first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of the first transistor T1 are all folded.

[0199] In this way, during the fabrication of the first transistor T1, which is furthest from the substrate 1 along the first direction Z, the etching of the portion of the top wall B of the stacked structure 21 covered by the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 can be avoided, which helps to reduce the difficulty of fabricating the first transistor T1 and the memory array 100.

[0200] Here, as Figure 8d As shown, in the same memory cell subarray 2, when the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of each first transistor T1 are located on the same sidewall A (e.g., the first sidewall A1) of the stacked structure 21, if the first gate dielectric layer 23 of multiple first transistors T1 corresponding to the same column memory cell MC is connected, the first gate dielectric layer 23 of the multiple first transistors T1 will be in the shape of a "7" or an inverted "L"; if the first gate 24 of multiple first transistors T1 corresponding to the same column memory cell MC is connected, the first gate 24 of the multiple first transistors T1 will be in the shape of a "7" or an inverted "L".

[0201] like Figure 9dAs shown, in the same memory cell subarray 2, when the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of each first transistor T1 are located on the two sidewalls A of the stacked structure 21, if the first gate dielectric layer 23 of multiple first transistors T1 corresponding to the same column memory cell MC is connected, the first gate dielectric layer 23 of the multiple first transistors T1 is generally inverted "U" shape and is fastened to the stacked structure 21; if the first gate 24 of multiple first transistors T1 corresponding to the same column memory cell MC is connected, the first gate 24 of the multiple first transistors T1 is generally inverted "U" shape and is fastened to the stacked structure 21.

[0202] In other possible embodiments, such as Figure 10a As shown, the first channel layer 22 of each first transistor T1 surrounds the memory cell MC.

[0203] In some examples, such as Figure 10d As shown, in the first transistor T1 corresponding to each memory cell MC, the cross-sectional pattern of the first channel layer 22, the first gate dielectric layer 23 and the first gate 24 is annular along the first direction Z and along the third direction Y. The first channel layer 22 surrounds the memory cell MC, the first gate dielectric layer 23 surrounds the first channel layer 22, and the first gate 24 surrounds the first gate dielectric layer 23.

[0204] "Along the first direction Z and along the third direction Y" refers to the extension direction along a plane perpendicular to the second direction X. The cross-sectional shape of the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 is annular, and correspondingly, the three-dimensional shape of the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 is tubular. A portion of each conductive block 211a in the memory cell MC is located within the tubular first channel layer 22 and contacts the inner wall of the first channel layer 22, while another portion extends out of the tubular first channel layer 22 and is located outside the tubular first channel layer 22. The storage function layer in the memory cell MC is located within the tubular first channel layer 22 and contacts the inner wall of the first channel layer 22. The tubular first gate dielectric layer 23 is sleeved on the tubular first channel layer 22, and the two are in contact. The tubular first gate 24 is sleeved on the tubular first gate dielectric layer 23, and the two are in contact.

[0205] By adopting the above configuration, the structure of each first transistor T1 is a full-gate structure, which effectively increases the overlap area of ​​the first gate 24 and the first channel layer 22, thereby effectively improving the control capability of the first gate 24 on the first channel layer 22 and improving the performance of the first transistor T1 and the memory array 100.

[0206] Optionally, among the plurality of first transistors T1 corresponding to the same column of memory cells MC, the first gate dielectric layers 23 of two adjacent first transistors T1 are spaced apart, and the first gates 24 of two adjacent first transistors T1 are spaced apart.

[0207] Optionally, the first gates 24 of a plurality of first transistors T1 corresponding to the same column of memory cells MC are connected and located between the sidewall A of the stacked structure 21 and two adjacent first gate dielectric layers 23. For example, the gap between the first gate dielectric layers 23 of two adjacent first transistors T1 is filled with the material of the first gate 24, so that the first gates 24 are interconnected and form an integral structure. The overall structure of the first gates 24 of the plurality of first transistors T1 is a honeycomb structure with multiple holes (the multiple holes are arranged in a column along the first direction Z).

[0208] In this way, the first gate 24 of the multiple first transistors T1 can be electrically connected to the same word line WL, which helps to reduce the number of word lines WL and simplify the structure of the memory array 100.

[0209] In some embodiments of this application, such as Figure 6 As shown, the memory cell subarray 2 further includes a plurality of second transistors T2. These second transistors T2 are arranged in a column along the first direction Z. One second transistor T2 is located at the end of a row of memory cells MC. Along the second direction X, the first transistor T1 and the second transistor T2 corresponding to the row of memory cells MC are arranged sequentially. For example, the plurality of second transistors T2 correspond one-to-one with multiple rows of memory cells MC in the memory cell subarray 2.

[0210] In some examples, the second transistor T2 includes a second gate 25, a second source 26, and a second drain 27. The second gate 25 of each second transistor T2 is electrically connected to a select signal line BS, one of the second source 26 and the second drain 27 of the second transistor T2 is electrically connected to the first transistor T1 located in the same row and adjacent to it, and the other of the second source 26 and the second drain 27 of the second transistor T2 is electrically connected to a bit line BL.

[0211] Figure 7 The equivalent circuit diagram shown illustrates a row of memory cells MC, a first transistor T1 corresponding to the row of memory cells MC, and a second transistor T2 corresponding to the row of memory cells MC. Figure 7 In the middle, the second transistor T2 is located at the right end of the row memory cell MC and is electrically connected to the first transistor T1 located on the far right. The first transistor T1 located on the far right is electrically connected to the bit line BL through the second transistor T2.

[0212] Here, the aforementioned second transistor T2 can also be called a selection transistor. Within the same column of second transistors T2, different second transistors T2 are electrically connected to different selection signal lines BS and different bit lines BL. During the operation of the memory cell subarray 2, the operating state of the second transistors T2 in the same column can be controlled by the selection signals transmitted through different selection signal lines BS. For example, if the selection signal transmitted by one selection signal line BS is at a high level, controlling the corresponding second transistor T2 to turn on, and the selection signals transmitted by the remaining selection signal lines BS are at a low level, controlling the corresponding second transistors T2 to turn off, then when electrical signals are transmitted on each word line WL, the row of first transistors T1 and memory cells MC corresponding to each turned-off second transistor T2 will not operate, while the row of first transistors T1 and memory cells MC corresponding to each turned-on second transistor T2 will operate (e.g., storing or retrieving data).

[0213] By setting the second transistor T2, the operation of a specific row of memory cells MC in the memory cell subarray 2 can be selectively controlled. When the first gate 24 of the first transistor T1 corresponding to the memory cell MC in the same column is connected and formed as a single unit, interference between memory cells MC in different rows can be avoided, ensuring that the memory cell subarray 2 and the memory array 100 can operate normally.

[0214] In some examples, the second transistor T2 further includes a second channel layer 28 and a second gate dielectric layer. Two adjacent conductive blocks 211a located at the end of a row of memory cells MC respectively form a second source 26 and a second drain 27, with a third insulating block 217 disposed between the second source 26 and the second drain 27. At least a portion of the second channel layer 28 is located on the sidewall A of the stacked structure 21, the second gate dielectric layer covers the second channel layer 28, and the second gate 25 is located on the side of the second gate dielectric layer away from the second channel layer 28. That is, the second channel layer 28, the second gate dielectric layer, and the second gate 25 are stacked sequentially in a third direction Y, away from the sidewall A. The second gate dielectric layer separates the second gate 25 from the second channel layer 28, preventing contact between them, and also separates the second gate 25 from the conductive blocks 211a in the stacked structure 21, preventing short circuits between them.

[0215] like Figure 6 As shown, the second channel layer 28 is in contact with the second source 26, the second drain 27, and the third insulating block 217. Specifically, the second channel layer 28 forms an ohmic contact with the second source 26 and the second drain 27.

[0216] exist Figure 6In the array, the two adjacent conductive blocks 211a at the rightmost end of the row of memory cells MC serve as the second source 26 and the second drain 27 of the second transistor T2, respectively. Here, the rightmost memory cell MC can, for example, share a conductive block 211a with the second transistor T2. This allows the rightmost memory cell MC (or the first transistor T1) to form an electrical connection with the second transistor T2, and also simplifies the structure of the memory cell subarray 2.

[0217] For example, the second channel layer 28, the second gate dielectric layer, and the second gate 25 of the second transistor T2 can be formed synchronously with the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 of the first transistor T1, respectively. The configuration of the second channel 28 of the second transistor T2 can be the same as the configuration of the first channel layer 22 of the first transistor T1. This simplifies the fabrication process of the memory cell subarray 2 and the memory array 100.

[0218] Based on the positional relationship between the second gate 25 and the second channel layer 28 in the second transistor T2, the structure of the second transistor T2 forms a transistor structure with a vertical channel. Therefore, the second transistor T2 can be called a vertical channel field-effect transistor. Compared with horizontal channel transistors, the second transistor T2 has a smaller projected area on the substrate 1, which avoids affecting the storage density of the storage array 100.

[0219] In some embodiments, the storage functional layer 212 in the stacked structure 21 includes a ferroelectric material layer, a resistive switching layer material, or a phase change material layer.

[0220] For example, the ferroelectric material layer includes, for instance, a hafnium-based ferroelectric dielectric (or HfO2-based ferroelectric dielectric). The ferroelectric material layer material includes, but is not limited to, ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or materials based on this material (e.g., HfO2) doped with other elements, and any combination thereof. The resistive switching material layer material includes, but is not limited to, NiO. x TaO x TiO x HfO x WO x ZrO x Al y O x SrTiO x The materials for the phase change material layer include, but are not limited to, GeTe alloys, Sb2Te5 alloys, and Ge2Sb2Te5.

[0221] Some embodiments of this application also provide a method for fabricating a storage array. For example... Figure 13As shown, the preparation method includes: S100~S300.

[0222] S100 provides substrate 1.

[0223] S200, an initial stacked structure 21a is formed on the substrate 1. The initial stacked structure 21a includes multiple conductive layers 211 stacked along a first direction Z and multiple storage functional layers 212. The conductive layers 211 include multiple conductive blocks 211a arranged at intervals along a second direction X. A storage functional layer 212 is disposed between two adjacent conductive blocks 211a, and two adjacent conductive blocks 211a and the storage functional layer 212 located between the two adjacent conductive blocks 211a form a storage cell. The first direction Z is perpendicular to the substrate 1, and the second direction X is parallel to the substrate 1.

[0224] For example, embodiments of this application may employ multiple processes such as deposition, etching, and polishing to form the initial stacked structure 21a. The deposition processes include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Etching processes include, but are not limited to, photolithography. Polishing processes include, but are not limited to, CMP (chemical mechanical polishing).

[0225] Here, the architecture of the initial stacked structure 21a is basically the same as that of the stacked structure 21 described above. The stacked structure 21 can be obtained by replacing the film layer (i.e., the first sacrificial layer or the second sacrificial layer mentioned below) in the initial stacked structure 21a. For the configuration of the conductive layer 211, conductive block 211a and storage function layer 212 in the initial stacked structure 21a, please refer to the description of the conductive layer 211, conductive block 211a and storage function layer 212 in the stacked structure 21 above, which will not be repeated here.

[0226] In step S300, a first channel layer 22, a first gate dielectric layer 23, and a first gate 24 are formed. The first channel layer 22 corresponds to the memory cell MC, and at least a portion of the first channel layer 22 is located on the sidewall A of the initial stacked structure 21a and is in contact with two adjacent conductive blocks 211a and the memory functional layer 212 in the memory cell MC. The first gate dielectric layer 23 covers the first channel layer 22, and the first gate 24 is located on the side of the first gate dielectric layer 23 away from the first channel layer 22. The two adjacent conductive blocks 211a, the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 form a first transistor T1.

[0227] For example, in the embodiments of this application, any one of the first channel layer 22, the first gate dielectric layer 23 and the first gate 24 can be formed by multiple processes such as deposition process and etching process.

[0228] The first channel layer 22, the first gate dielectric layer 23, and the first gate 24 prepared in S300 have the same structure and arrangement as the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 mentioned above. For details, please refer to the description of the first channel layer 22, the first gate dielectric layer 23, and the first gate 24 mentioned above, which will not be repeated here.

[0229] The method for preparing a storage array provided in this application is used to prepare a storage array 100 as described in any of the above embodiments. The beneficial effects that this preparation method can achieve are the same as those that the storage array 100 can achieve, and will not be repeated here.

[0230] The aforementioned initial stacked structure 21a corresponds to one memory cell subarray 2. Since the memory array 100 includes multiple memory cell subarrays 2 located on the substrate 1, multiple initial stacked structures 21a are simultaneously formed on the substrate 1. This application embodiment uses the fabrication of one memory cell subarray 2 as an example to illustrate the fabrication method of the memory array.

[0231] In some embodiments of this application, the positional relationship between two adjacent conductive blocks 211a and the storage functional layer 212 in the same storage cell MC includes various methods. Correspondingly, in the above S200, there are various methods for forming the initial stacked structure 21a.

[0232] In some possible embodiments, two adjacent conductive blocks 211a in the same storage cell MC are located in the same conductive layer 211.

[0233] Based on this, such as Figures 14a-14d As shown, in the above S200, an initial stacked structure 21a is formed on the substrate 1, including: alternatingly forming a first composite layer 3 and a first sacrificial layer 4 on the substrate 1.

[0234] Here, the film layer in contact with the substrate 1 is, for example, the first sacrificial layer 4, and the film layer furthest from the substrate 1 along the first direction Z is, for example, the first composite layer 3.

[0235] For example, the first composite layer 3 and the first sacrificial layer 4 can have different etching selectivity ratios. This allows the first composite layer 3 to be retained and the first sacrificial layer 4 to be removed in subsequent processes, thereby forming a gap between any two adjacent first composite layers 3, which can then be filled with insulating material.

[0236] Optionally, the material of the first sacrificial layer 4 may include, but is not limited to, silicon nitride.

[0237] For example, the formation of the first composite layer 3 includes: S210a to S230a.

[0238] S210a, such as Figure 14a As shown, a first conductive thin film D1 is formed.

[0239] For example, embodiments of this application may employ CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the first conductive thin film D1. The dimension of the first conductive thin film D1 in the second direction X is, for example, larger than its dimension in the third direction Y, such that the orthographic projection of the first conductive thin film D1 onto the substrate 1 is rectangular or strip-shaped. The third direction Y is parallel to the substrate 1, and the second direction X and the third direction Y are perpendicular to each other.

[0240] S220a, such as Figure 14b As shown, the first conductive thin film D1 is etched to form a plurality of conductive blocks 211a arranged at intervals along the second direction X, thereby obtaining a conductive layer 211.

[0241] For example, in embodiments of this application, a photolithography process can be used to etch the first conductive film D1, breaking the first conductive film D1 to obtain a plurality of spaced conductive blocks 211a. This step is, for example, referred to as photolithography along the second direction X.

[0242] S230a, such as Figure 14c As shown, a storage function layer 212 is formed between two adjacent conductive blocks 211a, and two adjacent conductive blocks 211a in the same storage cell MC are located in the conductive layer 211 in the first composite layer 3.

[0243] For example, in this embodiment, a storage function film can first be formed on the conductive layer 211 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. A portion of the storage function film is located on each conductive block 211a, and another portion is located between any two adjacent conductive blocks 211a. Then, a polishing process such as CMP can be used to polish the storage function film (or perform surface planarization treatment), removing the portion located on each conductive block 211a, and retaining the portion located between any two adjacent conductive blocks 211a. The portion of the storage function film located between two adjacent conductive blocks 211a constitutes the storage function layer 212. The conductive layer 211 can serve as a stop layer for the polishing process, improving the surface flatness of the first composite layer 3.

[0244] Using the above preparation method, two adjacent conductive blocks 211a and storage functional layers 212 in the same storage cell MC can be located in the same layer. In the first composite layer 3 formed, the conductive blocks 211a and storage functional layers 212 are alternately arranged along the second direction X, so that two adjacent storage cells MC in the same first composite layer 3 share a conductive block 211a and are electrically connected to each other through the shared conductive block 211a.

[0245] In some examples, in the above S300, a first channel layer 22, a first gate dielectric layer 23 and a first gate 24 are formed, including: S310a to S360a.

[0246] S310a, such as Figure 14e As shown, a channel film E is formed. The channel film E at least covers the sidewalls of the initial stacked structure 21a.

[0247] For example, the trench film E can be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0248] For example, the channel film E is planar in shape and covers one sidewall of the initial laminated structure 21a. Alternatively, the channel film E may include two planar portions that cover two opposite sidewalls of the initial laminated structure 21a. Or, for example... Figure 14e As shown in (b), the channel film E is in the shape of an inverted U, and the channel film E covers the two opposite sidewalls and the top wall of the initial stacked structure 21a.

[0249] S320a, such as Figure 14f As shown, a gate dielectric film F is formed. The gate dielectric film F covers the channel film E.

[0250] For example, the embodiments of this application may employ CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the gate dielectric thin film F.

[0251] For example, the gate dielectric film F has the same shape as the channel film E, and the gate dielectric film F and the channel film E are arranged in the same way.

[0252] Optionally, such as Figure 14f As shown in (b), the channel film E is in an inverted U-shape, and correspondingly, the gate dielectric film F is in an inverted U-shape and is located on the channel film E, covering the two opposite sidewalls and the top wall of the initial stacked structure 21a.

[0253] S330a, such as Figure 14g As shown, a gate thin film G is formed. The gate thin film G covers the gate dielectric thin film F.

[0254] For example, the gate thin film G can be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0255] For example, the gate film G has the same shape as the gate dielectric film F, and the gate film G and the gate dielectric film F (or the channel film E) are arranged in the same way.

[0256] Optionally, such as Figure 14g As shown in (b), the gate dielectric film F is in an inverted U-shape, and correspondingly, the gate film G is in an inverted U-shape and is located on the channel film E, covering the two opposite sidewalls and the top wall of the initial stacked structure 21a.

[0257] This application uses an example where the channel film E, the gate dielectric film F, and the gate film G are all inverted U-shaped.

[0258] S340a, such as Figure 14h As shown, the gate film G, the gate dielectric film F, and the channel film E are etched to form an initial gate G1, an initial gate dielectric layer F1, and an initial channel layer E1 extending along the first direction Z.

[0259] For example, embodiments of this application may employ photolithography to simultaneously etch the gate film G, the gate dielectric film F, and the channel film E, breaking the gate film G to obtain a plurality of initial gates G1 arranged at intervals along the second direction X, breaking the gate dielectric film F to obtain a plurality of initial gate dielectric layers F1 arranged at intervals along the second direction X, and breaking the channel film E to obtain a plurality of initial channel layers E1 arranged at intervals along the second direction X. This step is, for example, referred to as photolithography along the second direction X.

[0260] For example, the initial gate G1, the initial gate dielectric layer F1 and the initial channel layer E1 located at the same position have the same shape, and their orthogonal projections on the substrate 1 coincide.

[0261] S350a, such as Figure 14i As shown, the first sacrificial layer 4 is removed through the sidewalls of the initial stacked structure 21a that are not covered by the initial gate G1, the initial gate dielectric layer F1 and the initial channel layer E1 to form the first gap H1.

[0262] For example, in this embodiment of the application, a selective wet etching process can be used to remove the first sacrificial layer 4. After etching the gate film G, the gate dielectric film F, and the channel film E, a portion of the surface of the first sacrificial layer 4 will be covered by the initial channel layer E1, the initial gate dielectric layer F1, and the initial gate G1, while the other portion of the surface will be exposed. The etchant can then gradually etch the first sacrificial layer 4 through the exposed portion of the surface until the first sacrificial layer 4 is completely removed, and the space occupied by the first sacrificial layer 4 forms the first gap H1.

[0263] Here, the first composite layer 3, the initial gate G1, the initial gate dielectric layer F1, and the initial channel layer E1 all have different etching selectivity ratios compared to the first sacrificial layer 4. This allows only the first sacrificial layer 4 to be removed during the removal process, avoiding corrosion of the first composite layer 3, the initial gate G1, the initial gate dielectric layer F1, and the initial channel layer E1. This, in turn, helps ensure the structural integrity of the first composite layer 3, the initial gate G1, the initial gate dielectric layer F1, and the initial channel layer E1.

[0264] S360a, such as Figure 14j As shown, the initial channel layer E1 is etched through the first gap H1 to remove the portion of the initial channel layer E1 that is opposite to the first gap H1.

[0265] For example, in this embodiment of the application, a selective wet etching process can be used to remove the portion of the initial channel layer E1 opposite to the first slit H1. The etching solution can enter the first slit H1, allowing the portion of the initial channel layer E1 opposite to the first slit H1 to come into contact with the etching solution and be removed. By controlling the etching time, the removal of the portion of the initial channel layer E1 in contact with the first composite layer 3 can be avoided.

[0266] Here, the first composite layer 3, the initial gate G1, and the initial gate dielectric layer F1 all have different etching selectivity ratios compared to the initial channel layer E1. This allows for etching only the initial channel layer E1 during the removal of the portion of the initial channel layer E1 opposite to the first gap H1, avoiding corrosion of the first composite layer 3, the initial gate G1, and the initial gate dielectric layer F1. This, in turn, helps ensure the structural integrity of the first composite layer 3, the initial gate G1, and the initial gate dielectric layer F1.

[0267] like Figure 14jAs shown in (b), after removing the portion of the initial channel layer E1 opposite to the first gap H1, the initial channel layer E1 can be broken to obtain a plurality of first channel patterns E2 arranged at intervals along the first direction Z. Among them, along the first direction Z, the first channel pattern E2 farthest from the substrate 1 is located on the two opposite sides and the top surface of the first composite layer 3 farthest from the substrate 1, and in the remaining first channel patterns E2, each first channel pattern E2 is located on one side of the corresponding first composite layer 3.

[0268] In some examples, two adjacent conductive blocks 211a in the first composite layer 3 and the storage function layer 212 located between the two adjacent conductive blocks 211a can be used as a storage cell MC. The first channel pattern E2 obtained in step S360a above and in contact with the storage cell MC can be used as the first channel layer 22. The portion of the initial gate dielectric layer F1 opposite to the first channel layer 22 can be used as the first gate dielectric layer 23. The portion of the initial gate G1 opposite to the first channel layer 22 can be used as the first gate 24.

[0269] At this time, along the first direction Z, the first channel layer 22 furthest from the substrate 1 is located on both sides and the top surface of the memory cell MC, and the remaining first channel layers 22 include two first channel patterns E2, each of which is located on one side of the corresponding memory cell MC. The first gate dielectric layer 23 and the first gate 24 are similarly located.

[0270] Furthermore, along the first direction Z, the first gate dielectric layer 23 of the first transistor T1 in the same column is an integral structure, and the first gate 24 is an integral structure.

[0271] For example, such as Figure 14k As shown, after forming the first channel layer 22, the first gate dielectric layer 23 and the first gate 24, that is, after S360a above, the preparation method further includes filling the first gap H1 with insulating material to form a first insulating layer 213.

[0272] For example, in embodiments of this application, an ALD process or any combination thereof can be used to backfill insulating material into the first gap H1 to form a first insulating layer 213.

[0273] After the first insulating layer 213 is formed, the structure formed by the first composite layer 3 and the first insulating layer 213 is the stacked structure 21.

[0274] In addition to occupying the space occupied by the first sacrificial layer 4, the first insulating layer 213 also occupies the space between two adjacent first channel layers 22, which facilitates the separation of the two adjacent first channel layers 22, so that the two adjacent first channel layers 22 are electrically insulated (or electrically isolated).

[0275] In other examples, the initial gate G1, the initial gate dielectric layer F1, and the initial channel layer E1 are all located on at least two opposite sidewalls of the initial stacked structure 21a. For example... Figure 15a As shown, before S350 above, that is, before removing the first sacrificial layer 4 through the sidewalls of the initial stacked structure 21a that are not covered by the initial gate G1, the initial gate dielectric layer F1, and the initial channel layer E1, the process further includes: etching at least the initial stacked structure 21a along the first direction Z and along the second direction X to form a first initial stacked structure 21a-1 and a second initial stacked structure 21a-2 disposed opposite to each other. The initial gate G1, the initial gate dielectric layer F1, and the initial channel layer E1 are all divided into two parts, with one part of each located on the sidewall of the first initial stacked structure 21a-1 and the other part located on the sidewall of the second initial stacked structure 21a-2.

[0276] For example, the first initial stacked structure 21a-1 and the second initial stacked structure 21a-2 are symmetrical to each other, the two parts of the initial gate G1 are symmetrical to each other, the two parts of the initial gate dielectric layer F1 are symmetrical to each other, and the two parts of the initial channel layer E1 are symmetrical to each other.

[0277] like Figure 15b and Figure 15c As shown, there is a gap between the first initial stacked structure 21a-1 and the second initial stacked structure 21a-2. Thus, in S350, the first sacrificial layer 4 can be removed through this gap and the sidewalls of the first and second initial stacked structures 21a-1 and 21a-2 that are not covered by the initial gate G1, the initial gate dielectric layer F1, and the initial channel layer E1. The portion of the initial channel layer E1 opposite to the first gap H1 is also removed. This increases the contact area between the etchant and the first sacrificial layer 4, which is beneficial for improving the removal rate of the first sacrificial layer 4.

[0278] For example, such as Figure 15d As shown, after S360a, the preparation method further includes: filling the first gap H1 with insulating material to form a first insulating layer 213. The first insulating layer 213 occupies not only the space occupied by the first sacrificial layer 4, but also the space between two adjacent channel patterns and the aforementioned gap.

[0279] For example, in embodiments of this application, an ALD process or any combination thereof can be used to backfill insulating material into the first gap H1 to form a first insulating layer 213.

[0280] After the first insulating layer 213 is formed, the first initial stacked structure 21a-1 and the second initial stacked structure 21a-2 can each serve as a stacked structure 21. Each first channel pattern E2 obtained in S360a above can serve as a first channel layer 22.

[0281] At this time, along the first direction Z, the first channel layer 22 furthest from the substrate 1 is located on one side and the top surface of the memory cell MC, and the remaining first channel layers 22 include a first channel pattern E2, which is located on one side of the corresponding memory cell MC. The first gate dielectric layer 23 and the first gate 24 are similarly located.

[0282] Furthermore, along the first direction Z, the first gate dielectric layer 23 of the first transistor T1 in the same column is an integral structure, and the first gate 24 is an integral structure.

[0283] In other examples, two adjacent conductive blocks 211a in the first composite layer 3 and the storage function layer 212 located between the two adjacent conductive blocks 211a constitute a storage cell MC. In the above S300, the formation of the first channel layer 22, the first gate dielectric layer 23 and the first gate 24 also includes: S370a to S31000a.

[0284] S370a, such as Figure 16a As shown, the initial gate dielectric layer F1 is etched through the first gap H1 to remove the portion of the initial gate dielectric layer F1 opposite to the first gap H1, forming the first gate dielectric pattern F2.

[0285] For example, in this embodiment of the application, a selective wet etching process can be used to remove the portion of the initial gate dielectric layer F1 opposite to the first gap H1. The etching solution can enter the first gap H1, allowing the portion of the initial gate dielectric layer F1 opposite to the first gap H1 to come into contact with the etching solution and be removed. By controlling the etching time, the portion of the initial gate dielectric layer F1 in contact with the first channel pattern E2 can be avoided.

[0286] Here, the first composite layer 3, the initial gate G1, and the first channel pattern E2 all have different etching selectivity ratios compared to the initial gate dielectric layer F1. This allows for etching only the initial gate dielectric layer F1 during the removal of the portion of the initial gate dielectric layer F1 opposite to the first gap H1, avoiding corrosion of the first composite layer 3, the initial gate G1, and the first channel pattern E2. This, in turn, helps ensure the structural integrity of the first composite layer 3, the initial gate G1, and the first channel pattern E2.

[0287] like Figure 16aAs shown in (b), after removing the portion of the initial gate dielectric layer F1 opposite to the first gap H1, the initial gate dielectric layer F1 can be broken to obtain a plurality of first gate dielectric patterns F2 arranged at intervals along the first direction Z. The first gate dielectric pattern F2 and the first channel pattern E2 in contact with it have the same or approximately the same shape, and their orthogonal projection areas on the plane perpendicular to the third direction Y are the same or approximately the same.

[0288] S380a, such as Figure 16b As shown, material for the first channel layer 22 is deposited within the first gap H1 to form a second channel pattern E3. The first channel pattern E2 and the second channel pattern E3 form the first channel layer 22. The cross-sectional pattern of the first channel layer 22 is annular along the first direction Z and along the third direction Y. The first channel layer 22 surrounds the memory cell MC. The third direction Y is parallel to the substrate 1 and perpendicular to the second direction X.

[0289] For example, in embodiments of this application, a thin film deposition process, such as ALD process or any combination thereof, can be used to backfill the material of the first channel layer 22 into the first gap H1 to form the second channel pattern E3.

[0290] like Figure 16b As shown in (b), the material of the first channel layer 22 is deposited on the top and / or bottom surfaces of each memory cell MC to form a second channel pattern E3, such that the two first channel layers 22 located on the two sides of each memory cell MC are connected to the second channel pattern E3 to form the first channel layer 22. The first channel layer 22 is tubular in shape and surrounds the memory cell MC located inside it.

[0291] S390a, such as Figure 16c As shown, material of the first gate dielectric layer 23 is deposited in the first gap H1 to form a second gate dielectric pattern F3. The first gate dielectric pattern F2 and the second gate dielectric pattern F3 form the first gate dielectric layer 23. The cross-sectional pattern of the first gate dielectric layer 23 is annular along the first direction Z and the third direction Y, and the first gate dielectric layer 23 surrounds the first channel layer 22.

[0292] For example, in embodiments of this application, a thin film deposition process, such as ALD process or any combination thereof, can be used to backfill the material of the first gate dielectric layer 23 into the first gap H1 to form the second gate dielectric pattern F3.

[0293] like Figure 16cAs shown in (b), the material of the first gate dielectric layer 23 is deposited on the top and / or bottom surface of the first channel layer 22, that is, on the surface of the second channel pattern E3, forming the second gate dielectric pattern F3. This allows the two first gate dielectric patterns F2 located on the two sides of each first channel layer 22 to be connected with the second gate dielectric pattern F3, forming the first gate dielectric layer 23. The first gate dielectric layer 23 is generally tubular, surrounding the first channel layer 22 located inside it.

[0294] S3100a, such as Figure 16d As shown, material for the first gate 24 is deposited within the first gap H1 to form a first gate pattern G2. The portions of the first gate pattern G2 and the initial gate G1 located on opposite sides of the same memory cell MC form the first gate 24. The cross-sectional pattern of the first gate 24 is annular along the first direction Z and the third direction Y, and the first gate 24 surrounds the first gate dielectric layer 23.

[0295] For example, in embodiments of this application, a thin film deposition process, such as ALD process or any combination thereof, can be used to backfill the material of the first gate 24 into the first gap H1 to form the first gate pattern G2.

[0296] For example, the material of the first gate 24 is deposited on the top and / or bottom surface of the first gate dielectric layer 23, that is, on the surface of the first gate pattern G2, forming the first gate pattern G2, such that the portions of the initial gate G1 located on opposite sides of the same memory cell MC are connected to the first gate pattern G2, forming the first gate 24. The first gate 24 is tubular in shape, surrounding the first gate dielectric layer 23 located inside it.

[0297] If the material of the first gate 24 does not completely fill the first gap H1, insulating material can be backfilled into the first gap H1.

[0298] For example, the material of the first gate 24 fills the first gap H1, and along the first direction Z, two adjacent first gates 24 share a first gate pattern G2.

[0299] The first transistor T1 obtained in step S3100a above is a full-gate transistor.

[0300] like Figure 16e As shown, after S3100a above, the preparation method further includes: filling the first gap H1 with insulating material to form a first insulating layer 213.

[0301] In some other possible embodiments, two adjacent conductive blocks 211a in the same storage cell MC are located in two adjacent conductive layers 211, respectively.

[0302] Based on this, such as Figure 17g and Figure 18d As shown, in the above S200, an initial stacked structure 21a is formed on the substrate 1, including: alternatingly forming a second composite layer 5 and a second sacrificial layer 6 on the substrate 1.

[0303] Here, the film layer in contact with the substrate 1 is, for example, the second sacrificial layer 6, and the film layer furthest from the substrate 1 along the first direction Z is, for example, the second composite layer 5.

[0304] For example, the second composite layer 5 and the second sacrificial layer 6 can have different etching selectivity ratios. This allows the second composite layer 5 to be retained and the second sacrificial layer 6 to be removed in subsequent processes, forming a gap between any two adjacent second composite layers 5, which can then be filled with insulating material.

[0305] Optionally, the material of the second sacrificial layer 6 may include, but is not limited to, silicon nitride.

[0306] For example, the formation of the second composite layer 5 includes: S210b to S250b.

[0307] S210b, such as Figure 17a As shown, a second conductive thin film D2 is formed.

[0308] For example, embodiments of this application may employ CVD, PVD, ALD, or any combination thereof thin film deposition processes to form the second conductive thin film D2. The dimension of the second conductive thin film D2 in the second direction X is, for example, larger than its dimension in the third direction Y, such that the orthographic projection shape of the second conductive thin film D2 on the substrate 1 is rectangular or strip-shaped.

[0309] S220b, such as Figure 17b As shown, the second conductive film D2 is etched to form a plurality of conductive blocks 211a arranged at intervals along the second direction X, thereby obtaining a conductive layer 211.

[0310] For example, in embodiments of this application, a photolithography process can be used to etch the second conductive film D2, breaking the second conductive film D2 to obtain a plurality of spaced conductive blocks 211a. This step is, for example, referred to as photolithography along the second direction X.

[0311] S230b, such as Figure 17c As shown, a storage function layer 212 is formed on the plurality of conductive blocks 211a.

[0312] For example, before forming the storage functional layer 212, this embodiment of the application may use a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form an insulating film on the plurality of conductive blocks 211a. A portion of the insulating film is located on each conductive block 211a, and another portion is located between any two adjacent conductive blocks 211a. Then, a polishing process such as CMP can be used to polish the insulating film (or perform surface planarization treatment) to remove the portion located on each conductive block 211a, retaining the portion located between any two adjacent conductive blocks 211a. The portion of the storage functional layer located between two adjacent conductive blocks 211a constitutes the first insulating block 214. Afterward, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form the storage functional layer 212 on the plurality of conductive blocks 211a.

[0313] The conductive layer 211 can serve as a stop layer in the polishing process, improving the surface flatness of the conductive layer 211, thereby improving the flatness of the storage function layer 212. The storage function layer 212 covers the aforementioned plurality of conductive blocks 211a and plurality of first insulating blocks 214.

[0314] S240b, such as Figure 17d As shown, a third conductive film D3 is formed on the storage functional layer 212.

[0315] For example, in embodiments of this application, a third conductive thin film D3 can be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The orthographic projection of the third conductive thin film D3 on the substrate 1 coincides, for example, with the orthographic projection of the second conductive thin film D2 on the substrate 1.

[0316] S250b, such as Figure 17e and Figure 18c As shown, the third conductive film D3 is etched to form a plurality of conductive blocks 211a arranged sequentially at intervals along the second direction X, resulting in a conductive layer 211. Along the first direction Z, two adjacent conductive blocks 211a in the same memory cell MC are respectively located in two adjacent conductive layers 211 in the second composite layer 5, and the orthographic projections of the two adjacent conductive blocks 211a on the substrate 1 overlap.

[0317] For example, in embodiments of this application, a photolithography process can be used to etch the second conductive film D2, breaking the second conductive film D2 to obtain a plurality of spaced conductive blocks 211a. This step is, for example, referred to as photolithography along the second direction X.

[0318] For example, such as Figure 17f and Figure 18cAs shown, after etching the third conductive film D3, this embodiment of the application can use CVD, PVD, ALD, or any combination thereof to form an insulating film on the plurality of conductive blocks 211a. A portion of the insulating film is located on each conductive block 211a, and another portion is located between any two adjacent conductive blocks 211a. Then, CMP or other polishing processes can be used to polish the insulating film (or perform surface planarization treatment) to remove the portion located on each conductive block 211a, retaining the portion located between any two adjacent conductive blocks 211a. The portion of the insulating film located between two adjacent conductive blocks 211a constitutes the first insulating block 214.

[0319] The two adjacent conductive layers 211, the storage function layer 212 located between the two adjacent conductive layers 211, and the first insulating block 214 located in each conductive layer 211 constitute the second composite layer 5.

[0320] The aforementioned storage functional layer 212 is planar, which can effectively reduce the number of photomask operations and lower the cost of the storage array fabrication method.

[0321] In some examples, such as Figure 18a and Figure 18b As shown, before S240b above, that is, before the formation of the third conductive film D3 on the storage functional layer 212, the preparation method further includes: forming a plurality of second insulating blocks 216 arranged sequentially at intervals along the second direction X on the plurality of conductive blocks 211a, forming a storage functional layer 212 between two adjacent second insulating blocks 216, and the plurality of storage functional layers 212 arranged sequentially at intervals along the second direction X.

[0322] In the second composite layer 5, among two adjacent conductive layers 211, the conductive block 211a located in one conductive layer 211 is the first conductive block 211a-1, and the conductive block 211a located in the other conductive layer 211 is the second conductive block 211a-2. In the orthographic projection of the two adjacent conductive layers 211 onto the substrate 1, along the second direction X, multiple first conductive blocks 211a-1 and multiple second conductive blocks 211a-2 are alternately arranged. Along the first direction Z, one first conductive block 211a-1 and two second conductive blocks 211a-2 overlap, and one first conductive block 211a-1 overlaps with two storage functional layers 212.

[0323] For example, in this embodiment of the application, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form an insulating film on the plurality of conductive blocks 211a, and a photolithography process can be used to etch the insulating film to form a plurality of second insulating blocks 216; then, in this embodiment of the application, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a storage function film on the plurality of second insulating blocks 216, a portion of which is located on each second insulating block 216, and another portion is located between any two adjacent second insulating blocks 216; then, a polishing process such as CMP can be used to polish the storage function film (or perform surface planarization treatment), removing the portion located on each second insulating block 216, and retaining the portion located between any two adjacent second insulating blocks 216. The portion of the storage function film located between two adjacent second insulating blocks 216 constitutes the storage function layer 212.

[0324] The configuration of the first conductive block 211a-1, the second conductive block 211a-2, and the storage function layer 212 in the second composite layer 5 can be found in the description above, and will not be repeated here.

[0325] In some examples, in the above S300, the formation of a first channel layer 22, a first gate dielectric layer 23, and a first gate 24 includes: S310b to S370b.

[0326] S310b, forming a channel film E, which at least covers the sidewalls of the initial stacked structure 21a.

[0327] S320b forms a gate dielectric film F, which covers the channel film E.

[0328] S330b forms a gate thin film G, which covers the gate dielectric thin film F.

[0329] S340b etches the gate film G, the gate dielectric film F, and the channel film E to form an initial gate G1, an initial gate dielectric layer F1, and an initial channel layer E1 extending along the first direction Z.

[0330] S350b, through the sidewalls of the initial stacked structure 21a that are not covered by the initial gate G1, the initial gate dielectric layer F1 and the initial channel layer E1, the second sacrificial layer 6 is removed to form the second gap.

[0331] S360b, through the second gap, the initial channel layer E1 is etched to remove the portion of the initial channel layer E1 opposite to the second gap, forming a plurality of first channel layers 22 spaced apart in the first direction Z.

[0332] The steps in S310b to S360b are basically the same as the corresponding steps in S310a to S360a in some of the examples above. For details, please refer to the descriptions of the corresponding steps in S310a to S360a in some of the examples above. They will not be repeated here.

[0333] S370b, filling the second gap with insulating material to form a second insulating layer 215.

[0334] For example, in this embodiment of the application, an ALD process or any combination thereof can be used to backfill insulating material into the second gap H2 to form a second insulating layer 215. After performing the above steps S310b to S370b, the resulting structure is as follows: Figures 11a to 12d As shown.

[0335] In some embodiments, the second transistor T2 can be fabricated simultaneously with the first transistor T1, and the fabrication method of the second transistor T2 will not be described in detail.

[0336] In the above Figures 14a to 17g In the figures, (a) represents the front view of the structure obtained by the corresponding step, and (b) represents the cross-sectional view of the structure obtained by the corresponding step along the first direction Z and the third direction Y.

[0337] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, The memory array includes: a substrate and a plurality of memory cell subarrays located on the substrate; The storage cell subarray includes: A stacked structure includes multiple conductive layers and multiple storage functional layers stacked along a first direction. Each conductive layer includes multiple conductive blocks spaced apart along a second direction. The storage functional layer is disposed between two adjacent conductive blocks, and the two adjacent conductive blocks and the storage functional layer located between the two adjacent conductive blocks form a storage cell. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate. A first channel layer corresponding to the memory cell, at least a portion of the first channel layer is located on the sidewall of the stacked structure and is in contact with two adjacent conductive blocks and the memory functional layer in the memory cell; A first gate dielectric layer covering the first channel layer; and, A first gate is located on the side of the first gate dielectric layer away from the first channel layer; the two adjacent conductive blocks, the first channel layer, the first gate dielectric layer, and the first gate form a first transistor.

2. The storage array according to claim 1, characterized in that, Two adjacent conductive blocks in the storage unit are located on the same conductive layer. Along the second direction, the storage function layer in the storage cell is located between the two adjacent conductive blocks.

3. The storage array according to claim 2, characterized in that, In the same conductive layer, the conductive block and the storage function layer are alternately arranged along the second direction.

4. The storage array according to claim 2, characterized in that, The stacked structure further includes multiple first insulating layers, and along the first direction, the multiple conductive layers and the multiple first insulating layers are alternately arranged.

5. The storage array according to claim 1, characterized in that, In the memory cell, two adjacent conductive blocks are located in two adjacent conductive layers, and the orthographic projections of the two adjacent conductive blocks on the substrate overlap. Along the first direction, the storage function layer in the storage cell is located between the two adjacent conductive blocks.

6. The storage array according to claim 5, characterized in that, In the two adjacent conductive layers, the conductive block located in one of the conductive layers is the first conductive block, and the conductive block located in the other conductive layer is the second conductive block; In the orthographic projection of the two adjacent conductive layers onto the substrate, along the second direction, a plurality of first conductive blocks and a plurality of second conductive blocks are alternately arranged; Along the first direction, one first conductive block and two second conductive blocks overlap, and one first conductive block and two storage function layers overlap.

7. The storage array according to claim 5, characterized in that, The stacked structure also includes a plurality of first insulating blocks, and in the same conductive layer, along the second direction, a plurality of conductive blocks and a plurality of first insulating blocks are alternately arranged.

8. The storage array according to claim 5, characterized in that, The storage cell subarray includes multiple rows of storage cells, and each row of storage cells includes a plurality of the storage cells arranged along the second direction; The stacked structure also includes multiple layers of second insulating layers, which are located between adjacent rows of memory cells.

9. The storage array according to claim 5, characterized in that, The storage cell subarray includes multiple rows of storage cells, and each row of storage cells includes a plurality of the storage cells arranged along the second direction; The stacked structure further includes multiple second insulating blocks, and in the same row of storage cells, the storage functional layers of multiple storage cells and multiple second insulating blocks are alternately arranged; or, In the same row of storage units, the storage function layers of multiple storage units are connected and form an integrated structure.

10. The storage array according to claim 1, characterized in that, The storage cell subarray includes multiple columns of storage cells, and each column of storage cells includes multiple storage cells stacked along the first direction; In the same column of storage cells, the orthographic projections of the storage function layers of any two storage cells onto the substrate at least partially overlap.

11. The storage array according to claim 1, characterized in that, The plurality of said stacked structures are arranged sequentially along a third direction, which is parallel to the substrate and perpendicular to the second direction; the stacked structures have opposing first sidewalls and second sidewalls; The plurality of stacked structures include at least one stacked structure pair, the stacked structure pair including an adjacent first stacked structure and a second stacked structure, wherein a first sidewall of the first stacked structure is located on a side away from the second stacked structure, and a second sidewall of the second stacked structure is located on a side away from the first stacked structure. The first channel layer, first gate dielectric layer, and first gate of the first transistor corresponding to the memory cell in the first stacked structure are located on the first sidewall of the first stacked structure, and the first channel layer, first gate dielectric layer, and first gate of the first transistor corresponding to the memory cell in the second stacked structure are located on the second sidewall of the second stacked structure.

12. The storage array according to claim 1, characterized in that, The stacked structure has opposing first and second sidewalls; In the first transistor corresponding to the memory cell in the stacked structure, a portion of the first channel layer, a portion of the first gate dielectric layer, and a portion of the first gate are located on the first sidewall, and another portion of the first channel layer, another portion of the first gate dielectric layer, and another portion of the first gate are located on the second sidewall.

13. The storage array according to any one of claims 1 to 12, characterized in that, The storage cell subarray includes multiple columns of storage cells, and each column of storage cells includes multiple storage cells arranged sequentially along the first direction; Along the first direction and the second direction, the first channel layers of two adjacent first transistors are separated from each other; The first gate dielectric layer of a plurality of first transistors corresponding to the same column of memory cells is connected and located on the sidewall of the stacked structure; The first gates of a plurality of first transistors corresponding to the same column of memory cells are connected and located on the sidewall of the stacked structure.

14. The storage array according to claim 13, characterized in that, In the first transistor furthest from the substrate along the first direction, the first channel layer, the first gate dielectric layer, and the first gate also cover the top wall of the stacked structure.

15. The storage array according to claim 1, characterized in that, In the first transistor corresponding to each of the memory cells, the cross-sectional pattern of the first channel layer, the first gate dielectric layer and the first gate is annular along the first direction and along the third direction. The first channel layer surrounds the memory cell, the first gate dielectric layer surrounds the first channel layer, and the first gate surrounds the first gate dielectric layer. The third direction is parallel to the substrate and perpendicular to the second direction.

16. The storage array according to claim 15, characterized in that, The storage cell subarray includes multiple columns of storage cells, and each column of storage cells includes multiple storage cells stacked along the first direction; The first gates of a plurality of first transistors corresponding to the same column of memory cells are connected and located between the sidewalls of the stacked structure and two adjacent first gate dielectric layers.

17. The storage array according to claim 1, characterized in that, At least two of the storage cell subarrays are arranged sequentially along the second direction, and at least two of the storage cell subarrays are arranged sequentially along the third direction; The third direction is parallel to the substrate and perpendicular to the second direction.

18. The storage array according to claim 17, characterized in that, At least two of the memory cell subarrays are arranged sequentially along the first direction; The storage array further includes an encapsulation layer, which is located between two adjacent storage cell subarrays along the first direction.

19. The storage array according to claim 1, characterized in that, The storage cell subarray includes multiple rows of storage cells, and each row of storage cells includes a plurality of the storage cells arranged along the second direction; The memory cell subarray further includes: a plurality of second transistors, the second transistors being located at the ends of a row of memory cells, the plurality of second transistors being arranged in a column along the first direction; the second transistors include a second source, a second drain, a second channel layer, a second gate dielectric layer, and a second gate. Two adjacent conductive blocks located at the end of the row of memory cells respectively form the second source and the second drain, and a third insulating block is disposed between the second source and the second drain; At least a portion of the second channel layer is located on the sidewall of the stacked structure and is in contact with the second source, the second drain, and the third insulating block; The second gate dielectric layer covers the second channel layer; The second gate is located on the side of the second gate dielectric layer away from the second channel layer.

20. The storage array according to claim 1, characterized in that, The storage functional layer includes a ferroelectric material layer, a resistive switching layer, or a phase change material layer.

21. A method for fabricating a memory array, characterized in that, The preparation method includes: Provide substrate; An initial stacked structure is formed on the substrate, the initial stacked structure including multiple conductive layers and multiple storage functional layers stacked along a first direction; the conductive layers include multiple conductive blocks arranged at intervals along a second direction, the storage functional layer is disposed between two adjacent conductive blocks, and the two adjacent conductive blocks and the storage functional layer located between the two adjacent conductive blocks form a storage cell; the first direction is perpendicular to the substrate, and the second direction is parallel to the substrate. A first channel layer, a first gate dielectric layer, and a first gate are formed. The first channel layer corresponds to the memory cell. At least a portion of the first channel layer is located on the sidewall of the initial stacked structure and is in contact with two adjacent conductive blocks and the memory functional layer in the memory cell. The first gate dielectric layer covers the first channel layer. The first gate is located on the side of the first gate dielectric layer away from the first channel layer. The two adjacent conductive blocks, the first channel layer, the first gate dielectric layer, and the first gate form a first transistor.

22. The preparation method according to claim 21, characterized in that, The formation of the initial stacked structure on the substrate includes: A first composite layer and a first sacrificial layer are alternately formed on the substrate; Forming the first composite layer includes: Forming a first conductive thin film; The first conductive film is etched to form a plurality of conductive blocks that are spaced apart sequentially along the second direction, thereby obtaining the conductive layer; The storage function layer is formed between two adjacent conductive blocks, and the two adjacent conductive blocks in the same storage cell are located in the conductive layer of the first composite layer.

23. The preparation method according to claim 22, characterized in that, The formation of the first channel layer, the first gate dielectric layer, and the first gate includes: A channel film is formed, the channel film at least covering the sidewalls of the initial stacked structure; A gate dielectric film is formed, the gate dielectric film covering the channel film; A gate thin film is formed, the gate thin film covering the gate dielectric film; The gate film, the gate dielectric film, and the channel film are etched to form an initial gate, an initial gate dielectric layer, and an initial channel layer extending along the first direction; The first sacrificial layer is removed through the sidewalls of the initial stacked structure that are not covered by the initial gate, the initial gate dielectric layer and the initial channel layer to form a first gap; The initial trench layer is etched through the first gap to remove the portion of the initial trench layer opposite to the first gap.

24. The preparation method according to claim 23, characterized in that, The initial gate, the initial gate dielectric layer, and the initial channel layer are all located on at least two opposite sidewalls of the initial stacked structure; Before removing the first sacrificial layer via the portion of the sidewalls not covered by the initial gate, the initial gate dielectric layer, and the initial channel layer in the initial stacked structure, the method further includes: At least the initial stacked structure is etched along the first direction and along the second direction to form a first initial stacked structure and a second initial stacked structure disposed opposite to each other. The gate, the initial gate dielectric layer and the initial channel layer are each divided into two parts, with one part of each located on the sidewall of the first initial stacked structure and the other part located on the sidewall of the second initial stacked structure.

25. The preparation method according to claim 23 or 24, characterized in that, After forming the first channel layer, the first gate dielectric layer, and the first gate, the fabrication method further includes: The first gap is filled with insulating material to form a first insulating layer.

26. The preparation method according to claim 23, characterized in that, The initial gate, the initial gate dielectric layer, and the initial channel layer are all located at least on two opposite sidewalls of the initial stacked structure; after etching the initial channel layer through the first gap, a first channel pattern is obtained; The formation of the first channel layer, the first gate dielectric layer, and the first gate also includes: The initial gate dielectric layer is etched through the first gap to remove the portion of the initial gate dielectric layer opposite to the first gap, thereby forming a first gate dielectric pattern; Material of the first trench layer is deposited within the first gap to form a second trench pattern, the first trench pattern and the second trench pattern forming the first trench layer; the cross-sectional pattern of the first trench layer is annular along the first direction and along a third direction, the first trench layer surrounds the memory cell, the third direction is parallel to the substrate and perpendicular to the second direction; Material of the first gate dielectric layer is deposited in the first gap to form a second gate dielectric pattern. The first gate dielectric pattern and the second gate dielectric pattern form the first gate dielectric layer. The cross-sectional shape of the first gate dielectric layer is annular along the first direction and along the third direction. The first gate dielectric layer surrounds the first channel layer. Material of the first gate is deposited within the first gap to form a first gate pattern. The first gate pattern and portions of the initial gate located on opposite sides of the same memory cell form the first gate. The cross-sectional pattern of the first gate is annular along the first direction and along the third direction, and the first gate surrounds the first gate dielectric layer.

27. The preparation method according to claim 21, characterized in that, The formation of the initial stacked structure on the substrate includes: A second composite layer and a second sacrificial layer are alternately formed on the substrate; Forming the second composite layer includes: Forming a second conductive thin film; The second conductive film is etched to form a plurality of conductive blocks that are spaced apart sequentially along the second direction, thereby obtaining the conductive layer; A storage function layer is formed on the plurality of conductive blocks; A third conductive film is formed on the storage functional layer; The third conductive film is etched to form a plurality of conductive blocks spaced apart sequentially along the second direction, thus obtaining a conductive layer; along the first direction, two adjacent conductive blocks in the same memory cell are respectively located in two adjacent conductive layers in the second composite layer, and the orthogonal projections of the two adjacent conductive blocks on the substrate overlap.

28. The preparation method according to claim 27, characterized in that, The formation of a storage function layer on the plurality of conductive blocks includes: A plurality of second insulating blocks are formed on the plurality of conductive blocks and are spaced apart sequentially along the second direction; A storage functional layer is formed between two adjacent second insulating blocks, and multiple storage functional layers are sequentially spaced along the second direction; in two adjacent conductive layers of the second composite layer, the conductive block located in one conductive layer is a first conductive block, and the conductive block located in the other conductive layer is a second conductive block; in the orthogonal projection of the two adjacent conductive layers on the substrate, multiple first conductive blocks and multiple second conductive blocks are alternately arranged along the second direction; along the first direction, one first conductive block and two second conductive blocks overlap, and one first conductive block and two storage functional layers overlap.

29. The preparation method according to claim 27, characterized in that, The formation of the first channel layer, the first gate dielectric layer, and the first gate includes: A channel film is formed, the channel film at least covering the sidewalls of the initial stacked structure; A gate dielectric film is formed, the gate dielectric film covering the channel film; A gate thin film is formed, the gate thin film covering the gate dielectric film; The gate film, the gate dielectric film, and the channel film are etched to form an initial gate, an initial gate dielectric layer, and an initial channel layer extending along the first direction; The second sacrificial layer is removed through the sidewalls of the initial stacked structure that are not covered by the initial gate, the initial gate dielectric layer and the initial channel layer to form a second gap; The initial channel layer is etched through the second gap to remove the portion of the initial channel layer opposite to the second gap, thereby forming a plurality of first channel layers spaced apart in the first direction; The second gap is filled with insulating material to form a second insulating layer.

30. A memory, characterized in that, The memory includes: a controller, and a memory array as described in any one of claims 1 to 20.

31. An electronic device, characterized in that, The electronic device includes: a processor, and a memory as described in claim 30; The memory is used to store the data generated by the processor.

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