Pixel circuit, driving method, and display device

Abstract

The present disclosure provides a pixel circuit, a driving method, and a display device. The pixel circuit includes a light-emitting element, a first energy storage circuit, a first driving circuit, a second driving circuit, a first driving control circuit, a second driving control circuit, a second energy storage circuit, and a first control data voltage writing circuit; the first control data voltage writing circuit controls writing a first control data voltage into a third node under the control of a first writing control signal; a first end of the first driving circuit and a first end of the second driving circuit are both electrically connected to a power supply voltage terminal, the first driving circuit drives the light-emitting element under the control of the potential of its control terminal, and the second driving circuit is configured to drive the light-emitting element under the control of the potential of its control terminal. The present disclosure can be used for multi-gray-scale display, realizes ultra-conventional 256 gray-scale display, and can increase the number of display gray scales without significantly increasing the cost.

Description

Technical Field

[0001] The present disclosure relates to the technical field, and in particular, to a pixel circuit, a driving method, and a display device. Background Art

[0002] In recent years, with the progress of intelligent display technology, organic light-emitting diodes (OLEDs) have become one of the hotspots in the current display research field. With the thinning of the display panel and the narrowing of the border, the optimal design of the display panel has become increasingly severe.

[0003] Related pixel circuits cannot be used for multi-gray-scale display, cannot achieve ultra-conventional 256 gray-scale display, and cannot increase the number of display gray scales without significantly increasing costs. Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a first energy storage circuit, a first driving circuit, a second driving circuit, a first driving control circuit, a second driving control circuit, a second energy storage circuit, and a first control data voltage writing circuit;

[0005] A first end of the first energy storage circuit is electrically connected to a first node, a second end of the first energy storage circuit is electrically connected to a second node, and the first energy storage circuit is used for storing electrical energy;

[0006] A control end of the first driving control circuit is electrically connected to a third node; a control end of the second driving control circuit is electrically connected to a fourth node;

[0007] The first driving control circuit is further respectively electrically connected to the second node and a control end of the first driving circuit, and is used for controlling the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node;

[0008] The second driving control circuit is further respectively electrically connected to the second node and a control end of the second driving circuit, and is used for controlling the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node;

[0009] A first end of the second energy storage circuit is electrically connected to the third node, a second end of the second energy storage circuit is electrically connected to a first end of the first driving circuit, and the second energy storage circuit is used for storing electrical energy;

[0010] The first control data voltage writing circuit is electrically connected to the first writing control terminal, the first control data voltage writing terminal, and the third node respectively, and is configured to control writing the first control data voltage provided by the first control data voltage writing terminal into the third node under the control of a first writing control signal provided by the first writing control terminal;

[0011] The first end of the first driving circuit and the first end of the second driving circuit are both electrically connected to the power supply voltage terminal, the second end of the first driving circuit and the second end of the second driving circuit are both electrically connected to the light-emitting element, the first driving circuit is configured to drive the light-emitting element under the control of the potential of its control terminal, and the second driving circuit is configured to drive the light-emitting element under the control of the potential of its control terminal.

[0012] Optionally, the third node and the fourth node are the same node.

[0013] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third energy storage circuit and a second control data voltage writing circuit;

[0014] The first end of the third energy storage circuit is electrically connected to the first end of the first driving circuit, the second end of the third energy storage circuit is electrically connected to the control terminal of the second driving control circuit, and the third energy storage circuit is configured to store electrical energy;

[0015] The second control data voltage writing circuit is electrically connected to the second writing control terminal, the second control data voltage writing terminal, and the fourth node respectively, and is configured to write the second control data voltage provided by the second control data voltage writing terminal into the fourth node under the control of a second writing control signal provided by the second writing control terminal.

[0016] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit, a setting circuit, and a compensation control circuit;

[0017] The data writing circuit is electrically connected to the data line, the third writing control terminal, and the first node respectively, and is configured to write the data voltage provided by the data line into the first node under the control of a third writing control signal provided by the third writing control terminal;

[0018] The setting circuit is electrically connected to the setting control terminal, the setting voltage terminal, and the first node respectively, and is configured to write the setting voltage provided by the setting voltage terminal into the first node under the control of a setting control signal provided by the setting control terminal;

[0019] The compensation control circuit is electrically connected to the compensation control terminal, the second node, and the second end of the first driving circuit respectively, and is configured to control the connection or disconnection between the second node and the second end of the first driving circuit under the control of a compensation control signal provided by the compensation control terminal.

[0020] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a light emission control circuit;

[0021] The light emission control circuit is electrically connected to the light emission control terminal, the second end of the first driving circuit, and the first pole of the light emitting element respectively, and is configured to control the connection or disconnection between the second end of the first driving circuit and the first pole of the light emitting element under the control of a light emission control signal provided by the light emission control terminal;

[0022] The second pole of the light emitting element is electrically connected to the first voltage terminal.

[0023] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a reset circuit;

[0024] The reset circuit is electrically connected to the reset control terminal, the reset voltage terminal, and the first pole of the light emitting element respectively, and is configured to write a reset voltage provided by the reset voltage terminal into the first pole of the light emitting element under the control of a reset control signal provided by the reset control terminal;

[0025] The second pole of the light emitting element is electrically connected to the first voltage terminal.

[0026] Optionally, the first driving control circuit includes a first transistor, the second driving control circuit includes a second transistor, the first driving circuit includes a first driving transistor, and the second driving circuit includes a second driving transistor; the control electrode of the first transistor is electrically connected to the third node, the first pole of the first transistor is electrically connected to the second node, and the second pole of the first transistor is electrically connected to the control terminal of the first driving circuit;

[0027] The control electrode of the second transistor is electrically connected to the fourth node, the first pole of the second transistor is electrically connected to the second node, and the second pole of the second transistor is electrically connected to the control terminal of the second driving circuit;

[0028] The control electrode of the first driving transistor is electrically connected to the control terminal of the first driving circuit, the first pole of the first driving transistor is electrically connected to the first end of the first driving circuit, and the second pole of the first driving transistor is electrically connected to the second end of the first driving circuit;

[0029] The control electrode of the second driving transistor is electrically connected to the control terminal of the second driving circuit, the first electrode of the second driving transistor is electrically connected to the first terminal of the second driving circuit, and the second electrode of the second driving transistor is electrically connected to the second terminal of the second driving circuit.

[0030] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0031] The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the second node;

[0032] The first terminal of the second capacitor is electrically connected to the third node, and the second terminal of the second capacitor is electrically connected to the first terminal of the first driving circuit.

[0033] Optionally, the first control data voltage writing circuit includes a third transistor;

[0034] The control electrode of the third transistor is electrically connected to the first writing control terminal, the first electrode of the third transistor is electrically connected to the first control data voltage writing terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0035] Optionally, the third energy storage circuit includes a third capacitor, and the second control data voltage writing circuit includes a fourth transistor;

[0036] The first terminal of the third capacitor is electrically connected to the first terminal of the first driving circuit, and the second terminal of the third capacitor is electrically connected to the control terminal of the second driving control circuit;

[0037] The control electrode of the fourth transistor is electrically connected to the second writing control terminal, the first electrode of the fourth transistor is electrically connected to the second control data voltage writing terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0038] Optionally, the data writing circuit includes a fifth transistor; the setting circuit includes a sixth transistor; the compensation control circuit includes a seventh transistor;

[0039] The control electrode of the fifth transistor is electrically connected to the third writing control terminal, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the first node;

[0040] The control electrode of the sixth transistor is electrically connected to the setting control terminal, the first electrode of the sixth transistor is electrically connected to the setting voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first node;

[0041] The control electrode of the seventh transistor is electrically connected to the compensation control terminal, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second terminal of the first driving circuit.

[0042] Optionally, the light-emitting control circuit includes an eighth transistor;

[0043] The control electrode of the eighth transistor is electrically connected to the light-emitting control terminal, the first electrode of the eighth transistor is electrically connected to the second terminal of the first driving circuit, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light-emitting element.

[0044] Optionally, the reset circuit includes a ninth transistor;

[0045] The control electrode of the ninth transistor is electrically connected to the reset control terminal, the first electrode of the ninth transistor is electrically connected to the reset voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first electrode of the light-emitting element.

[0046] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above pixel circuit. The driving method includes:

[0047] The first driving control circuit controls the connection or disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node;

[0048] The second driving control circuit controls the connection or disconnection between the second node and the control terminal of the second driving circuit under the control of the potential of the fourth node;

[0049] The first control data voltage writing circuit controls the writing of the first control data voltage provided by the first control data voltage writing terminal into the third node under the control of the first writing control signal;

[0050] The first driving circuit drives the light-emitting element under the control of the potential of its control terminal; the second driving circuit drives the light-emitting element under the control of the potential of its control terminal.

[0051] Optionally, the third node and the fourth node are the same node; the pixel circuit further includes a data writing circuit, a setting circuit, a compensation control circuit, a light-emitting control circuit, and a reset circuit; the display period includes a first stage, a second stage, and a third stage set in sequence; the driving method includes:

[0052] In the first stage, under the control of a reset control signal, the reset circuit writes a reset voltage provided by a reset voltage terminal to a first electrode of a light-emitting element. The light-emitting control circuit controls, under the control of a light-emitting control signal, the connection between a second terminal of a first driving circuit and the first electrode of the light-emitting element. The compensation control circuit controls, under the control of a compensation control signal, the connection between a second node and the second terminal of the first driving circuit to write the reset voltage to the second node. The setting circuit writes a setting voltage provided by a setting voltage terminal to a first node under the control of a setting control signal.

[0053] In the second stage, under the control of a third writing control signal, a data writing circuit writes a data voltage provided by a data line to the first node. The reset circuit writes a reset voltage provided by a reset voltage terminal to a first electrode of the light-emitting element under the control of a reset control signal. The light-emitting control circuit controls, under the control of a light-emitting control signal, the connection between a second terminal of a first driving circuit and the first electrode of the light-emitting element. The compensation control circuit controls, under the control of a compensation control signal, the connection between a second node and the second terminal of the first driving circuit. A first control data voltage writing circuit controls, under the control of a first writing control signal, the writing of a first control data voltage provided by a first control data voltage terminal to a third node. The first driving control circuit controls the connection or disconnection between the second node and a control terminal of the first driving circuit under the control of the potential of the third node. The second driving control circuit controls the connection or disconnection between the second node and a control terminal of the second driving circuit under the control of the potential of the third node.

[0054] In the third stage, the setting circuit writes a setting voltage provided by a setting voltage terminal to the first node under the control of a setting control signal. The light-emitting control circuit controls, under the control of a light-emitting control signal, the connection between a second terminal of a first driving circuit and the first electrode of the light-emitting element, and the first driving circuit or the second driving circuit drives the light-emitting element to emit light.

[0055] Optionally, in the second stage, the step in which the first driving control circuit controls the connection or disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node includes:

[0056] When the first control data voltage is a second voltage signal, the first driving control circuit controls the connection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node.

[0057] When the first control data voltage is a third voltage signal, the first driving control circuit controls the disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node.

[0058] In the second stage, the step of the second driving control circuit controlling the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the third node includes:

[0059] When the first control data voltage is the second voltage signal, the second driving control circuit controls the disconnection between the second node and the control end of the second driving circuit under the control of the potential of the third node;

[0060] When the first control data voltage is the third voltage signal, the second driving control circuit controls the connection between the second node and the control end of the second driving circuit under the control of the potential of the third node;

[0061] The step of the first driving circuit or the second driving circuit driving the light-emitting element to emit light includes:

[0062] When in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit under the control of the potential of the third node, in the third stage, the first driving circuit drives the light-emitting element to emit light;

[0063] When in the second stage, the second driving control circuit controls the connection between the second node and the control end of the second driving circuit under the control of the potential of the third node, in the third stage, the second driving circuit drives the light-emitting element to emit light.

[0064] Optionally, the pixel circuit further includes a third energy storage circuit and a second control data voltage writing circuit; the pixel circuit further includes a data writing circuit, a setting circuit, a compensation control circuit, a light-emitting control circuit, and a reset circuit; the display cycle includes a first stage, a second stage, and a third stage set in sequence; the driving method includes:

[0065] In the first stage, the reset circuit writes the reset voltage provided by the reset voltage terminal to the first pole of the light-emitting element under the control of the reset control signal, the light-emitting control circuit controls the connection between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the compensation control circuit controls the connection between the second node and the second end of the first driving circuit under the control of the compensation control signal to write the reset voltage to the second node; the setting circuit writes the setting voltage provided by the setting voltage terminal to the first node under the control of the setting control signal;

[0066] In the second stage, the data writing circuit writes the data voltage provided by the data line to the first node under the control of the third writing control signal. The reset circuit writes the reset voltage provided by the reset voltage terminal to the first pole of the light-emitting element under the control of the reset control signal. The light-emitting control circuit controls the connection between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal. The compensation control circuit controls the connection between the second node and the second end of the first driving circuit under the control of the compensation control signal. The first control data voltage writing circuit controls the writing of the first control data voltage provided by the first control data voltage writing terminal to the third node under the control of the first writing control signal. The second control data voltage writing circuit writes the second control data voltage provided by the second control data voltage writing terminal to the fourth node under the control of the second writing control signal. The first driving control circuit controls the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node. The second driving control circuit controls the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node.

[0067] In the third stage, the setting circuit writes the setting voltage provided by the setting voltage terminal to the first node under the control of the setting control signal. The light-emitting control circuit controls the connection between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal, and the first driving circuit and / or the second driving circuit drives the light-emitting element to emit light.

[0068] Optionally, in the second stage, the step of the first driving control circuit controlling the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node includes:

[0069] When the first control data voltage is the fourth voltage signal, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit.

[0070] When the first control data voltage is the fifth voltage signal, the first driving control circuit controls the disconnection between the second node and the control end of the first driving circuit.

[0071] In the second stage, the step of the second driving control circuit controlling the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node includes:

[0072] When the second control data voltage is the sixth voltage signal, the second driving control circuit controls the connection between the second node and the control end of the second driving circuit.

[0073] When the second control data voltage is the seventh voltage signal, the second driving control circuit controls the disconnection between the second node and the control end of the second driving circuit;

[0074] The step of driving the light-emitting element by the first driving circuit and / or the second driving circuit includes: when, in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the disconnection between the second node and the control end of the second driving circuit, the first driving circuit drives the light-emitting element to emit light under the control of the potential at its control end;

[0075] When, in the second stage, the first driving control circuit controls the disconnection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the connection between the second node and the control end of the second driving circuit, the second driving circuit drives the light-emitting element to emit light under the control of the potential at its control end;

[0076] When, in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the connection between the second node and the control end of the second driving circuit, the first driving circuit and the second driving circuit jointly drive the light-emitting element to emit light respectively under the control of the potentials at the corresponding control ends.

[0077] In a third aspect, an embodiment of the present disclosure provides a display device, including the above-mentioned pixel circuit. Description of the Drawings

[0078] Figure 1 is a structural diagram of the pixel circuit according to an embodiment of the present disclosure;

[0079] Figure 2 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0080] Figure 3 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0081] Figure 4 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0082] Figure 5 is a structural diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0083] Figure 6 is a circuit diagram of the pixel circuit according to at least one embodiment of the present disclosure;

[0084] Figure 7 is as in the present disclosure Figure 6The working timing diagram of at least one embodiment of the pixel circuit shown;

[0085] Figure 8A This is the disclosure as Figure 6 A schematic diagram of the working state of at least one embodiment of the pixel circuit shown in the first stage S1;

[0086] Figure 8B This is the disclosure as Figure 6 A schematic diagram of the working state of at least one embodiment of the pixel circuit shown in the second stage S2;

[0087] Figure 8C This is the disclosure as Figure 6 A schematic diagram of the working state of at least one embodiment of the pixel circuit shown in the third stage S3;

[0088] Figure 9A The waveform diagram of the current I flowing through the organic light-emitting diode O1 during high gray-scale display

[0089] Figure 9B The waveform diagram of the current I flowing through the organic light-emitting diode O1 during low gray-scale display;

[0090] Figure 10 This is the circuit diagram of the pixel circuit according to at least one embodiment of the disclosure;

[0091] Figure 11 This is the disclosure as Figure 10 The working timing diagram of at least one embodiment of the pixel circuit shown;

[0092] Figure 12A This is the disclosure as Figure 10 A schematic diagram of the working state of at least one embodiment of the pixel circuit shown in the first stage S1;

[0093] Figure 12B This is the disclosure as Figure 10 A schematic diagram of the working state of at least one embodiment of the pixel circuit shown in the second stage S2;

[0094] Figure 12C This is the disclosure as Figure 10 A schematic diagram of the working state of at least one embodiment of the pixel circuit shown in the third stage S3. Detailed implementation manners

[0095] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.

[0096] All the transistors used in all embodiments of the present disclosure may be triodes, thin-film transistors or field-effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the control pole, one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0097] During actual operation, when the transistor is a triode, the control pole may be the base, the first pole may be the collector, and the second pole may be the emitter; alternatively, the control pole may be the base, the first pole may be the emitter, and the second pole may be the collector.

[0098] During actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control pole may be the gate, the first pole may be the drain, and the second pole may be the source; alternatively, the control pole may be the gate, the first pole may be the source, and the second pole may be the drain.

[0099] As Figure 1 shown, the pixel circuit described in the embodiments of the present disclosure includes a light-emitting element E0, a first energy storage circuit 11, a first driving circuit 12, a second driving circuit 13, a first driving control circuit 14, a second driving control circuit 15, a second energy storage circuit 16, and a first control data voltage writing circuit 17;

[0100] The first end of the first energy storage circuit 11 is electrically connected to the first node c, the second end of the first energy storage circuit 11 is electrically connected to the second node b, and the first energy storage circuit 11 is used for storing electrical energy;

[0101] The control end of the first driving control circuit 14 is electrically connected to the third node a; the control end of the second driving control circuit 15 is electrically connected to the fourth node d;

[0102] The first driving control circuit 14 is further electrically connected to the second node b and the control end of the first driving circuit 12 respectively, and is used for controlling the connection or disconnection between the second node b and the control end of the first driving circuit 12 under the control of the potential of the third node a;

[0103] The second driving control circuit 15 is further electrically connected to the second node b and the control end of the second driving circuit 13 respectively, and is used for controlling the connection or disconnection between the second node b and the control end of the second driving circuit 13 under the control of the potential of the fourth node d;

[0104] The first end of the second energy storage circuit 16 is electrically connected to the third node a, the second end of the second energy storage circuit 16 is electrically connected to the first end of the first driving circuit 12, and the second energy storage circuit 16 is used for storing electrical energy;

[0105] The first control data voltage writing circuit 17 is electrically connected to the first writing control terminal G1, the first control data voltage writing terminal D1, and the third node a respectively, and is configured to control the writing of the first control data voltage Vdata1 provided by the first control data voltage writing terminal D1 into the third node a under the control of the first writing control signal provided by the first writing control terminal G1;

[0106] The first end of the first driving circuit 12 and the first end of the second driving circuit 13 are both electrically connected to the power supply voltage terminal ELVDD, the second end of the first driving circuit 12 and the second end of the second driving circuit 13 are both electrically connected to the light-emitting element E0, the first driving circuit 12 is configured to drive the light-emitting element E0 under the control of the potential of its control terminal, and the second driving circuit 13 is configured to drive the light-emitting element E0 under the control of the potential of its control terminal.

[0107] In a specific implementation, the power supply voltage terminal ELVDD is configured to provide a power supply voltage Vdd.

[0108] When the pixel circuit according to the embodiment of the present disclosure is operating, when displaying a low gray level, the first driving circuit 12 is used to drive the light-emitting element E0 to emit light, and when displaying a high gray level, the second driving circuit 13 is used to drive the light-emitting element E0 to emit light; alternatively, when displaying a low gray level, the first driving circuit 12 is used to drive the light-emitting element E0 to emit light, and when displaying a medium gray level, the second driving circuit 13 is used to drive the light-emitting element E0 to emit light; when displaying a high gray level, the first driving circuit 12 and the second driving circuit 13 are used to jointly drive the light-emitting element E0 to emit light;

[0109] The subthreshold swing of the first driving transistor included in the first driving circuit 12 is the same as the SS swing of the second driving transistor included in the second driving circuit 13, and a common data voltage value range can be shared.

[0110] In at least one embodiment of the present disclosure, the width-to-length ratio of the first driving transistor is different from the width-to-length ratio of the second driving transistor, and the width-to-length ratio of the second driving transistor is greater than the width-to-length ratio of the first driving transistor. For example, the width-to-length ratio of the second driving transistor can be twice the width-to-length ratio of the first driving transistor, but not limited thereto.

[0111] The pixel circuit according to the embodiment of the present disclosure can be used for multi-gray-level display, realizing an ultra-conventional 256 gray-level display, and can increase the number of display gray levels without significantly increasing the cost.

[0112] In at least one embodiment of the present disclosure, the third node and the fourth node can be the same node.

[0113] As Figure 2 shown, based on the embodiment of the pixel circuit shown in Figure 1 the third node and the fourth node may be the same node;

[0114] The control end of the second driving control circuit 15 is electrically connected to the third node a, and is configured to control the connection or disconnection between the second node b and the control end of the second driving circuit 13 under the control of the potential of the third node a.

[0115] As Figure 3 shown, based on the embodiment of the pixel circuit shown in Figure 1 the pixel circuit according to at least one embodiment of the present disclosure may further include a third energy storage circuit 31 and a second control data voltage writing circuit 32;

[0116] The first end of the third energy storage circuit 31 is electrically connected to the first end of the first driving circuit 12, the second end of the third energy storage circuit 31 is electrically connected to the control end of the second driving control circuit 15, and the third energy storage circuit 31 is configured to store electrical energy;

[0117] The second control data voltage writing circuit 32 is respectively electrically connected to the second writing control end G2, the second control data voltage writing end D2 and the fourth node d, and is configured to write the second control data voltage Vdata2 provided by the second control data voltage writing end D2 into the fourth node d under the control of the second writing control signal provided by the second writing control end G2.

[0118] In at least one embodiment of the present disclosure, the first writing control end and the second writing control end may be the same writing control end, but not limited thereto.

[0119] In at least one embodiment of the present disclosure, the pixel circuit further includes a data writing circuit, a setting circuit and a compensation control circuit;

[0120] The data writing circuit is respectively electrically connected to the data line, the third writing control end and the first node, and is configured to write the data voltage provided by the data line into the first node under the control of the third writing control signal provided by the third writing control end, so as to perform data voltage writing;

[0121] The setting circuit is respectively electrically connected to the setting control end, the setting voltage end and the first node, and is configured to write the setting voltage provided by the setting voltage end into the first node under the control of the setting control signal provided by the setting control end, so as to set the potential of the first node;

[0122] The compensation control circuit is electrically connected to the compensation control terminal, the second node, and the second terminal of the first driving circuit respectively, and is configured to control the connection or disconnection between the second node and the second terminal of the first driving circuit under the control of a compensation control signal provided by the compensation control terminal.

[0123] In at least one embodiment of the present disclosure, the first write control terminal, the second write control terminal, and the third write control terminal may be the same write control terminal, but not limited thereto.

[0124] The pixel circuit according to at least one embodiment of the present disclosure further includes a light emission control circuit;

[0125] The light emission control circuit is electrically connected to the light emission control terminal, the second terminal of the first driving circuit, and the first electrode of the light emitting element respectively, and is configured to control the connection or disconnection between the second terminal of the first driving circuit and the first electrode of the light emitting element under the control of a light emission control signal provided by the light emission control terminal, so as to perform light emission control;

[0126] The second electrode of the light emitting element is electrically connected to the first voltage terminal.

[0127] The pixel circuit according to at least one embodiment of the present disclosure further includes a reset circuit;

[0128] The reset circuit is electrically connected to the reset control terminal, the reset voltage terminal, and the first electrode of the light emitting element respectively, and is configured to write the reset voltage provided by the reset voltage terminal into the first electrode of the light emitting element under the control of a reset control signal provided by the reset control terminal, so as to reset the potential of the first electrode of the light emitting element;

[0129] The second electrode of the light emitting element is electrically connected to the first voltage terminal.

[0130] As Figure 4 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 2 the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 41, a setting circuit 42, a compensation control circuit 43, a light emission control circuit 44, and a reset circuit 45;

[0131] The data writing circuit 41 is electrically connected to the data line D0, the third write control terminal G3, and the first node c respectively, and is configured to write the data voltage provided by the data line D0 into the first node c under the control of a third write control signal provided by the third write control terminal G3;

[0132] The setting circuit 42 is electrically connected to the setting control terminal Z1, the setting voltage terminal Vz, and the first node c respectively, and is configured to write the setting voltage provided by the setting voltage terminal Vz into the first node c under the control of the setting control signal provided by the setting control terminal Z1;

[0133] The compensation control circuit 43 is electrically connected to the compensation control terminal R0, the second node b, and the second terminal of the first driving circuit 12 respectively, and is configured to control the connection or disconnection between the second node b and the second terminal of the first driving circuit 12 under the control of the compensation control signal provided by the compensation control terminal R0;

[0134] The light-emitting control circuit 44 is electrically connected to the light-emitting control terminal E1, the second terminal of the first driving circuit 12, and the first pole of the light-emitting element E0 respectively, and is configured to control the connection or disconnection between the second terminal of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal provided by the light-emitting control terminal E1;

[0135] The second pole of the light-emitting element E0 is electrically connected to the first voltage terminal V1;

[0136] The reset circuit 45 is electrically connected to the reset control terminal R1, the reset voltage terminal Vr, and the first pole of the light-emitting element E0 respectively, and is configured to write the reset voltage provided by the reset voltage terminal Vr into the first pole of the light-emitting element under the control of the reset control signal provided by the reset control terminal R1.

[0137] In at least one embodiment of the present disclosure, the setting control terminal may be the light-emitting control terminal, the setting voltage terminal may be the first voltage terminal, the compensation control terminal R0 and the reset control terminal R1 may be the same control terminal, and the reset voltage terminal Vr may be the first voltage terminal, but not limited thereto.

[0138] As described in the present disclosure Figure 4 When at least one embodiment of the pixel circuit shown works, the display period includes a first stage, a second stage, and a third stage set successively; the driving method includes:

[0139] In the first stage, under the control of the reset control signal, the reset circuit 45 writes the reset voltage provided by the reset voltage terminal Vr to the first pole of the light-emitting element E0 to control the light-emitting element E0 not to emit light and clear the residual charge at the first pole of the light-emitting element E0; the light-emitting control circuit 44 controls the connection between the second terminal of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the compensation control circuit 43 controls the connection between the second node b and the second terminal of the first driving circuit 12 under the control of the compensation control signal to write the reset voltage to the second node b; the setting circuit 42 writes the setting voltage provided by the setting voltage terminal Vz to the first node c under the control of the setting control signal; optionally, the reset voltage and the setting voltage may be equal, for example, they may both be the low voltage Vss provided by the low voltage terminal.

[0140] In the second stage, under the control of the third write control signal, the data write circuit 41 writes the data voltage Vdata0 provided by the data line D0 to the first node c. The reset circuit 45 writes the reset voltage provided by the reset voltage terminal Vr to the first pole of the light-emitting element under the control of the reset control signal. The light-emitting control circuit 44 controls the connection between the second terminal of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the compensation control circuit 43 controls the connection between the second node b and the second terminal of the first driving circuit 12 under the control of the compensation control signal. The first control data voltage write circuit 17 controls the writing of the first control data voltage Vdata1 provided by the first control data voltage write terminal D1 to the third node a under the control of the first write control signal; the first drive control circuit 14 controls the connection or disconnection between the second node b and the control terminal of the first driving circuit 12 under the control of the potential of the third node a; the second drive control circuit 15 controls the connection or disconnection between the second node b and the control terminal of the second driving circuit 13 under the control of the potential of the third node a.

[0141] In the third stage, the setting circuit 42 writes the setting voltage provided by the setting voltage terminal Vz to the first node c under the control of the setting control signal; the light-emitting control circuit 44 controls the connection between the second terminal of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal, and the first driving circuit 12 or the second driving circuit 13 drives the light-emitting element E0 to emit light.

[0142] As described in this disclosure Figure 4 When at least one embodiment of the pixel circuit shown operates, in the second stage,

[0143] When the first control data voltage Vdata1 is a second voltage signal, the first driving control circuit 14 controls the connection between the second node b and the control end of the first driving circuit 12 under the control of the potential of the third node a;

[0144] When the first control data voltage Vdata1 is a third voltage signal, the first driving control circuit 14 controls the disconnection between the second node b and the control end of the first driving circuit 12 under the control of the potential of the third node a;

[0145] When the first control data voltage Vdata1 is a second voltage signal, the second driving control circuit 15 controls the disconnection between the second node b and the control end of the second driving circuit 13 under the control of the potential of the third node a;

[0146] When the first control data voltage Vdata1 is a third voltage signal, the second driving control circuit 15 controls the connection between the second node b and the control end of the second driving circuit 13 under the control of the potential of the third node a;

[0147] When in the second stage, when the first driving control circuit 14 controls the connection between the second node b and the control end of the first driving circuit 12 under the control of the potential of the third node a, in the third stage, the first driving circuit 12 drives the light-emitting element E0 to emit light;

[0148] When in the second stage, when the second driving control circuit 15 controls the connection between the second node b and the control end of the second driving circuit 13 under the control of the potential of the third node, in the third stage, the second driving circuit 13 drives the light-emitting element E0 to emit light.

[0149] In at least one embodiment of the present disclosure, the second voltage signal may be a high voltage signal, and the third voltage signal may be a low voltage signal, but it is not limited thereto.

[0150] As Figure 5 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 3 at least one embodiment of the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit 41, a setting circuit 42, a compensation control circuit 43, a light-emitting control circuit 44, and a reset circuit 45;

[0151] The data writing circuit is electrically connected to the data line D0, the third writing control end G3, and the first node c respectively, and is used to write the data voltage provided by the data line D0 into the first node c under the control of the third writing control signal provided by the third writing control end G3;

[0152] The setting circuit 42 is electrically connected to the setting control terminal Z1, the setting voltage terminal Vz, and the first node c respectively, and is configured to write the setting voltage provided by the setting voltage terminal Vz to the first node c under the control of the setting control signal provided by the setting control terminal Z1;

[0153] The compensation control circuit 43 is electrically connected to the compensation control terminal R0, the second node b, and the second end of the first driving circuit 12 respectively, and is configured to control the connection or disconnection between the second node b and the second end of the first driving circuit 12 under the control of the compensation control signal provided by the compensation control terminal R0;

[0154] The light-emitting control circuit 44 is electrically connected to the light-emitting control terminal E1, the second end of the first driving circuit 12, and the first pole of the light-emitting element E0 respectively, and is configured to control the connection or disconnection between the second end of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal provided by the light-emitting control terminal E1;

[0155] The second pole of the light-emitting element E0 is electrically connected to the first voltage terminal V1;

[0156] The reset circuit 45 is electrically connected to the reset control terminal R1, the reset voltage terminal Vr, and the first pole of the light-emitting element E0 respectively, and is configured to write the reset voltage provided by the reset voltage terminal Vr to the first pole of the light-emitting element under the control of the reset control signal provided by the reset control terminal R1.

[0157] In at least one embodiment of the present disclosure, the setting control terminal may be the light-emitting control terminal, the setting voltage terminal may be the first voltage terminal, the compensation control terminal R0 and the reset control terminal R1 may be the same control terminal, and the reset voltage terminal Vr may be the first voltage terminal, but not limited thereto.

[0158] The present disclosure Figure 5 When at least one embodiment of the pixel circuit shown in the present disclosure is working, the display period may include a first stage, a second stage, and a third stage set in sequence;

[0159] In the first stage, the reset circuit 45 writes the reset voltage provided by the reset voltage terminal Vr to the first pole of the light-emitting element E0 under the control of the reset control signal, and the light-emitting control circuit 44 controls the connection between the second end of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal; the compensation control circuit 43 controls the connection between the second node b and the second end of the first driving circuit 12 under the control of the compensation control signal to write the reset voltage to the second node b; the setting circuit 42 writes the setting voltage provided by the setting voltage terminal Vz to the first node c under the control of the setting control signal;

[0160] In the second stage, the data writing circuit 41 writes the data voltage Vdata0 provided by the data line D0 into the first node c under the control of the third writing control signal. The reset circuit 45 writes the reset voltage provided by the reset voltage terminal Vr into the first pole of the light-emitting element E0 under the control of the reset control signal. The light-emitting control circuit 44 controls the connection between the second end of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal. The compensation control circuit 43 controls the connection between the second node b and the second end of the first driving circuit 12 under the control of the compensation control signal. The first control data voltage writing circuit 17 controls the writing of the first control data voltage Vdata1 provided by the first control data voltage writing terminal D1 into the third node a under the control of the first writing control signal. The second control data voltage writing circuit 32 writes the second control data voltage Vdata2 provided by the second control data voltage writing terminal D2 into the fourth node d under the control of the second writing control signal. The first driving control circuit 14 controls the connection or disconnection between the second node b and the control end of the first driving circuit 12 under the control of the potential of the third node a. The second driving control circuit 15 controls the connection or disconnection between the second node b and the control end of the second driving circuit 13 under the control of the potential of the fourth node d.

[0161] In the third stage, the setting circuit 42 writes the setting voltage provided by the setting voltage terminal Vz into the first node c under the control of the setting control signal. The light-emitting control circuit 44 controls the connection between the second end of the first driving circuit 12 and the first pole of the light-emitting element E0 under the control of the light-emitting control signal, and the first driving circuit 12 and / or the second driving circuit 13 drives the light-emitting element E0 to emit light.

[0162] The present disclosure Figure 5 When at least one embodiment of the pixel circuit shown in the present disclosure is operating, in the second stage, when the first control data voltage is the fourth voltage signal, the first driving control circuit 14 controls the connection between the second node b and the control end of the first driving circuit 12.

[0163] When the first control data voltage is the fifth voltage signal, the first driving control circuit 14 controls the disconnection between the second node b and the control end of the first driving circuit 12.

[0164] In the second stage, when the second control data voltage is the sixth voltage signal, the second driving control circuit 15 controls the connection between the second node b and the control end of the second driving circuit 13.

[0165] When the second control data voltage is the seventh voltage signal, the second driving control circuit 15 controls the disconnection between the second node b and the control end of the second driving circuit 13;

[0166] When in the second stage, the first driving control circuit 14 controls the connection between the second node b and the control end of the first driving circuit 12, and the second driving control circuit 15 controls the disconnection between the second node b and the control end of the second driving circuit 13, the first driving circuit 12 drives the light-emitting element to emit light under the control of the potential at its control end;

[0167] When in the second stage, the first driving control circuit 14 controls the disconnection between the second node b and the control end of the first driving circuit 12, and the second driving control circuit 15 controls the connection between the second node b and the control end of the second driving circuit 13, the second driving circuit 13 drives the light-emitting element E0 to emit light under the control of the potential at its control end;

[0168] When in the second stage, the first driving control circuit 14 controls the connection between the second node b and the control end of the first driving circuit 12, and the second driving control circuit 15 controls the connection between the second node b and the control end of the second driving circuit 13, the first driving circuit 12 and the second driving circuit 13 respectively drive the light-emitting element E0 to emit light under the control of the potentials at the corresponding control ends.

[0169] In at least one embodiment of the present disclosure, the fourth voltage signal and the sixth voltage signal may be low voltage signals, and the fifth voltage signal and the seventh voltage signal may be high voltage signals, but not limited thereto.

[0170] Optionally, the first driving control circuit includes a first transistor, the second driving control circuit includes a second transistor, the first driving circuit includes a first driving transistor, and the second driving circuit includes a second driving transistor; the control electrode of the first transistor is electrically connected to the third node, the first pole of the first transistor is electrically connected to the second node, and the second pole of the first transistor is electrically connected to the control end of the first driving circuit;

[0171] The control electrode of the second transistor is electrically connected to the fourth node, the first pole of the second transistor is electrically connected to the second node, and the second pole of the second transistor is electrically connected to the control end of the second driving circuit;

[0172] The control electrode of the first driving transistor is electrically connected to the control end of the first driving circuit, the first pole of the first driving transistor is electrically connected to the first end of the first driving circuit, and the second pole of the first driving transistor is electrically connected to the second end of the first driving circuit;

[0173] The control electrode of the second driving transistor is electrically connected to the control terminal of the second driving circuit, the first electrode of the second driving transistor is electrically connected to the first terminal of the second driving circuit, and the second electrode of the second driving transistor is electrically connected to the second terminal of the second driving circuit.

[0174] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0175] The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the second node;

[0176] The first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the first end of the first driving circuit.

[0177] Optionally, the first control data voltage writing circuit includes a third transistor;

[0178] The control electrode of the third transistor is electrically connected to the first writing control terminal, the first electrode of the third transistor is electrically connected to the first control data voltage writing terminal, and the second electrode of the third transistor is electrically connected to the third node.

[0179] Optionally, the third energy storage circuit includes a third capacitor, and the second control data voltage writing circuit includes a fourth transistor;

[0180] The first end of the third capacitor is electrically connected to the first end of the first driving circuit, and the second end of the third capacitor is electrically connected to the control terminal of the second driving control circuit;

[0181] The control electrode of the fourth transistor is electrically connected to the second writing control terminal, the first electrode of the fourth transistor is electrically connected to the second control data voltage writing terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

[0182] Optionally, the data writing circuit includes a fifth transistor; the setting circuit includes a sixth transistor; the compensation control circuit includes a seventh transistor;

[0183] The control electrode of the fifth transistor is electrically connected to the third writing control terminal, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the first node;

[0184] The control electrode of the sixth transistor is electrically connected to the setting control terminal, the first electrode of the sixth transistor is electrically connected to the setting voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first node;

[0185] The control electrode of the seventh transistor is electrically connected to the compensation control terminal, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second end of the first driving circuit.

[0186] Optionally, the light emitting control circuit includes an eighth transistor;

[0187] The control electrode of the eighth transistor is electrically connected to the light emitting control terminal, the first electrode of the eighth transistor is electrically connected to the second end of the first driving circuit, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.

[0188] Optionally, the reset circuit includes a ninth transistor;

[0189] The control electrode of the ninth transistor is electrically connected to the reset control terminal, the first electrode of the ninth transistor is electrically connected to the reset voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element.

[0190] As Figure 6 shown, based on at least one embodiment of the pixel circuit shown in Figure 4 shown, the light emitting element is an organic light emitting diode O1;

[0191] The first driving control circuit 14 includes a first transistor T1, the second driving control circuit 15 includes a second transistor T2, the first driving circuit 12 includes a first driving transistor T01, and the second driving circuit 13 includes a second driving transistor T02;

[0192] The gate of the first transistor T1 is electrically connected to the third node a, the source of the first transistor T1 is electrically connected to the second node b, and the drain of the first transistor T1 is electrically connected to the gate of the first driving transistor T01;

[0193] The gate of the second transistor T2 is electrically connected to the third node a, the source of the second transistor T2 is electrically connected to the second node b, and the drain of the second transistor T2 is electrically connected to the gate of the second driving transistor T02;

[0194] The first energy storage circuit 11 includes a first capacitor C1, and the second energy storage circuit 16 includes a second capacitor C2;

[0195] The first end of the first capacitor C1 is electrically connected to the first node c, and the second end of the first capacitor C1 is electrically connected to the second node b;

[0196] The first terminal of the second capacitor C2 is electrically connected to the third node a, and the second terminal of the second capacitor C2 is electrically connected to the source of the first driving transistor T01;

[0197] The sources of the first driving transistor T01 and the second driving transistor T02 are both electrically connected to the power supply voltage terminal ELVDD; the power supply voltage terminal ELVDD is used to provide the power supply voltage Vdd;

[0198] The drain of the second driving transistor T02 is electrically connected to the second node b;

[0199] The first control data voltage writing circuit 17 includes a third transistor T3;

[0200] The gate of the third transistor T3 is electrically connected to the first writing control terminal G1, the source of the third transistor T3 is electrically connected to the first control data voltage writing terminal D1, and the drain of the third transistor T3 is electrically connected to the third node a;

[0201] The data writing circuit 41 includes a fifth transistor T5; the setting circuit 42 includes a sixth transistor T6; the compensation control circuit 43 includes a seventh transistor T7;

[0202] The gate of the fifth transistor T5 is electrically connected to the first writing control terminal G1, the source of the fifth transistor T5 is electrically connected to the data line D0, and the drain of the fifth transistor T5 is electrically connected to the first node c;

[0203] The gate of the sixth transistor T6 is electrically connected to the light emission control terminal E1, the source of the sixth transistor T6 is electrically connected to the low voltage terminal VS, and the drain of the sixth transistor T6 is electrically connected to the first node c; the low voltage terminal VS is used to provide the low voltage Vss;

[0204] The gate of the seventh transistor T7 is electrically connected to the reset control terminal R1, the source of the seventh transistor T7 is electrically connected to the second node b, and the drain of the seventh transistor T7 is electrically connected to the drain of the first driving transistor T01;

[0205] The light emission control circuit 44 includes an eighth transistor T8;

[0206] The gate of the eighth transistor T8 is electrically connected to the light emission control terminal E1, the source of the eighth transistor T8 is electrically connected to the drain of the first driving transistor T01, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1;

[0207] The reset circuit 45 includes a ninth transistor T9;

[0208] The gate of the ninth transistor T9 is electrically connected to the reset control terminal R1, the first pole of the ninth transistor T9 is electrically connected to the low voltage terminal VS, and the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1.

[0209] In Figure 6 In at least one embodiment of the pixel circuit shown, the first write control terminal G1 and the third write control terminal are the same write control terminal; the set control terminal is the light emission control terminal E1; the compensation control terminal is the reset control terminal R1; the set voltage terminal is the low voltage terminal VS; the reset voltage terminal is the low voltage terminal VS; but not limited thereto.

[0210] In Figure 6 In at least one embodiment of the pixel circuit shown, T1 is an n-type transistor, and the transistors included in the pixel circuit other than T1 are p-type transistors, but not limited thereto.

[0211] In Figure 6 In at least one embodiment of the pixel circuit shown, the aspect ratio of T02 can be twice the aspect ratio of T01, but not limited thereto.

[0212] As Figure 7 As shown, when at least one embodiment of the pixel circuit of the present disclosure is in operation, the display period may include a first stage S1, a second stage S2, and a third stage S3 set successively; Figure 6

[0213] In the first stage S1, R1 provides a low voltage signal, E1 provides a low voltage signal, G1 provides a high voltage signal, as Figure 8A shown, T7 is turned on, and T6, T9, and T8 are all turned on to control the potential of the second node b to be VSS and the potential of the third node a to be VSS;

[0214] Figure 8B In the second stage S2, R1 provides a low voltage signal, E1 provides a high voltage signal, G1 provides a low voltage signal, as Figure 8B shown, T9, T7, T5, and T3 are all turned on, and D1 provides the first control data voltage Vdata1 to the third node a; D0 provides the data voltage Vdata0 to the first node c;

[0215] In the second stage S2, when Vdata1 is a low voltage signal, T2 is turned on and T1 is turned off; at the start of the second stage S2, T02 is turned on, and the power supply voltage Vdd charges C1 through T02 and T7 to raise the potential of the gate of T02 until T02 is turned off, at which time the gate potential of T02 becomes Vdd + Vth2, where Vth2 is the threshold voltage of T02;

[0216] In the second stage S2, when Vdata1 is a high-voltage signal, T1 is turned on and T2 is turned off; at the beginning of the second stage S2, T01 is turned on, and the power supply voltage Vdd charges C1 through T01 and T7 to increase the potential of the gate of T01 until T01 is turned off. At this time, the gate potential of T01 becomes Vdd + Vth1, where Vth1 is the threshold voltage of T01.

[0217] In the third stage S3, R1 provides a high-voltage signal, E1 provides a low-voltage signal, and G1 provides a high-voltage signal. As Figure 8C shown, T6 and T8 are turned on.

[0218] When in the second stage S2, Vdata1 is a low-voltage signal, in the third stage S3, the potential of the second node b becomes Vdd + Vth2 + Vss - Vdata0, and T02 drives O1 to emit light for high gray-scale display. At this time, the current I flowing through O1 is equal to K2×(Vdd + Vth2 + Vss - Vdata0 - Vdd - Vth2) 2 , I is equal to K2×(Vss - Vdata0) 2 ; K2 is the current coefficient of T02.

[0219] When in the second stage S2, Vdata1 is a high-voltage signal, in the third stage S3, the potential of the second node b becomes Vdd + Vth1 + Vss - Vdata0, and T01 drives O1 to emit light for low gray-scale display. At this time, the current I flowing through O1 is equal to K1×(Vdd + Vth1 + Vss - Vdata0 - Vdd - Vth1) 2 , I is equal to K1×(Vss - Vdata0) 2 ; K1 is the current coefficient of T01.

[0220] At least one embodiment of the pixel circuit of the present disclosure as Figure 6 shown can have a display gray scale of 0 - 255 when performing low gray-scale display, but is not limited thereto.

[0221] When in Figure 6 at least one embodiment of the pixel circuit shown, when the aspect ratio of T02 is 20um / 5um and the aspect ratio of T01 is 10um / 5um, Figure 9A is the waveform diagram of the current I flowing through O1 during high gray-scale display, Figure 9B is the waveform diagram of the current I flowing through O1 during low gray-scale display.

[0222] In Figure 9A and Figure 9B , the horizontal axis is time t with the unit of second, and the vertical axis is the current I flowing through O1 with the unit of A (ampere).

[0223] In at least one embodiment of the present disclosure, the current coefficient of the driving transistor is proportional to the aspect ratio of the driving transistor. When other parameters remain unchanged and the aspect ratio of the driving transistor is changed, the driving current generated by the driving transistor will also change.

[0224] As Figure 10 shown, based on at least one embodiment of the pixel circuit shown in Figure 5 the light-emitting element is an organic light-emitting diode O1;

[0225] The first driving control circuit 14 includes a first transistor T1, the second driving control circuit 15 includes a second transistor T2, the first driving circuit 12 includes a first driving transistor T01, and the second driving circuit 13 includes a second driving transistor T02;

[0226] The gate of the first transistor T1 is electrically connected to the third node a, the source of the first transistor T1 is electrically connected to the second node b, and the drain of the first transistor T1 is electrically connected to the gate of the first driving transistor T01;

[0227] The gate of the second transistor T2 is electrically connected to the third node a, the source of the second transistor T2 is electrically connected to the second node b, and the drain of the second transistor T2 is electrically connected to the gate of the second driving transistor T02;

[0228] The first energy storage circuit 11 includes a first capacitor C1, and the second energy storage circuit 16 includes a second capacitor C2;

[0229] The first end of the first capacitor C1 is electrically connected to the first node c, and the second end of the first capacitor C1 is electrically connected to the second node b;

[0230] The first end of the second capacitor C2 is electrically connected to the third node a, and the second end of the second capacitor C2 is electrically connected to the source of the first driving transistor T01;

[0231] The sources of the first driving transistor T01 and the second driving transistor T02 are both electrically connected to the power supply voltage terminal ELVDD; the power supply voltage terminal ELVDD is used to provide a power supply voltage Vdd;

[0232] The drain of the second driving transistor T02 is electrically connected to the second node b;

[0233] The third energy storage circuit 31 includes a third capacitor C3, and the second control data voltage writing circuit 32 includes a fourth transistor T4;

[0234] The first end of the third capacitor C3 is electrically connected to the source of the first driving transistor T01, and the second end of the third capacitor C3 is electrically connected to the gate of the second transistor T2;

[0235] The gate of the fourth transistor T4 is electrically connected to the first writing control terminal G1, the source of the fourth transistor T4 is electrically connected to the second control data voltage writing terminal D2, and the drain of the fourth transistor T4 is electrically connected to the fourth node d;

[0236] The first control data voltage writing circuit 17 includes a third transistor T3;

[0237] The gate of the third transistor T3 is electrically connected to the first writing control terminal G1, the source of the third transistor T3 is electrically connected to the first control data voltage writing terminal D1, and the drain of the third transistor T3 is electrically connected to the third node a;

[0238] The data writing circuit 41 includes a fifth transistor T5; the setting circuit 42 includes a sixth transistor T6; the compensation control circuit 43 includes a seventh transistor T7;

[0239] The gate of the fifth transistor T5 is electrically connected to the first writing control terminal G1, the source of the fifth transistor T5 is electrically connected to the data line D0, and the drain of the fifth transistor T5 is electrically connected to the first node c;

[0240] The gate of the sixth transistor T6 is electrically connected to the light emission control terminal E1, the source of the sixth transistor T6 is electrically connected to the low voltage terminal VS, and the drain of the sixth transistor T6 is electrically connected to the first node c; the low voltage terminal VS is used to provide a low voltage Vss;

[0241] The gate of the seventh transistor T7 is electrically connected to the reset control terminal R1, the source of the seventh transistor T7 is electrically connected to the second node b, and the drain of the seventh transistor T7 is electrically connected to the drain of the first driving transistor T01;

[0242] The light emission control circuit 44 includes an eighth transistor T8;

[0243] The gate of the eighth transistor T8 is electrically connected to the light emission control terminal E1, the source of the eighth transistor T8 is electrically connected to the drain of the first driving transistor T01, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1;

[0244] The reset circuit 45 includes a ninth transistor T9;

[0245] The gate of the ninth transistor T9 is electrically connected to the reset control terminal R1, the first pole of the ninth transistor T9 is electrically connected to the low voltage terminal VS, and the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1.

[0246] In Figure 10 In at least one embodiment of the pixel circuit shown, the first write control terminal G1, the second write control terminal, and the third write control terminal are all the same write control terminal; the set control terminal is the light emission control terminal E1; the compensation control terminal is the reset control terminal R1; the set voltage terminal is the low voltage terminal VS; the reset voltage terminal is the low voltage terminal VS; however, this is not limiting.

[0247] In Figure 10 In at least one embodiment of the pixel circuit shown, all transistors are p-type transistors; however, this is not limiting.

[0248] In Figure 10 In at least one embodiment of the pixel circuit shown, the threshold voltage of the first driving transistor T01 is equal to the threshold voltage of the second driving transistor T02, and the threshold voltages of T01 and T02 are both the threshold voltage Vth; however, this is not limiting.

[0249] In Figure 10 In at least one embodiment of the pixel circuit shown, the aspect ratio of T02 can be twice the aspect ratio of T01; however, this is not limiting.

[0250] As Figure 11 As shown, when at least one embodiment of the pixel circuit of the present disclosure is in operation, the display period may include a first stage S1, a second stage S2, and a third stage S3 that are set successively; Figure 10 In the first stage S1, R1 provides a low voltage signal, E1 provides a low voltage signal, G1 provides a high voltage signal, T7 is turned on, as

[0251] shown, T6, T9, and T8 are all turned on, the potential of the second node b is Vss, and the potential of the first node c is Vss; Figure 12A

[0252] In the second stage S2, R1 provides a low voltage signal, E1 provides a high voltage signal, G1 provides a low voltage signal, as Figure 12B shown, T9, T7, T5, and T3 are all turned on; D1 provides the first control data voltage Vdata1 to the third node a; D2 provides the second control data voltage Vdata2 to the fourth node d; D0 provides the data voltage Vdata0 to the first node c;

[0253] ​In the second stage S2, when Vdata1 is a low-voltage signal and Vdata2 is a high-voltage signal, T1 is turned on and T2 is turned off; at the start of the second stage S2, T01 is turned on, and the power supply voltage Vdd charges C1 through T01 and T7 to raise the potential of the gate of T01 until T01 is turned off. At this time, the gate potential of T01 becomes Vdd + Vth;

[0254] In the second stage S2, when Vdata1 is a high-voltage signal and Vdata2 is a low-voltage signal, T1 is turned off and T2 is turned on; at the start of the second stage S2, T02 is turned on, and the power supply voltage Vdd charges C1 through T02 and T7 to raise the potential of the gate of T02 until T02 is turned off. At this time, the gate potential of T02 becomes Vdd + Vth;

[0255] In the second stage S2, when Vdata1 is a low-voltage signal and Vdata2 is a low-voltage signal, T1 and T2 are turned on; at the start of the second stage S2, both T01 and T02 are turned on, and the power supply voltage Vdd charges C1 through T01, T02, and T7 to raise the potential of the gate of T01 and the potential of the gate of T02 until T01 and T02 are turned off. At this time, the gate potential of T01 and the gate potential of T02 are Vdd + Vth;

[0256] In the third stage S3, R1 provides a high-voltage signal, E1 provides a low-voltage signal, and G1 provides a high-voltage signal, as Figure 12C shown, T6 and T8 are turned on;

[0257] When in the second stage S2, Vdata1 is a low-voltage signal and Vdata2 is a high-voltage signal, in the third stage S3, the potential of the second node b becomes Vdd + Vth1 + Vss - Vdata0, and T01 drives O1 to emit light for low gray-scale display. At this time, the current I flowing through O1 is equal to K1×(Vdd + Vth + Vss - Vdata0 - Vdd - Vth) 2 , I is equal to K1×(Vss - Vdata0) 2 ; K1 is the current coefficient of T01;

[0258] When in the second stage S2, Vdata1 is a high-voltage signal and Vdata2 is a low-voltage signal, in the third stage S3, the potential of the second node b becomes Vdd + Vth1 + Vss - Vdata0, and T02 drives O1 to emit light for medium gray-scale display. At this time, the current I flowing through O1 is equal to K2×(Vdd + Vth + Vss - Vdata0 - Vdd - Vth) 2 , I is equal to K2×(Vss - Vdata0) 2 ; K2 is the current coefficient of T02;

[0259] When, in the second stage S2, Vdata1 is a low-voltage signal and Vdata2 is a low-voltage signal, in the third stage S3, the potential of the second node b becomes Vdd + Vth1 + Vss - Vdata0, and T01 and T01 jointly drive O1 to emit light for high gray-scale display. At this time, the current I flowing through O1 is equal to (K1 + K2) × (Vdd + Vth + Vss - Vdata0 - Vdd - Vth) 2 , I is equal to (K1 + K2) × (Vss - Vdata0) 2 ; K1 is the current coefficient of T01; K2 is the current coefficient of T02.

[0260] In at least one embodiment of the present invention, when the pixel circuit is applied to a wearable device, the aspect ratio W / L of the driving transistor of the red pixel circuit, the aspect ratio of the driving transistor in the green pixel circuit, and the aspect ratio of the driving transistor in the blue pixel circuit can be set differently, but not limited thereto.

[0261] The driving method described in the embodiments of the present disclosure is applied to the above pixel circuit. The driving method includes:

[0262] The first driving control circuit controls the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node;

[0263] The second driving control circuit controls the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node;

[0264] The first control data voltage writing circuit controls the writing of the first control data voltage provided by the first control data voltage writing end into the third node under the control of the first writing control signal;

[0265] The first driving circuit drives the light-emitting element under the control of the potential of its control end; the second driving circuit drives the light-emitting element under the control of the potential of its control end.

[0266] Optionally, the third node and the fourth node are the same node; the pixel circuit further includes a data writing circuit, a setting circuit, a compensation control circuit, a light-emitting control circuit, and a reset circuit; the display period includes a first stage, a second stage, and a third stage set in sequence; the driving method includes:

[0267] In the first stage, under the control of a reset control signal, the reset circuit writes a reset voltage provided by a reset voltage terminal to a first pole of a light-emitting element. The light-emitting control circuit controls the connection between a second terminal of a first driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal. The compensation control circuit controls the connection between a second node and the second terminal of the first driving circuit under the control of a compensation control signal to write the reset voltage to the second node. The setting circuit writes a setting voltage provided by a setting voltage terminal to a first node under the control of a setting control signal.

[0268] In the second stage, under the control of a third writing control signal, a data writing circuit writes a data voltage provided by a data line to the first node. The reset circuit writes a reset voltage provided by a reset voltage terminal to a first pole of the light-emitting element under the control of a reset control signal. The light-emitting control circuit controls the connection between a second terminal of a first driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal. The compensation control circuit controls the connection between a second node and the second terminal of the first driving circuit under the control of a compensation control signal. A first control data voltage writing circuit controls the writing of a first control data voltage provided by a first control data voltage writing terminal to a third node under the control of a first writing control signal. The first driving control circuit controls the connection or disconnection between the second node and a control terminal of the first driving circuit under the control of the potential of the third node. The second driving control circuit controls the connection or disconnection between the second node and a control terminal of the second driving circuit under the control of the potential of the third node.

[0269] In the third stage, the setting circuit writes a setting voltage provided by a setting voltage terminal to the first node under the control of a setting control signal. The light-emitting control circuit controls the connection between a second terminal of a first driving circuit and the first pole of the light-emitting element under the control of a light-emitting control signal, and the first driving circuit or the second driving circuit drives the light-emitting element to emit light.

[0270] In at least one embodiment of the present disclosure, in the second stage, the step that the first driving control circuit controls the connection or disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node includes:

[0271] When the first control data voltage is a second voltage signal, the first driving control circuit controls the connection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node.

[0272] When the first control data voltage is a third voltage signal, the first driving control circuit controls the disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node.

[0273] In the second stage, the step of the second driving control circuit controlling the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the third node includes:

[0274] When the first control data voltage is the second voltage signal, the second driving control circuit disconnects between the second node and the control end of the second driving circuit under the control of the potential of the third node;

[0275] When the first control data voltage is the third voltage signal, the second driving control circuit connects between the second node and the control end of the second driving circuit under the control of the potential of the third node;

[0276] The step of the first driving circuit or the second driving circuit driving the light-emitting element to emit light includes:

[0277] When in the second stage, the first driving control circuit connects between the second node and the control end of the first driving circuit under the control of the potential of the third node, in the third stage, the first driving circuit drives the light-emitting element to emit light;

[0278] When in the second stage, the second driving control circuit connects between the second node and the control end of the second driving circuit under the control of the potential of the third node, in the third stage, the second driving circuit drives the light-emitting element to emit light.

[0279] Optionally, the pixel circuit further includes a third energy storage circuit and a second control data voltage writing circuit; the pixel circuit further includes a data writing circuit, a setting circuit, a compensation control circuit, a light-emitting control circuit and a reset circuit; the display cycle includes a first stage, a second stage and a third stage set in sequence; the driving method includes:

[0280] In the first stage, the reset circuit writes the reset voltage provided by the reset voltage terminal to the first pole of the light-emitting element under the control of the reset control signal, the light-emitting control circuit connects between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the compensation control circuit connects between the second node and the second end of the first driving circuit under the control of the compensation control signal to write the reset voltage to the second node; the setting circuit writes the setting voltage provided by the setting voltage terminal to the first node under the control of the setting control signal;

[0281] In the second stage, the data writing circuit writes the data voltage provided by the data line into the first node under the control of the third writing control signal. The reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal. The light-emitting control circuit controls the connection between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal. The compensation control circuit controls the connection between the second node and the second end of the first driving circuit under the control of the compensation control signal. The first control data voltage writing circuit controls the writing of the first control data voltage provided by the first control data voltage writing terminal into the third node under the control of the first writing control signal. The second control data voltage writing circuit writes the second control data voltage provided by the second control data voltage writing terminal into the fourth node under the control of the second writing control signal. The first driving control circuit controls the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node. The second driving control circuit controls the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node.

[0282] In the third stage, the setting circuit writes the setting voltage provided by the setting voltage terminal into the first node under the control of the setting control signal. The light-emitting control circuit controls the connection between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal. The first driving circuit and / or the second driving circuit drives the light-emitting element to emit light.

[0283] In at least one embodiment of the present disclosure, in the second stage, the step of the first driving control circuit controlling the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node includes:

[0284] When the first control data voltage is the fourth voltage signal, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit.

[0285] When the first control data voltage is the fifth voltage signal, the first driving control circuit controls the disconnection between the second node and the control end of the first driving circuit.

[0286] In the second stage, the step of the second driving control circuit controlling the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node includes:

[0287] When the second control data voltage is the sixth voltage signal, the second driving control circuit controls the connection between the second node and the control end of the second driving circuit.

[0288] When the second control data voltage is the seventh voltage signal, the second driving control circuit controls the disconnection between the second node and the control end of the second driving circuit;

[0289] The step of driving the light-emitting element by the first driving circuit and / or the second driving circuit includes: when, in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the disconnection between the second node and the control end of the second driving circuit, the first driving circuit drives the light-emitting element to emit light under the control of the potential at its control end;

[0290] When, in the second stage, the first driving control circuit controls the disconnection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the connection between the second node and the control end of the second driving circuit, the second driving circuit drives the light-emitting element to emit light under the control of the potential at its control end;

[0291] When, in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the connection between the second node and the control end of the second driving circuit, the first driving circuit and the second driving circuit jointly drive the light-emitting element to emit light under the control of the potentials at their respective control ends.

[0292] The display device according to at least one embodiment of the present disclosure includes the above pixel circuit.

[0293] The display device provided by the embodiments of the present disclosure can be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0294] The above are the preferred embodiments of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present disclosure, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that, It includes a light-emitting element, a first energy storage circuit, a first driving circuit, a second driving circuit, a first driving control circuit, a second driving control circuit, a second energy storage circuit, and a first control data voltage writing circuit; A first end of the first energy storage circuit is electrically connected to a first node, and a second end of the first energy storage circuit is electrically connected to a second node. The first energy storage circuit is used for storing electrical energy; A control end of the first driving control circuit is electrically connected to a third node; a control end of the second driving control circuit is electrically connected to a fourth node; The first driving control circuit is further respectively electrically connected to the second node and a control end of the first driving circuit, and is used for controlling connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node; The second driving control circuit is further respectively electrically connected to the second node and a control end of the second driving circuit, and is used for controlling connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node; A first end of the second energy storage circuit is electrically connected to the third node, and a second end of the second energy storage circuit is electrically connected to a first end of the first driving circuit. The second energy storage circuit is used for storing electrical energy; The first control data voltage writing circuit is respectively electrically connected to a first writing control end, a first control data voltage writing end, and the third node, and is used for controlling writing the first control data voltage provided by the first control data voltage writing end into the third node under the control of a first writing control signal provided by the first writing control end; A first end of the first driving circuit and a first end of the second driving circuit are both electrically connected to a power supply voltage end, a second end of the first driving circuit and a second end of the second driving circuit are both electrically connected to the light-emitting element. The first driving circuit is used for driving the light-emitting element under the control of the potential of its control end, and the second driving circuit is used for driving the light-emitting element under the control of the potential of its control end.

2. The pixel circuit according to claim 1, wherein The third node and the fourth node are the same node.

3. The pixel circuit according to claim 1, wherein It further includes a third energy storage circuit and a second control data voltage writing circuit; A first end of the third energy storage circuit is electrically connected to a first end of the first driving circuit, and a second end of the third energy storage circuit is electrically connected to a control end of the second driving control circuit. The third energy storage circuit is used for storing electrical energy; The second control data voltage writing circuit is respectively electrically connected to a second writing control end, a second control data voltage writing end, and the fourth node, and is used for writing the second control data voltage provided by the second control data voltage writing end into the fourth node under the control of a second writing control signal provided by the second writing control end.

4. The pixel circuit according to any one of claims 1 to 3, characterized in that, It further includes a data writing circuit, a setting circuit, and a compensation control circuit; The data writing circuit is respectively electrically connected to a data line, a third writing control end, and the first node, and is used for writing the data voltage provided by the data line into the first node under the control of a third writing control signal provided by the third writing control end; The set circuit is electrically connected to the set control terminal, the set voltage terminal, and the first node respectively, and is configured to write the set voltage provided by the set voltage terminal into the first node under the control of the set control signal provided by the set control terminal; The compensation control circuit is electrically connected to the compensation control terminal, the second node, and the second terminal of the first driving circuit respectively, and is configured to control the connection or disconnection between the second node and the second terminal of the first driving circuit under the control of the compensation control signal provided by the compensation control terminal.

5. The pixel circuit according to any one of claims 1 to 3, wherein It further includes a light-emitting control circuit; The light-emitting control circuit is electrically connected to the light-emitting control terminal, the second terminal of the first driving circuit, and the first pole of the light-emitting element respectively, and is configured to control the connection or disconnection between the second terminal of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; The second pole of the light-emitting element is electrically connected to the first voltage terminal.

6. The pixel circuit according to any one of claims 1 to 3, characterized in that It further includes a reset circuit; The reset circuit is electrically connected to the reset control terminal, the reset voltage terminal, and the first pole of the light-emitting element respectively, and is configured to write the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal provided by the reset control terminal; The second pole of the light-emitting element is electrically connected to the first voltage terminal.

7. The pixel circuit according to any one of claims 1 to 3, characterized in that, The first driving control circuit includes a first transistor, the second driving control circuit includes a second transistor, the first driving circuit includes a first driving transistor, and the second driving circuit includes a second driving transistor; the control pole of the first transistor is electrically connected to the third node, the first pole of the first transistor is electrically connected to the second node, and the second pole of the first transistor is electrically connected to the control terminal of the first driving circuit; The control pole of the second transistor is electrically connected to the fourth node, the first pole of the second transistor is electrically connected to the second node, and the second pole of the second transistor is electrically connected to the control terminal of the second driving circuit; The control pole of the first driving transistor is electrically connected to the control terminal of the first driving circuit, the first pole of the first driving transistor is electrically connected to the first terminal of the first driving circuit, and the second pole of the first driving transistor is electrically connected to the second terminal of the first driving circuit; The control pole of the second driving transistor is electrically connected to the control terminal of the second driving circuit, the first pole of the second driving transistor is electrically connected to the first terminal of the second driving circuit, and the second pole of the second driving transistor is electrically connected to the second terminal of the second driving circuit.

8. The pixel circuit according to any one of claims 1 to 3, characterized in that The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the second node; The first end of the second capacitor is electrically connected to the third node, and the second end of the second capacitor is electrically connected to the first terminal of the first driving circuit.

9. The pixel circuit according to claim 2, wherein The first control data voltage writing circuit includes a third transistor; The control electrode of the third transistor is electrically connected to the first writing control terminal, the first electrode of the third transistor is electrically connected to the first control data voltage writing terminal, and the second electrode of the third transistor is electrically connected to the third node.

10. The pixel circuit according to claim 3, wherein The third energy storage circuit includes a third capacitor, and the second control data voltage writing circuit includes a fourth transistor; The first end of the third capacitor is electrically connected to the first end of the first driving circuit, and the second end of the third capacitor is electrically connected to the control terminal of the second driving control circuit; The control electrode of the fourth transistor is electrically connected to the second writing control terminal, the first electrode of the fourth transistor is electrically connected to the second control data voltage writing terminal, and the second electrode of the fourth transistor is electrically connected to the fourth node.

11. The pixel circuit according to claim 4, wherein The data writing circuit includes a fifth transistor; the setting circuit includes a sixth transistor; the compensation control circuit includes a seventh transistor; The control electrode of the fifth transistor is electrically connected to the third writing control terminal, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the setting control terminal, the first electrode of the sixth transistor is electrically connected to the setting voltage terminal, and the second electrode of the sixth transistor is electrically connected to the first node; The control electrode of the seventh transistor is electrically connected to the compensation control terminal, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second end of the first driving circuit.

12. The pixel circuit according to claim 5, wherein The light emitting control circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the light emitting control terminal, the first electrode of the eighth transistor is electrically connected to the second end of the first driving circuit, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.

13. The pixel circuit according to claim 6, wherein The reset circuit includes a ninth transistor; The control electrode of the ninth transistor is electrically connected to the reset control terminal, the first electrode of the ninth transistor is electrically connected to the reset voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element.

14. A driving method, applied to the pixel circuit according to any one of claims 1 to 13, characterized in that, The driving method includes: The first driving control circuit controls the connection or disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node; The second driving control circuit controls the connection or disconnection between the second node and the control terminal of the second driving circuit under the control of the potential of the fourth node; The first control data voltage writing circuit controls the writing of the first control data voltage provided by the first control data voltage writing terminal into the third node under the control of the first writing control signal; The first driving circuit drives the light emitting element under the control of the potential of its control terminal; the second driving circuit drives the light emitting element under the control of the potential of its control terminal.

15. The driving method according to claim 14, characterized in that, The third node and the fourth node are the same node; the pixel circuit further includes a data writing circuit, a setting circuit, a compensation control circuit, a light emitting control circuit and a reset circuit; the display period includes a first stage, a second stage and a third stage set successively; the driving method includes: In the first stage, under the control of the reset control signal, the reset circuit writes the reset voltage provided by the reset voltage terminal to the first pole of the light-emitting element. The light-emitting control circuit controls the connection between the second terminal of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal. The compensation control circuit controls the connection between the second node and the second terminal of the first driving circuit under the control of the compensation control signal to write the reset voltage to the second node. The setting circuit writes the setting voltage provided by the setting voltage terminal to the first node under the control of the setting control signal. In the second stage, under the control of the third write control signal, the data writing circuit writes the data voltage provided by the data line to the first node. Under the control of the reset control signal, the reset circuit writes the reset voltage provided by the reset voltage terminal to the first pole of the light-emitting element. The light-emitting control circuit controls the connection between the second terminal of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal. The compensation control circuit controls the connection between the second node and the second terminal of the first driving circuit under the control of the compensation control signal. The first control data voltage writing circuit controls the writing of the first control data voltage provided by the first control data voltage writing terminal to the third node under the control of the first write control signal. The first driving control circuit controls the connection or disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node. The second driving control circuit controls the connection or disconnection between the second node and the control terminal of the second driving circuit under the control of the potential of the third node. In the third stage, the setting circuit writes the setting voltage provided by the setting voltage terminal to the first node under the control of the setting control signal. The light-emitting control circuit controls the connection between the second terminal of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal, and the first driving circuit or the second driving circuit drives the light-emitting element to emit light.

16. The driving method according to claim 15, wherein In the second stage, the step that the first driving control circuit controls the connection or disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node includes: When the first control data voltage is the second voltage signal, the first driving control circuit controls the connection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node. When the first control data voltage is the third voltage signal, the first driving control circuit controls the disconnection between the second node and the control terminal of the first driving circuit under the control of the potential of the third node. In the second stage, the step that the second driving control circuit controls the connection or disconnection between the second node and the control terminal of the second driving circuit under the control of the potential of the third node includes: When the first control data voltage is the second voltage signal, the second driving control circuit controls the disconnection between the second node and the control terminal of the second driving circuit under the control of the potential of the third node. When the first control data voltage is the third voltage signal, the second driving control circuit controls the connection between the second node and the control end of the second driving circuit under the control of the potential of the third node; The step of driving the light-emitting element by the first driving circuit or the second driving circuit includes: When in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit under the control of the potential of the third node, in the third stage, the first driving circuit drives the light-emitting element to emit light; When in the second stage, the second driving control circuit controls the connection between the second node and the control end of the second driving circuit under the control of the potential of the third node, in the third stage, the second driving circuit drives the light-emitting element to emit light.

17. The driving method according to claim 14, characterized in that, The pixel circuit further includes a third energy storage circuit and a second control data voltage writing circuit; the pixel circuit further includes a data writing circuit, a setting circuit, a compensation control circuit, a light-emitting control circuit and a reset circuit; the display period includes a first stage, a second stage and a third stage arranged in sequence; the driving method includes: In the first stage, the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal, and the light-emitting control circuit controls the connection between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the compensation control circuit controls the connection between the second node and the second end of the first driving circuit under the control of the compensation control signal to write the reset voltage into the second node; the setting circuit writes the setting voltage provided by the setting voltage terminal into the first node under the control of the setting control signal; In the second stage, the data writing circuit writes the data voltage provided by the data line into the first node under the control of the third writing control signal, the reset circuit writes the reset voltage provided by the reset voltage terminal into the first pole of the light-emitting element under the control of the reset control signal, and the light-emitting control circuit controls the connection between the second end of the first driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal; the compensation control circuit controls the connection between the second node and the second end of the first driving circuit under the control of the compensation control signal; the first control data voltage writing circuit controls the writing of the first control data voltage provided by the first control data voltage terminal into the third node under the control of the first writing control signal; the second control data voltage writing circuit writes the second control data voltage provided by the second control data voltage terminal into the fourth node under the control of the second writing control signal; the first driving control circuit controls the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node; the second driving control circuit controls the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node; In the third stage, under the control of the set control signal, the set circuit writes the set voltage provided by the set voltage terminal into the first node; under the control of the light emission control signal, the light emission control circuit controls the connection between the second end of the first driving circuit and the first pole of the light emitting element, and the first driving circuit and / or the second driving circuit drive the light emitting element to emit light.

18. The driving method according to claim 17, wherein, In the second stage, the step of the first driving control circuit controlling the connection or disconnection between the second node and the control end of the first driving circuit under the control of the potential of the third node includes: When the first control data voltage is the fourth voltage signal, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit; When the first control data voltage is the fifth voltage signal, the first driving control circuit controls the disconnection between the second node and the control end of the first driving circuit; In the second stage, the step of the second driving control circuit controlling the connection or disconnection between the second node and the control end of the second driving circuit under the control of the potential of the fourth node includes: When the second control data voltage is the sixth voltage signal, the second driving control circuit controls the connection between the second node and the control end of the second driving circuit; When the second control data voltage is the seventh voltage signal, the second driving control circuit controls the disconnection between the second node and the control end of the second driving circuit; The step of the first driving circuit and / or the second driving circuit driving the light emitting element to emit light includes: when in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the disconnection between the second node and the control end of the second driving circuit, the first driving circuit drives the light emitting element to emit light under the control of the potential of its control end; When in the second stage, the first driving control circuit controls the disconnection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the connection between the second node and the control end of the second driving circuit, the second driving circuit drives the light emitting element to emit light under the control of the potential of its control end; When in the second stage, the first driving control circuit controls the connection between the second node and the control end of the first driving circuit, and the second driving control circuit controls the connection between the second node and the control end of the second driving circuit, the first driving circuit and the second driving circuit jointly drive the light emitting element to emit light under the control of the potentials of their respective control ends.

19. A display device, characterized in that, Comprising the pixel circuit according to any one of claims 1 to 13.

Images