Display substrate and display device

Abstract

This disclosure provides a display substrate and a display device. The display substrate includes a driving module disposed on a substrate, the driving module including multiple driving units, each driving unit including a multi-stage driving circuit; each driving unit includes a first signal line, and each driving circuit includes an output sub-circuit; the display substrate includes at least two metal layers stacked along a direction away from the substrate; in at least one driving unit, the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of at least one transistor included in the output sub-circuit on the substrate, and the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the at least one transistor on the substrate; the first electrode and the second electrode are disposed on the same metal layer, and the first electrode and the first signal line are disposed on different metal layers. This disclosure reduces the width of the display substrate along a first direction, which is beneficial for achieving a narrow bezel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Active-Matrix Organic Light-Emitting Diode (AMOLED) display panels are widely used in various fields due to their advantages such as low power consumption, low manufacturing cost, and wide color gamut.

[0003] An AMOLED display panel includes pixel circuits located in the display area and driving modules located in the edge area. The pixel circuits include multiple pixel circuits distributed in an array, and the arrangement of the driving modules determines the bezel width of the AMOLED display panel. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a display substrate including a driving module disposed on a substrate, the driving module including a plurality of driving units, each driving unit including a multi-stage driving circuit; the driving circuit is configured to provide driving signals.

[0005] The driving unit includes a first signal line, and the driving circuit includes an output sub-circuit, which is configured to output the driving signal.

[0006] The display substrate includes at least two metal layers stacked along a direction away from the substrate.

[0007] In at least one driving unit, the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the at least one transistor included in the output sub-circuit on the substrate, and the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the at least one transistor on the substrate.

[0008] The first electrode and the second electrode are disposed on the same metal layer, while the first electrode and the first signal line are disposed on different metal layers.

[0009] Optionally, the orthographic projection of the first signal line included in one of the plurality of driving units onto the substrate at least partially overlaps with the orthographic projection of the second signal line included in another of the plurality of driving units onto the substrate.

[0010] Optionally, the first signal line and the second signal line are configured to provide the same signal.

[0011] Optionally, the first signal line is a low-voltage DC signal line, a high-voltage DC signal line, or a clock signal line;

[0012] The second signal line is a low-voltage DC signal line, a high-voltage DC signal line, or a clock signal line.

[0013] Optionally, in the plurality of driving units, at least three signal lines have orthographic projections on the substrate that at least partially overlap.

[0014] Optionally, the driving module includes a first driving unit; the first driving unit includes a multi-stage first driving circuit, the first driving circuit being configured to provide a first driving signal; the first driving unit includes a first first voltage line and a first second voltage line; the first driving circuit includes a first output sub-circuit; the first signal line is the first first voltage line;

[0015] The first output sub-circuit includes a first driving transistor and a first driving reset transistor;

[0016] The first electrode of the first driving transistor is electrically connected to the first second voltage line, the second electrode of the first driving transistor is electrically connected to the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor is electrically connected to the first first voltage line.

[0017] The display substrate includes a first metal layer and a second metal layer sequentially stacked along a direction away from the substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all disposed on the first metal layer, and the first voltage line is disposed on the second metal layer;

[0018] The orthographic projection of the first electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the first electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate.

[0019] Optionally, the driving module includes a first driving unit; the first driving unit includes a multi-stage first driving circuit, the first driving circuit being configured to provide a first driving signal; the first driving unit includes a first first voltage line and a first second voltage line; the first driving circuit includes a first output sub-circuit; the first signal line is the first first voltage line;

[0020] The first output sub-circuit includes a first driving transistor and a first driving reset transistor;

[0021] The first electrode of the first driving transistor is electrically connected to the first second voltage line, the second electrode of the first driving transistor is electrically connected to the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor is electrically connected to the first first voltage line.

[0022] The display substrate includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially along a direction away from the substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all disposed on the first metal layer, and the first first voltage line is disposed on the third metal layer;

[0023] The orthographic projection of the first electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the first electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate.

[0024] Optionally, the first driving unit further includes a second first voltage line, a first first clock signal line, a first second clock signal line, a first second voltage line, a first start signal line, and a first reset line;

[0025] The first clock signal line, the first second clock signal line, and the first reset line are all disposed on the first metal layer;

[0026] The second first voltage line, the first start signal line, and the first second voltage line are all disposed on the second metal layer.

[0027] Optionally, the first driving circuit includes a first on / off control transistor and a second on / off control transistor;

[0028] The gates of the first on / off control transistor and the second on / off transistor are both electrically connected to the second first voltage line;

[0029] At least a portion of the orthographic projection of the second first voltage line onto the substrate is disposed between the orthographic projection of the gate of the first on / off control transistor onto the substrate and the orthographic projection of the gate of the second on / off control transistor onto the substrate.

[0030] Optionally, the orthographic projection of the first start signal line on the substrate is positioned between the orthographic projection of the second first voltage line on the substrate and the orthographic projection of the first reset line on the substrate.

[0031] Optionally, the driving module includes a second driving unit; the first driving unit includes a multi-stage second driving circuit, the second driving circuit being configured to provide a second driving signal; the second driving unit includes a third first voltage line; the second driving circuit includes a second output sub-circuit; the second output sub-circuit includes a second driving transistor;

[0032] The orthogonal projection of the third first voltage line on the substrate is located on the side of the orthogonal projection of the second driving transistor on the substrate that is away from the display area;

[0033] The third first voltage line is disposed on a different layer than the first first voltage line;

[0034] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate.

[0035] Optionally, the orthographic projection of the third first voltage line on the substrate coincides with the orthographic projection of the first first voltage line on the substrate.

[0036] Optionally, the first driving circuit is configured to provide an N-type gate driving signal, and the second driving circuit is configured to provide a reset control signal.

[0037] Optionally, the first voltage line is disposed on the second metal layer, and the third voltage line is disposed on the third metal layer; or,

[0038] The first voltage line is disposed on the third metal layer, and the third voltage line is disposed on the second metal layer.

[0039] Optionally, the first first voltage line and the third first voltage line are low-voltage DC signal lines; or, the first first voltage line and the third first voltage line are high-voltage DC signal lines.

[0040] Optionally, the second output sub-circuit is arranged adjacent to the third first voltage line.

[0041] Optionally, the second driving unit further includes a second start signal line, a second first clock signal line, a second second clock signal line, and a second second voltage line;

[0042] The third first voltage line, the second start signal line, the second first clock signal line, the second second clock signal line, and the second second voltage line are arranged sequentially along the direction closest to the display area.

[0043] Optionally, the second output sub-circuit may further include a second drive reset transistor;

[0044] The orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second driving transistor on the substrate, and the orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second driving transistor on the substrate.

[0045] The orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second drive reset transistor on the substrate, and the orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second drive reset transistor on the substrate.

[0046] Optionally, the orthographic projection of the transistors included in the second driving circuit on the substrate is positioned on the side of the orthographic projection of the third first voltage line on the substrate closer to the display area.

[0047] Optionally, the second driving circuit further includes a fifteenth transistor, a twentieth transistor, and a twenty-first transistor;

[0048] The gate of the fifteenth transistor is electrically connected to the second first clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the second electrode of the twenty-first transistor; the first electrode of the twenty-first transistor is electrically connected to the second electrode of the twentyth transistor.

[0049] The gate of the twentieth transistor is electrically connected to the gate of the second drive reset transistor, and the gate of the twentieth eleventh transistor is electrically connected to the second clock signal line.

[0050] The orthographic projection of the gate of the fifteenth transistor on the substrate, the orthographic projection of the gate of the twentieth transistor on the substrate, and the orthographic projection of the gate of the twenty-first transistor on the substrate are disposed between the orthographic projection of the second clock signal line on the substrate and the orthographic projection of the second voltage line on the substrate.

[0051] Optionally, the second driving circuit further includes a sixteenth transistor;

[0052] The gate of the sixteenth transistor is electrically connected to the second electrode of the fifteenth transistor, the first electrode of the sixteenth transistor is electrically connected to the second first clock signal line, and the second electrode of the sixteenth transistor is electrically connected to the gate of the drive reset transistor.

[0053] The orthographic projection of the gate of the sixteenth transistor on the substrate is positioned between the orthographic projection of the second first clock signal line on the substrate and the orthographic projection of the second second clock signal line on the substrate.

[0054] Optionally, the substrate includes a peripheral region and a display region; the driving units included in the driving module are all disposed in the peripheral region of the substrate.

[0055] The first driving unit is located on the side of the second driving unit that is away from the display area.

[0056] Optionally, the drive module includes a third drive unit, the third drive unit includes a multi-stage third drive circuit, and the third drive circuit is configured to provide a third drive signal;

[0057] The third drive unit is located on the side of the first drive unit away from the second drive unit.

[0058] Optionally, the drive module includes a fourth drive unit, the drive unit includes a multi-stage fourth drive circuit, and the fourth drive circuit is configured to provide a fourth drive signal;

[0059] The fourth driving unit is located on the side of the second driving unit that is close to the display area.

[0060] In a second aspect, embodiments of this disclosure provide a display device including the display substrate described above. Attached Figure Description

[0061] Figure 1 This is a circuit diagram of at least one embodiment of the first driving circuit in the display substrate described in this disclosure;

[0062] Figure 2This is a circuit diagram of at least one embodiment of the first driving circuit in the display substrate described in this disclosure;

[0063] Figure 3 It corresponds to Figure 2 A layout diagram of at least one embodiment of the first driving circuit shown;

[0064] Figure 4 yes Figure 3 Layout diagram of the semiconductor layer in the diagram;

[0065] Figure 5 yes Figure 3 Layout diagram of the first gate metal layer in the middle;

[0066] Figure 6 yes Figure 3 Layout diagram of the second gate metal layer;

[0067] Figure 7 yes Figure 3 Layout diagram of the first metal layer in the middle;

[0068] Figure 8 yes Figure 3 The layout diagram of the second metal layer.

[0069] Figure 9 This is a circuit diagram of at least one embodiment of the second driving circuit in the display substrate described in this disclosure;

[0070] Figure 10 This is a circuit diagram of at least one embodiment of the second driving circuit in the display substrate described in this disclosure;

[0071] Figure 11 It corresponds to Figure 10 A layout diagram of at least one embodiment of the second driving circuit shown;

[0072] Figure 12 yes Figure 11 Layout diagram of the semiconductor layer in the diagram;

[0073] Figure 13 yes Figure 11 Layout diagram of the first gate metal layer in the middle;

[0074] Figure 14 yes Figure 11 Layout diagram of the second gate metal layer;

[0075] Figure 15 yes Figure 11 Layout diagram of the first metal layer in the middle;

[0076] Figure 16 yes Figure 11 Layout diagram of the second metal layer in the middle;

[0077] Figure 17 yes Figure 11 Layout diagram of the third metal layer in the middle;

[0078] Figure 18A This is a layout diagram of the first driving circuit and the second driving circuit included in at least one embodiment of the display substrate described in this disclosure;

[0079] Figure 18B yes Figure 18A A-A' section view in the diagram;

[0080] Figure 18C for Figure 18A Layout diagram of the second source / drain metal layer in the image;

[0081] Figure 18D This is a layout diagram of the third source / drain metal layer in 18A;

[0082] Figure 19 This discloses a structural diagram of a display substrate according to at least one embodiment;

[0083] Figure 20 It corresponds to Figure 10 Another layout diagram of at least one embodiment of the second driving circuit shown;

[0084] Figure 21 yes Figure 20 Layout diagram of the semiconductor layer in the diagram;

[0085] Figure 22 yes Figure 20 Layout diagram of the first gate metal layer in the middle;

[0086] Figure 23 yes Figure 20 Layout diagram of the second gate metal layer;

[0087] Figure 24 yes Figure 22 Layout diagram of the first metal layer in the middle;

[0088] Figure 25 yes Figure 22 Layout diagram of the second metal layer in the middle;

[0089] Figure 26 yes Figure 3 At least one embodiment of the first driving circuit shown and Figure 20 A schematic diagram showing the arrangement of at least one embodiment of the second driving circuit;

[0090] Figure 27A This is a circuit diagram of at least one embodiment of the third driving circuit in the display substrate described in this disclosure;

[0091] Figure 27BThis is a circuit diagram of at least one embodiment of the third driving circuit in the display substrate described in this disclosure;

[0092] Figure 28 yes Figure 27B The layout diagram corresponding to at least one embodiment of the third driving circuit shown;

[0093] Figure 29 yes Figure 28 Layout diagram of the semiconductor layer in the diagram;

[0094] Figure 30 yes Figure 28 Layout diagram of the first gate metal layer in the middle;

[0095] Figure 31 yes Figure 28 Layout diagram of the second gate metal layer;

[0096] Figure 32 This is the layout diagram of the first metal layer in 28;

[0097] Figure 33A This is a circuit diagram of at least one embodiment of the fourth driving circuit in the display substrate described in this disclosure;

[0098] Figure 33B This is a circuit diagram of at least one embodiment of the fourth driving circuit in the display substrate described in this disclosure;

[0099] Figure 34 yes Figure 33B The layout diagram corresponding to at least one embodiment of the fourth driving circuit shown;

[0100] Figure 35 yes Figure 34 Layout diagram of the semiconductor layer in the diagram;

[0101] Figure 36 yes Figure 34 Layout diagram of the first gate metal layer in the middle;

[0102] Figure 37 yes Figure 34 Layout diagram of the second gate metal layer;

[0103] Figure 38 yes Figure 34 Layout diagram of the first metal layer in the middle;

[0104] Figure 39 Is Figure 34 The layout diagram shown shows the addition of a second metal layer.

[0105] Figure 40 This is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0106] Figure 41 This is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0107] Figure 42 This is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0108] Figure 43 This is a structural diagram of a display substrate according to at least one embodiment of the present disclosure. Detailed Implementation

[0109] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0110] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first electrode, and the other terminal as the second electrode.

[0111] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0112] The display substrate described in this embodiment includes a driving module disposed on a substrate, the driving module including a plurality of driving units, the driving unit including a multi-stage driving circuit; the driving circuit is used to provide driving signals.

[0113] The driving unit includes a first signal line, and the driving circuit includes an output sub-circuit, which is configured to output the driving signal.

[0114] The display substrate includes at least two metal layers stacked along a direction away from the substrate.

[0115] In at least one driving unit, the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the at least one transistor included in the output sub-circuit on the substrate, and the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the at least one transistor included in the output sub-circuit on the substrate.

[0116] The first electrode and the second electrode are disposed on the same metal layer, while the first electrode and the first signal line are disposed on different metal layers.

[0117] The display substrate described in this embodiment includes a driving module. In at least one driving unit included in the driving module, a first electrode and a second electrode are disposed on the same metal layer, and the first electrode and a first signal line are disposed on different metal layers. The orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the at least one transistor included in the output sub-circuit on the substrate, and the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the at least one transistor included in the output sub-circuit on the substrate, thereby reducing the width of the display substrate in the first direction and facilitating the realization of a narrow bezel.

[0118] In at least one embodiment of this disclosure, the first direction may be the direction of extension of the gate line, for example, the first direction may be a horizontal direction, but is not limited thereto.

[0119] In at least one embodiment of this disclosure, the orthographic projection of the first signal line included in one of the plurality of driving units onto the substrate at least partially overlaps with the orthographic projection of the second signal line included in another of the plurality of driving units onto the substrate.

[0120] In a specific implementation, the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the second signal line on the substrate, so as to reduce the width of the display substrate in the first direction and facilitate the realization of a narrow bezel.

[0121] Optionally, the first signal line and the second signal line are configured to provide the same signal.

[0122] Optionally, the first signal line is a low-voltage DC signal line, a high-voltage DC signal line, or a clock signal line;

[0123] The second signal line is a low-voltage DC signal line, a high-voltage DC signal line, or a clock signal line.

[0124] In at least one embodiment of this disclosure, the first signal line and the second signal line may be configured to provide the same signal. For example, the first signal line and the second signal line may both be low-voltage DC signal lines, or the first signal line and the second signal line may both be high-voltage DC signal lines, or the first signal line and the second signal line may both be clock signal lines; but this is not a limitation.

[0125] In specific implementations, the first signal line and the second signal line may also be configured to provide different signals. For example, the first signal line may be a low-voltage DC signal line and the second signal line may be a high-voltage DC signal line; or, the first signal line may be a clock signal line and the second signal line may be a high-voltage DC signal line; or, the first signal line may be a clock signal line and the second signal line may be a low-voltage DC signal line; but this is not a limitation.

[0126] In at least one embodiment of this disclosure, in the plurality of driving units, at least three signal lines have orthographic projections on the substrate that at least partially overlap.

[0127] In a specific implementation, among the plurality of driving units, at least three signal lines have at least partial overlap in their orthogonal projections onto the substrate, so as to reduce the width of the display substrate in the first direction and facilitate the realization of a narrow bezel.

[0128] In at least one embodiment of this disclosure, the driving module includes a first driving unit; the first driving unit includes a multi-stage first driving circuit, the first driving circuit being used to provide a first driving signal; the first driving unit includes a first first voltage line and a first second voltage line; the first driving circuit includes a first output sub-circuit; the first signal line is the first first voltage line;

[0129] The first output sub-circuit includes a first driving transistor and a first driving reset transistor;

[0130] The first electrode of the first driving transistor is electrically connected to the first second voltage line, the second electrode of the first driving transistor is electrically connected to the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor is electrically connected to the first first voltage line.

[0131] The display substrate includes a first metal layer and a second metal layer sequentially stacked along a direction away from the substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all disposed on the first metal layer, and the first voltage line is disposed on the second metal layer;

[0132] The orthographic projection of the first electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the first electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate.

[0133] Optionally, the first driving unit is used to provide a first driving signal, which may be an N-type gate driving signal. The N-type gate driving signal may be a high-level active gate driving signal provided to the N-type transistor included in the pixel circuit, but is not limited thereto.

[0134] In at least one embodiment of this disclosure, the first driving transistor and the first driving reset transistor may be arranged along a second direction;

[0135] The second direction can be the extension direction of the first voltage line, for example, the second direction can be the vertical direction, but is not limited thereto.

[0136] Optionally, the first voltage line can be a low voltage line and the second voltage line can be a high voltage line, but this is not a limitation.

[0137] In at least one embodiment of this disclosure, the driving module includes a first driving unit; the first driving unit includes a multi-stage first driving circuit, the first driving circuit being used to provide a first driving signal; the first driving unit includes a first first voltage line and a first second voltage line; the first driving circuit includes a first output sub-circuit; the first signal line is the first first voltage line;

[0138] The first output sub-circuit includes a first driving transistor and a first driving reset transistor;

[0139] The first electrode of the first driving transistor is electrically connected to the first second voltage line, the second electrode of the first driving transistor is electrically connected to the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor is electrically connected to the first first voltage line.

[0140] The display substrate includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially along a direction away from the substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all disposed on the first metal layer, and the first first voltage line is disposed on the second metal layer or the third metal layer;

[0141] The orthographic projection of the first electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the first electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate; the orthographic projection of the second electrode of the first driving reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate, thereby reducing the width of the display substrate along the first direction, which is beneficial for achieving a narrow bezel.

[0142] In a specific implementation, the display substrate may include three metal layers. The first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all disposed on the first metal layer. The first voltage line may be disposed on the second metal layer or the third metal layer.

[0143] In at least one embodiment of this disclosure, the first metal layer may be a first source / drain metal layer, the second metal layer may be a second source / drain metal layer, and the third metal layer may be a third source / drain metal layer, but is not limited thereto.

[0144] like Figure 1 As shown, at least one embodiment of the first driving circuit includes a first output sub-circuit 10;

[0145] The first output sub-circuit 10 includes a first driving transistor T9 and a first driving reset transistor T10;

[0146] The first driving circuit further includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, an eleventh transistor T11, a twelfth transistor T12, a first on / off control transistor T13, a second on / off control transistor T14, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0147] The gate of T1 is electrically connected to the first second clock signal line NCB, the first electrode of T1 is electrically connected to the first input terminal I1, and the second electrode of T1 is electrically connected to the gate of T2.

[0148] The first electrode of T2 is electrically connected to the first second clock signal line NCB, and the second electrode of T2 is electrically connected to the second electrode of T3.

[0149] The gate of T3 is electrically connected to the first second clock signal line NCB, and the first electrode of T3 is electrically connected to the second first voltage line VGL_N2.

[0150] The gate of T4 is electrically connected to the gate of T5; the first electrode of T4 is electrically connected to the first clock signal line NCK; the second electrode of T4 is electrically connected to the first plate of C3; and the second plate of C3 is electrically connected to the gate of T5.

[0151] The gate of T5 is electrically connected to the first electrode of T5, and the second electrode of T5 is electrically connected to the gate of T10.

[0152] The gate of T6 is electrically connected to the first plate of C1, the first electrode of T6 is electrically connected to the first clock signal line NCK, and the second electrode of T6 is electrically connected to the second plate of C1.

[0153] The gate of T7 is electrically connected to the first clock signal line NCK, the first electrode of T7 is electrically connected to the second plate of C1, and the second electrode of T7 is electrically connected to the gate of T9.

[0154] The gate of T8 is electrically connected to the gate of T2, the first electrode of T8 is electrically connected to the first second voltage line VGH_N, and the second electrode of T8 is electrically connected to the gate of T9.

[0155] The first electrode of T9 is electrically connected to the first second voltage line VGH_N, and the second electrode of T9 is electrically connected to the first drive signal output terminal O1.

[0156] The first electrode of T10 is electrically connected to the first drive signal output terminal O1, and the second electrode of T10 is electrically connected to the first first voltage line VGL_N1.

[0157] The gate of T11 is electrically connected to the second electrode of T6, the first electrode of T11 is electrically connected to the first second voltage line VGH_N, and the second electrode of T11 is electrically connected to the gate of T10.

[0158] The gate of T12 is electrically connected to the first reset line RST_N, the first electrode of T12 is electrically connected to the first second voltage line VGH_N, and the second electrode of T12 is electrically connected to the gate of T10.

[0159] The gate of T13 is electrically connected to the second first voltage line VGL_N2, the first electrode of T13 is electrically connected to the gate of T2, and the second electrode of T13 is electrically connected to the gate of T4.

[0160] The gate of T14 is electrically connected to the second first voltage line VGL_N2, the first electrode of T14 is electrically connected to the second electrode of T2, and the second electrode of T14 is electrically connected to the gate of T6.

[0161] The first plate of C2 is electrically connected to the gate of T9, and the second plate of C2 is electrically connected to the first second voltage line VGH_N.

[0162] exist Figure 1 In at least one embodiment shown, T9 can be the ninth transistor included in at least one embodiment of the first driving circuit, T10 can be the tenth transistor included in at least one embodiment of the first driving circuit, T13 can be the thirteenth transistor included in at least one embodiment of the first driving circuit, and T14 can be the fourteenth transistor included in at least one embodiment of the first driving circuit.

[0163] like Figure 1 All transistors included in at least one embodiment of the first driving circuit shown may be P-type transistors, but are not limited thereto.

[0164] In at least one embodiment of this disclosure, each first voltage line may be a low-voltage DC signal line and each second voltage line may be a high-voltage DC signal line, but this is not a limitation.

[0165] Figure 2 Is Figure 1 A schematic diagram showing the labels of each electrode and plate based on the above.

[0166] like Figure 2 As shown, at least one embodiment of the first driving circuit includes a first output sub-circuit 10;

[0167] The first output sub-circuit 10 includes a first driving transistor T9 and a first driving reset transistor T10;

[0168] The first driving circuit further includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, an eleventh transistor T11, a twelfth transistor T12, a first on / off control transistor T13, a second on / off control transistor T14, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0169] The gate G1 of T1 is electrically connected to the first second clock signal line NCB, the first electrode S1 of T1 is electrically connected to the first input terminal I1, and the second electrode D1 of T1 is electrically connected to the gate G2 of T2.

[0170] The first electrode S2 of T2 is electrically connected to the first second clock signal line NCB, and the second electrode D2 of T2 is electrically connected to the second electrode D3 of T3.

[0171] The gate G3 of T3 is electrically connected to the first second clock signal line NCB, and the first electrode S3 of T3 is electrically connected to the second first voltage line VGL_N2.

[0172] The gate G4 of T4 is electrically connected to the gate G5 of T5. The first electrode S4 of T4 is electrically connected to the first clock signal line NCK. The second electrode D4 of T4 is electrically connected to the first plate C3a of C3. The second plate C3b of C3 is electrically connected to the gate G5 of T5.

[0173] The gate G5 of T5 is electrically connected to the first electrode S5 of T5, and the second electrode D5 of T5 is electrically connected to the gate G10 of T10.

[0174] The gate G6 of T6 is electrically connected to the first plate C1a of C1, the first electrode S6 of T6 is electrically connected to the first clock signal line NCK, and the second electrode D6 of T6 is electrically connected to the second plate C1b of C1.

[0175] The gate G7 of T7 is electrically connected to the first clock signal line NCK, the first electrode S7 of T7 is electrically connected to the second plate C1b of C1, and the second electrode D7 of T7 is electrically connected to the gate G9 of T9.

[0176] The gate G8 of T8 is electrically connected to the gate G2 of T2, the first electrode S8 of T8 is electrically connected to the first second voltage line VGH_N, and the second electrode D8 of T8 is electrically connected to the gate G9 of T9.

[0177] The first electrode S9 of T9 is electrically connected to the first second voltage line VGH_N, and the second electrode D9 of T9 is electrically connected to the first drive signal output terminal O1.

[0178] The first electrode S10 of T10 is electrically connected to the first drive signal output terminal O1, and the second electrode D10 of T10 is electrically connected to the first voltage line VGL_N1.

[0179] The gate G11 of T11 is electrically connected to the second electrode of T6, the first electrode S11 of T11 is electrically connected to the first second voltage line VGH_N, and the second electrode D11 of T11 is electrically connected to the gate of T10.

[0180] The gate G12 of T12 is electrically connected to the first reset line RST_N, the first electrode S12 of T12 is electrically connected to the first second voltage line VGH_N, and the second electrode D12 of T12 is electrically connected to the gate G10 of T10.

[0181] The gate G13 of T13 is electrically connected to the second first voltage line VGL_N2, the first electrode S13 of T13 is electrically connected to the gate G2 of T2, and the second electrode D13 of T13 is electrically connected to the gate G4 of T4.

[0182] The gate G14 of T14 is electrically connected to the second first voltage line VGL_N2, the first electrode S14 of T14 is electrically connected to the second electrode D2 of T2, and the second electrode D14 of T14 is electrically connected to the gate G6 of T6.

[0183] The first plate C2a of C2 is electrically connected to the gate G9 of T9, and the second plate C2b of C2 is electrically connected to the first second voltage line VGH_N.

[0184] Figure 3 It corresponds to Figure 2 The layout diagram shows at least one embodiment of the first driving circuit.

[0185] exist Figure 3 In the diagram, VGL_N1 is the first voltage line, VGL_N2 is the second voltage line, VGH_N is the first voltage line, NCK is the first clock signal line, NCB is the first clock signal line, NSTV is the first start signal line, and RST_N is the first reset line.

[0186] Figure 4 yes Figure 3 Layout diagram of the semiconductor layer in the middle. Figure 5 yes Figure 3 Layout diagram of the first gate metal layer in the middle. Figure 6 yes Figure 3 The layout diagram of the second gate metal layer in the middle, Figure 7 yes Figure 3 Layout diagram of the first metal layer in the middle. Figure 8 yes Figure 3 The layout diagram of the second metal layer.

[0187] exist Figures 3-8 In at least one embodiment of the first driving circuit shown, T2, T11 and T12 are dual-gate transistors, but are not limited thereto.

[0188] exist Figure 7In the diagram, the electrode labeled S9 is the first electrode of T9, the electrode labeled D9 is the second electrode of T9, the electrode labeled S10 is the first electrode of T10, and the electrode labeled D10 is the second electrode of T10.

[0189] like Figures 3-8 As shown, the orthographic projection of S9 on the substrate partially overlaps with the orthographic projection of VGL_N1 on the substrate, the orthographic projection of D9 on the substrate partially overlaps with the orthographic projection of VGL_N1 on the substrate, the orthographic projection of S10 on the substrate partially overlaps with the orthographic projection of VGL_N1 on the substrate, and the orthographic projection of D10 on the substrate partially overlaps with the orthographic projection of VGL_N1 on the substrate, in order to reduce the width of the display substrate in the horizontal direction and facilitate the realization of a narrow bezel.

[0190] Optionally, the first driving unit further includes a second first voltage line, a first first clock signal line, a first second clock signal line, a first second voltage line, a first start signal line, and a first reset line;

[0191] The first clock signal line, the first second clock signal line, and the first reset line are all disposed on the first metal layer;

[0192] The second first voltage line, the first start signal line, and the first second voltage line are all disposed on the second metal layer.

[0193] like Figure 8 As shown, the first first voltage line VGL_N1, the second first voltage line VGL_N2, the first start signal line NSTV, and the first second voltage line VGH_N are all disposed on the second metal layer;

[0194] like Figure 7 As shown, the first clock signal line NCK, the first second clock signal line NCB, and the first reset line RST_N are all located on the first metal layer;

[0195] like Figures 3-8 As shown, the orthographic projections of NCB, NCK, VGL_N2, NSTV, RST_N, VGH_N, and VGL_N1 on the substrate are arranged sequentially along the edge of the display area.

[0196] NCB, NCK, VGL_N2, NSTV, RST_N, VGH_N, and VGL_N1 can all extend in the vertical direction, but are not limited to this.

[0197] like Figures 3-8As shown, G9 and G10 are arranged in the vertical direction.

[0198] Optionally, the first driving circuit includes a first on / off control transistor and a second on / off control transistor;

[0199] The gates of the first on / off control transistor and the second on / off transistor are both electrically connected to the second first voltage line;

[0200] At least a portion of the orthographic projection of the second first voltage line onto the substrate is disposed between the orthographic projection of the gate of the first on / off control transistor onto the substrate and the orthographic projection of the gate of the second on / off control transistor onto the substrate.

[0201] like Figures 3-8 As shown, the gate G13 of the first on / off control transistor T13 and the gate G14 of the second on / off control transistor T14 are electrically connected to each other through the first conductive connection portion L1.

[0202] The first conductive connection part L1 is electrically connected to VGL_N2 through a via;

[0203] The portion of VGL_N2 projected onto the substrate is positioned between the projected portions of G13 and G14 on the substrate, so that G13 and G14 can be electrically connected to VGL_N2. VGL_N2 is positioned using the space between G13 and G14, which helps to reduce the width of the display substrate in the horizontal direction and facilitates the achievement of a narrow bezel.

[0204] In at least one embodiment of this disclosure, the orthographic projection of the first start signal line on the substrate is disposed between the orthographic projection of the second first voltage line on the substrate and the orthographic projection of the first reset line on the substrate.

[0205] like Figures 3-8 As shown, the orthographic projection of NSTV on the substrate is positioned between the orthographic projection of VGL_N2 on the substrate and the orthographic projection of RST_N on the substrate. This utilizes the space between VGL_N2 and RST_N to set up NSTV, which helps to reduce the width of the display substrate in the horizontal direction and facilitates the realization of a narrow bezel.

[0206] like Figures 3-8 As shown, the orthographic projection of the first electrode C1a of C1 on the substrate partially overlaps with the orthographic projection of NSTV on the substrate, and the orthographic projection of the second electrode C1b of C1 on the substrate partially overlaps with the orthographic projection of NSTV on the substrate.

[0207] The orthographic projection of the first electrode plate C3a of C3 onto the substrate overlaps with the orthographic projection of NSTV onto the substrate, and the orthographic projection of the second electrode plate C3b of C3 onto the substrate overlaps with the orthographic projection of NSTV onto the substrate.

[0208] The orthographic projection of the gate G6 of T6 onto the substrate is included in the orthographic projection of NSTV onto the substrate.

[0209] like Figures 3-8 As shown, T1, T3 and T14 are arranged in sequence along the vertical direction, T7, T8 and T5 are arranged in sequence along the vertical direction, and T9 and T10 are arranged in sequence along the vertical direction.

[0210] like Figures 3-8 As shown, the first plate of each capacitor and the gate of each transistor are disposed on the first gate metal layer, the second plate of each capacitor is disposed on the second gate metal layer, and the active layer of each transistor is disposed on the semiconductor layer.

[0211] exist Figure 4 In the diagram, A9 is the active layer of T9, A10 is the active layer of T10, S1 is the first electrode of T1, and D1 is the second electrode of T1; S2 is the first electrode of T2, and D2 is the second electrode of T2; S3 is the first electrode of T3, and D3 is the second electrode of T3; S4 is the first electrode of T4, and D4 is the second electrode of T4; S5 is the first electrode of T5, and D5 is the second electrode of T5; S6 is the first electrode of T6, and D6 is the second electrode of T6. The second electrode of T6; the electrode labeled S7 is the first electrode of T7, and the electrode labeled D7 is the second electrode of T7; the electrode labeled S8 is the first electrode of T8, and the electrode labeled D8 is the second electrode of T8; the electrode labeled S11 is the first electrode of T11, and the electrode labeled D11 is the second electrode of T11; the electrode labeled S12 is the first electrode of T12, and the electrode labeled D12 is the second electrode of T12; the electrode labeled S13 is the first electrode of T13, and the electrode labeled D13 is the second electrode of T13; the electrode labeled S14 is the first electrode of T14, and the electrode labeled D14 is the second electrode of T14.

[0212] exist Figure 5In the diagram, G1 is the gate of T1, G2 is the gate of T2, G3 is the gate of T3, G4 is the gate of T4, G5 is the gate of T5, G6 is the gate of T6, G7 is the gate of T7, G8 is the gate of T8, G9 is the gate of T9, G10 is the gate of T10, G11 is the gate of T11, G12 is the gate of T12, G13 is the gate of T13, and G14 is the gate of T14; C1a is the first plate of C1, C2a is the first plate of C2, and C3a is the first plate of C3.

[0213] exist Figure 6 In the diagram, the plate labeled C1b is the second plate of C1, the plate labeled C2b is the second plate of C2, and the plate labeled C3b is the second plate of C3.

[0214] Optionally, the first driving circuit is a driving circuit that generates an N-type gate driving signal, and the first driving signal is the N-type gate driving signal.

[0215] In at least one embodiment of this disclosure, the driving module includes a second driving unit; the first driving unit includes a multi-stage second driving circuit, the second driving circuit being configured to provide a second driving signal; the second driving unit includes a third first voltage line; the second driving circuit includes a second output sub-circuit; the second output sub-circuit includes a second driving transistor;

[0216] The orthogonal projection of the third first voltage line on the substrate is located on the side of the orthogonal projection of the second driving transistor on the substrate that is away from the display area;

[0217] The third first voltage line is disposed on a different layer than the first first voltage line;

[0218] The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate.

[0219] In at least one embodiment of this disclosure, the first signal line may be a first first voltage line, and the second signal line may be a third first voltage line, but is not limited thereto.

[0220] In a specific implementation, the driving module may further include a second driving unit, which can be used to provide a second driving signal. The second driving signal may be a reset control signal provided for the P-type transistor in the pixel circuit. The third first voltage line included in the second driving unit is disposed on a different layer from the first first voltage line, and the orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate, so as to reduce the width of the display substrate in the first direction and facilitate the realization of a narrow bezel.

[0221] In at least one embodiment of this disclosure, the orthographic projection of the third first voltage line on the substrate coincides with the orthographic projection of the first first voltage line on the substrate, thus achieving the best effect of narrow bezel.

[0222] Optionally, the first voltage line is disposed on the second metal layer, and the third voltage line is disposed on the third metal layer; or,

[0223] The first voltage line is disposed on the third metal layer, and the third voltage line is disposed on the second metal layer.

[0224] like Figure 9 As shown, at least one embodiment of the second driving circuit includes a second output sub-circuit 90; the second output sub-circuit 90 includes a second driving transistor T19 and a second driving reset transistor T18;

[0225] At least one embodiment of the second driving circuit further includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a fourth capacitor C4, and a fifth capacitor C5;

[0226] The gate of T15 is electrically connected to the second first clock signal line RCK, the first electrode of T15 is electrically connected to the second input terminal I2, and the second electrode of T15 is electrically connected to the gate of T17.

[0227] The first electrode of T17 is electrically connected to the second first clock signal line RCK, and the second electrode of T17 is electrically connected to the gate of T18.

[0228] The gate of T16 is electrically connected to the second first clock signal line RCK, the first electrode of T16 is electrically connected to the third first voltage line VGL_R, and the second electrode of T16 is electrically connected to the gate of T20.

[0229] The gate of T18 is electrically connected to the first plate of C4, the first electrode of T18 is electrically connected to the second voltage line VGH_R, and the second electrode of T18 is electrically connected to the second drive signal output terminal O2.

[0230] The gate of T19 is electrically connected to the first plate of C5, the first electrode of T19 is electrically connected to the second drive signal output terminal O2, and the second electrode of T19 is electrically connected to the second clock signal line RCB.

[0231] The gate of T20 is electrically connected to the gate of T18, the first electrode of T20 is electrically connected to the second voltage line VGH_R, and the second electrode of T20 is electrically connected to the first electrode of T21.

[0232] The gate of T21 is electrically connected to the second clock signal line RCB, and the second electrode of T21 is electrically connected to the gate of T17.

[0233] The gate of T22 is electrically connected to the third first voltage line VGL_R, the first electrode of T22 is electrically connected to the gate of T17, and the second electrode of T22 is electrically connected to the gate of T19.

[0234] The second electrode of C4 is electrically connected to the second second voltage line VGH_R;

[0235] The second electrode of C5 is electrically connected to the second drive signal output terminal O2.

[0236] exist Figure 9 In at least one embodiment of the second driving circuit shown, each transistor is a P-type transistor, but this is not a limitation.

[0237] Figure 10 Is Figure 9 This is a schematic diagram showing the electrodes of each transistor and the plates of each capacitor.

[0238] like Figure 10 As shown, the gate G15 of T15 is electrically connected to the second clock signal line RCB, the first electrode S15 of T15 is electrically connected to the second input terminal I2, and the second electrode D15 of T15 is electrically connected to the gate G17 of T17.

[0239] The first electrode S17 of T17 is electrically connected to the second first clock signal line RCK, and the second electrode D17 of T17 is electrically connected to the gate of T18.

[0240] The gate G16 of T16 is electrically connected to the second first clock signal line RCK, the first electrode S16 of T16 is electrically connected to the third first voltage line VGL_R, and the second electrode D16 of T16 is electrically connected to the gate of T20.

[0241] The gate G18 of T18 is electrically connected to the first plate C4a of C4, the first electrode S18 of T18 is electrically connected to the second voltage line VGH_R, and the second electrode D18 of T18 is electrically connected to the second drive signal output terminal O2.

[0242] The gate G19 of T19 is electrically connected to the first plate C5a of C5, the first electrode S19 of T19 is electrically connected to the second drive signal output terminal O2, and the second electrode D19 of T19 is electrically connected to the second clock signal line RCB.

[0243] The gate G20 of T20 is electrically connected to the gate G18 of T18, the first electrode S20 of T20 is electrically connected to the second voltage line VGH_R, and the second electrode D20 of T20 is electrically connected to the first electrode S21 of T21.

[0244] The gate G21 of T21 is electrically connected to the second clock signal line RCB, and the second electrode D21 of T21 is electrically connected to the gate G17 of T17.

[0245] The gate G22 of T22 is electrically connected to the third first voltage line VGL_R, the first electrode S22 of T22 is electrically connected to the gate G17 of T17, and the second electrode D22 of T22 is electrically connected to the gate G19 of T19.

[0246] The second plate C4b of C4 is electrically connected to the second voltage line VGH_R.

[0247] The second electrode plate C5b of C5 is electrically connected to the second drive signal output terminal O2.

[0248] In at least one embodiment of this disclosure, the second driving unit further includes a second start signal line, a second first clock signal line, a second second clock signal line, and a second second voltage line;

[0249] The third first voltage line, the second start signal line, the second first clock signal line, the second second clock signal line, and the second second voltage line are arranged sequentially along the direction closest to the display area.

[0250] Figure 11 It corresponds to Figure 10 The layout diagram shows at least one embodiment of the second driving circuit. Figure 12 yes Figure 11 Layout diagram of the semiconductor layer in the middle. Figure 13 yes Figure 11 Layout diagram of the first gate metal layer in the middle. Figure 14 yes Figure 11 The layout diagram of the second gate metal layer in the middle, Figure 15 yes Figure 11 Layout diagram of the first metal layer in the middle. Figure 16 yes Figure 11 The layout diagram of the second metal layer in the middle, Figure 17 yes Figure 11 The layout diagram of the third metal layer.

[0251] like Figures 11-17 As shown, the gate of each transistor and the first plate of each capacitor are disposed on the first gate metal layer, the second plate of each capacitor is disposed on the second gate metal layer, and the active layer of each transistor is disposed on the semiconductor layer.

[0252] like Figures 11-17 As shown, the second start signal line RSTV, the second first clock signal line RCK, the second second clock signal line RCB, and the second second voltage line VGH_R are all disposed on the second metal layer;

[0253] The third first voltage line VGL_R is set on the third metal layer.

[0254] In at least one embodiment of this disclosure, when VGL_R is disposed on the third metal layer, VGL_N1 can be disposed on the second metal layer. The orthographic projection of VGL_R on the substrate can at least partially overlap with the orthographic projection of VGL_N1 on the substrate, thereby reducing the width of the display substrate in the horizontal direction and facilitating the realization of a narrow bezel.

[0255] In practice, VGL_R can be set on the second metal layer, and VGL_N1 can be set on the third metal layer.

[0256] like Figures 11-17 As shown, the orthographic projection of the third first voltage line VGL_R on the substrate is disposed on the side of the orthographic projection of the gate G19 of the second driving transistor T19 on the substrate away from the display area, so that VGL_R and VGL_N1 overlap each other.

[0257] Optionally, the second output sub-circuit may further include a second drive reset transistor;

[0258] The orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second driving transistor on the substrate, and the orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second driving transistor on the substrate.

[0259] The orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second drive reset transistor on the substrate, and the orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second drive reset transistor on the substrate.

[0260] like Figures 11-17 As shown, the orthographic projection of the second start signal line RSTV on the substrate overlaps with the orthographic projection of the first electrode S19 of the second driving transistor T19 on the substrate, the orthographic projection of the second start signal line RSTV on the substrate overlaps with the orthographic projection of the second electrode D19 of the second driving transistor T19 on the substrate, the orthographic projection of the second start signal line RSTV on the substrate overlaps with the orthographic projection of the first electrode S18 of the second driving reset transistor T18 on the substrate, and the orthographic projection of the second start signal line RSTV on the substrate overlaps with the orthographic projection of the second electrode D18 of the second driving reset transistor T18 on the substrate. This can reduce the width of the display substrate along the first direction, which is beneficial for achieving a narrow bezel.

[0261] Optionally, the second driving circuit further includes a fifteenth transistor, a twentieth transistor, and a twenty-first transistor;

[0262] The gate of the fifteenth transistor is electrically connected to the second first clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the second electrode of the twenty-first transistor; the first electrode of the twenty-first transistor is electrically connected to the second electrode of the twentyth transistor.

[0263] The gate of the twentieth transistor is electrically connected to the gate of the second drive reset transistor, and the gate of the twentieth eleventh transistor is electrically connected to the second clock signal line.

[0264] The orthographic projection of the gate of the fifteenth transistor on the substrate, the orthographic projection of the gate of the twentieth transistor on the substrate, and the orthographic projection of the gate of the twenty-first transistor on the substrate are disposed between the orthographic projection of the second clock signal line on the substrate and the orthographic projection of the second voltage line on the substrate.

[0265] Optionally, the second driving circuit further includes a sixteenth transistor;

[0266] The gate of the sixteenth transistor is electrically connected to the second electrode of the fifteenth transistor, the first electrode of the sixteenth transistor is electrically connected to the second first clock signal line, and the second electrode of the sixteenth transistor is electrically connected to the gate of the drive reset transistor.

[0267] The orthographic projection of the gate of the sixteenth transistor on the substrate is positioned between the orthographic projection of the second first clock signal line on the substrate and the orthographic projection of the second second clock signal line on the substrate.

[0268] like Figures 11-17As shown, the orthographic projections of gate G15 of T15, gate G20 of T20, and gate G21 of T21 on the substrate are arranged sequentially in the vertical direction.

[0269] The orthographic projections of G15, G20, and G21 on the substrate can all be positioned between the orthographic projection of the second clock signal line RCB on the substrate and the orthographic projection of the second voltage line VGH_R on the substrate, in order to reduce the width of the display substrate in the horizontal direction and facilitate the realization of a narrow bezel.

[0270] like Figures 11-17 As shown, the orthographic projection of the gate G16 of T16 on the substrate is positioned between the orthographic projection of the second first clock signal line RCK on the substrate and the orthographic projection of the second second clock signal line RCB on the substrate, in order to reduce the width of the display substrate in the horizontal direction and facilitate the realization of a narrow bezel.

[0271] like Figures 11-17 As shown, the orthographic projection of the gate G22 of T22 on the substrate is located within the orthographic projection of the second first clock signal line RCK on the substrate, and the orthographic projection of the gate G17 of T17 on the substrate is located within the orthographic projection of the second second clock signal line RCB on the substrate.

[0272] The orthographic projection of the first plate C4a of the fourth capacitor C4 onto the substrate partially overlaps with the orthographic projection of the second first clock signal line RCK onto the substrate. The orthographic projection of the second plate C4b of the fourth capacitor C4 onto the substrate partially overlaps with the orthographic projection of the second first clock signal line RCK onto the substrate.

[0273] In at least one embodiment of this disclosure, the orthogonal projection of the transistors included in the second driving circuit on the substrate is disposed on the side of the orthogonal projection of the third first voltage line on the substrate closer to the display area.

[0274] like Figures 11-17 As shown, the orthographic projections of the gate G15 of T15, the gate G16 of T16, the gate G17 of T17, the gate G18 of T18, the gate G19 of T19, the gate G20 of T20, the gate G21 of T21, and the gate G22 of T22 on the substrate are all located on the side of the orthographic projection of the third first voltage line VGL_R on the substrate that is close to the display area.

[0275] like Figure 18A As shown, the orthographic projection of the third first voltage line VGL_R on the substrate overlaps with the orthographic projection of VGL_N1 on the substrate; VGL_N1 is disposed on the second metal layer, and VGL_R is disposed on the third metal layer.

[0276] Figure 18B yes Figure 18A Cross-sectional view of A-A'.

[0277] exist Figure 18B In the diagram, 180 is the substrate, 181 is the semiconductor layer, 182 is the first insulating layer, 183 is the first gate metal layer, 184 is the second insulating layer, 185 is the third insulating layer, 186 is the first metal layer, 187 is the fourth insulating layer, 188 (marked in red) is the second metal layer, 189 is the fifth insulating layer, and 1810 is the third metal layer.

[0278] Figure 18C for Figure 18A The layout diagram of the second metal layer in the middle, Figure 18D This is a layout diagram of the third metal layer in 18A.

[0279] In at least one embodiment of this disclosure, T9, T10, VGL_R, and VGL_N1 are overlapped. VGL_N1 has a shielding effect, which can reduce the parasitic capacitance between T9 and VGL_N1, and reduce the parasitic capacitance between T10 and VGL_N1. Since VGL_N1 and VGL_R are DC voltage lines, their overlap has a relatively small impact.

[0280] like Figure 12 As shown, layer A18 is the active layer of T18, and layer A19 is the active layer of T19.

[0281] The electrode labeled S15 is the first electrode of T15, and the electrode labeled D15 is the second electrode of T15; the electrode labeled S16 is the first electrode of T16, and the electrode labeled D16 is the second electrode of T16; the electrode labeled S17 is the first electrode of T17, and the electrode labeled D17 is the second electrode of T17; the electrode labeled S20 is the first electrode of T20, and the electrode labeled D20 is the second electrode of T20; the electrode labeled S21 is the first electrode of T21, and the electrode labeled D21 is the second electrode of T21; the electrode labeled S22 is the first electrode of T22, and the electrode labeled D22 is the second electrode of T22.

[0282] like Figure 13As shown, the gate labeled G15 is the gate of T15, the gate labeled G16 is the gate of T16, the gate labeled G17 is the gate of T17, the gate labeled G18 is the gate of T18, the gate labeled G19 is the gate of T19, the gate labeled G20 is the gate of T20, the gate labeled G21 is the gate of T21, and the gate labeled G22 is the gate of T22.

[0283] The plate labeled C4a is the first plate of C4, and the plate labeled C5a is the first plate of C5.

[0284] like Figure 14 As shown, the plate labeled C4b is the second plate of C4, and the plate labeled C5b is the second plate of C5.

[0285] like Figure 15 As shown, the electrode labeled S18 is the first electrode of T18, and the electrode labeled D18 is the second electrode of T18; the electrode labeled S19 is the first electrode of T19, and the electrode labeled D19 is the second electrode of T19.

[0286] Optionally, the substrate includes a peripheral region and a display region; the driving units included in the driving module are all disposed in the peripheral region of the substrate.

[0287] The first driving unit is located on the side of the second driving unit that is away from the display area.

[0288] like Figure 19 As shown, the substrate includes a peripheral region B0 and a display region A0;

[0289] The first drive unit GA1 and the second drive unit GA2 are both located in the surrounding area B0;

[0290] The first driving unit GA1 is located on the side of the second driving unit GA2 that is away from the display area A0.

[0291] Figure 20 It corresponds to Figure 10 Another layout diagram of at least one embodiment of the second driving circuit shown.

[0292] Figure 21 yes Figure 20 Layout diagram of the semiconductor layer in the middle. Figure 22 yes Figure 20 Layout diagram of the first gate metal layer in the middle. Figure 23 yes Figure 20 The layout diagram of the second gate metal layer in the middle, Figure 24 yes Figure 22 Layout diagram of the first metal layer in the middle. Figure 25 yes Figure 22 The layout diagram of the second metal layer.

[0293] exist Figure 21 In the diagram, layer A18 is the active layer of T18, and layer A19 is the active layer of T19.

[0294] The electrode labeled S15 is the first electrode of T15, and the electrode labeled D15 is the second electrode of T15; the electrode labeled S16 is the first electrode of T16, and the electrode labeled D16 is the second electrode of T16; the electrode labeled S17 is the first electrode of T17, and the electrode labeled D17 is the second electrode of T17; the electrode labeled S20 is the first electrode of T20, and the electrode labeled D20 is the second electrode of T20; the electrode labeled S21 is the first electrode of T21, and the electrode labeled D21 is the second electrode of T21; the electrode labeled S22 is the first electrode of T22, and the electrode labeled D22 is the second electrode of T22.

[0295] like Figure 22 As shown, the gate labeled G15 is the gate of T15, the gate labeled G16 is the gate of T16, the gate labeled G17 is the gate of T17, the gate labeled G18 is the gate of T18, the gate labeled G19 is the gate of T19, the gate labeled G20 is the gate of T20, the gate labeled G21 is the gate of T21, and the gate labeled G22 is the gate of T22.

[0296] The plate labeled C4a is the first plate of C4, and the plate labeled C5a is the first plate of C5.

[0297] like Figure 23 As shown, the plate labeled C4b is the second plate of C4, and the plate labeled C5b is the second plate of C5.

[0298] like Figure 24 As shown, the electrode labeled S18 is the first electrode of T18, and the electrode labeled D18 is the second electrode of T18; the electrode labeled S19 is the first electrode of T19, the electrode labeled D19 is the second electrode of T19, and the electrode labeled VGL_R is the third first voltage line VGL_R.

[0299] exist Figure 25 In the diagram, VGH_R is the second voltage line, RCB is the second clock signal line, RCK is the second clock signal line, and RSTV is the second start signal line.

[0300] like Figures 20-25 As shown, VGH_R, RCB, VGL_R, RCK, and RSTV are arranged sequentially along the direction closest to the display area.

[0301] Figure 26 yes Figure 3 At least one embodiment of the first driving circuit shown and Figure 20A schematic diagram showing the arrangement of at least one embodiment of the second driving circuit.

[0302] In at least one embodiment of this disclosure, the drive module includes a third drive unit, the third drive unit includes a multi-stage third drive circuit, and the third drive circuit is configured to provide a third drive signal;

[0303] The third drive unit is located on the side of the first drive unit away from the second drive unit.

[0304] In a specific implementation, the drive module may further include a third drive unit, the third drive unit including a third drive circuit configured to provide a third drive signal, and the third drive unit may be located on the side of the first drive unit away from the second drive unit.

[0305] Optionally, the third driving signal can be a light emission control signal, but is not limited thereto.

[0306] like Figure 27A As shown, at least one embodiment of the third driving circuit includes a third output sub-circuit;

[0307] The third output sub-circuit includes a third driving transistor T31 and a third driving reset transistor T32;

[0308] The third driving circuit also includes the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, the thirtieth transistor T30, the thirty-third transistor T33, the thirty-fourth transistor T34, the third on / off control transistor T35, the fourth on / off control transistor T36, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8;

[0309] The gate of T23 is electrically connected to the third second clock signal line ECB, the first electrode of T23 is electrically connected to the third input terminal I3, and the second electrode of T23 is electrically connected to the gate G24 of T24.

[0310] The first electrode of T24 is electrically connected to the three second clock signal lines ECB, and the second electrode of T24 is electrically connected to the second electrode D25 of T25.

[0311] The gate of T25 is electrically connected to the third second clock signal line ECB, and the first electrode of T25 is electrically connected to the fifth first voltage line VGL_E2.

[0312] The gate of T26 is electrically connected to the gate of T27; the first electrode of T26 is electrically connected to the third first clock signal line ECK; the second electrode of T26 is electrically connected to the first plate C8a of C8; and the second plate of C8 is electrically connected to the gate of T27.

[0313] The gate of T27 is electrically connected to the first electrode of T27, and the second electrode of T27 is electrically connected to the gate of T32;

[0314] The gate of T28 is electrically connected to the first plate of C6, the first electrode of T28 is electrically connected to the third first clock signal line ECK, and the second electrode of T28 is electrically connected to the second plate of C6.

[0315] The gate of T29 is electrically connected to the third first clock signal line ECK, the first electrode of T29 is electrically connected to the second plate of C6, and the second electrode of T29 is electrically connected to the gate of T31.

[0316] The gate of T30 is electrically connected to the gate of T24, the first electrode of T30 is electrically connected to the third second voltage line VGH_E, and the second electrode of T30 is electrically connected to the gate of T31 G31.

[0317] The first electrode of T31 is electrically connected to the third second voltage line VGH_E, and the second electrode of T31 is electrically connected to the third drive signal output terminal O3.

[0318] The first electrode of T32 is electrically connected to the third drive signal output terminal O3, and the second electrode of T32 is electrically connected to the fourth first voltage line VGL_E1.

[0319] The gate of T33 is electrically connected to the second electrode of T28, the first electrode of T33 is electrically connected to the third second voltage line VGH_E, and the second electrode of T33 is electrically connected to the gate of T32.

[0320] The gate of T34 is electrically connected to the third reset line RST_, the first electrode of T34 is electrically connected to the third second voltage line VGH_E, and the second electrode of T34 is electrically connected to the gate of T32.

[0321] The gate of T35 is electrically connected to the fifth first voltage line VGL_E2, the first electrode of T35 is electrically connected to the gate of T24, and the second electrode of T35 is electrically connected to the gate of T26.

[0322] The gate of T36 is electrically connected to the fifth first voltage line VGL_E2, the first electrode of T36 is electrically connected to the second electrode of T24, and the second electrode of T36 is electrically connected to the gate of T28.

[0323] The first plate of C7 is electrically connected to the gate of T31, and the second plate of C7 is electrically connected to the third second voltage line VGH_E.

[0324] like Figure 27B As shown, at least one embodiment of the third driving circuit includes a third output sub-circuit;

[0325] The third output sub-circuit includes a third driving transistor T31 and a third driving reset transistor T32;

[0326] The third driving circuit also includes the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, the thirtieth transistor T30, the thirty-third transistor T33, the thirty-fourth transistor T34, the third on / off control transistor T35, the fourth on / off control transistor T36, the sixth capacitor C6, the seventh capacitor C7, and the eighth capacitor C8;

[0327] The gate G23 of T23 is electrically connected to the third second clock signal line ECB, the first electrode S23 of T23 is electrically connected to the third input terminal I3, and the second electrode D23 of T23 is electrically connected to the gate G24 of T24.

[0328] The first electrode S24 of T24 is electrically connected to the three second clock signal lines ECB, and the second electrode D24 of T24 is electrically connected to the second electrode D25 of T25.

[0329] The gate G25 of T25 is electrically connected to the third second clock signal line ECB, and the first electrode S25 of T25 is electrically connected to the fifth first voltage line VGL_E2.

[0330] The gate G26 of T26 is electrically connected to the gate G27 of T27. The first electrode S26 of T26 is electrically connected to the third first clock signal line ECK. The second electrode D26 of T26 is electrically connected to the first plate C8a of C8. The second plate C8b of C8 is electrically connected to the gate G27 of T27.

[0331] The gate G27 of T27 is electrically connected to the first electrode S27 of T27, and the second electrode D27 of T27 is electrically connected to the gate G32 of T32.

[0332] The gate G28 of T28 is electrically connected to the first plate C6a of C6, the first electrode S28 of T28 is electrically connected to the third first clock signal line ECK, and the second electrode D28 of T28 is electrically connected to the second plate C6b of C6.

[0333] The gate G29 of T29 is electrically connected to the third first clock signal line ECK, the first electrode S29 of T29 is electrically connected to the second plate C6b of C6, and the second electrode D29 of T29 is electrically connected to the gate G31 of T31.

[0334] The gate G30 of T30 is electrically connected to the gate G24 of T24, the first electrode S30 of T30 is electrically connected to the third second voltage line VGH_E, and the second electrode D30 of T30 is electrically connected to the gate G31 of T31.

[0335] The first electrode S31 of T31 is electrically connected to the third second voltage line VGH_E, and the second electrode D31 of T31 is electrically connected to the third drive signal output terminal O3.

[0336] The first electrode S32 of T32 is electrically connected to the third drive signal output terminal O3, and the second electrode D32 of T32 is electrically connected to the fourth first voltage line VGL_E1.

[0337] The gate G33 of T33 is electrically connected to the second electrode D28 of T28, the first electrode S33 of T33 is electrically connected to the third second voltage line VGH_E, and the second electrode D33 of T33 is electrically connected to the gate G32 of T32.

[0338] The gate G34 of T34 is electrically connected to the third reset line RST_E, the first electrode S34 of T34 is electrically connected to the third second voltage line VGH_E, and the second electrode D34 of T34 is electrically connected to the gate G32 of T32.

[0339] The gate G35 of T35 is electrically connected to the fifth first voltage line VGL_E2, the first electrode S35 of T35 is electrically connected to the gate G24 of T24, and the second electrode D35 of T35 is electrically connected to the gate G26 of T26.

[0340] The gate G36 of T36 is electrically connected to the fifth first voltage line VGL_E2, the first electrode S36 of T36 is electrically connected to the second electrode D24 of T24, and the second electrode D36 of T36 is electrically connected to the gate G28 of T28.

[0341] The first plate C7a of C7 is electrically connected to the gate G31 of T31, and the second plate C7b of C7 is electrically connected to the third second voltage line VGH_E.

[0342] exist Figure 27A , Figure 27B In at least one embodiment of the third driving circuit shown, all transistors are P-type transistors, but this is not a limitation.

[0343] Figure 28 yes Figure 27BThe layout diagram corresponding to at least one embodiment of the third driving circuit shown is as follows. Figure 29 yes Figure 28 Layout diagram of the semiconductor layer in the middle. Figure 30 yes Figure 28 Layout diagram of the first gate metal layer in the middle. Figure 31 yes Figure 28 The layout diagram of the second gate metal layer in the middle, Figure 32 This is the layout diagram of the first metal layer in 28.

[0344] like Figures 28-32 As shown, the first plate of each capacitor and the gate of each transistor are disposed on the first gate metal layer, the second plate of each capacitor is disposed on the second gate metal layer, and the active layer of each transistor is disposed on the semiconductor layer.

[0345] exist Figure 28 and Figure 32 In the diagram, ESTV is the third start signal line, ECK is the third first clock signal line, ECB is the third second clock signal line, RST_E is the third reset line, VGH_E is the third second voltage line, VGL_E1 is the fourth first voltage line, and VGL_E2 is the fifth first voltage line.

[0346] like Figure 32 As shown, ESTV, ECK, ECB, RST_E, VGH_E, VGL_E1, and VGL_E2 are all set on the first metal layer.

[0347] exist Figures 28-32 In at least one embodiment of the corresponding third driving circuit, T33 and T34 are dual-gate transistors, but are not limited thereto.

[0348] exist Figure 29In the diagram, A31 is the active layer of T31, A32 is the active layer of T32, S23 is the first electrode of T23, D23 is the second electrode of T23; S24 is the first electrode of T24, D24 is the second electrode of T24; S25 is the first electrode of T25, D25 is the second electrode of T25; S26 is the first electrode of T26, D26 is the second electrode of T26; S27 is the first electrode of T27, D27 is the second electrode of T27; and S28 is the first electrode of T28. The electrode labeled D28 is the second electrode of T28; the electrode labeled S29 is the first electrode of T29, and the electrode labeled D29 is the second electrode of T29; the electrode labeled S30 is the first electrode of T30, and the electrode labeled D30 is the second electrode of T30; the electrode labeled S33 is the first electrode of T33, and the electrode labeled D33 is the second electrode of T33; the electrode labeled S34 is the first electrode of T34, and the electrode labeled D34 is the second electrode of T34; the electrode labeled S35 is the first electrode of T35, and the electrode labeled D35 is the second electrode of T35; the electrode labeled S36 is the first electrode of T36, and the electrode labeled D36 is the second electrode of T36.

[0349] exist Figure 30 In the diagram, G23 is the gate of T23, G24 is the gate of T24, G25 is the gate of T25, G26 is the gate of T26, G27 is the gate of T27, G28 is the gate of T28, G29 is the gate of T29, G30 is the gate of T30, G31 is the gate of T31, G32 is the gate of T32, G33 is the gate of T33, G34 is the gate of T34, G35 is the gate of T35, G36 is the gate of T36, C6a is the first plate of C6, C7a is the first plate of C7, and C8a is the first plate of C8.

[0350] exist Figure 31 In the diagram, the plate labeled C6b is the second plate of C6, the plate labeled C7b is the second plate of C7, and the plate labeled C8b is the second plate of C8.

[0351] In at least one embodiment of this disclosure, the driving module includes a fourth driving unit, the driving unit includes a multi-stage fourth driving circuit, the fourth driving circuit is used to provide a fourth driving signal, the fourth driving signal is a P-type gate driving signal;

[0352] The fourth driving unit is located on the side of the second driving unit that is close to the display area.

[0353] In specific implementations, the P-type gate drive signal may be a high-level active gate drive signal provided to the P-type transistors included in the pixel circuit, but is not limited thereto.

[0354] like Figure 33A As shown, at least one embodiment of the fourth driving circuit includes a fourth output sub-circuit, which includes a fourth driving transistor T42 and a fourth driving reset transistor T41.

[0355] At least one embodiment of the fourth driving circuit further includes the thirty-seventh transistor T37, the thirty-eighth transistor T38, the thirty-ninth transistor T39, the fortieth transistor T40, the forty-third transistor T43, the forty-fourth transistor T44, the forty-fifth transistor T45, the forty-sixth transistor T46, the ninth capacitor C9, and the tenth capacitor C10.

[0356] The gate of T37 is electrically connected to the first clock signal terminal GCK1, the first electrode of T37 is electrically connected to the fourth input terminal I4, and the second electrode of T37 is electrically connected to the first electrode of T38.

[0357] The gate of T38 is electrically connected to the gate of T37, and the second electrode of T38 is electrically connected to the gate of T42;

[0358] The gate of T39 is electrically connected to the third clock signal terminal GCK3, the first electrode of T39 is electrically connected to the first voltage terminal VGL_G, and the second electrode of T39 is electrically connected to the gate of T41 G41.

[0359] The gate of T40 is electrically connected to the fourth input terminal I4, the first electrode of T40 is electrically connected to the second voltage terminal VGH_G, and the second electrode of T40 is electrically connected to the gate G41 of T41.

[0360] The gate of T41 is electrically connected to the first electrode of C10, the first electrode of T41 is electrically connected to the second voltage terminal VGH_G, and the second electrode of T41 is electrically connected to the fourth drive signal output terminal O4.

[0361] The gate of T42 is electrically connected to the first electrode of C9, and the first electrode of T42 is electrically connected to the fourth drive signal output terminal O4; the second electrode of T42 is electrically connected to the second clock signal terminal GCK2.

[0362] The gate of T43 is electrically connected to the gate of T41, the first electrode of T43 is electrically connected to the second voltage terminal VGH_G, and the second electrode of T43 is electrically connected to the first electrode of T44.

[0363] The gate of T44 is electrically connected to the second electrode of T40; the second electrode of T44 is electrically connected to the gate of T42.

[0364] The gate of T45 is electrically connected to the fourth drive signal output terminal O4, the first electrode of T45 is electrically connected to the second clock signal terminal GCK2, and the second electrode of T45 is electrically connected to the second electrode D37 of T37.

[0365] The gate of T46 is electrically connected to the gate of T42, the first electrode of T46 is electrically connected to the second electrode of T43, and the second electrode of T46 is electrically connected to the first voltage terminal VGL_G.

[0366] The second electrode of C9 is electrically connected to the fourth drive signal output terminal O4, and the second electrode of C10 is electrically connected to the second voltage terminal VGH_G.

[0367] like Figure 33B As shown, at least one embodiment of the fourth driving circuit includes a fourth output sub-circuit, which includes a fourth driving transistor T42 and a fourth driving reset transistor T41.

[0368] At least one embodiment of the fourth driving circuit further includes the thirty-seventh transistor T37, the thirty-eighth transistor T38, the thirty-ninth transistor T39, the fortieth transistor T40, the forty-third transistor T43, the forty-fourth transistor T44, the forty-fifth transistor T45, the forty-sixth transistor T46, the ninth capacitor C9, and the tenth capacitor C10.

[0369] The gate G37 of T37 is electrically connected to the first clock signal terminal GCK1, the first electrode S37 of T37 is electrically connected to the fourth input terminal I4, and the second electrode D37 of T37 is electrically connected to the first electrode S38 of T38.

[0370] The gate G38 of T38 is electrically connected to the gate G37 of T37, and the second electrode D38 of T38 is electrically connected to the gate G42 of T42.

[0371] The gate G39 of T39 is electrically connected to the third clock signal terminal GCK3, the first electrode S39 of T39 is electrically connected to the first voltage terminal VGL_G, and the second electrode D39 of T39 is electrically connected to the gate G41 of T41.

[0372] The gate G40 of T40 is electrically connected to the fourth input terminal I4, the first electrode S40 of T40 is electrically connected to the second voltage terminal VGH_G, and the second electrode D40 of T40 is electrically connected to the gate G41 of T41.

[0373] The gate G41 of T41 is electrically connected to the first plate C10a of C10, the first electrode S41 of T41 is electrically connected to the second voltage terminal VGH_G, and the second electrode D41 of T41 is electrically connected to the fourth drive signal output terminal O4.

[0374] The gate G42 of T42 is electrically connected to the first plate C9a of C9; the first electrode S42 of T42 is electrically connected to the four drive signal output terminal O4; the second electrode D42 of T42 is electrically connected to the second clock signal terminal GCK2.

[0375] The gate G43 of T43 is electrically connected to the gate G411 of T41, the first electrode S43 of T43 is electrically connected to the second voltage terminal VGH_G, and the second electrode D43 of T43 is electrically connected to the first electrode S44 of T44.

[0376] The gate G44 of T44 is electrically connected to the second electrode D40 of T40; the second electrode D44 of T44 is electrically connected to the gate G42 of T42.

[0377] The gate G45 of T45 is electrically connected to the fourth drive signal output terminal O4, the first electrode S45 of T45 is electrically connected to the second clock signal terminal GCK2, and the second electrode D45 of T45 is electrically connected to the second electrode D37 of T37.

[0378] The gate G46 of T46 is electrically connected to the gate G42 of T42, the first electrode S46 of T46 is electrically connected to the second electrode D43 of T43, and the second electrode D46 of T46 is electrically connected to the first voltage terminal VGL_G.

[0379] The second electrode plate C9b of C9 is electrically connected to the fourth drive signal output terminal O4, and the second electrode plate C10b of C10 is electrically connected to the second voltage terminal VGH_G.

[0380] exist Figure 33A , Figure 33B In at least one embodiment of the fourth driving circuit shown, all transistors are P-type transistors, but this is not a limitation.

[0381] Figure 34 yes Figure 33B The layout diagram corresponds to at least one embodiment of the fourth driving circuit shown. Figure 35 yes Figure 34 Layout diagram of the semiconductor layer in the middle. Figure 36 yes Figure 34 Layout diagram of the first gate metal layer in the middle. Figure 37 yes Figure 34 The layout diagram of the second gate metal layer in the middle, Figure 38 yes Figure 34 The layout diagram of the first metal layer in the middle.

[0382] exist Figure 34 Based on the layout diagram, the display substrate may also include a second metal layer. Figure 39 This is a layout diagram of the added second metal layer.

[0383] exist Figure 35 In the diagram, A41 is the active layer of T41, A42 is the active layer of T42, S37 is the first electrode of T37, D37 is the second electrode of T37, S38 is the first electrode of T38, D38 is the second electrode of T38, S39 is the first electrode of T39, D39 is the second electrode of T39, S40 is the first electrode of T40, D40 is the second electrode of T40, S43 is the first electrode of T43, D43 is the second electrode of T43, S44 is the first electrode of T44, D44 is the second electrode of T44, S45 is the first electrode of T45, D45 is the second electrode of T45, S46 is the first electrode of T46, D46 is the second electrode of T46.

[0384] exist Figure 36 In the diagram, the gate of T37 is labeled G37, the gate of T38 is labeled G38, the gate of T39 is labeled G39, the gate of T40 is labeled G40, the gate of T41 is labeled G41, the gate of T42 is labeled G42, the gate of T43 is labeled G43, the gate of T44 is labeled G44, the gate of T45 is labeled G45, and the gate of T45 is labeled G45; the first electrode of C9 is labeled C9a, and the first electrode of C10 is labeled C10a.

[0385] exist Figure 38 In the diagram, the plate labeled C9b is the second plate of C9, and the plate labeled C10b is the second plate of C10.

[0386] exist Figure 38 In the diagram, S41 is the source of T41, D41 is the drain of T41, S42 is the source of T42, and D42 is the drain of T42.

[0387] exist Figures 34 to 38 In the diagram, GCK1_E1 is the first clock signal line of the first even-numbered row, GCK2_E1 is the second clock signal line of the first even-numbered row, GCK3_E1 is the third clock signal line of the first even-numbered row, GSTV_P1 is the first fourth start signal line, VGL_P1 is the first third voltage line, GCK1_O1 is the first clock signal line of the first odd-numbered row, GCK2_O1 is the second clock signal line of the first odd-numbered row, GCK3_O1 is the third clock signal line of the first odd-numbered row, and VGH_P1 is the first fourth voltage line.

[0388] like Figure 39As shown, GCK1_E2 is the first clock signal line of the second even-numbered row, GCK2_E2 is the second clock signal line of the second even-numbered row, GCK3_E2 is the third clock signal line of the second even-numbered row, GSTV_P2 is the second fourth start signal line, VGL_P2 is the second third voltage line, GCK1_O2 is the first clock signal line of the second odd-numbered row, GCK2_O2 is the second clock signal line of the second odd-numbered row, GCK3_O2 is the third clock signal line of the second odd-numbered row, and VGH_P2 is the second fourth voltage line.

[0389] exist Figure 34 In the corresponding embodiment, in the fourth driving circuit, the first voltage terminal VGL_G is electrically connected to the first third voltage line VGL_P1, and the second voltage terminal VGH_G is electrically connected to the first fourth voltage line VGH_P1.

[0390] In the fourth driving circuit of the even row, the first clock signal terminal GCK1 is electrically connected to the first clock signal line GCK1_E1 of the first even row, the second clock signal terminal GCK2 is electrically connected to the second clock signal line GCK2_E1 of the first even row, and the third clock signal terminal GCK3 is electrically connected to the third clock signal line GCK3_E1 of the first even row.

[0391] In the fourth driving circuit of the odd row, the first clock signal terminal GCK1 is electrically connected to the first clock signal line GCK1_O1 of the first odd row, the second clock signal terminal GCK2 is electrically connected to the second clock signal line GCK2_O1 of the first odd row, and the third clock signal terminal GCK3 is electrically connected to the third clock signal line GCK3_O1 of the first odd row.

[0392] In at least one embodiment of this disclosure, the first clock signal line GCK1_E2 of the second even-numbered row is electrically connected to the first clock signal line GCK1_E1 of the first even-numbered row via a via, the second clock signal line GCK2_E2 of the second even-numbered row is electrically connected to the second clock signal line GCK2_E1 of the first even-numbered row via a via, and the third clock signal line GCK3_E2 of the second even-numbered row is electrically connected to the third clock signal line GCK3_E1 of the first even-numbered row via a via, so as to reduce the loading of each clock signal line;

[0393] The first clock signal line GCK1_O2 of the second odd-numbered row is electrically connected to the first clock signal line GCK1_O1 of the first odd-numbered row via a via, the second clock signal line GCK2_O2 of the second odd-numbered row is electrically connected to the second clock signal line GCK2_O1 of the first odd-numbered row via a via, and the third clock signal line GCK3_O2 of the second odd-numbered row is electrically connected to the third clock signal line GCK3_O1 of the first odd-numbered row via a via, in order to reduce the loading of each clock signal line;

[0394] The second third voltage line VGL_P2 is electrically connected to the first third voltage line VGL_P1 through a via, for loading of the third voltage line;

[0395] The second fourth voltage line VGH_P2 is electrically connected to the first fourth voltage line VGH_P1 through a via to reduce the loading of the fourth voltage line;

[0396] The second fourth start signal line GSTV_P2 is electrically connected to the first fourth start signal line GSTV_P1 via a via to reduce the loading of each clock signal line.

[0397] In at least one embodiment of this disclosure, in Figure 34 Based on the layout diagram, the display substrate may further include a second metal layer and a third metal layer. The third metal layer may be provided with a third even-numbered row first clock signal line, a third even-numbered row second clock signal line, a third even-numbered row third clock signal line, a third odd-numbered row first clock signal line, a third odd-numbered row second clock signal line, a third odd-numbered row third clock signal line, a third third voltage line and a third fourth voltage line.

[0398] The first clock signal line of the third even-numbered row is electrically connected to the first clock signal line of the second even-numbered row via a via; the second clock signal line of the third even-numbered row is electrically connected to the second clock signal line of the second even-numbered row via a via; the third clock signal line of the third even-numbered row is electrically connected to the third clock signal line of the second even-numbered row via a via; the first clock signal line of the third odd-numbered row is electrically connected to the third clock signal line of the second odd-numbered row via a via; the second clock signal line of the third odd-numbered row is electrically connected to the second clock signal line of the second odd-numbered row via a via; the third clock signal line of the third odd-numbered row is electrically connected to the third clock signal line of the second odd-numbered row via a via; this is to reduce the loading of each clock signal line;

[0399] The third voltage line is electrically connected to the second voltage line through a via to reduce the loading of the third voltage line;

[0400] The third fourth voltage line is electrically connected to the second fourth voltage line through a via to reduce the loading of the fourth voltage line.

[0401] In at least one embodiment of this disclosure, each third voltage line may be a low-voltage DC signal line and each fourth voltage line may be a high-voltage DC signal line, but this is not a limitation.

[0402] In at least one embodiment of this disclosure, the orthographic projection of the first clock signal line GCK1_E2 in the second even-numbered row on the substrate at least partially overlaps with the orthographic projection of the first clock signal line GCK1_E1 in the first even-numbered row on the substrate, the orthographic projection of the second clock signal line GCK2_E2 in the second even-numbered row on the substrate at least partially overlaps with the orthographic projection of the second clock signal line GCK2_E1 in the first even-numbered row on the substrate, and the orthographic projection of the third clock signal line GCK3_E2 in the second even-numbered row on the substrate at least partially overlaps with the orthographic projection of the third clock signal line GCK3_E1 in the first even-numbered row on the substrate.

[0403] The orthographic projection of the first clock signal line GCK1_O2 in the second odd-numbered row on the substrate at least partially overlaps with the orthographic projection of the first clock signal line GCK1_O1 in the first odd-numbered row on the substrate; the orthographic projection of the second clock signal line GCK2_O2 in the second odd-numbered row on the substrate at least partially overlaps with the orthographic projection of the second clock signal line GCK2_O1 in the first odd-numbered row on the substrate; the orthographic projection of the third clock signal line GCK3_O2 in the second odd-numbered row on the substrate at least partially overlaps with the orthographic projection of the third clock signal line GCK3_O1 in the first odd-numbered row on the substrate.

[0404] The orthographic projection of the second third voltage line VGL_P2 onto the substrate at least partially overlaps with the orthographic projection of the first third voltage line VGL_P1 onto the substrate.

[0405] The orthographic projection of the second fourth voltage line VGH_P2 onto the substrate at least partially overlaps with the orthographic projection of the first fourth voltage line VGH_P1 onto the substrate.

[0406] The orthographic projection of the second fourth start signal line GSTV_P2 on the substrate overlaps at least partially with the orthographic projection of the first fourth start signal line GSTV_P1 on the substrate.

[0407] like Figure 40 As shown, the substrate includes a peripheral region B0 and a display region A0;

[0408] The first drive unit GA1, the second drive unit GA2, the third drive unit GA3, and the fourth drive unit GA4 are all located in the surrounding area B0;

[0409] The third driving unit GA3, the first driving unit GA1, the second driving unit GA2, and the fourth driving unit GA4 are arranged sequentially along the direction close to the display area A0.

[0410] like Figure 41 As shown, the first driving unit GA1 includes a first second voltage line VGH_N, and the second driving unit GA2 includes a second second voltage line VGH_R.

[0411] The orthographic projection of VGH_N on the substrate and the orthographic projection of VGH_R on the substrate at least partially overlap;

[0412] VGH_N can be set on the second metal layer, and VGH_R can be set on the third metal layer, but this is not a limitation.

[0413] In at least one embodiment of this disclosure, the first signal line is VGH_N and the second signal line is VGH_R, but this is not a limitation.

[0414] exist Figure 41 In at least one embodiment shown, VGH_N and VGH_R can both be configured to provide a high-voltage DC signal, and VGH_N and VGH_R are disposed on different metal layers. Figure 42 As shown, the first driving unit GA1 includes a first second clock signal line NCB, and the second driving unit GA2 includes a second second clock signal line RCB.

[0415] The orthographic projection of the NCB on the substrate at least partially overlaps with the orthographic projection of the RCB on the substrate;

[0416] NCB can be placed on the second metal layer, and RCB can be placed on the third metal layer, but this is not a limitation.

[0417] exist Figure 42 In at least one embodiment shown, the NCB can be configured to provide a clock signal, the RCB can be configured to provide a clock signal, and the NCB and RCB are disposed on different metal layers.

[0418] In at least one embodiment of this disclosure, the first signal line is NCB and the second signal line is RCB, but this is not a limitation.

[0419] like Figure 43 As shown, the first driving unit GA1 includes a second first voltage line VGL_N1, and the third driving unit GA3 includes a third second voltage line VGH_E.

[0420] The orthographic projection of VGL_R on the substrate at least partially overlaps with the orthographic projection of VGH_E on the substrate;

[0421] VGL_N1 can be set on the second metal layer, and VGH_E can be set on the third metal layer.

[0422] exist Figure 43 In at least one embodiment shown, VGL_N1 can be configured as a low-voltage DC signal, and VGH_E can be configured to provide a high-voltage DC signal, with VGL_N1 and VGH_E disposed on different metal layers.

[0423] In at least one embodiment of this disclosure, the first signal line is VGL_N1 and the second signal line is VGH_E, but this is not a limitation.

[0424] The display device described in this disclosure includes the display substrate described above.

[0425] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0426] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, characterized in that, The device includes a driving module disposed on a substrate, the driving module comprising multiple driving units, each driving unit comprising a multi-stage driving circuit; the driving circuit is configured to provide driving signals. The driving unit includes a first signal line, and the driving circuit includes an output sub-circuit, which is configured to output the driving signal. The display substrate includes at least two metal layers stacked along a direction away from the substrate. In at least one driving unit, the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the at least one transistor included in the output sub-circuit on the substrate, and the orthographic projection of the first signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the at least one transistor on the substrate. The first electrode and the second electrode are disposed on the same metal layer, while the first electrode and the first signal line are disposed on different metal layers; In at least one driving unit, the orthographic projection of the same first signal line on the substrate overlaps at least partially with the orthographic projection of the first electrode of the at least one transistor on the substrate and the orthographic projection of the second electrode of the at least one transistor on the substrate. The driving module includes a first driving unit; the first driving unit includes a multi-stage first driving circuit, the first driving circuit being configured to provide a first driving signal; the first driving unit includes a first first voltage line and a first second voltage line; the first driving circuit includes a first output sub-circuit; the first signal line is the first first voltage line. The first output sub-circuit includes a first driving transistor and a first driving reset transistor; The first electrode of the first driving transistor is electrically connected to the first second voltage line, the second electrode of the first driving transistor is electrically connected to the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor is electrically connected to the first first voltage line. The orthographic projection of the first electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate. The orthographic projection of the second electrode of the first driving transistor on the substrate at least partially overlaps with the orthographic projection of the first voltage line on the substrate. The orthographic projection of the first electrode of the first drive reset transistor on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate. The orthographic projection of the second electrode of the first drive reset transistor on the substrate at least partially overlaps with the orthographic projection of the first voltage line on the substrate.

2. The display substrate as described in claim 1, characterized in that, The orthographic projection of the first signal line included in one of the plurality of driving units onto the substrate at least partially overlaps with the orthographic projection of the second signal line included in another of the plurality of driving units onto the substrate.

3. The display substrate as described in claim 2, characterized in that, The first signal line and the second signal line are configured to provide the same signal.

4. The display substrate as described in claim 2, characterized in that, The first signal line is a low-voltage DC signal line, a high-voltage DC signal line, or a clock signal line; The second signal line is a low-voltage DC signal line, a high-voltage DC signal line, or a clock signal line.

5. The display substrate as described in claim 1, characterized in that, In the plurality of driving units, at least three signal lines have at least partial overlap in their orthogonal projections onto the substrate.

6. The display substrate as described in claim 1, characterized in that, The display substrate includes a first metal layer and a second metal layer stacked sequentially along a direction away from the substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all disposed on the first metal layer, and the first voltage line is disposed on the second metal layer.

7. The display substrate as described in claim 1, characterized in that, The display substrate includes a first metal layer, a second metal layer, and a third metal layer stacked sequentially along a direction away from the substrate; the first electrode of the first driving transistor, the second electrode of the first driving transistor, the first electrode of the first driving reset transistor, and the second electrode of the first driving reset transistor are all disposed on the first metal layer, and the first voltage line is disposed on the third metal layer.

8. The display substrate as described in claim 6 or 7, characterized in that, The first driving unit further includes a second first voltage line, a first first clock signal line, a first second clock signal line, a first second voltage line, a first start signal line, and a first reset line; The first clock signal line, the first second clock signal line, and the first reset line are all disposed on the first metal layer; The second first voltage line, the first start signal line, and the first second voltage line are all disposed on the second metal layer.

9. The display substrate as described in claim 8, characterized in that, The first driving circuit includes a first on / off control transistor and a second on / off control transistor. The gates of the first on / off control transistor and the second on / off control transistor are both electrically connected to the second first voltage line; At least a portion of the orthographic projection of the second first voltage line onto the substrate is disposed between the orthographic projection of the gate of the first on / off control transistor onto the substrate and the orthographic projection of the gate of the second on / off control transistor onto the substrate.

10. The display substrate as claimed in claim 9, characterized in that, The orthographic projection of the first start signal line on the substrate is positioned between the orthographic projection of the second first voltage line on the substrate and the orthographic projection of the first reset line on the substrate.

11. The display substrate as described in claim 6 or 7, characterized in that, The driving module includes a second driving unit; the first driving unit includes a multi-stage second driving circuit, the second driving circuit being configured to provide a second driving signal; the second driving unit includes a third first voltage line; the second driving circuit includes a second output sub-circuit; the second output sub-circuit includes a second driving transistor; The orthogonal projection of the third first voltage line on the substrate is located on the side of the orthogonal projection of the second driving transistor on the substrate that is away from the display area; The third first voltage line is disposed on a different layer than the first first voltage line; The orthographic projection of the third first voltage line on the substrate at least partially overlaps with the orthographic projection of the first first voltage line on the substrate.

12. The display substrate as claimed in claim 11, characterized in that, The orthographic projection of the third first voltage line on the substrate coincides with the orthographic projection of the first first voltage line on the substrate.

13. The display substrate as claimed in claim 11, characterized in that, The first driving circuit is configured to provide an N-type gate driving signal, and the second driving circuit is configured to provide a reset control signal.

14. The display substrate as claimed in claim 11, characterized in that, The first voltage line is disposed on the second metal layer, and the third voltage line is disposed on the third metal layer; or... The first voltage line is disposed on the third metal layer, and the third voltage line is disposed on the second metal layer.

15. The display substrate as claimed in claim 14, characterized in that, The first and third first voltage lines are low-voltage DC signal lines; or, the first and third first voltage lines are high-voltage DC signal lines.

16. The display substrate as claimed in claim 11, characterized in that, The second output sub-circuit is arranged adjacent to the third first voltage line.

17. The display substrate as claimed in claim 11, characterized in that, The second driving unit further includes a second start signal line, a second first clock signal line, a second second clock signal line, and a second second voltage line; The third first voltage line, the second start signal line, the second first clock signal line, the second second clock signal line, and the second second voltage line are arranged sequentially along the direction closest to the display area.

18. The display substrate as claimed in claim 17, characterized in that, The second output sub-circuit also includes a second drive reset transistor; The orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second driving transistor on the substrate, and the orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second driving transistor on the substrate. The orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the first electrode of the second drive reset transistor on the substrate, and the orthographic projection of the second start signal line on the substrate at least partially overlaps with the orthographic projection of the second electrode of the second drive reset transistor on the substrate.

19. The display substrate as claimed in claim 17, characterized in that, The transistors included in the second driving circuit are positioned on the substrate with their orthogonal projections onto the side of the third first voltage line on the substrate closest to the display area.

20. The display substrate as claimed in claim 18, characterized in that, The second driving circuit also includes a fifteenth transistor, a twentieth transistor, and a twenty-first transistor; The gate of the fifteenth transistor is electrically connected to the second first clock signal line, and the second electrode of the fifteenth transistor is electrically connected to the second electrode of the twenty-first transistor; the first electrode of the twenty-first transistor is electrically connected to the second electrode of the twentyth transistor. The gate of the twentieth transistor is electrically connected to the gate of the second drive reset transistor, and the gate of the twentieth eleventh transistor is electrically connected to the second clock signal line. The orthographic projection of the gate of the fifteenth transistor on the substrate, the orthographic projection of the gate of the twentieth transistor on the substrate, and the orthographic projection of the gate of the twenty-first transistor on the substrate are disposed between the orthographic projection of the second clock signal line on the substrate and the orthographic projection of the second voltage line on the substrate.

21. The display substrate as claimed in claim 20, characterized in that, The second driving circuit also includes a sixteenth transistor; The gate of the sixteenth transistor is electrically connected to the second electrode of the fifteenth transistor, the first electrode of the sixteenth transistor is electrically connected to the second first clock signal line, and the second electrode of the sixteenth transistor is electrically connected to the gate of the drive reset transistor. The orthographic projection of the gate of the sixteenth transistor on the substrate is positioned between the orthographic projection of the second first clock signal line on the substrate and the orthographic projection of the second second clock signal line on the substrate.

22. The display substrate as claimed in claim 11, characterized in that, The substrate includes a peripheral area and a display area; the driving module includes driving units that are all disposed in the peripheral area of ​​the substrate. The first driving unit is located on the side of the second driving unit that is away from the display area.

23. The display substrate as claimed in claim 22, characterized in that, The drive module includes a third drive unit, the third drive unit includes a multi-stage third drive circuit, and the third drive circuit is configured to provide a third drive signal. The third drive unit is located on the side of the first drive unit away from the second drive unit.

24. The display substrate as claimed in claim 23, characterized in that, The drive module includes a fourth drive unit, the drive unit includes a multi-stage fourth drive circuit, and the fourth drive circuit is configured to provide a fourth drive signal. The fourth driving unit is located on the side of the second driving unit that is close to the display area.

25. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 24.

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