Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a driving backplate comprising a substrate and a circuit layer, a wiring layer and a first planar layer stacked in turn in a direction away from the substrate; the circuit layer comprising a plurality of pixel circuits; the wiring layer comprising data lines and power lines distributed in a row direction, the width of the power lines being greater than that of the data lines; the power lines being provided with a plurality of through holes distributed in a column direction, the through holes being provided with switching parts in the same layer as the power lines and spaced apart from the power lines, one switching part being connected to one pixel circuit; light emitting devices being distributed on a side of the first planar layer away from the substrate and connected to the pixel circuits; the light emitting devices comprising first electrodes, light emitting layers and second electrodes; at least part of the light emitting devices overlapping with regions of the power lines where no through holes are provided; an anti-reflection layer being provided on a side of the light emitting devices away from the substrate and comprising a plurality of arrayed light filtering parts, one light filtering part overlapping with one light emitting device; the color of the light filtering part being the same as the light emitting color of the light emitting device overlapping therewith.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) display panels have advantages such as self-illumination, wide color gamut, high contrast, flexibility, and high response, and have broad application prospects. However, current display panels suffer from color separation, color shift, and other phenomena that affect display performance.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a display panel and a display device.

[0005] According to one aspect of this disclosure, a display panel is provided, comprising:

[0006] A driving backplane includes a substrate and a circuit layer, a wiring layer, and a first planarization layer stacked sequentially in a direction away from the substrate; the circuit layer includes a plurality of pixel circuits distributed in an array; the wiring layer includes data lines and power lines distributed in a row direction, one of the data lines and one of the power lines being connected to a column of pixel circuits; the width of the power line is greater than that of the data line; the power line has a plurality of vias distributed in the column direction, each via having a transition portion at intervals and on the same layer as the power line, and one of the transition portions being connected to a pixel circuit;

[0007] Multiple light-emitting devices are arrayed on the side of the first planarization layer away from the substrate and connected to the pixel circuit; each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially in a direction away from the substrate; the light-emitting devices include at least two types of light-emitting devices with different emission colors; at least a portion of the light-emitting devices overlaps with the area of ​​the power line where the via is not provided;

[0008] An anti-reflective layer is disposed on the side of the light-emitting device away from the substrate, and includes a plurality of arrayed filter sections, one of which overlaps with one of the light-emitting devices; the color of the filter section is the same as the emission color of the light-emitting device that overlaps with it.

[0009] In an exemplary embodiment of the present disclosure, the data lines and the power lines are alternately arranged along the row direction; one power line overlaps with one column of the light emitting devices, and one column of the light emitting devices is arranged between two adjacent data lines; and the boundary of at least part of the light emitting devices is located within the boundary of the power line overlapping therewith.

[0010] In an exemplary embodiment of the present disclosure, the light emitting devices are arranged into a plurality of device columns along the row direction, and the light emitting devices of one device column overlap with one power line.

[0011] In an exemplary embodiment of the present disclosure, the light emitting devices include first light emitting devices of a first color, second light emitting devices of a second color, and third light emitting devices of a third color.

[0012] The first light emitting devices have a larger range than the second light emitting devices and the third light emitting devices, and the boundary of at least one of the second light emitting devices and the third light emitting devices is located within the boundary of the power line overlapping therewith.

[0013] In an exemplary embodiment of the present disclosure, each device column includes a first device column and a second device column alternately arranged along the row direction; the first device column includes the first light emitting devices and the second light emitting devices alternately arranged along the column direction, and the second device column includes the third light emitting devices.

[0014] In an exemplary embodiment of the present disclosure, the first electrode includes an electrode body and an electrode connecting portion extending outward from the electrode body, and one electrode connecting portion is connected to one pixel circuit through a contact hole penetrating the first planar layer.

[0015] The display panel further includes:

[0016] A pixel definition layer is arranged on the side of the first planar layer away from the substrate, and is provided with a plurality of openings for defining the range of the light emitting devices, one opening exposes one electrode body, and the boundary of the opening is located within the boundary of the electrode body exposed thereto.

[0017] The distance between the contact hole connected to the electrode connecting portion connected to the electrode body exposed by one opening and the contact hole connected to the electrode connecting portion connected to the electrode body exposed by another opening is the offset distance of the light emitting device defined by the openings.

[0018] The offset distance of the first light emitting devices is 2.9 μm - 3 μm; the offset distance of the second light emitting devices is 6.5 μm - 6.6 μm; and the offset distance of the third light emitting devices is 5.2 μm - 5.3 μm.

[0019] In an example embodiment of the present disclosure, the data lines are divided into a plurality of data line groups, one data line group including two data lines; the power lines are divided into a plurality of power line groups, one power line group including two power lines, and the two power lines being in one body structure; the data line groups and the power line groups are alternately distributed along the row direction; two pixel circuits in two rows connected by the two power lines of one power line group are symmetrically arranged about the central axis of the two power lines.

[0020] At least part of the boundary of the light emitting device is located within the boundary of the power line group, and at most part of the light emitting device overlaps the data line group.

[0021] In an example embodiment of the present disclosure, each light emitting device is arranged into a plurality of device columns along the row direction, and the light emitting devices of part of the device columns overlap one power line group, and the light emitting devices of part of the device columns overlap the data line group.

[0022] In an example embodiment of the present disclosure, the light emitting device includes a first light emitting device of a first color, a second light emitting device of a second color, and a third light emitting device of a third color.

[0023] The range of the first light emitting device is greater than that of the second light emitting device and the third light emitting device, the boundary of the first light emitting device is located within the boundary of the power line group overlapping it, and at most one of the second light emitting device and the third light emitting device overlaps the data line group.

[0024] In an example embodiment of the present disclosure, each device column includes a first device column and a second device column alternately distributed along the row direction; the first device column includes the first light emitting device and the second light emitting device alternately distributed along the column direction, and the second device column includes the third light emitting device.

[0025] The boundary of the light emitting device of the first device column is located within the boundary of the power line group overlapping it; and the light emitting device of the second device column overlaps the data line group.

[0026] In an example embodiment of the present disclosure, the first electrode includes an electrode body and an electrode connecting portion extending outward from the electrode body, and one electrode connecting portion is connected to one pixel circuit through a contact hole penetrating the first flat layer.

[0027] The display panel further includes:

[0028] A pixel definition layer is disposed on the side of the first planar layer away from the substrate and has a plurality of openings for defining the range of the light emitting device, one of the openings exposes one of the electrode bodies, and the boundary of the opening is within the boundary of the electrode body exposed thereby;

[0029] The distance between one of the openings and the contact hole connected to the electrode connecting part connected to the electrode body exposed thereby is the misalignment distance of the light emitting device defined by the opening;

[0030] The misalignment distance of the first light emitting device is 9-11 μm, the misalignment distance of the second light emitting device is 15-17 μm, and the misalignment distance of the third light emitting device is 6-8 μm.

[0031] In an exemplary embodiment of the present disclosure, the pixel circuit includes a plurality of transistors, the circuit layer includes a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a dielectric layer, a source-drain layer, a passivation layer, and a second planar layer distributed in the direction away from the substrate, and the wiring layer is disposed on the side of the second planar layer away from the substrate.

[0032] The channel of each of the transistors is located in the semiconductor layer.

[0033] In an exemplary embodiment of the present disclosure, in one of the pixel circuits and the data line and the power line connected thereto, the pixel circuit includes a first reset transistor, a compensation transistor, a drive transistor, a write transistor, a first light emitting control transistor, a second light emitting control transistor, a second reset transistor, and a storage capacitor.

[0034] The first electrode of the first reset transistor is used to receive a first reset signal, and the second electrode is connected to the gate of the drive transistor and the first plate of the storage capacitor.

[0035] The first electrode of the compensation transistor is connected to the second electrode of the drive transistor, and the second electrode is connected to the gate of the drive transistor. The compensation transistor has two channels in series.

[0036] The first electrode of the write transistor is connected to one of the data lines, and the second electrode is connected to the first electrode of the drive transistor.

[0037] The first electrode of the first light emitting control transistor and the second plate of the storage capacitor are connected to the power line, and the second electrode is connected to the first electrode of the drive transistor.

[0038] The first electrode of the second light emitting control transistor is connected to the second electrode of the drive transistor, and the second electrode is connected to one of the first electrodes through one of the adapter parts.

[0039] The first electrode of the second reset transistor is configured to receive a second reset signal, and the second electrode is connected to the second electrode of the second light emitting control transistor;

[0040] The first gate layer includes the gate of each of the transistors and the first plate of the storage capacitor; the second gate layer includes the second plate of the storage capacitor, a shielding block and a shielding block; the source-drain layer includes a connecting portion connecting the second electrode of the compensation transistor and the gate of the driving transistor, and the connecting portion and the gate of the driving transistor are located on the same side of the data line;

[0041] At least part of the area of the shielding block overlaps the semiconductor layer between the two channels of the compensation transistor; the shielding block is at least partially located between the data line and the connecting portion, and the shielding block is connected to the power supply line.

[0042] In an exemplary embodiment of the present disclosure, the display panel includes a display area, the display area including a main display area and a sub-display area located outside the main display area; the light emitting devices are distributed in the main display area and the sub-display area;

[0043] The pixel circuit connected to at least part of the light emitting devices in the sub-display area is located in the main display area and connected to the light emitting devices through a conductive line;

[0044] The circuit layer further includes a conductive layer and an insulating layer, the conductive layer being located on the side of the passivation layer away from the substrate, the insulating layer covering the conductive layer, and the second planar layer covering the insulating layer; the conductive layer includes the conductive line.

[0045] In an exemplary embodiment of the present disclosure, the conductive layer further includes a plurality of overlapping portions located in the display area, and one pixel circuit is connected to the power supply line through one overlapping portion.

[0046] According to an aspect of the present disclosure, a display device is provided, including the display panel as described in any one of the above.

[0047] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. It is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor based on these drawings.

[0049] Figure 1 A schematic diagram showing a display region and a peripheral region of an embodiment of the display panel of the present disclosure.

[0050] Figure 2 A partial cross-sectional view of an embodiment of the display panel of the present disclosure.

[0051] Figure 3 A schematic diagram of a light emitting device and a wiring layer of a first embodiment of the display panel of the present disclosure.

[0052] Figure 4 A schematic diagram of a light emitting device and a wiring layer of a second embodiment of the display panel of the present disclosure.

[0053] Figure 5 A schematic diagram of a pixel circuit in an embodiment of the display panel of the present disclosure.

[0054] Figures 6-12 A partial top view of each film layer of a first embodiment of the display panel of the present disclosure.

[0055] Figure 13 A partial top view of a semiconductor layer and a first gate layer of a first embodiment of the display panel of the present disclosure.

[0056] Figure 14 A partial top view of a semiconductor layer to a second gate layer of a first embodiment of the display panel of the present disclosure

[0057] Figure 15 A partial top view of a semiconductor layer to a conductive layer of a first embodiment of the display panel of the present disclosure.

[0058] Figure 16 A partial top view of a semiconductor layer to a wiring layer of a first embodiment of the display panel of the present disclosure.

[0059] Figure 17 A partial top view of a first embodiment of the display panel of the present disclosure.

[0060] Figures 18-24 A partial top view of each film layer of a second embodiment of the display panel of the present disclosure.

[0061] Figure 25 A partial top view of a semiconductor layer and a first gate layer of a second embodiment of the display panel of the present disclosure.

[0062] Figure 26 A partial top view of a semiconductor layer to a second gate layer of a second embodiment of the display panel of the present disclosure

[0063] Figure 27 A partial top view of a semiconductor layer to a conductive layer of a second embodiment of the display panel of the present disclosure.

[0064] Figure 28 This is a partial top view of the semiconductor layer to the wiring layer of the second embodiment of the display panel of this disclosure.

[0065] Figure 29 This is a partial top view of a second embodiment of the display panel of this disclosure. Detailed Implementation

[0066] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0067] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0068] In this document, the row direction X and column direction Y are only two mutually perpendicular directions. In the accompanying drawings of this disclosure, the row direction X can be horizontal and the column direction Y can be vertical, but are not limited to this. If the display panel is rotated, the actual orientation of the row direction X and column direction Y may change.

[0069] In this paper, the "overlap" of features A and B means that the orthographic projections of features A and B on the substrate at least partially coincide.

[0070] The transistors in the pixel circuit disclosed herein can be N-type transistors, P-type transistors, or both. Each transistor can have a gate, a first terminal, and a second terminal. The gate controls the transistor's on / off state. The first and second terminals can be used for input and output signals. The first terminal can be the source of the transistor, and the second terminal can be the drain. However, when the transistor's operating state changes, such as when the current direction changes, the source and drain of the transistor can be interchanged.

[0071] like Figures 2-4 As shown, this disclosure provides a display panel that may include a driving backplane (BP), a light-emitting diode (LD), and an anti-reflective layer (COE), wherein:

[0072] The driving backplane BP may include a substrate SU and a circuit layer CL, a wiring layer SD2, and a first planarization layer PLN2 stacked sequentially in a direction away from the substrate SU; the circuit layer CL includes a plurality of pixel circuits PC distributed in an array; the wiring layer SD2 includes a data line DAL and a power line VDL distributed in the row direction X, and a data line DAL and a power line VDL are connected to a column of pixel circuits PC; the width of the power line VDL is greater than that of the data line DAL; the power line VDL has a plurality of vias VDH distributed in the column direction, and the vias VDH have a transition portion VDL1 on the same layer as the power line VDL and spaced apart, and a transition portion VDL1 is connected to a pixel circuit PC.

[0073] The number of light-emitting devices (LDs) is multiple, and they are arrayed on the side of the first planarization layer PLN2 away from the substrate SU and connected to the pixel circuit PC. The light-emitting device LD includes a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked sequentially in the direction away from the substrate SU. The light-emitting device LD includes at least two light-emitting devices with different emission colors. At least some of the light-emitting devices LD overlap with the power line VDL.

[0074] The anti-reflective layer COE can be disposed on the side of the light-emitting device LD away from the substrate SU, and includes multiple arrayed filter sections CF, one filter section CF overlapping one light-emitting device LD; the color of the filter section CF is the same as the emission color of the light-emitting device LD that overlaps with it.

[0075] The display panel disclosed herein features a filter section (CF) in the anti-reflective layer (COE) that allows only monochromatic light to pass through. This reduces ambient light entering the display panel. Even if some ambient light is reflected by the light-emitting diode (LD) and pixel circuit (PC), the remaining reflected light is blocked by the filter section (CF) and cannot escape. This reduces the display panel's reflection of ambient light, effectively functioning as a circular polarizer. Consequently, the typically thick circular polarizer can be eliminated, reducing the overall thickness of the display panel. Furthermore, the first electrode (ANO) is made of a reflective material. Since the power line (VDL) is wider than the data line (DAL), and the area without the through-hole (VDH) overlaps with the light-emitting diode (LD), the first electrode (ANO) is made flatter. This prevents unevenness in the first electrode (ANO) from interfering with light propagation, thus mitigating color separation and color shift issues caused by light path interference when emanating from the anti-reflective layer (COE).

[0076] The overall architecture of the display panel disclosed herein will be described in detail below:

[0077] like Figure 1As shown, the display panel may have a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous or discontinuous annular area surrounding the display area AA, or it may be a semi-enclosed area. The shape of the peripheral area WA is not specifically limited here. Light-emitting devices (LDs) may be distributed in the display area AA. By emitting light from the light-emitting devices LDs, images can be displayed, while the peripheral area WA does not emit light.

[0078] like Figure 2 As shown, the driving backplane BP may include a substrate SU and a circuit layer CL, a wiring layer SD2, and a first planarization layer PLN2 stacked on one side of the substrate SU, wherein:

[0079] The substrate SU can be the base for the driving backplane BP, and it can carry the circuit layer CL. The substrate SU can be a rigid or flexible structure, and it can be a single-layer or multi-layer structure, without any special limitation.

[0080] The circuit layer CL may include driving circuitry for driving the light-emitting devices (LDs) to emit light independently to display images. The driving circuitry may include pixel circuitry PC and peripheral circuitry. The pixel circuitry PC may be located within the display area AA and connected to the light-emitting devices LD. Alternatively, a portion of the pixel circuitry PC may be located within the peripheral area WA. The peripheral circuitry is located within the peripheral area WA and connected to the pixel circuitry PC. The peripheral circuitry can connect to the light-emitting devices LD via the pixel circuitry PC, applying a first power signal VDD to the first electrode ANO of the light-emitting devices LD. Simultaneously, the peripheral circuitry can also connect to the second electrode CAT of the light-emitting devices LD and apply a second power signal VSS to the second electrode CAT. By controlling the pixel circuitry PC, the current flowing through the light-emitting devices LD can be controlled, thereby controlling the brightness of the light-emitting devices LD. The peripheral circuitry may include gate driving circuitry and light-emitting control circuitry, and may also include other circuits. The specific structure of the peripheral circuitry is not specifically limited here.

[0081] Each pixel circuit PC may include multiple transistors and storage capacitors. The channels of each transistor can be arranged on the same layer and are all made of semiconductor materials such as polysilicon. A pixel circuit PC may include multiple transistors and capacitors; it can be a 3T1C, 7T1C, or other similar pixel circuit PC. nTmC indicates that one pixel circuit PC includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). There can be multiple pixel circuit PCs, and they can be arranged in multiple rows and columns. One pixel circuit PC can be connected to one light-emitting device (LD). Of course, it is also possible for one pixel circuit PC to be connected to multiple light-emitting devices (LDs). This article only illustrates the example of a one-to-one connection between pixel circuit PCs and light-emitting devices (LDs).

[0082] like Figure 2As shown, the wiring layer SD2 is located on the side of the circuit layer CL away from the substrate SU, and includes at least the data line DAL and the power line VDL connected to the pixel circuit PC. The wiring layer SD2 and the circuit layer CL can form a driving circuit.

[0083] like Figure 3 and Figure 4 As shown, there are multiple data lines (DAL) and power lines (VDL), all extending along the column direction (Y) and distributed along the row direction (X). One data line (DAL) can connect to at least one column of pixel circuits (PC), and one power line (VDL) can also connect to at least one column of pixel circuits (PC). The data line (DAL) can input a data signal (DA) to the pixel circuit (PC), and the power line (VDL) can input a first power signal (VDD) to the pixel circuit (PC).

[0084] like Figure 2 As shown, the first planarization layer PLN2 can cover the wiring layer SD2. The material of the first planarization layer PLN2 can be a transparent resin or other organic material, and the surface of the first planarization layer PLN2 facing away from the driving backplane BP is flat so that the light-emitting device LD can be placed on it.

[0085] like Figure 2 As shown, each light-emitting device (LD) can be arrayed on the surface of the first planarization layer PLN2 away from the wiring layer SD2. The light-emitting device LD can be an organic light-emitting diode, which includes a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked along the direction away from the substrate SU, wherein:

[0086] A first electrode ANO is connected to a pixel circuit PC. The first electrode ANO serves as the anode and can be a single-layer or multi-layer structure. Its material can include one or more of conductive metals, metal oxides, and alloys. The first electrode ANO can be a light-shielding structure. For example, the first electrode ANO may include three metal layers. The material of the middle metal layer can be silver, aluminum, etc., and the material of the other two metal layers can be titanium or other metals, without special limitation.

[0087] like Figure 2As shown, the light-emitting layer EL is at least partially disposed within the opening PH, and may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer sequentially stacked along a direction away from the substrate SU. Visible light is generated by causing holes and electrons to recombine into excitons in the light-emitting material layer, and the excitons radiate photons. The specific light-emitting principle is not detailed here. The light-emitting layers EL can be arrayed, with each light-emitting device LD having an independently emitting light-emitting layer EL, allowing each light-emitting device LD to emit light independently, and different light-emitting devices LD can emit different colors. For example, there are multiple light-emitting layers EL, arrayed in each opening PH, and stacked with the first electrode ANO exposed in the opening PH. Alternatively, each light-emitting layer EL may share at least a portion of the film layer except for the light-emitting material layer, but the light-emitting material layers are independently disposed, which can also result in light-emitting devices LD with different emission colors.

[0088] like Figure 2 As shown, the second electrode CAT can cover the light-emitting layer EL, and it can serve as the cathode of the light-emitting device LD. The second electrode CAT can be a single-layer or multi-layer structure, and its material can include one or more of conductive metals, metal oxides, and alloys. Each light-emitting device LD can share the same second electrode CAT. Specifically, the second electrode CAT is a continuous conductive layer CR covering the light-emitting layer EL and the pixel definition layer PDL of each light-emitting device LD. That is, the orthogonal projection of the second electrode CAT onto the pixel definition layer PDL covers each opening PH.

[0089] like Figure 2 As shown, to define the range of each light-emitting device (LD), a pixel definition layer (PDL) can be formed on the surface of the first planarization layer PLN2 facing away from the substrate SU. The PDL can be used to separate the individual LDs, thereby preventing color crosstalk between adjacent LDs. Specifically, the PDL can have multiple openings PH, each opening PH corresponding to and exposing one of the first electrodes ANO, and the boundary of the opening PH is within the boundary of the first electrode ANO it exposes. The range defined by each opening PH is the range of one LD.

[0090] Furthermore, such as Figure 2 , Figure 12 and Figure 24As shown, the first electrode ANO may include an electrode body AN1 and an electrode connection portion AN2 extending outward from the electrode body AN1. An opening PH exposes an electrode body AN1, and the boundary of the opening PH is located within the boundary of the exposed electrode body AN1. The electrode connection portion AN2 extends beyond the boundary of the opening PH and can be connected to a pixel circuit PC through a contact hole AH penetrating the first planarization layer PLN2, so that no contact hole AH is required within the range of the light-emitting device LD, thus avoiding affecting the light-emitting area. At the same time, the distance between an opening PH and the contact hole AH connected to the electrode connection portion AN2 connected to the exposed electrode body AN1 can be defined as the offset distance of the light-emitting device LD defined by the opening PH. The inventors have found that the contact hole AH and the opening PH affect the flatness of the first planarization layer PLN2, and the smaller the offset distance, the less flat the first planarization layer PLN2 around the electrode body AN1, which will cause the first electrode ANO to be uneven, thus causing problems such as color separation and color shift.

[0091] A light-emitting device (LD) may include a first light-emitting device LDb of a first color, a second light-emitting device LDR of a second color, and a third light-emitting device LDg of a third color. The first color may be blue, the second color may be red, and the third color may be green. To ensure the consistency of the lifespan of the LDs, the range of the first light-emitting device LDb (the range of the opening PHb of the first light-emitting device LDb) may be larger than that of the second light-emitting device LDR (the range of the opening PHr of the second light-emitting device LDR) and the third light-emitting device LDg (the range of the opening PHg of the third light-emitting device LDg). Increasing the size can improve the lifespan of blue light-emitting LDs with shorter lifespans. In addition, the range of the second light-emitting device LDR may be larger than that of the third light-emitting device LDg.

[0092] Each light-emitting device (LD) can be arranged into multiple device columns along the row direction X. A device column can include multiple light-emitting devices (LDs) distributed along the column direction Y. For example:

[0093] Each device column may include a first device column and a second device column that are alternately distributed along the row direction X. The first device column may include a first light-emitting device LDb and a second light-emitting device LDr that are alternately distributed along the column direction Y. The second device column includes a third light-emitting device LDg. That is, the third light-emitting device LDg is not in the same column as the first light-emitting device LDb and the second light-emitting device LDr.

[0094] like Figure 12 and Figure 24As shown, in some embodiments of this disclosure, each light-emitting device (LD) can be divided into multiple light-emitting units. Each light-emitting unit may include a first light-emitting device (LDb), a second light-emitting device (LDr), and two third light-emitting devices (LDg). The first and second light-emitting devices (LDb and LDr) can be distributed along the column direction Y, and the two third light-emitting devices (LDg) can be distributed along the row direction X on both sides of the first and second light-emitting devices (LDb and LDr), thus forming a quadrilateral distribution, which can be a rhombus. Adjacent light-emitting units may share some of the light-emitting devices (LDs), or they may not share them. Furthermore, in other embodiments of this disclosure, the light-emitting devices (LDs) can be arranged in other ways. No special limitation is made to their arrangement here; only the rhombus arrangement described above is used for illustration.

[0095] like Figure 2 As shown, the anti-reflective layer COE can be disposed on the side of the light-emitting device LD away from the driving backplate BP, and has multiple filter sections CF. The filter sections CF can be used to transmit monochromatic light, which can be red light, blue light, green light, etc. Each filter section CF can be overlapped with each light-emitting device LD in a one-to-one correspondence, and the colors of the overlapping light-emitting devices LD and filter sections CF are the same, that is, the color of the light emitted by the light-emitting device LD is the same as the color of the filter section CF it overlaps with. At the same time, the anti-reflective layer COE may also include a light-shielding section BM separating each filter section CF. The light-shielding section BM can be made of black resin material, or other materials can be used, as long as they can block light. Furthermore, in order to improve the light extraction efficiency and reduce the light blocking by the light-shielding section BM, the orthographic projection of the light-emitting device LD on the substrate SU can be located within the orthographic projection of the overlapping filter section CF on the substrate SU.

[0096] In addition, the display panel may also include an encapsulation layer that covers the light-emitting devices (LDs) to protect them and prevent external water and oxygen from corroding them. An anti-reflective layer (COE) may be located on the side of the encapsulation layer facing away from the substrate (SU). For example, the encapsulation layer may be implemented using a thin-film encapsulation method, and may include a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer covers the light-emitting devices (LDs), and the organic layer may be located on the surface of the first inorganic layer facing away from the driving backplate (BP). The boundary of the organic layer is defined inside the boundary of the first inorganic layer, and the boundary of the orthographic projection of the organic layer onto the driving backplate (BP) may be located in the peripheral region (WA), ensuring that the organic layer covers each light-emitting device (LD). The second inorganic layer may cover the organic layer and the first inorganic layer not covered by the organic layer. The second inorganic layer can block water and oxygen intrusion, and the flexible organic layer can achieve planarization.

[0097] In some embodiments of this disclosure, the display panel may further include a touch layer, which may be disposed between the anti-reflective layer COE and the encapsulation layer. The touch layer may adopt a self-capacitive or mutual-capacitive touch structure, and its specific structure is not particularly limited here, as long as it can realize the touch function. Of course, the touch layer may also be disposed on the side of the anti-reflective layer COE away from the driving backplane BP, and its specific position and process are not particularly limited here.

[0098] Furthermore, in some embodiments of this disclosure, the display panel may also include a transparent cover plate, which can be adhered to the anti-reflective COE layer and can achieve planarization. The transparent cover plate is used to protect the underlying film layer, and its material can be a transparent material such as glass or acrylic, without special limitation.

[0099] In some embodiments of this disclosure, such as Figure 1 As shown, the display panel can be an under-display camera-enabled display panel. Its displayable area AA can include a sub-display area FA and a main display area MA located outside the sub-display area FA. Light-emitting devices (LDs) can be distributed in the main display area MA and the sub-display area FA. Pixel circuits (PCs) connecting at least some of the LDs within the sub-display area FA can be located within the main display area MA and connected to the LDs via conductive lines. This reduces the number of pixel circuits (PCs) within the sub-display area FA, increases the light transmittance of the sub-display area FA, and thus enables under-display camera-enabled images through the sub-display area FA. Of course, to accommodate more pixel circuits (PCs) within the main display area MA, the size of some pixel circuits (PCs) can be compressed, for example, by reducing the width of some pixel circuits (PCs) along the row direction X. The conductive lines can be made of transparent conductive materials such as indium tin oxide (ITO) to improve the light transmittance of the sub-display area FA and can extend from the sub-display area FA to the main display area MA. The lengths of different conductive lines can vary. The conductive lines can be located in the circuit layer CL or between the driving backplane BP and the LDs. This paper only illustrates the case where the conductive lines are located in the circuit layer CL.

[0100] The structure of the pixel circuit PC of this disclosure is illustrated below:

[0101] In some embodiments of this disclosure, such as Figure 5 As shown, the pixel circuit PC can be a 7T1C structure, that is, it can have 7 transistors and 1 capacitor, namely the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the storage capacitor Cst.

[0102] like Figure 5As shown, the first terminal of the first reset transistor T1 is connected to the first reset signal line VIL1 to receive the first reset signal Vinit1, and the second terminal is connected to the gate of the driving transistor T3 and the first plate of the storage capacitor Cst.

[0103] The first terminal of the compensation transistor T2 is connected to the second terminal of the driving transistor T3, and the second terminal is connected to the gate of the driving transistor T3.

[0104] The first terminal of the write transistor T4 is connected to the data line DAL to receive the data signal DA, and the second terminal is connected to the first terminal of the drive transistor T3.

[0105] The first terminal of the first light-emitting control transistor T5 and the second terminal of the storage capacitor Cst are connected to the power line VDL to receive the first power signal VDD. The second terminal is connected to the first terminal of the driving transistor T3.

[0106] The first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T3, and the second electrode is connected to the first electrode ANO of a light-emitting device LD.

[0107] The first electrode of the second reset transistor T7 is connected to the second reset signal line VIL2 to receive the second reset signal Vinit2, and the second electrode is connected to the second electrode of the second light-emitting control transistor T6. The second electrode CAT of the light-emitting device LD can receive the second power supply signal VSS.

[0108] Simultaneously, to control the on / off state of each transistor, the gate of the first reset transistor T1 is connected to the first reset control line REL1 to input the first reset control signal RE1, and the gate of the second reset transistor T7 is connected to the second reset control line REL2 to input the second reset control signal RE2. The gates of the compensation transistor T2 and the write transistor T4 are connected to the scan line GL to input the scan signal GA, and the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control line EML to input the light-emitting control signal EM. This pixel circuit PC can be used to drive the connected light-emitting device LD to emit light in response to the signals provided by the connected signal terminals.

[0109] Furthermore, transistors can be classified into N-type and P-type transistors based on their characteristics. This disclosure uses an example where all transistors are P-type. Based on the description and teachings of this disclosure, those skilled in the art can readily conceive of using at least some N-type transistors in the pixel circuit PC structure of this disclosure, i.e., using N-type transistors or a combination of N-type and P-type transistors, without any inventive effort. Therefore, these implementations are also within the protection scope of this disclosure.

[0110] The following explanation uses the example of a pixel circuit PC where all transistors are P-type low-temperature polysilicon transistors to illustrate its working principle:

[0111] During the reset phase: the first reset control signal RE1 is a low-level signal, the first reset transistor T1 is turned on, the gate of the driving transistor T3 and the first plate of the storage capacitor Cst are written with the reset signal Vinit1, the N1 node is initialized, and the influence of the data of the previous frame image is eliminated.

[0112] During the writing phase: A low-level scan signal GA turns on the writing transistor T4 and the compensation transistor T2, writing the data signal DA to the gate of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst. This data signal DA is written to the N1 node via nodes N3 and N2 until the potential reaches Vdata + Vth. Here, Vdata is the voltage of the data signal DA, and Vth is the threshold voltage of the driving transistor T3. The scan signal GA for the writing transistor T4 and the compensation transistor T2 can be the same signal. Simultaneously, a low-level second reset control signal RE2 turns on the second reset transistor T7. The first electrode ANO of the light-emitting device LD and the second electrode of the second light-emitting control transistor T6 are written with the second reset signal Vinit2, resetting node N4 and initializing it, further eliminating the influence of the previous frame's data.

[0113] During the light-emitting stage: the light-emitting control signal EM is a low-level signal, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving transistor T3 is turned on under the action of the voltage Vdata+Vth stored in the storage capacitor Cst and the first power supply signal VDD. At this time, the light-emitting device LD emits light.

[0114] The following section will use the aforementioned 7T1C pixel circuit as an example to explain in detail the driving backplane BP:

[0115] In some implementations, such as Figure 2 As shown, the transistors and capacitors of the pixel circuit PC are both located in the circuit layer CL. Taking the top-gate type low-temperature polysilicon transistor as an example, the circuit layer CL may include a semiconductor layer SEL, a first gate insulating layer GI1, a first gate layer GAT1, a second gate insulating layer GI2, a second gate layer GAT2, a dielectric layer ILD, a source / drain layer SD1, a passivation layer PVX, and a second planarization layer PLN1 distributed along a direction away from the substrate SU.

[0116] like Figure 6 and Figure 18As shown, the semiconductor layer SEL may include the channels of each transistor (T1-T7) and doped regions that connect at least part of the channels, through which the connection of some transistors can be realized.

[0117] like Figure 7 , Figure 13 , Figure 19 and Figure 25 As shown, the first gate layer GAT1 may include the first plate Cst1 of the storage capacitor Cst, a scan line GL, a first reset control line REL1, a second reset control line REL2, and a light emission control line EML. The area where the scan line GL overlaps with the semiconductor layer SEL is the gate of the write transistor T4 and the compensation transistor T2. The area where the first reset control line REL1 overlaps with the semiconductor layer SEL is the gate of the first reset transistor T1. The area where the second reset control line REL2 overlaps with the semiconductor layer SEL is the gate of the second reset transistor T7. The area where the light emission control line EML overlaps with the semiconductor layer SEL is the gate of the first light emission control transistor T5 and the second light emission control transistor T6. The area where the first plate Cst1 overlaps with the semiconductor layer SEL is the gate of the drive transistor T3, that is, the first plate Cst1 is multiplexed as the gate of the drive transistor T3. Among them, there are two overlapping areas where the scan line GL and the semiconductor layer SEL are interconnected, forming two channels in series, which are the channels of the compensation transistor T2.

[0118] In addition, the second reset control line REL2 connected to the nth row pixel circuit PC can be reused as the first reset control line REL1 connected to the (n+1)th row pixel circuit PC, so that when the nth row pixel circuit PC is in the reset phase, the (n+1)th row pixel circuit PC can reset the light-emitting device LD, thereby improving working efficiency.

[0119] like Figure 8 , Figure 14 , Figure 20 and 26As shown, the second gate layer GAT2 may include a second electrode Cst2 of the storage capacitor Cst, a first reset signal line VIL1, and a second reset signal line VIL2. The first reset signal line VIL1 and the second reset signal line VIL2 extend along the row direction X and are distributed along the column direction Y. The second electrode Cst2 is located between the first reset signal line VIL1 and the second reset signal line VIL2. The second electrode Cst2 overlaps with the first electrode Cst1 and has an opening. The orthogonal projection of the first electrode Cst1 onto the substrate SU can cover the orthogonal projection of the opening onto the substrate SU. Furthermore, the second gate layer GAT2 may also include a shielding block BL1. At least a portion of the shielding block BL1 overlaps with the semiconductor layer SEL between the two channels of the compensation transistor T2, thereby shielding the compensation transistor T2 and preventing changes in its electrical characteristics due to light exposure. Additionally, the shielding block BL1 can be connected to the power line VDL, which serves two purposes: firstly, it acts as a signal shield to prevent interference from other signals to the compensation transistor T2; secondly, it reduces the impedance of the power line VDL.

[0120] like Figure 9 , Figure 15 , Figure 21 and Figure 27 As shown, the source / drain layer SD1 may include multiple connection portions, including a first connection portion SDL1 and a second connection portion SDL2. The first connection portion SDL1 can connect to the first reset transistor T1 and the first reset signal line VIL1 via a via. The second connection portion SDL2 can connect to the compensation transistor T2 and the first electrode plate Cst1 via a via, and the via connecting the compensation transistor T2 and the first electrode plate Cst1 passes through the opening of the second electrode plate Cst2, thereby connecting the second electrode of the compensation transistor T2 and the gate of the driving transistor T3. Furthermore, for a pixel circuit and its connected data line DAL, the second connection portion SDL2 can extend along the column direction Y, and the gate of the second connection portion SDL2 and the driving transistor T3 are located on the same side of the data line DAL.

[0121] To prevent the data signal on the data line DAL from interfering with the gate of the driving transistor T3 through the second connection portion SDL2, the second gate layer GAT2 may further include a shielding block BL2, which is at least partially located between the data line DAL and the second connection portion SDL2. Specifically, the orthographic projection of the shielding block BL2 onto the substrate SU is at least partially located between the orthographic projections of the data line DAL and the second connection portion SDL2 onto the substrate SU. Simultaneously, the shielding block BL2 can be connected to the power line VDL, thereby shielding the data signal on the data line DAL from interfering with the gate signal of the driving transistor T3 by inputting a constant first power supply signal to the shielding block BL2.

[0122] The blocking block BL1 and shielding block BL2 of two adjacent pixel circuits PC can be an integral structure, or they can be independent structures that are spaced apart.

[0123] The second planarization layer PLN1 can be disposed on the side of the source / drain layer SD1 away from the substrate SU.

[0124] In addition, such as Figure 10 , Figure 15 , Figure 22 and Figure 27 As shown, the circuit layer CL may also include a conductive layer CR and an insulating layer EBB. The conductive layer CR may be disposed on the surface of the passivation layer PVX away from the substrate SU, and the insulating layer EBB may cover the conductive layer CR. The second planarization layer PLN1 may cover the insulating layer EBB. The material of the insulating layer EBB may be an inorganic material such as silicon nitride, or an organic insulating material. The conductive lines connecting the main display area MA and the sub-display area FA are located in the conductive layer CR. Simultaneously, the conductive layer CR may also include multiple overlapping portions CR1 located in the display area AA. The overlapping portions CR1 are spaced apart from the conductive lines. A pixel circuit PC can be connected to the power line VDL through an overlapping portion CR1, thus serving as a transfer mechanism. The material of the conductive layer CR may be a transparent conductive material such as indium tin oxide to reduce the impact of the conductive lines on the light transmittance of the sub-display area FA.

[0125] like Figure 11 , Figure 16 , Figure 23 and Figure 28 As shown, the wiring layer SD2 can be disposed on the surface of the first planarization layer PLN2 away from the substrate SU. The inventors discovered that the wiring layer SD2 is not a continuous, whole-layer structure; its pattern affects the flatness of the surface of the first planarization layer PLN2 away from the substrate SU. This, in turn, directly affects the flatness of the first electrode ANO of the light-emitting device LD. If the flatness of the first electrode ANO is low, it will affect the optical path of the reflected light, easily leading to color separation and color shift display defects after emission from the anti-reflective layer COE. To solve this problem, the inventors proposed that the width of the power line VDL be greater than that of the data line DAL, and that it overlap with at least part of the light-emitting device LD. This allows the power line VDL to at least flatten the area of ​​the first electrode ANO within the opening pH range, improving the flatness of the first electrode ANO within the opening pH range, thereby improving display abnormalities such as color separation and color shift.

[0126] The power line VDL is wider than the data line DAL, thus increasing the area of ​​the power line VDL, which helps to flatten the first electrode ANO. The following is an exemplary illustration of the scheme for flattening the first electrode ANO using the power line VDL:

[0127] like Figure 3 ,Figure 12 and Figure 17 As shown, in the first embodiment of this disclosure, the data lines DAL and power lines VDL are alternately distributed along the row direction X, with only one power line VDL between two adjacent data lines DAL. In this embodiment, two adjacent pixel circuits PC in the row direction X can be obtained by translating the pixel circuit PC along the row direction X.

[0128] A row of light-emitting devices (LDs) can be placed between two adjacent data lines (DALs). That is, there is only one row of light-emitting devices (LDs) (with an opening PH) projected onto the substrate SU between the orthogonal projections of two adjacent data lines (DALs). It should be noted that for a row of light-emitting devices (LDs), as long as more than 80% of its area is between the two data lines (DALs), it can be considered to be located between the two data lines (DALs), not necessarily completely in front of the two data lines (DALs). It can overlap with the data lines (DALs) to a certain extent.

[0129] A power line VDL overlaps with a row of light-emitting devices (LDs). Among the overlapping LDs and power lines VDL, at least a portion of the boundaries of the LDs lie within the boundaries of the power lines VDL they overlap with. That is, the orthogonal projection of the openings PH of at least a portion of the LDs onto the substrate SU lies within the boundaries of the power lines VDL. Therefore, the power lines VDL can at least flatten the first electrode ANO within the opening PH area. Alternatively, the boundaries of at least a portion of the first electrode ANO can be made within the boundaries of the power lines VDL to further improve the flatness of the first electrode ANO.

[0130] Furthermore, the light-emitting devices (LDs) of a device array can overlap with a power line (VDL). For example, the boundary of at least one of the second light-emitting devices (LDr) and the third light-emitting device (LDg) is located within the boundary of the power line (VDL) with which it overlaps. For example, the boundaries of the second light-emitting device (LDr) and the third light-emitting device (LDg) are both located within the boundary of the power line (VDL) with which they overlap, while the range of the first light-emitting device (LDb) is larger. It can extend beyond the boundary of the power line (VDL) with which it overlaps and overlap with the data line (DAL), but the area extending beyond it is no more than 20% of the first light-emitting device (LDb).

[0131] To facilitate the connection between the light-emitting device (LD) and the pixel circuit (PC), the power line VDL can be provided with multiple through holes VDH distributed along the column direction Y. The through holes VDH are provided with adapter portions VDL1 on the same layer as the power line VDL and spaced apart. One adapter portion VDL1 can be connected to a lap portion CR1 and connected to a pixel circuit PC through the lap portion CR1, thereby connecting a first electrode ANO to a pixel circuit PC.

[0132] like Figure 4 , Figure 24 andFigure 29 As shown, in the second embodiment of this disclosure, the data lines DAL can be divided into multiple data line DAL groups, and a data line group DAS includes two data lines DAL. Similarly, the power lines VDL can be divided into multiple power line groups VDS, and a power line group VDS includes two power lines VDL. Furthermore, the two power lines VDL within the same power line group VDS can be a single integrated structure, and the range of one power line group VDS is equivalent to the sum of the ranges of the two power line VDLs. Simultaneously, the data line groups DAS and power line groups VDS can be alternately distributed along the row direction X, with one data line group DAS located between two adjacent power line groups VDS. To match the integrated structure of the power line groups VDS, the two columns of pixel circuits PC connected to the two power lines VDL of one power line group VDS can be symmetrically arranged about the central axis of the two power lines VDL. Symmetrical arrangement means that the patterns of each film layer of the pixel circuit PC are mirror-image distributed about the central axis.

[0133] Because the power line group VDS has two integrated power lines VDL, the area is increased, allowing at least part of the light-emitting device (LD) boundary to be located within the boundary of the power line group VDL. This increased power line VDL helps to level the first electrode ANO of the LD, thus improving display anomalies such as color shift and color separation. Simultaneously, due to the distribution of the LDs, some LDs can overlap with the data line group DAL.

[0134] Furthermore, in some device columns, the light-emitting diodes (LDs) overlap with a power line group (VDL), and in others, they overlap with a data line group (DAS). For example, at most one of the second light-emitting diode (LDr) and the third light-emitting diode (LDg) overlaps with the data line group (DAL). Furthermore, the boundary of the light-emitting diode (LD) in the first device column may be located within the boundary of the power line group (VDL) it overlaps with, and the light-emitting diode (LD) in the second device column may overlap with the data line group (DAL).

[0135] In two columns of pixel circuits PC connected by the same power line group VDS, the blocking blocks BL1 of adjacent columns of pixel circuit PCs are a single structure, and the shielding blocks BL2 of adjacent columns of pixel circuit PCs can also be a single structure. Of course, they can also be independent and spaced apart.

[0136] Furthermore, to facilitate the connection between the light-emitting device (LD) and the pixel circuit (PC), multiple through-holes (VDHs) distributed along the column direction Y can be formed in each power line VDL group. Each through-hole VDH can contain a transition part VDL1 at the same layer as the power line VDL and spaced apart. One transition part VDL1 can be connected to one pixel circuit PC. The third light-emitting device (LDg) in the second device column overlaps with part of the through-holes VDH, in addition to overlapping with the data line group DAS.

[0137] The inventors also discovered that since openings in the first planarization layer PLN2 affect the flatness around the openings, if the distance between the contact hole AH connecting the first electrode ANO and the overlapping portion CR1 and the opening PH is too close, i.e., the offset distance defined above is too small, it will affect the flatness of the area where the first electrode ANO is located within the opening PH. Therefore, based on the first and second embodiments described above, the inventors, through experiments and analysis, limited the offset distance. For example:

[0138] like Figure 3 , Figure 12 and Figure 17 As shown, in the first embodiment described above, the offset distance Sb of the first light-emitting device LDb is 2.9μm-3μm, for example, 2.93μm; the offset distance of the second light-emitting device LDr is 6.5μm-6.6μm, for example, 6.56μm; and the offset distance Sg of the third light-emitting device LDg is 5.2μm-5.3μm, for example, 5.24μm. Furthermore, in the same light-emitting unit, the distance Sbg between the first light-emitting device LDb and the third light-emitting device LDg is smaller than the distance Srg between the second light-emitting device LDr and the third light-emitting device LDg.

[0139] like Figure 4 , Figure 24 and Figure 29 As shown, for the second embodiment described above, the offset distance Sb of the first light-emitting device LDb is 9μm-11μm, for example 10μm; the offset distance Sr of the second light-emitting device LDr is 15μm-17μm, for example 16μm; and the offset distance Sg of the third light-emitting device LDg is 6μm-8μm, for example 7μm.

[0140] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. Its specific structure and beneficial effects can be referred to the embodiments of the display panel described above, and will not be repeated here. The display device of this disclosure can be a smartwatch, a wristband, or, of course, can also be used in mobile phones, tablets, and other electronic devices with display functions, which will not be listed here.

[0141] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, comprising: A drive backplane includes a substrate and circuit layers, wiring layers and a first planarization layer stacked sequentially in a direction away from the substrate; The circuit layer includes multiple pixel circuits arranged in an array; the wiring layer includes data lines and power lines arranged along the row direction, one of the data lines and one of the power lines being connected to a column of pixel circuits; the width of the power line is greater than that of the data line; the power line is provided with multiple through holes arranged along the column direction, and each through hole is provided with an adapter portion on the same layer as the power line and spaced apart, and one of the adapter portions being connected to a pixel circuit; Multiple light-emitting devices are arrayed on the side of the first planarization layer away from the substrate and connected to the pixel circuit; each light-emitting device includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially in a direction away from the substrate; the light-emitting devices include at least two types of light-emitting devices with different emission colors; the light-emitting devices overlap with the area of ​​the power line where the through-hole is not provided; An anti-reflective layer is disposed on the side of the light-emitting device away from the substrate, and includes a plurality of arrayed filter sections, one of which overlaps with one of the light-emitting devices; the color of the filter section is the same as the emission color of the light-emitting device that overlaps with it; The light-emitting device includes a first light-emitting device of a first color, a second light-emitting device of a second color, and a third light-emitting device of a third color; the range of the first light-emitting device is larger than that of the second and third light-emitting devices. The first light-emitting device overlaps with the area of ​​the power line where the through hole is provided and the area where the through hole is not provided; the boundary of the second light-emitting device is located within the boundary of the power line that overlaps with it, and does not overlap with the through hole; the third light-emitting device overlaps with the area of ​​the power line where the through hole is provided and the area where the through hole is not provided. The area where the first light-emitting device overlaps with the area of ​​the power line without the through hole is greater than the area where it overlaps with the through hole, and the area where the third light-emitting device overlaps with the area of ​​the power line without the through hole is greater than the area where it overlaps with the through hole.

2. The display panel according to claim 1, wherein, The data lines and power lines are alternately distributed along the row direction; one power line overlaps with a column of light-emitting devices, and a column of light-emitting devices is provided between two adjacent data lines; among the overlapping light-emitting devices and power lines.

3. The display panel according to claim 2, wherein, Each of the light-emitting devices is arranged in multiple device columns along the row direction, and the light-emitting devices in one of the device columns overlap with a power line.

4. The display panel according to claim 3, wherein, Each of the device columns includes a first device column and a second device column that are alternately distributed along the row direction; the first device column includes a first light-emitting device and a second light-emitting device that are alternately distributed along the column direction, and the second device column includes the third light-emitting device.

5. The display panel according to claim 1, wherein, The first electrode includes an electrode body and an electrode connection portion extending outward from the electrode body. The electrode connection portion is connected to a pixel circuit through a contact hole penetrating the first planarization layer. The display panel also includes: A pixel definition layer is provided on the side of the first flat layer away from the substrate, and has a plurality of openings for defining the range of the light-emitting device. One of the openings exposes an electrode body, and the distance between the contact hole connected to the electrode connection portion connected to the exposed electrode body of the opening is the offset distance of the light-emitting device defined by the opening. The offset distance of the first light-emitting device is 2.9μm-3μm; the offset distance of the second light-emitting device is 6.5μm-6.6μm; and the offset distance of the third light-emitting device is 5.2μm-5.3μm.

6. The display panel according to claim 1, wherein, The data lines are divided into multiple data line groups, and each data line group includes two data lines; the power lines are divided into multiple power line groups, and each power line group includes two power lines, and the two power lines are an integral structure; the data line groups and the power line groups are alternately distributed along the row direction; the two columns of pixel circuits connected by the two power lines of a power line group are symmetrically arranged about the central axis of the two power lines; At least a portion of the light-emitting devices are located within the boundary of the power line group, and at most a portion of the light-emitting devices overlap with the data line group.

7. The display panel according to claim 6, wherein, Each of the light-emitting devices is arranged in multiple device columns along the row direction, and the light-emitting devices of some of the device columns overlap with a power line group, and the light-emitting devices of some of the device columns overlap with the data line group.

8. The display panel according to claim 7, wherein, At most one of the second and third light-emitting devices overlaps with the data line group.

9. The display panel according to claim 8, wherein, Each of the device columns includes a first device column and a second device column that are alternately distributed along the row direction; the first device column includes a first light-emitting device and a second light-emitting device that are alternately distributed along the column direction, and the second device column includes the third light-emitting device; The boundary of the light-emitting device in the first device column is located within the boundary of the power line group that overlaps with it; the light-emitting device in the second device column overlaps with the data line group.

10. The display panel according to claim 9, wherein, The first electrode includes an electrode body and an electrode connection portion extending outward from the electrode body. The electrode connection portion is connected to a pixel circuit through a contact hole penetrating the first planarization layer. The display panel also includes: A pixel definition layer is disposed on the side of the first flat layer away from the substrate, and has a plurality of openings for defining the range of the light-emitting device, one of the openings exposing an electrode body, and the boundary of the opening is located within the boundary of the exposed electrode body. The distance between the opening and the contact hole connected to the electrode connection portion of the exposed electrode body is the offset distance of the light-emitting device defined by the opening; The offset distance of the first light-emitting device is 9μm-11μm; the offset distance of the second light-emitting device is 15μm-17μm; and the offset distance of the third light-emitting device is 6μm-8μm.

11. The display panel according to claim 1, wherein, The pixel circuit includes a plurality of transistors; the circuit layer includes a semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a dielectric layer, a source / drain layer, a passivation layer, and a second planarization layer distributed along a direction away from the substrate; the wiring layer is disposed on the side of the second planarization layer away from the substrate; The channels of each transistor are located in the semiconductor layer.

12. The display panel according to claim 11, wherein, In a pixel circuit and its connected data and power lines, the pixel circuit includes a first reset transistor, a compensation transistor, a driving transistor, a write transistor, a first light-emitting control transistor, a second light-emitting control transistor, a second reset transistor, and a storage capacitor; The first terminal of the first reset transistor is used to receive the first reset signal, and the second terminal is connected to the gate of the driving transistor and the first plate of the storage capacitor; The first terminal of the compensation transistor is connected to the second terminal of the driving transistor, and the second terminal is connected to the gate of the driving transistor; the compensation transistor has two channels connected in series. The first terminal of the write transistor is connected to a data line, and the second terminal is connected to the first terminal of the drive transistor. The first terminal of the first light-emitting control transistor and the second terminal of the storage capacitor are connected to the power line, and the second terminal is connected to the first terminal of the driving transistor. The first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode through a transition portion; The first terminal of the second reset transistor is used to receive the second reset signal, and the second terminal is connected to the second terminal of the second light-emitting control transistor; The first gate layer includes the gate of each of the transistors and the first plate of the storage capacitor; the second gate layer includes the second plate of the storage capacitor, a blocking block and a shielding block; the source-drain layer includes a connection portion connecting the second plate of the compensation transistor and the gate of the driving transistor, the connection portion and the gate of the driving transistor being located on the same side of the data line; At least a portion of the shielding block overlaps with the semiconductor layer between the two channels of the compensation transistor; the shielding block is at least partially located between the data line and the connection portion, and the shielding block is connected to the power line.

13. The display panel according to claim 11, wherein, The display panel includes a display area, which includes a sub-display area and a main display area located outside the sub-display area; the light-emitting devices are distributed in the main display area and the sub-display area. The pixel circuits connecting at least a portion of the light-emitting devices in the sub-display area are located in the main display area and are connected to the light-emitting devices via conductive lines; The circuit layer further includes a conductive layer and an insulating layer. The conductive layer is disposed on the side of the passivation layer away from the substrate. The insulating layer covers the conductive layer, and the second planarization layer covers the insulating layer. The conductive layer includes the conductive lines.

14. The display panel according to claim 13, wherein, The conductive layer also includes a plurality of overlapping portions located in the display area, and a pixel circuit is connected to the power line through one of the overlapping portions.

15. A display device comprising the display panel according to any one of claims 1-14.

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