Display substrate, preparation method thereof and display device

Abstract

A display substrate comprises a display area (100) and a cathode ring area (300); further comprising an insulating layer (15) and a light-emitting structure layer (20) arranged on a substrate (10) in sequence, the light-emitting structure layer (20) comprises an anode layer, a pixel definition layer, a light-emitting layer and a cathode (35), the anode layer comprises a display anode (31A) located in the display area (100) and a cathode voltage line (32) located in the cathode ring area (300), the cathode (35) is connected with the cathode voltage line (32); the cathode voltage line (32) comprises a first cathode voltage line (320) and a second cathode voltage line (321), the first cathode voltage line (320) extends along a first direction (X), the second cathode voltage line (321) extends along a second direction (Y), the first direction (X) is a direction parallel to the edge of the display substrate, at least one second cathode voltage line (321) is arranged between two adjacent first cathode voltage lines (320) and connected with the two adjacent first cathode voltage lines (320).

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the substrate, and a display device. Background Technology

[0002] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve weight reduction. Silicon-based OLEDs are fabricated using mature Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for Virtual Reality (VR) and Augmented Reality (AR). Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, including a substrate and a display area and a cathode ring area disposed on the substrate, the cathode ring area being located outside the display area; on a plane perpendicular to the display substrate, the display substrate includes an insulating layer disposed on the substrate and a light-emitting structure layer disposed on the insulating layer, the light-emitting structure layer including an anode layer, a pixel definition layer, a light-emitting layer and a cathode, the anode layer including a plurality of display anodes located in the display area and a cathode voltage line located in the cathode ring area, the cathode being connected to the cathode voltage line, the substrate including a power supply electrode and a pixel driving circuit, the insulating layer including a first conductive pillar and a second conductive pillar, the display anode... The cathode voltage line is connected to the pixel driving circuit via the first conductive post; the cathode voltage line includes multiple first cathode voltage lines and multiple second cathode voltage lines, the first cathode voltage lines extend along a first direction, and the second cathode voltage lines extend along a second direction, the first direction being parallel to the edge of the display substrate, and the second direction intersecting the first direction; at least one second cathode voltage line is disposed between two adjacent first cathode voltage lines and connected to two adjacent first cathode voltage lines; the cathode voltage line is connected to the power supply electrode via the second conductive post, and the orthogonal projection of the cathode voltage line on the substrate covers the orthogonal projection of the second conductive post on the substrate.

[0005] This disclosure also provides a display device, including a display substrate as described in any embodiment of this disclosure.

[0006] This disclosure also provides a method for fabricating a display substrate, the display substrate including a display area and a cathode ring region located outside the display area, the fabrication method comprising:

[0007] A substrate is provided, wherein the substrate contains a pixel driving circuit and a power supply electrode;

[0008] An insulating layer and a light-emitting structure layer are sequentially formed on the substrate. The insulating layer includes a first conductive pillar and a second conductive pillar. The light-emitting structure layer includes an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer includes a display anode located in the display area and a cathode voltage line located in the cathode ring area. The cathode is connected to the cathode voltage line. The display anode is connected to the pixel driving circuit through the first conductive pillar. The cathode voltage line includes multiple first cathode voltage lines and multiple second cathode voltage lines. The first cathode voltage lines extend along a first direction, and the second cathode voltage lines extend along a second direction. The first direction is parallel to the edge of the display substrate, and the second direction intersects the first direction. At least one second cathode voltage line is disposed between two adjacent first cathode voltage lines and connected to two adjacent first cathode voltage lines. The cathode voltage line is connected to the power supply electrode through the second conductive pillar. The orthographic projection of the cathode voltage line on the substrate covers the orthographic projection of the second conductive pillar on the substrate.

[0009] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0010] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure, but do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0011] Figure 1 This is a schematic diagram of the structure of a silicon-based OLED display device;

[0012] Figure 2 This is a schematic diagram of a planar structure of a silicon-based OLED display device;

[0013] Figure 3 This is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device;

[0014] Figure 4A This is an equivalent circuit diagram of a pixel driving circuit;

[0015] Figure 4B This is a timing diagram of a pixel driving circuit.

[0016] Figure 5 This is a schematic diagram of the structure of a silicon-based OLED display substrate, which is an exemplary embodiment of the present disclosure.

[0017] Figure 6A for Figure 5 A schematic diagram of the cross-sectional structure along the AA' direction;

[0018] Figure 6B , Figure 6C , Figure 6D and Figure 6E for Figure 5 Schematic diagram of four enlarged structures in region B;

[0019] Figure 6F This is a schematic diagram of a display substrate after the anode layer has been fabricated.

[0020] Figure 6G This is a schematic diagram of a display substrate after the pixel definition layer has been prepared.

[0021] Figure 7 This is a schematic diagram showing the silicon substrate formed according to an embodiment of the present disclosure;

[0022] Figure 8 This is a schematic diagram showing the formation of the first insulating layer according to an embodiment of the present disclosure;

[0023] Figure 9 This is a schematic diagram showing the formation of the reflective layer according to an embodiment of the present disclosure;

[0024] Figure 10 This is a schematic diagram showing the formation of the second insulating layer pattern according to an embodiment of the present disclosure;

[0025] Figure 11 This is a schematic diagram showing the anode layer pattern formed according to an embodiment of the present disclosure;

[0026] Figure 12 This is a schematic diagram showing the formation of the first pixel definition layer pattern according to an embodiment of this disclosure;

[0027] Figure 13 This is a schematic diagram showing the cathode pattern formed according to an embodiment of the present disclosure;

[0028] Figure 14 This is a schematic diagram showing the encapsulation layer pattern formed according to an embodiment of the present disclosure;

[0029] Figure 15 for Figure 5 Another enlarged structural diagram of region B in the middle. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0031] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0032] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0033] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0034] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0035] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0036] In this specification, to distinguish the two terminals of a transistor other than the control terminal, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0037] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0038] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0039] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0040] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0041] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0042] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0043] Figure 1 This is a schematic diagram of the structure of a silicon-based OLED display device. Figure 1 As shown, a silicon-based OLED display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may use a clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a sub-pixel row basis, where n can be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, a scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. A sub-pixel array can include multiple pixel sub-Pxij. Each pixel sub-Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. A sub-pixel Pxij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and connected to the j-th data signal line.

[0044] Figure 2 This is a schematic diagram of a planar structure of a silicon-based OLED display device. Figure 2As shown, on a plane parallel to the silicon-based OLED display device, the silicon-based OLED display device may include a display area 100 and a dummy pixel area 200 located outside the display area 100. In an exemplary embodiment, the display area 100 is the effective area (AA) for image display, and may include multiple sub-pixels forming a pixel array. Each sub-pixel may include a pixel driving circuit and a display light-emitting device, and the multiple sub-pixels are configured to display moving images or still images. In an exemplary embodiment, the dummy pixel area 200 is located outside the display area 100 and may include multiple dummy light-emitting devices. These dummy light-emitting devices are configured to present the shape of the display light-emitting device but do not display images.

[0045] In an exemplary embodiment, the silicon-based OLED display device may further include a cathode ring region 300, which may be located around the dummy pixel region 200, i.e., the dummy pixel region 200 is located between the display region 100 and the cathode ring region 300. In an exemplary embodiment, the cathode ring region 300 may include cathode voltage lines configured to provide a common voltage (VCOM). The cathode voltage lines may form a ring structure around the dummy pixel region 200, and the ring structure of the cathode voltage lines may be referred to as a cathode ring.

[0046] Figure 3 This is a schematic diagram of the planar structure of the display area in a silicon-based OLED display device. Figure 3 As shown, the display area may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuit in each sub-pixel is connected to a scan signal line and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The display light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0047] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel emitting red (R) light, the second sub-pixel P2 can be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 can be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels can be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons, and they can be arranged in horizontal parallel, vertical parallel, X-shaped, cross-shaped, triangular, square, diamond-shaped, or delta-shaped arrangements, etc., without limitation herein.

[0048] In an exemplary embodiment, a pixel unit may include four sub-pixels, which is not limited herein.

[0049] Figure 4A This is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure, etc. Figure 4A As shown, the pixel driving circuit may include three transistors (first transistor T1 to third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to five signal lines (scan signal line S, data signal line D, reference signal line REF, first power supply line VDD, and cathode voltage line VSS). The first node N1 and the second node N2 are the junction points representing the relevant electrical connections in the circuit diagram.

[0050] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the cathode voltage line VSS.

[0051] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the scan signal line S, the first electrode of the first transistor T1 is connected to the data signal line D, and the second electrode of the first transistor T1 is connected to the first node N1.

[0052] In an exemplary embodiment, the control electrode of the second transistor T2 is connected to the reference signal line REF, the first electrode of the second transistor T2 is connected to the second node N2, the second electrode of the second transistor T2 is connected to the first electrode of the display light-emitting device XL, and the second electrode of the display light-emitting device XL is connected to the cathode voltage line VSS.

[0053] In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the first power line VDD, and the second electrode of the third transistor T3 is connected to the second node N2.

[0054] In an exemplary embodiment, the signal of the first power line VDD can be a continuously supplied high-level signal, the signal of the cathode voltage line VSS can be a continuously supplied low-level signal, and the reference signal line REF can be a continuously supplied low-level signal or a variable voltage signal.

[0055] In an exemplary embodiment, the first transistor T1 is configured to receive the data voltage transmitted by the data signal line D under the control of the signal of the scan signal line S, store the data voltage in the storage capacitor C, and provide the data voltage to the first control electrode of the third transistor T3. The second transistor T2 is configured to provide the voltage signal of the second node N2 to the first electrode of the display light-emitting device XL under the control of the signal of the reference signal line REF. The third transistor T3 is configured to provide the signal of the first power line VDD to the second node N2 under the control of the signal of the first node N1, so as to drive the display light-emitting device XL to emit light.

[0056] In one exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be P-type transistors. In another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type transistors. In yet another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may include both P-type and N-type transistors. For example, the first transistor T1 and the second transistor T2 may be P-type metal-oxide-semiconductor transistors (PMOS), and the third transistor T3 may be an N-type metal-oxide-semiconductor transistor (NMOS). In exemplary embodiments, the display light-emitting device XL may be an OLED, or it may be a QLED, etc., and this disclosure is not limited thereto.

[0057] In an exemplary embodiment, multiple pixel driving circuits may be disposed in the display area, and auxiliary circuits may be disposed on the periphery of the display area (e.g., a dummy pixel area or other area). Exemplarily, the auxiliary circuit may include a reset sub-circuit connected to the second node N2, the discharge signal line, and the initial signal line. The reset sub-circuit is configured to provide the initial voltage supplied by the initial signal line to the second node N2 under the control of the signal from the discharge signal line.

[0058] Figure 4B This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 4A The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 4A In the example pixel driving circuit, the first transistor T1 and the second transistor T2 are P-type transistors, and the third transistor T3 is an N-type transistor.

[0059] In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0060] The first stage, S1, is called the reset or initialization stage. In this stage, the scan signal line S is high, the data signal line D is low, the reference signal line REF is low, and the first power supply line VDD is low. The reset sub-circuit provides an initial voltage to the second node N2. The low-level signal of the reference signal line REF turns on the P-type second transistor T2, allowing the initial voltage to be supplied to the first electrode of the display light-emitting device XL through the turned-on transistor T2, initializing the display light-emitting device XL. This quickly discharges (clears) the charge stored in the first electrode of the display light-emitting device XL, ensuring that the display light-emitting device XL does not emit light and achieving better dynamic contrast. During this stage, the high-level signal of the scan signal line S turns off the P-type first transistor T1.

[0061] The second stage, S2, is called the data writing stage. In this stage, the scan signal line S is low, the data signal line D is high, the reference signal line REF is low, and the first power supply line VDD is low. The low-level signal on the scan signal line S turns on the first P-type transistor T1. The data voltage on the data signal line D is supplied to the first node N1 through the turned-on transistor T1, charging the storage capacitor C, so that the data voltage output from the data signal line D is stored in the storage capacitor C.

[0062] The third stage, S3, is called the light-emitting stage. In this stage, the scan signal line S is high, the data signal line D is low, the reference signal line REF is low, and the first power supply line VDD is high. The high-level signal on the scan signal line S turns off the first P-type transistor T1, and the data voltage stored in the storage capacitor C is supplied to the first node N1. The potential of the first node N1 is the data voltage of the data signal line D, causing the third N-type transistor T3 to conduct. The low-level signal on the reference signal line REF turns on the second P-type transistor T2, allowing the high-level signal output from the first power supply line VDD to be supplied to the first electrode of the display light-emitting device XL through the conducting third transistor T3 and second transistor T2, causing the display light-emitting device XL to emit light.

[0063] In an exemplary embodiment, during the pixel driving circuit driving process, the driving current flowing through the third transistor T3 (referred to as the driving transistor) is determined by the voltage difference between the control electrode and the first electrode of the third transistor T3. The driving current of the third transistor T3 is:

[0064] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vdate)-Vth]2

[0065] Where I represents the drive current flowing through the third transistor T3, K represents a constant, Vgs represents the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth represents the threshold voltage of the third transistor T3, Vdate represents the data voltage provided by the data signal line D, and Vdd represents the power supply voltage output by the first power supply line VDD.

[0066] Figure 5 This is a schematic diagram of the structure of a silicon-based OLED display substrate, which is an exemplary embodiment of this disclosure. Figure 5 As shown, in an exemplary embodiment, on a plane parallel to the silicon-based OLED display substrate, the silicon-based OLED display substrate may include a display area 100, a cathode ring region 300 located around the display area 100, and a dummy pixel region 200 located between the display area 100 and the cathode ring region 300.

[0067] In an exemplary embodiment, the display area 100 may include a plurality of pixel driving circuits and a plurality of display light-emitting devices P a Display light-emitting device P a It may include a display anode, a cathode, and a display light-emitting layer disposed between the display anode and the cathode, and multiple display light-emitting devices P a The display anode is connected to multiple pixel driving circuits.

[0068] In an exemplary embodiment, the dummy pixel region 200 may include a plurality of dummy light-emitting devices P b Virtual light-emitting device P b It may include a dummy anode, a cathode, and a dummy light-emitting layer disposed between the dummy anode and the cathode, and multiple dummy light-emitting devices P b The dummy anode can be in a floating state with no electrical connection, or multiple dummy light-emitting devices P b The dummy anode and cathode can both be connected to the cathode voltage line, and both have the same potential. Therefore, the dummy light-emitting device P can be guaranteed. b It does not emit light.

[0069] In an exemplary embodiment, the cathode ring region 300 may include a cathode voltage line and a cathode, the cathode voltage line being connected to the cathode through an opening in the pixel definition layer, and the cathode voltage line being configured to provide a common voltage (VCOM). The cathode voltage line may be located at the dummy light-emitting device P. b On the side furthest from the display area 100, and can form a ring around the dummy light-emitting device P. b The ring structure, the cathode voltage line of the ring structure can be called a cathode ring.

[0070] In some display panels, when the cathode voltage line is connected to the cathode through the pixel definition layer opening, the cathode becomes thinner at the beveled sidewall of the pixel definition layer opening, increasing the resistance. The connection structure of the entire cathode and multiple cathode voltage lines can be understood as a series resistance structure along the direction away from the display area, which further increases the cathode connection resistance, affects the voltage drop (IR DROP) of the display area, and in severe cases, can cause the display device to go black.

[0071] Figure 6A for Figure 5 A schematic diagram of the cross-sectional structure along the AA' direction. Figure 6A The display light-emitting device P a This illustrates a structure that achieves full color using white light and a color filter. For example... Figure 6A As shown, a silicon-based OLED display device may include: a silicon substrate 10, a pixel driving circuit integrated on the silicon substrate 10 of the display region 100, a power supply electrode integrated on the silicon substrate 10 of the cathode ring region 300, a light-emitting structure layer 20 disposed on the silicon substrate 10, a first encapsulation layer 40 disposed on the side of the light-emitting structure layer 20 away from the silicon substrate 10, a color filter structure layer 50 disposed on the side of the first encapsulation layer 40 away from the silicon substrate 10, a second encapsulation layer (not shown) disposed on the side of the color filter structure layer 50 away from the silicon substrate 10, and a cover plate layer (not shown) disposed on the side of the second encapsulation layer away from the silicon substrate 10. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited herein.

[0072] In an exemplary embodiment, the silicon substrate 10 can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The pixel driving circuit and power supply circuit can be fabricated on the silicon substrate 10 using silicon semiconductor processes (e.g., CMOS processes). The pixel driving circuit is connected to the scan signal lines and data signal lines, respectively, and may include multiple transistors and storage capacitors. Figure 6A The example uses only one transistor. The transistor may include a control electrode G, a first electrode S, and a second electrode D. The control electrode G, the first electrode S, and the second electrode D can be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and can be connected to other electrical structures (such as traces) through the connection electrodes.

[0073] In an exemplary embodiment, the light-emitting structure layer 20 of the display area 100 may include a display anode 31A, a pixel definition layer, a display light-emitting layer 34A, and a cathode 35. The display anode 31A is connected to the second electrode D of a transistor via a connecting electrode (first reflective electrode 141). The pixel definition layer is provided with a first pixel opening, which exposes at least a portion of the display anode 31A. The display light-emitting layer 34A is connected to the display anode 31A via the first pixel opening, and the cathode 35 is connected to the display light-emitting layer 34A. The display light-emitting layer 34A emits light under the drive of the display anode 31A and the cathode 35. In an exemplary embodiment, the display light-emitting layer 34A may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device emitting white light, the display light-emitting layers 34A of all sub-pixels may be a common layer connected together.

[0074] In an exemplary embodiment, the light-emitting structure layer 20 of the dummy pixel region 200 may include a dummy anode 31B, a pixel definition layer, a dummy light-emitting layer 34B, and a cathode 35. The dummy anode 31B may be in a floating state and have no electrical connection. The pixel definition layer is provided with a second pixel opening, which exposes at least part of the dummy anode 31B. The dummy light-emitting layer 34B is connected to the dummy anode 31B through the second pixel opening, and the cathode 35 is connected to the dummy light-emitting layer 34B.

[0075] In an exemplary embodiment, the light-emitting structure layer 20 of the cathode ring region 300 may include a cathode voltage line 32, a pixel definition layer and a cathode 35. The pixel definition layer is provided with a third opening, which exposes at least a portion of the cathode voltage line 32. The cathode voltage line 32 is connected to the cathode 35 through the third opening. The cathode voltage line 32 is connected to the power supply electrode 301 through a connection electrode (third reflection electrode 143) and is configured to provide a common voltage (VCOM).

[0076] In an exemplary embodiment, the first encapsulation layer 40 and the second encapsulation layer (not shown in the figure) can be encapsulated using a thin film encapsulation (TFE) method, which can ensure that external moisture cannot enter the light-emitting structure layer. The cover layer (not shown in the figure) can be made of glass, or a flexible plastic such as colorless polyimide.

[0077] In an exemplary embodiment, the color filter structure layer 50 may include a black matrix (BM) and a color filter (CF). The position of the color filter may correspond to the position of the light-emitting device. The black matrix may be located between adjacent color filters. The color filters are configured to filter the white light emitted by the light-emitting device into red (R) light, green (G) light, and blue (B) light, forming red sub-pixels, green sub-pixels, and blue sub-pixels.

[0078] Figure 6B , Figure 6C , Figure 6D and Figure 6E for Figure 5 A schematic diagram of four enlarged structures in region B. (See diagram below.) Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E As shown, the display substrate includes: a silicon substrate 10, an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode sequentially disposed on the silicon substrate 10. The anode layer includes a display anode 31A disposed in the display area 100 and a cathode voltage line 32 disposed in the cathode ring area 300. The cathode voltage line 32 includes multiple first cathode voltage lines 320 and multiple second cathode voltage lines 321. Each second cathode voltage line 321 is disposed between two adjacent first cathode voltage lines 320 and connected to the two adjacent first cathode voltage lines 320.

[0079] In this embodiment of the disclosure, the substrate of the display substrate may be made of other materials besides the silicon substrate 10, and this embodiment of the disclosure does not limit this.

[0080] In an exemplary implementation, such as Figure 6B and Figure 6C As shown, multiple first cathode voltage lines 320 extend along the first direction X, and multiple second cathode voltage lines 321 extend along the second direction Y, with the first direction X and the second direction Y intersecting.

[0081] In an exemplary embodiment, for both sides of the display device in the left-right direction, the first direction X is the row direction and the second direction Y is the column direction. For both sides of the display device in the up-down direction, the first direction X is the column direction and the second direction Y is the row direction. That is, the first direction X is a direction parallel to the edge of the display substrate.

[0082] In an exemplary embodiment, the first direction X and the second direction Y are perpendicular to each other.

[0083] In an exemplary implementation, such as Figure 6AAs shown, the silicon substrate 10 includes a power supply electrode 301, and a cathode voltage line 32 is connected to the power supply electrode 301 through a metal via (i.e., the second conductive post 13B and the fifth conductive post 16C described below; in some other exemplary embodiments, when no reflective layer is provided, the metal via is the second conductive post 13B described below). Exemplarily, the metal via can be a tungsten via.

[0084] like Figures 6B to 6E As shown in the present embodiment, the cathode voltage line 32 is connected to the power supply electrode 301 through a metal via. It can be either the first cathode voltage line 320 or the second cathode voltage line 321 connected to the power supply electrode 301 through a metal via. The specific position of the metal via can be adjusted according to the actual electrical connection needs. For example, it can be located in the area covered by the first cathode voltage line 320 or in the area covered by the second cathode voltage line 321 between adjacent first cathode voltage lines 320. The present embodiment does not limit this.

[0085] In an exemplary embodiment, the length of the metal via on a plane parallel to the display substrate can be between 0.3µm and 0.5µm, and the width of the metal via can be between 0.3µm and 0.5µm. For example, the length of the metal via can be 0.4µm, and the width of the metal via can be 0.4µm.

[0086] In an exemplary implementation, such as Figure 6B and Figure 6C As shown, the orthogonal projection of the cathode voltage line 32 on the silicon substrate 10 covers the orthogonal projection of the metal via on the silicon substrate 10.

[0087] In an exemplary implementation, such as Figure 6E As shown, the width b1 of the first cathode voltage line 320 along the direction perpendicular to the first direction X is greater than the width b2 of the second cathode voltage line 321 along the direction perpendicular to the second direction Y.

[0088] In an exemplary implementation, such as Figures 6B to 6E As shown, on the side of the cathode ring region 300 near the display region 100, the cathode voltage line 32 forms a first sawtooth structure edge 320_1, and the orthogonal projection of the pixel definition layer on the substrate 10 covers the orthogonal projection of the first sawtooth structure edge 320_1 on the substrate 10.

[0089] In some exemplary implementations, such as Figure 5 , Figures 6A to 6DAs shown, the anode layer also includes a dummy anode 31B located in the dummy pixel region 200. The dummy anode 31B forms a second sawtooth structure edge on the side near the cathode ring region 300. The edges of the first sawtooth structure and the edges of the second sawtooth structure are complementary structures.

[0090] In some exemplary implementations, such as Figure 6E As shown, the pixel definition layer of the cathode ring region 300 includes a third opening, which exposes at least a portion of the first cathode voltage line 320 and at least a portion of the second cathode voltage line 321 (the position of the third opening in the figure is the position of the exposed first cathode voltage line 320 and second cathode voltage line 321). The edge of the second cathode voltage line 321 exposed by the third opening near the dummy pixel region 200 is a smooth curved surface that bulges towards the dummy pixel region 200 (i.e., Figure 6E The area marked by the dashed box in the image (area C).

[0091] Figure 6F This is a schematic planar view of a display substrate after the anode layer has been prepared according to an embodiment of this disclosure. Figure 6G This is a schematic diagram of a display substrate after the pixel definition layer has been prepared according to an embodiment of this disclosure. In this diagram, 17 represents the first pixel definition layer, and 33 represents the second pixel definition layer. In some exemplary embodiments, the pixel definition layer may also be a single layer, and this disclosure does not limit this. Figure 6F and 6G As shown, in the cathode ring region 300, the anode layer includes a first etched region, which is located in the area enclosed by the adjacent first cathode voltage line 320 and the adjacent second cathode voltage line 321. The pixel definition layer of the cathode ring region 300 covers the first etched region and the cathode voltage lines located around the first etched region.

[0092] In this embodiment, the cathode voltage line 32 at the location of the first sawtooth structure edge 320_1 is covered by the pixel definition layer and therefore does not have conductive properties. Only the first cathode voltage line 320 and the second cathode voltage line 321 exposed by the third opening have conductive properties and can play the role of transmitting low voltage to the cathode 35.

[0093] In some exemplary implementations, such as Figures 6A to 6E As shown, the pixel definition layer of the dummy pixel region 200 includes a second pixel opening, which exposes the dummy anode 31B (the position of the second pixel opening in the figure is the same as the position of the dummy anode 31B).

[0094] The distance b3 between the edge of the cathode voltage line near the dummy pixel region 200 and the edge of the second pixel opening near the cathode ring region 300 is less than the width b1 of the first cathode voltage line 320 along the direction perpendicular to the first direction X.

[0095] In some exemplary implementations, such as Figures 6A to 6D As shown, the distance b4 between adjacent first cathode voltage lines 320 is greater than the width b1 of the first cathode voltage line 320 along the direction perpendicular to the first direction X.

[0096] In some exemplary implementations, such as Figures 6A to 6D As shown, the pixel definition layer of the display area 100 includes a first pixel opening, which exposes the display anode 31A (the position of the first pixel opening in the figure is the same as the position of the display anode 31A).

[0097] The pixel definition layer of the cathode ring region 300 includes a third opening, the shape of which is different from the shape of the first pixel opening.

[0098] In some exemplary implementations, such as Figures 6A to 6D As shown, the width b1 of the first cathode voltage line 320 along the direction perpendicular to the first direction X is smaller than the width b5 of the first pixel opening along the direction perpendicular to the first direction X.

[0099] In an exemplary implementation, such as Figure 6B and Figure 6C As shown, the first cathode voltage line 320 includes N lines, and the first first cathode voltage line 320 to the Nth first cathode voltage line 320 are arranged sequentially along the direction close to the display area 100. The second cathode voltage line 321 includes the first sub-second cathode voltage line 321_1 to the (N-1)th sub-second cathode voltage line 321_N-1, wherein the i-th sub-second cathode voltage line 321_i is located between the i-th first cathode voltage line 320 and the (i+1)th first cathode voltage line 320, and i is a natural number between 1 and N-1.

[0100] In an exemplary implementation, such as Figure 6B As shown, there exists at least one i-th sub-second cathode voltage line 321_i and one (i+1)-th sub-second cathode voltage line 321_i+1 that lie on a straight line.

[0101] In an exemplary implementation, such as Figure 6B As shown, for any i-th sub-second cathode voltage line 321_i, there exists an (i+1)-th sub-second cathode voltage line 321_i+1 that lies on the same straight line as the i-th sub-second cathode voltage line 321_i.

[0102] In an exemplary implementation, such as Figure 6B As shown, the number of second cathode voltage lines 321 between two adjacent first cathode voltage lines 320 is the same as the number of second conductive posts 13B covered by each first cathode voltage line 320.

[0103] In an exemplary implementation, such as Figure 6C As shown, neither the i-th sub-second cathode voltage line 321_i nor the (i+1)-th sub-second cathode voltage line 321_i+1 lies on a straight line.

[0104] In an exemplary embodiment, the ratio of the area of ​​the orthographic projection of the cathode voltage line 32 onto the silicon substrate 10 to the area of ​​the orthographic projection of the cathode ring region 300 onto the silicon substrate 10 is close to or the same as the ratio of the area of ​​the orthographic projection of the display anode 31A onto the silicon substrate 10 to the area of ​​the orthographic projection of the display area 100 onto the silicon substrate 10. That is, the distribution density of the cathode voltage line 32 in the cathode ring region 300 and the distribution density of the display anode 31A in the display area 100 are close to or the same. In this embodiment, "close to the same" means that the difference between the distribution density of the cathode voltage line 32 in the cathode ring region 300 and the distribution density of the display anode 31A in the display area 100 is less than a preset difference threshold. This difference threshold can be set according to actual needs, and this embodiment does not limit it.

[0105] In an exemplary embodiment, the anode layer includes a composite metal layer and a transparent oxide layer sequentially disposed on a silicon substrate 10. Exemplarily, the composite metal layer includes titanium / aluminum / titanium (Ti / Al / Ti); the transparent oxide layer is indium tin oxide (ITO).

[0106] In an exemplary embodiment, the anode layer includes a composite metal layer or a transparent oxide layer disposed on a silicon substrate 10.

[0107] In an exemplary implementation, such as Figure 6A , Figure 6B and Figure 6C As shown, the pixel definition layer includes a first pixel definition layer 17 and a second pixel definition layer 33. The surface of the first pixel definition layer 17 is flush with the surface of the anode layer. The anode layer includes multiple anode blocks, which can be a display anode 31A, a dummy anode 31B, and a cathode voltage line 32. The first pixel definition layer 17 is disposed in the spacer between adjacent anode blocks, and the second pixel definition layer 33 is disposed on the side of the first pixel definition layer 17 away from the silicon substrate 10 and covers the first pixel definition layer 17. Figure 6F As shown, in the display area 100 and the dummy pixel area 200, the interval between adjacent anode blocks is the area between adjacent display anodes 31A and the area between adjacent dummy anodes 31B; in the cathode ring area 300, the interval between adjacent anode blocks is the area enclosed by adjacent first cathode voltage lines 320 and adjacent second cathode voltage lines 321, which is the aforementioned first etching area.

[0108] In an exemplary implementation, such as Figure 6B, Figure 6C and Figure 6D As shown, in the cathode ring region 300, the pixel definition layer includes multiple pixel definition islands, which are set in the region enclosed by two adjacent first cathode voltage lines 320 and two adjacent second cathode voltage lines 321.

[0109] Figure 6B and Figure 6C The pixel definition of the island is a rounded rectangle. Figure 6D The pixel definition island is elliptical in shape; however, this embodiment of the present disclosure is not limited to this, and the pixel definition island can also be any other shape.

[0110] In some other exemplary embodiments, at least one pixel definition island may also exist in the cathode ring region 300, which is not located in the area enclosed by two adjacent first cathode voltage lines 320 and two adjacent second cathode voltage lines 321.

[0111] In some exemplary implementations, such as Figure 6B , Figure 6C and Figure 6D As shown, the distance b6 between the pixel definition island and the first cathode voltage line 320 along the second direction Y is greater than the distance b7 between the pixel definition island and the second cathode voltage line 321 along the first direction X.

[0112] In some exemplary implementations, such as Figure 6B and Figure 6C As shown, the shortest distance b8 between any vertices of the pixel definition island and the cathode voltage line in the third opening is greater than the shortest distance b9 between any side of the pixel definition island and the cathode voltage line in the third opening.

[0113] In an exemplary embodiment, on a plane parallel to the display substrate, the length of the pixel definition island can be between 3µm and 5µm, the width of the pixel definition island can be between 3µm and 5µm, and the spacing between adjacent pixel definition islands can be between 1µm and 3µm. For example, the spacing between adjacent pixel definition islands can be 2µm.

[0114] In an exemplary implementation, such as Figure 6A As shown, the orthographic projection of the second pixel definition layer 33 on the silicon substrate 10 overlaps with the orthographic projection of the display anode 31A on the silicon substrate 10.

[0115] In an exemplary implementation, such as Figure 6A As shown, the light-emitting device P a Display anode 31A, dummy light-emitting device P bThe dummy anode 31B and the cathode voltage line 32 of the cathode ring region 300 can be set in the same layer and formed simultaneously through the same patterning process.

[0116] In an exemplary implementation, such as Figure 6A As shown, the light-emitting device P a The display light-emitting layer 34A and the virtual light-emitting device P b The virtual light-emitting layer 34B can be set in the same layer and formed simultaneously through the same evaporation process.

[0117] In an exemplary implementation, such as Figure 6A As shown, the light-emitting device P a cathode, virtual light-emitting device P b The cathode and the cathode ring region 300 can be arranged in the same layer and are an integrated structure that is interconnected.

[0118] The following is an exemplary description of the fabrication process of a display device. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display device. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0119] In an exemplary embodiment, a silicon-based OLED display device may include a display area 100, a dummy pixel area 200 located around the display area 100, and a cathode ring area 300 located on the side of the dummy area area 200 away from the display area 100. Taking an example where the display area includes three display units, the fabrication process of the display device may include the following steps.

[0120] (1) A silicon substrate 10 is fabricated. The display area 100 includes multiple display units. Each display unit's silicon substrate 10 integrates a pixel driving circuit. The silicon substrate 10 of the cathode ring region 300 integrates a power supply circuit, such as... Figure 7 As shown. This is an illustrative example. Figure 7 The diagram illustrates three display units in the display area 100: a first display unit, a second display unit, and a third display unit. It also illustrates the driving transistor 11 included in the pixel driving circuit and the power supply electrode 301 of the cathode ring region 300. In an exemplary embodiment, the driving transistor 11 of the display area 100 includes an active layer, a gate electrode, a source electrode, a drain electrode, and a gate connection electrode. The source electrode and drain electrode are respectively connected to the active layer via conductive pillars, and the gate connection electrode is connected to the gate electrode via conductive pillars. The silicon substrate 10 can be fabricated using mature CMOS integrated circuit technology, and this disclosure does not limit this process. After fabrication, the surface of the silicon substrate 10 exposes the source electrode, drain electrode, and gate connection electrode of the display area 100, as well as the power supply electrode 301 of the cathode ring region 300.

[0121] (2) A first insulating film is deposited on a silicon substrate 10. The first insulating film is patterned using a patterning process to form a pattern of a first insulating layer 12 covering the silicon substrate 10. Multiple first vias are formed in the first insulating layer 12 of the display area 100, and at least one second via is formed in the first insulating layer 12 of the cathode ring region 300. The multiple first vias expose the drain electrode of each display unit, and the second vias expose the power supply electrode 301. Subsequently, multiple first conductive pillars 13A are formed within the first vias of the first insulating layer 12, and multiple second conductive pillars 13B are formed within the second vias of the first insulating layer 12. The first conductive pillars 13A within the first vias are connected to the drain electrode of the corresponding display unit, and the second conductive pillars 13B within the second vias are connected to the power supply electrode 301 of the cathode ring region 300. Figure 8As shown. In an exemplary embodiment, the first conductive post 13A and the second conductive post 13B can be made of metallic material. After the first conductive post 13A and the second conductive post 13B are formed through a filling process, a polishing process can be performed. The polishing process etches and rubs the surfaces of the first insulating layer 12, the first conductive post 13A, and the second conductive post 13B, removing part of the thickness of the first insulating layer 12, the first conductive post 13A, and the second conductive post 13B, so that the first insulating layer 12, the first conductive post 13A, and the second conductive post 13B form flush surfaces. In some possible implementations, the first conductive post 13A and the second conductive post 13B can be made of tungsten (W), and the via filled with tungsten metal is called a tungsten via (W-via). When the thickness of the first insulating layer 12 is large, using tungsten vias can ensure the stability of the conductive path. Since the process of making tungsten vias is mature, the surface flatness of the obtained first insulating layer 12 is good, which is beneficial to reducing contact resistance. Tungsten vias are not only suitable for connections between the silicon substrate 10 and the reflective layer, but also for connections between the reflective layer and the anode layer, as well as connections between other wiring layers.

[0122] (3) A first metal thin film is deposited on the silicon substrate 10 forming the aforementioned structure. The first metal thin film is patterned using a patterning process to form a reflective layer pattern on the first insulating layer 12. The reflective layer includes multiple first reflective electrodes 141 disposed in the display area 100, multiple second reflective electrodes 142 disposed in the dummy pixel area 200, and multiple third reflective electrodes 143 disposed in the cathode ring area 300. The first reflective electrodes 141 are connected to the drain electrode via a first conductive post 13A. The second reflective electrodes 142 are not connected to other signal lines. The third reflective electrodes 143 are connected to the power supply electrode 301 via a second conductive post 13B. Figure 9 As shown. In an exemplary embodiment, the first reflective electrode 141 of each display unit is used to form a microcavity structure with the subsequently formed cathode. By utilizing the strong reflection effect of the reflective electrode, the light emitted directly from the organic light-emitting layer interferes with the light reflected by the reflective electrode, thereby improving the color gamut of the emitted light and enhancing the brightness of the emitted light.

[0123] (4) A second insulating film is deposited on the silicon substrate 10 forming the aforementioned structure. The second insulating film is patterned by a patterning process to form a pattern of a second insulating layer 15 covering the silicon substrate 10. The second insulating layer 15 of the display area 100 forms a plurality of third vias. The second insulating layer 15 of the dummy pixel area 200 forms a plurality of fourth vias. The second insulating layer 15 of the cathode ring area 300 forms at least one fifth via. The plurality of third vias expose the first reflective electrode 141 of the display area 100, the plurality of fourth vias expose the second reflective electrode 142 of the dummy pixel area 200, and the fifth via exposes the third reflective electrode 143 of the cathode ring area 300. Subsequently, multiple third conductive pillars 16A are formed in the third via on the second insulating layer 15, multiple fourth conductive pillars 16B are formed in the fourth via on the second insulating layer 15, and multiple fifth conductive pillars 16C are formed in the fifth via on the second insulating layer 15. The third conductive pillars 16A in the third via are connected to the first reflective electrode 141 of the display unit, the fourth conductive pillars 16B in the fourth via are connected to the second reflective electrode 142 of the dummy pixel region 200, and the fifth conductive pillars 16C in the fifth via are connected to the third reflective electrode 143 of the cathode ring region 300. Figure 10 As shown. In an exemplary embodiment, the third conductive post 16A, the fourth conductive post 16B, and the fifth conductive post 16C can be made of metallic material. After forming the third conductive post 16A, the fourth conductive post 16B, and the fifth conductive post 16C through a filling process, a polishing process can be performed. The polishing process etches and abrades the surfaces of the second insulating layer 15, the third conductive post 16A, the fourth conductive post 16B, and the fifth conductive post 16C, removing a portion of their thickness, resulting in flush surfaces. In some possible implementations, the third conductive post 16A, the fourth conductive post 16B, and the fifth conductive post 16C can be made of tungsten (W).

[0124] (5) A composite metal thin film and a transparent conductive thin film are sequentially deposited on the silicon substrate 10 forming the aforementioned structure. The composite metal thin film and the transparent conductive thin film are patterned using a patterning process. An anode layer pattern is formed on the second insulating layer 15 of the display area 100, the dummy pixel area 200, and the cathode ring area 300. The anode layer includes a display anode 31A disposed in the display area 100, a dummy anode 31B disposed in the dummy pixel area 200, and a cathode voltage line 32 disposed in the cathode ring area 300. The display anode 31A is connected to the first reflective electrode 141 via a third conductive post 16A, the dummy anode 31B is connected to the second reflective electrode 142 via a fourth conductive post 16B, and the cathode voltage line 32 is connected to the third reflective electrode 143 via a fifth conductive post 16C. Figure 11 As shown. In the display area 100, the display anode 31A is connected to the first reflective electrode 141 via the third conductive post 16A. The first reflective electrode 141 is connected to the drain electrode of the driving thin-film transistor 11 via the first conductive post 13A. Thus, the electrical signal provided by the pixel driving circuit is transmitted to the display anode 31A through the first reflective electrode 141. The first reflective electrode 141 forms a conductive channel between the pixel driving circuit and the anode, and also forms a microcavity structure. This not only facilitates the control of the light-emitting device by the pixel driving circuit, but also makes the structure of the display substrate more compact, which is beneficial for the miniaturization of silicon-based OLED display devices. In the cathode ring region 300, the cathode voltage line 32 is connected to the third reflective electrode 143 via the fifth conductive post 16C. The third reflective electrode 143 is connected to the power supply electrode 301 via the second conductive post 13B. Thus, the low-voltage signal provided by the power supply electrode 301 is transmitted to the cathode voltage line 32 through the third reflective electrode 143.

[0125] For example, the anode layer material may include a composite metal layer and a transparent oxide layer sequentially disposed on the silicon substrate 10, or it may consist of only a single composite metal layer or a single transparent oxide layer. For example, the composite metal layer may include titanium / aluminum / titanium (Ti / Al / Ti); the transparent oxide layer may be indium tin oxide (ITO). The composite metal layer and the transparent oxide layer can be formed by deposition in two separate chambers followed by etching in a single step.

[0126] For example, the cathode voltage line 32 includes a plurality of first cathode voltage lines 320 and a plurality of second cathode voltage lines 321, each second cathode voltage line 321 being disposed between two adjacent first cathode voltage lines 320 and connected to the two adjacent first cathode voltage lines 320.

[0127] (6) A third insulating film is deposited on the silicon substrate 10 forming the aforementioned structure. The third insulating film is then etched indiscriminately using an etching gas to form a pattern of the first pixel definition layer 17 filling the gaps in the anode layer, such as... Figure 12 As shown.

[0128] (7) A pixel definition film is coated on the silicon substrate 10 forming the aforementioned structure. Through masking, exposure, and development processes, a second pixel definition layer (PDL) 33 pattern is formed in the display area 100, the dummy pixel area 200, and the cathode ring area 300. In the display area 100, the second pixel definition layer 33 has a first pixel opening that exposes the surface of the display anode 31A. In the dummy pixel area 200, the second pixel definition layer 33 has a second pixel opening that exposes the surface of the dummy anode 31B. In the cathode ring area 300, the second pixel definition layer 33 has a third opening that exposes part of the surface of the cathode voltage line 32. The first pixel opening limits the anode aperture ratio, the second pixel opening mainly increases the etching uniformity between the display area 100 and the dummy pixel area 200, and the third opening prevents corrosion of the metal in the cathode voltage line 32.

[0129] For example, a first pixel definition layer 17 is disposed in the spacer between adjacent anode blocks, and a second pixel definition layer 33 is disposed on the side of the first pixel definition layer 17 away from the silicon substrate 10 and covers the first pixel definition layer 17. In this way, the first pixel definition layer 17 can be prevented from being etched again.

[0130] Steps (6) and (7) in this embodiment can also be combined into one step, that is, only a single pixel definition layer is formed. This embodiment does not limit this.

[0131] For example, in the cathode ring region 300, the pixel definition layer includes multiple pixel definition islands (distributed in an island shape), each pixel definition island being disposed within the area enclosed by two adjacent first cathode voltage lines 320 and two adjacent second cathode voltage lines 321. The pixel definition islands not only facilitate cathode bonding (reducing cathode bonding resistance), but their uneven structure (in this embodiment, a portion of the pixel definition islands covers a portion of the cathode voltage lines, and another portion covers the first etched area; the height of the pixel definition islands covering the cathode voltage lines from the substrate is slightly greater than the height of the pixel definition islands covering the first etched area from the substrate) also facilitates subsequent thin-film encapsulation structures.

[0132] Subsequently, a display light-emitting layer 34A and a dummy light-emitting layer 34B are formed in the display area 100 and the dummy pixel area 200, respectively. Then, a cathode 35 is formed in the display area 100, the dummy pixel area 200, and the cathode ring area 300. For example, the cathode 35 can be a full-surface shape. In the display area 100, the display light-emitting layer 34A is connected to the display anode 31A through a first pixel opening, and the cathode 35 is connected to the display light-emitting layer 34A. In the dummy pixel area 200, the dummy light-emitting layer 34B is connected to the dummy anode 31B through a second pixel opening, and the cathode 35 is connected to the dummy light-emitting layer 34B. In the cathode ring area 300, the cathode 35 is connected to the cathode voltage line 32 through a third opening, as shown below. Figure 13 As shown. In an exemplary embodiment, the cathode 35 is a semi-transparent and semi-reflective electrode, which together with the aforementioned first reflective electrode 141 forms a microcavity structure.

[0133] In the aforementioned preparation process, the first, second, and third insulating films can be made of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), and can be a single-layer structure or a multi-layer composite structure. The first metal film can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The alloy material can be a single-layer structure or a multi-layer composite structure, such as a Mo / Cu / Mo composite structure. The transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO), or an ITO / Ag / ITO composite structure. The pixel defining layer can be made of polyimide, acrylic, or polyethylene terephthalate.

[0134] (8) On the silicon substrate 10 forming the aforementioned structure, a first encapsulation layer 40 pattern is formed in the display area 100, the dummy pixel area 200, and the cathode ring area 300. The first encapsulation layer 40 is a thin-film encapsulation structure, such as... Figure 14 As shown.

[0135] (9) On the silicon substrate 10 forming the aforementioned structure, a color filter layer 50 pattern is formed in the display area 100, the dummy pixel area 200, the cathode ring area 300, and a portion of the metal trace area 400. The color filter layer 50 of the display area 100 includes a first color unit 53, a second color unit 54, and a third color unit 55 that are spaced apart or overlapped. In an exemplary embodiment, the color units of the display area 100 may overlap to form a black matrix, or a black matrix may be set between the color units. The color filter layer 50 of the dummy pixel area 200 and the cathode ring area 300 may include the first color unit 53 and the second color unit 54 stacked together, such as... Figure 6AAs shown. In an exemplary embodiment, the first color unit can be a green unit G, the second color unit can be a red unit R, and the third color unit can be a blue unit B. In some possible implementations, the fabrication process of the color filter layer 50 includes: first forming the blue unit B, then forming the red unit R, and then forming the green unit G. The blue color filter has high adhesion; forming the blue unit B first can reduce the possibility of the color filter layer 50 peeling off from the cathode. Since the red unit R has low adhesion but good flowability, the formation of the red unit R can reduce the number of bubbles on the surfaces of the blue unit B and red unit R away from the cathode, thereby improving the uniformity of the film thickness at the overlapping position of the blue unit B and red unit R. Since the substrate material of the green unit G and the substrate material of the red unit R are approximately the same, the adhesion between the green unit G and the red unit R is large, which can reduce the possibility of the color filter layer 50 peeling off from the cathode. In some possible implementations, the color filter layer 50 may include other color units, such as white or yellow.

[0136] In subsequent processes, a second encapsulation layer pattern is formed in the display area 100, the dummy pixel area 200, and the cathode ring area 300. Then, a sealing process is used to form a cover plate, which is fixed to the silicon substrate 10 with sealant. Since the silicon substrate 10, the cover plate, and the sealant together form a closed space, it provides protection against water and oxygen, significantly improving the lifespan of the silicon-based OLED display substrate. Subsequently, the formed display motherboard is cut to form individual display substrates.

[0137] As can be seen from the structure of the display substrate and its fabrication process disclosed herein, by designing the shape of the cathode voltage lines as a mesh, this disclosure can ensure that the cathode voltage line etching load in the cathode ring region 300 is close to the display anode etching load in the display area, and can also improve the problem of cathode voltage line and cathode metal overlap, reduce cathode overlap resistance, reduce IR drop in the display area, and improve display effect.

[0138] The fabrication process disclosed herein can be implemented using mature fabrication equipment. The fabrication process is simple and does not require additional masking processes. It can be achieved simply by modifying the cathode ring metal arrangement. It has high compatibility, a simple process flow, is easy to maintain periodically, has high production efficiency, low production cost, and high yield. It is suitable for large-scale mass production. The fabricated display substrate can be used in virtual reality devices or augmented reality devices, or in other types of display devices, and has good application prospects.

[0139] The structure and its preparation process shown in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs. This disclosure does not limit these aspects.

[0140] Figure 15 for Figure 5 Another enlarged structural diagram of region B. In other exemplary embodiments, such as... Figure 15 As shown, at least one first cathode voltage line 320 includes a first sub-section 320_1 and a second sub-section 320_2 that are alternately arranged and interconnected along a first direction X. The shape of the first sub-section 320_1 is the same as the shape of the display anode 31A.

[0141] In some exemplary implementations, such as Figure 15 As shown, the orthographic projection of the first sub-part 320_1 on the silicon substrate 10 covers the orthographic projection of the second conductive post 13B on the silicon substrate 10.

[0142] In some exemplary implementations, such as Figure 15 As shown, the shape of the first sub-part 320_1 and the shape of the display anode 31A are both regular hexagonal; however, this disclosure does not limit this.

[0143] In some exemplary implementations, such as Figure 15 As shown, the second sub-part 320_2 is a connection structure provided between two adjacent first sub-parts 320_1 along the first direction X.

[0144] In some exemplary implementations, such as Figure 15 As shown, the second cathode voltage line 321 is a connection structure provided between two adjacent first sub-sections 320_1 along the second direction Y.

[0145] This disclosure also provides a method for fabricating a display substrate. In an exemplary embodiment, the display device includes a display area and a cathode ring region located outside the display area. The fabrication method includes the following steps:

[0146] A silicon substrate is provided, wherein the silicon substrate contains a pixel driving circuit and a power supply electrode;

[0147] An insulating layer and a light-emitting structure layer are sequentially formed on the substrate. The insulating layer includes a first conductive pillar and a second conductive pillar. The light-emitting structure layer includes an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer includes a display anode located in the display area and a cathode voltage line located in the cathode ring area. The cathode is connected to the cathode voltage line. The display anode is connected to the pixel driving circuit through the first conductive pillar. The cathode voltage line includes multiple first cathode voltage lines and multiple second cathode voltage lines. The first cathode voltage lines extend along a first direction, and the second cathode voltage lines extend along a second direction. The first direction is parallel to the edge of the display substrate, and the second direction intersects the first direction. At least one second cathode voltage line is disposed between two adjacent first cathode voltage lines and connected to two adjacent first cathode voltage lines. The cathode voltage line is connected to the power supply electrode through the second conductive pillar. The orthographic projection of the cathode voltage line on the substrate covers the orthographic projection of the second conductive pillar on the substrate.

[0148] This disclosure also provides a display device, including the display substrate described in any of the foregoing embodiments. The display device may be a virtual reality device, an augmented reality device, or a near-eye display device, or it may be a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, or any other product or component with display function.

[0149] While the embodiments disclosed herein are as described above, the above content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein, but the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a substrate and a display area and a cathode ring area disposed on the substrate, the cathode ring area being located outside the display area; On a plane perpendicular to the display substrate, the display substrate includes an insulating layer disposed on the substrate and a light-emitting structure layer disposed on the insulating layer. The light-emitting structure layer includes an anode layer, a pixel definition layer, a light-emitting layer, and a cathode. The anode layer includes a plurality of display anodes located in the display area and a cathode voltage line located in the cathode ring area. The cathode is connected to the cathode voltage line. The substrate includes a power supply electrode and a pixel driving circuit. The insulating layer includes a first conductive pillar and a second conductive pillar. The display anode is connected to the pixel driving circuit through the first conductive pillar. The display substrate further includes a dummy pixel region disposed between the display area and the cathode ring region. The dummy pixel region includes multiple dummy light-emitting devices. The cathode voltage line is located on the side of the dummy light-emitting device away from the display area, forming a ring structure around the dummy light-emitting device. In the ring structure, the cathode voltage line includes multiple first cathode voltage lines and multiple second cathode voltage lines. The first cathode voltage lines extend along a first direction, and the second cathode voltage lines extend along a second direction. The first direction is parallel to the edge of the display substrate, and the second direction intersects the first direction. At least one second cathode voltage line is disposed between two adjacent first cathode voltage lines and connected to the two adjacent first cathode voltage lines. The cathode voltage line is connected to the power supply electrode through the second conductive post, and the orthographic projection of the cathode voltage line on the substrate covers the orthographic projection of the second conductive post on the substrate; in, The distribution density of the cathode voltage lines in the cathode ring region is the same as or approximately the same as the distribution density of the display anode in the display region.

2. The display substrate according to claim 1, wherein, The width of the first cathode voltage line in the direction perpendicular to the first direction is greater than the width of the second cathode voltage line in the direction perpendicular to the second direction.

3. The display substrate according to claim 1, wherein, In the cathode ring region, the anode layer includes a first etched region located within the area enclosed by an adjacent first cathode voltage line and an adjacent second cathode voltage line. The pixel definition layer of the cathode ring region covers the first etched region and the cathode voltage lines located around the first etched region.

4. The display substrate according to claim 1, wherein, On the side of the cathode ring region near the display area, the cathode voltage line forms a first sawtooth structure edge, and the orthogonal projection of the pixel definition layer on the substrate covers the orthogonal projection of the first sawtooth structure edge on the substrate.

5. The display substrate according to claim 4, wherein the anode layer further includes a dummy anode located in the dummy pixel region, the dummy anode being floating.

6. The display substrate according to claim 5, wherein, The dummy anode forms a second sawtooth structure edge on the side near the cathode ring region, and the first sawtooth structure edge and the second sawtooth structure edge are complementary structures.

7. The display substrate according to claim 5, wherein, The pixel definition layer of the cathode ring region includes a third opening that exposes at least a portion of the first cathode voltage line and at least a portion of the second cathode voltage line. The edge of the second cathode voltage line exposed by the third opening near the dummy pixel region is a smooth curved surface that bulges toward the dummy pixel region.

8. The display substrate according to claim 5, wherein, The pixel definition layer of the virtual pixel region includes a second pixel opening; The distance between the edge of the cathode voltage line near the dummy pixel area and the edge of the second pixel opening near the cathode ring area is less than the width of the first cathode voltage line in the direction perpendicular to the first direction.

9. The display substrate according to claim 1, wherein, The distance between adjacent first cathode voltage lines is greater than the width of the first cathode voltage lines in the direction perpendicular to the first direction.

10. The display substrate according to claim 1, wherein, The pixel definition layer of the display area includes a first pixel opening; The width of the first cathode voltage line in the direction perpendicular to the first direction is smaller than the width of the first pixel opening in the direction perpendicular to the first direction.

11. The display substrate according to claim 1, wherein, The number of second cathode voltage lines between two adjacent first cathode voltage lines is the same as the number of second conductive pillars covered by each first cathode voltage line.

12. The display substrate according to claim 1, wherein, The second cathode voltage line and the arrangement of the second conductive post are on a straight line.

13. The display substrate according to claim 1, wherein, The pixel definition layer includes a first pixel definition layer and a second pixel definition layer. The surface of the first pixel definition layer away from the substrate is flush with the surface of the anode layer away from the substrate. The first pixel definition layer is disposed in the spacer portion of the anode layer. The second pixel definition layer is disposed on the side of the first pixel definition layer away from the substrate and covers the first pixel definition layer.

14. The display substrate according to claim 13, wherein, In the display area, the orthographic projection of the second pixel definition layer on the substrate overlaps with the orthographic projection of the display anode on the substrate.

15. The display substrate according to claim 1, wherein, The pixel definition layer of the cathode ring region includes multiple pixel definition islands, and the distance between the pixel definition island and the first cathode voltage line along the second direction is greater than the distance between the pixel definition island and the second cathode voltage line along the first direction.

16. The display substrate according to claim 15, wherein, The pixel definition layer of the cathode ring region includes a third opening that exposes at least a portion of the first cathode voltage line and at least a portion of the second cathode voltage line. The pixel definition island is rounded rectangular in shape. The shortest distance between any vertices of the pixel definition island and the cathode voltage line within the third opening is greater than the shortest distance between any side of the pixel definition island and the cathode voltage line within the third opening.

17. The display substrate according to claim 1, wherein, The first cathode voltage line includes N lines, and the first to the Nth first cathode voltage lines are arranged sequentially along the direction close to the display area; The second cathode voltage line includes the first sub-second cathode voltage line to the (N-1)th sub-second cathode voltage line. The i-th sub-second cathode voltage line is located between the i-th first cathode voltage line and the (i+1)-th first cathode voltage line, where i is a natural number between 1 and N-1.

18. The display substrate according to claim 17, wherein, There exists at least one i-th sub-second cathode voltage line and one (i+1)-th sub-second cathode voltage line lying on a straight line.

19. The display substrate according to claim 17, wherein, No two sub-second cathode voltage lines (i+1) are on the same straight line.

20. The display substrate according to claim 1, wherein, The ratio of the area of ​​the orthographic projection of the cathode voltage line on the substrate to the area of ​​the orthographic projection of the cathode ring region on the substrate is a first ratio, and the ratio of the area of ​​the orthographic projection of the display anode on the substrate to the area of ​​the orthographic projection of the display area on the substrate is a second ratio. The first ratio is the same as the second ratio, or the difference between the first ratio and the second ratio is less than a preset difference threshold.

21. The display substrate according to claim 1, wherein, At least one first cathode voltage line includes a first sub-section and a second sub-section that are alternately arranged and interconnected along the first direction. The shape of the first sub-section is the same as that of the display anode, and the second sub-section is a connection structure disposed between two adjacent first sub-sections along the first direction.

22. The display substrate according to claim 21, wherein, The orthographic projection of the first sub-part on the substrate overlaps the orthographic projection of the second conductive post on the substrate.

23. A display device, comprising: The display substrate as described in any one of claims 1 to 22.

24. A method for fabricating a display substrate, the display substrate comprising a display area, a dummy pixel area, and a cathode ring area, the cathode ring area being located outside the display area, the dummy pixel area being disposed between the display area and the cathode ring area, the dummy pixel area comprising a plurality of dummy light-emitting devices, the fabrication method comprising: A substrate is provided, wherein the substrate contains a pixel driving circuit and a power supply electrode; An insulating layer and a light-emitting structure layer are sequentially formed on the substrate. The insulating layer includes a first conductive pillar and a second conductive pillar. The light-emitting structure layer includes an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer includes a display anode located in the display area and a cathode voltage line located in the cathode ring area. The cathode is connected to the cathode voltage line. The display anode is connected to the pixel driving circuit through the first conductive pillar. The cathode voltage line is located on the side of the dummy light-emitting device away from the display area, forming a ring structure around the dummy light-emitting device. In the ring structure, the cathode voltage line includes multiple first cathode voltage lines and multiple second cathode voltage lines. The first cathode voltage lines extend along a first direction, and the second cathode voltage lines extend along a second direction. The first direction is parallel to the edge of the display substrate, and the second direction intersects the first direction. At least one second cathode voltage line is disposed between two adjacent first cathode voltage lines and connected to the two adjacent first cathode voltage lines. The cathode voltage line is connected to the power supply electrode through the second conductive post, and the orthographic projection of the cathode voltage line on the substrate covers the orthographic projection of the second conductive post on the substrate. The distribution density of the cathode voltage lines in the cathode ring region is the same as or approximately the same as the distribution density of the display anode in the display region.

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