Memory exception detection system, motherboard, electronic device and exception detection method

Abstract

The application provides a memory abnormality detection system, a mainboard, an electronic device and an abnormality detection method. The memory abnormality detection system comprises a processor, a control module, a memory and a monitoring module. The memory comprises a plurality of storage units. The processor is electrically connected to each storage unit through the control module. The monitoring module is electrically connected to the processor, the control module and the storage units. The monitoring module is used for monitoring the level of signals generated between each storage unit and the control module and between the control module and the processor, and confirming whether an abnormality occurs according to the level of the signals. The memory abnormality detection system provided by the application can quickly confirm the storage unit where the abnormality occurs, and effectively reduces the maintenance cost.

Description

Technical Field

[0001] This invention relates to the field of testing, and more particularly to a memory anomaly detection system, motherboard, electronic device, and anomaly detection method. Background Technology

[0002] With the development of big data and cloud computing, enterprises, research institutions, and other organizations have increasingly greater demands for storage capacity. Consequently, the number of storage devices in servers is also increasing. However, because each storage device is connected to the computer motherboard, it is difficult to quickly pinpoint the specific storage device that malfunctions when a storage device fails. Summary of the Invention

[0003] In view of the above, the present invention provides a memory anomaly detection system, motherboard, electronic device, and anomaly detection method for rapidly identifying anomalies.

[0004] This application provides a memory anomaly detection system, including a processor, a control module, a memory, and a monitoring module. The memory includes a plurality of storage cells. The processor is electrically connected to each storage cell via the control module. The monitoring module is electrically connected to the processor, the control module, and the storage cells. The monitoring module monitors the signal levels generated between each storage cell and the control module, and between the control module and the processor, and determines whether an anomaly has occurred based on the signal level status.

[0005] A second aspect of this application provides a motherboard including a memory anomaly detection system as described in any of the preceding claims.

[0006] A third aspect of this application provides an electronic device including a memory anomaly detection system as described in any of the preceding claims.

[0007] This application provides a fourth aspect of an anomaly detection method applied to a memory anomaly detection system, the memory anomaly detection system including a processor, a monitoring module, and several memory units. The anomaly detection method includes the following steps:

[0008] Acquire the first, second, third, and fourth signals generated between each storage unit and the monitoring module, and between the monitoring module and the processor;

[0009] Detect the level status of the first, second, third, and fourth signals;

[0010] Confirm whether the processor or storage unit is malfunctioning based on the test results.

[0011] Compared with existing technologies, the above-mentioned memory anomaly detection system is more efficient in quickly identifying memory anomalies, has lower costs, and is easier to operate. Attached Figure Description

[0012] Figure 1 This is a structural block diagram of a memory anomaly detection system provided in an embodiment of this application.

[0013] Figure 2 yes Figure 1 The signal flow diagram of the memory anomaly detection system is shown.

[0014] Figure 3 This is a flowchart illustrating an anomaly detection method provided in an embodiment of this application.

[0015] Explanation of main component symbols

[0016] Memory anomaly detection system 100

[0017] Processor 10

[0018] Control Module 20

[0019] Memory 30

[0020] Storage unit 31

[0021] Monitoring Module 40

[0022] BMC 50

[0023] User terminal 200

[0024] Electronic Devices 300

[0025] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that when one component is referred to as "electrically connected" to another component, it can be directly on the other component or there can be an intervening component. When one component is considered to be "electrically connected" to another component, it can be a contact connection, such as a wire connection, or a non-contact connection, such as a non-contact coupling.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0029] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0030] With the development of big data and cloud computing, enterprises, research institutions, and other organizations have increasingly higher demands for storage capacity. Consequently, the number of storage devices in servers is also increasing. For example, with advancements in storage technology, existing servers can accommodate up to 64 Dual-Inline-Memory Modules (DIMMs), and these DIMMs can be memory devices compliant with the DDR5 computer memory specification. However, since each memory device needs to be connected to the server's processor, it is difficult to quickly locate the faulty memory device when it malfunctions, requiring significant manpower and resources for testing.

[0031] To resolve at least one of the above issues, please refer to Figure 1 This application provides a memory anomaly detection system 100, which operates in an electronic device 300. The electronic device 300 may include, but is not limited to, desktop computers, laptop computers, tablet computers, personal digital assistants (PDAs), smartphones, gaming devices, server computers, etc.

[0032] In this embodiment, the memory anomaly detection system 100 includes a processor 10, a control module 20, a memory 30, and a monitoring module 40. The processor 10 is electrically connected to the memory 30 via the control module 20. The control module 20 enters a corresponding state after power-on to coordinate with the working state of the processor 10. The processor 10 confirms its working state with the memory 30 through the control module 20, and then retrieves data stored in the memory 30 or controls the memory 30 to perform corresponding operations. The memory 30 includes several storage units 31. Each storage unit 31 is electrically connected to the control module 20. That is, in this embodiment, several storage units 31 in the memory 30 are connected in parallel to the control module 20. The processor 10 is electrically connected to each storage unit 31 through the control module 20. Thus, the processor 10 can confirm its working state with any storage unit 31 through the control module 20. The monitoring module 40 is electrically connected to each storage unit 31 in the processor 10, the control module 20, and the memory 30. It is used to monitor the level of the signals generated between each storage unit 31 and the control module 20, and between the control module 20 and the processor 10. The monitoring module 40 confirms whether an abnormality has occurred based on the level of the signals and generates a corresponding monitoring log.

[0033] The memory anomaly detection system 100 provided in this application can be integrated onto the same motherboard (MB). When the motherboard equipped with the memory anomaly detection system 100 is installed on a corresponding computer, the memory 30 can be monitored in real time while controlling the corresponding computer to perform the corresponding functions.

[0034] It is understood that the processor 10 is the computing and control core of the electronic device 300, used to interpret computer instructions and process data in computer software. In this embodiment, the processor 10 may be a central processing unit (CPU).

[0035] In this embodiment, the control module 20 and the monitoring module 40 can be integrated on a complex programmable logic device (CPLD).

[0036] It is understood that memory 30 is used to store data and programs. In this embodiment, memory 30 may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR). For example, memory 30 may be fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory DDR5.

[0037] In this embodiment, each storage unit 31 is a dual-inline-memory module (DIMM). After the electronic device 300 is powered on, the control module 20 sequentially goes through a first state (e.g., ST_IDLE state), a second state (e.g., ST_DDRIO state), a third state (e.g., ST_LINK state), and a fourth state (e.g., ST_FAULT state). In this embodiment, the first state is the initial state, the second state is the pending activation state, the third state is the connected state, and the fourth state is the fault state.

[0038] Please refer to the following: Figure 2 After the electronic device 300 is powered on and the control module 20 enters the third state, the storage unit 31 outputs a first signal to the control module 20. Upon receiving the first signal, the control module 20 outputs a second signal to the processor 10. Thus, when the processor 10 receives the second signal, it can confirm that the storage unit 31 has been powered on normally and can begin operation.

[0039] After receiving the second signal, the processor 10 outputs a third signal to the control module 20. Upon receiving the third signal, the control module 20 outputs a fourth signal to the storage unit 31. Thus, when the storage unit 31 receives the fourth signal, it confirms that the processor 10 is operating normally. In this way, the processor 10 can perform data retrieval or writing operations on the memory 30.

[0040] In this embodiment, when the electronic device 300 is in operation, i.e., after the control module 20 of the electronic device 300 enters the third state, and the monitoring module 40 detects that the level of any one of the first signal, second signal, third signal, and fourth signal is at the first level (e.g., low level), it indicates that an abnormality has occurred. It can be understood that when the control module 20 enters the fourth state, it indicates that the memory 30 has malfunctioned. However, when the control module 20 enters a state other than the fourth state, the cause of the abnormality needs to be determined by combining the level states of the first, second, third, and fourth signals with the current state of the control module 20.

[0041] For example, embodiments of this application illustrate methods for determining faults under different states through the following scenarios.

[0042] The first scenario: During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal is at the first level and the control module 20 is in the fourth state, it is determined that the storage unit 31 has malfunctioned.

[0043] The second scenario: During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal is at the first level and the control module 20 is in the first state or the second state, it is determined that the control module 20 has malfunctioned.

[0044] The third scenario: During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal is at the second level (e.g., high level) and the second signal is at the first level, and the control module 20 is in the third state, it is determined that the control module 20 has malfunctioned.

[0045] The fourth scenario: During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal and the second signal are both at the second level and the third signal is at the first level, and the control module 20 is in the third state, it is determined that the processor 10 is abnormal; when the control module 20 is in the third state and the monitoring module 40 detects that the first signal, the second signal and the third signal are all at the second level and the fourth signal is at the first level, it is determined that the control module 20 is abnormal.

[0046] It is understood that in this embodiment of the application, the monitoring module 40 can monitor whether the corresponding signal (e.g., the first signal, the second signal, the third signal and the fourth signal) is at the first level, that is, to confirm whether the corresponding signal has generated a falling edge, and the state of the control module 20, thereby confirming whether the corresponding electronic component (e.g., the processor 10, the storage unit 31) or related circuit has malfunctioned.

[0047] Please refer to it again. Figure 1 In some embodiments, the memory anomaly detection system 100 further includes a Baseboard Management Controller (BMC) 50. The monitoring module 40 is also equipped with several registers (not shown) to record the level states of a first, second, third, and fourth signal of the corresponding memory cell 31. In this embodiment, when the monitoring module 40 detects that any one of the first, second, third, or fourth signals is at the first level, the monitoring module 40 assigns a value to the corresponding register. The several registers on the monitoring module 40 are electrically connected to the BMC 50 via a bidirectional two-wire synchronous serial bus (Inter-Integrated Circuit, I2C) to output the values ​​on the registers to the BMC 50 to record the level states of the first, second, third, and fourth signals. Thus, the BMC 50 can generate a corresponding detection log.

[0048] In this embodiment, the BMC50 is also electrically connected to the user terminal 200, such as another computer, via a USB interface. This allows technicians to view relevant logs on the user terminal 200 to identify components malfunctioning during the operation of the electronic device 300. Furthermore, if a memory malfunction is confirmed during the operation of the electronic device 300, technicians can view the logs on the user terminal 200 to identify the corresponding malfunctioning memory unit 31, effectively reducing labor and time costs for repairs.

[0049] In this embodiment, each storage unit 31 is also assigned a corresponding number. The data output by the register corresponding to each storage unit 31 includes the number. Thus, the monitoring module 40 can output data including the number of the corresponding storage unit 31 and the level state of the corresponding signal through the register to help identify the storage unit 31 in the electronic device 300 that has malfunctioned, thereby effectively reducing the time and labor costs during inspection and repair.

[0050] It is understood that this application does not limit the specific type of monitoring module 40. For example, in other embodiments, monitoring module 40 may also be a field-programmable gate array (FPGA), a microcontroller or other programmable controller.

[0051] It is understood that the memory anomaly detection system 100 provided in this application, by setting up a monitoring module 40 to record the level states of the first, second, third, and fourth signals generated during the operation of the electronic device 300, can identify the components that malfunction during the operation of the electronic device 300 by analyzing the level states. The memory anomaly detection system 100 provided in this application is easy to operate and can effectively reduce maintenance costs.

[0052] Please continue reading. Figure 3 An embodiment of this application also provides an anomaly detection method, applied to... Figure 1 The memory anomaly detection system 100 shown is used to detect whether an abnormal condition has occurred in the memory of the electronic device 300. The memory anomaly detection system includes a processor 10, a monitoring module 40, and several memory units 31 connected in sequence. The anomaly detection method includes the following steps:

[0053] Step S1: Acquire the first signal, second signal, third signal and fourth signal generated between each storage unit 31 and the control module 20, and between the control module 20 and the processor 10 during the operation of the electronic device 300.

[0054] It is understood that the specific flow of the first, second, third, and fourth signals can be found in the above-mentioned content, and will not be repeated here.

[0055] Step S2: Detect the level status of the first signal, the second signal, the third signal and the fourth signal.

[0056] Step S3: Confirm whether any abnormality has occurred based on the level status of the above signals.

[0057] It is understood that in step S3, the level state includes a first level and a second level. In the embodiments of this application, the first level refers to a low level, and the second level refers to a high level.

[0058] During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal is at the first level and the control module 20 is in the fourth state, it can be determined that the storage unit 31 has malfunctioned.

[0059] During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal is at the first level and the control module 20 is in the first state or the second state, it can be determined that the control module 20 has malfunctioned.

[0060] During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal is at the second level and the second signal is at the first level, and the control module 20 is in the third state, it can be determined that the control module 20 is malfunctioning.

[0061] During the operation of the electronic device 300, when the monitoring module 40 detects that the first signal and the second signal are both at the second level and the third signal is at the first level, and the control module 20 is in the third state, it can be determined that the processor 10 is malfunctioning; when the control module 20 is in the third state and the monitoring module 40 detects that the first signal, the second signal and the third signal are all at the second level and the fourth signal is at the first level, it can be determined that the control module 20 is malfunctioning.

[0062] It is understood that the modules included in the above embodiments can be integrated into a calculator device or tool, or they can be set as separate functional entities and connected to the calculator device or tool to provide the functions of each module to the calculator device or tool.

[0063] It is worth noting that the modules included in the above-described device embodiments are divided according to functional logic only, and are not limited to the above division, as long as they can achieve the corresponding functions. Furthermore, the specific names of each functional module are only for easy differentiation and are not intended to limit the scope of protection of this invention.

[0064] The above embodiments are merely illustrative of the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the preferred embodiments above, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention should not depart from the spirit and scope of the present invention. Those skilled in the art can also make other changes within the spirit of the present invention and use them in the design of the present invention, as long as they do not deviate from the technical effects of the present invention. These changes made according to the spirit of the present invention should all be included within the scope of protection claimed by the present invention.

Claims

1. A memory anomaly detection system, characterized in that, The memory anomaly detection system includes a processor, a control module, a memory, and a monitoring module. The memory includes several storage units. The processor is electrically connected to each storage unit through the control module. The monitoring module is electrically connected to the processor, the control module, and the storage units. The monitoring module is used to monitor the signal levels between each storage unit and the control module, and between the control module and the processor. The monitoring module determines whether an anomaly has occurred based on the signal level and the state of the control module. The control module is in a state including a first state, a second state, a third state, and a fourth state. The first state is an initial state, the second state is a pending activation state, the third state is a connection state, and the fourth state is a fault state. The signals generated between each storage unit and the control module, and between the control module and the processor, include a first signal, a second signal, a third signal, and a fourth signal. After the memory anomaly detection system is powered on, each memory cell outputs the first signal to the control module. After receiving the first signal, the control module outputs the second signal to the processor. After receiving the second signal, the processor then outputs the third signal to the control module. After receiving the third signal, the control module then outputs the fourth signal to the storage unit.

2. The memory anomaly detection system according to claim 1, characterized in that, When the control module enters the third state, and the monitoring module detects that the level of any one of the first signal, the second signal, the third signal, and the fourth signal is at the first level, the monitoring module determines that an abnormality has occurred.

3. The memory anomaly detection system according to claim 2, characterized in that, When the monitoring module detects that the first signal is at the first level and the control module is in the fourth state, the monitoring module determines that the memory has malfunctioned. or When the monitoring module detects that the first signal is at the first level, and the control module is in the first state or the second state, the monitoring module determines that the control module has malfunctioned. or When the monitoring module detects that the first signal is at the second level and the second signal is at the first level, and the control module is in the third state, the monitoring module determines that the control module has malfunctioned. or When the monitoring module detects that the first signal and the second signal are both at the second level, and the third signal is at the first level, and the control module is in the third state, the monitoring module determines that the control module is malfunctioning. or When the monitoring module detects that the first signal, the second signal, and the third signal are all at the second level, and the fourth signal is at the first level, and the control module is in the third state, the monitoring module determines that the control module has malfunctioned.

4. The memory anomaly detection system according to claim 2, characterized in that, The memory anomaly detection system further includes a baseboard management controller, and the monitoring module further includes several registers. The several registers are used to record the level states of the first signal, the second signal, the third signal, and the fourth signal of the corresponding memory cell. The baseboard management controller is electrically connected to the several registers and is used to receive the data output by the several registers to generate corresponding detection logs.

5. The memory anomaly detection system according to claim 4, characterized in that, The storage unit is assigned a corresponding number, and the data output by the register includes the corresponding storage unit number and the level states of the corresponding first signal, second signal, third signal, and fourth signal.

6. A motherboard, characterized in that, The motherboard includes a memory anomaly detection system as described in any one of claims 1-5.

7. An electronic device, characterized in that, The electronic device includes a memory anomaly detection system as described in any one of claims 1-5.

8. An anomaly detection method, characterized in that, The memory anomaly detection system applied to any one of claims 1-5, the anomaly detection method comprising the following steps: Acquire the first signal, second signal, third signal, and fourth signal generated between each of the storage units and the control module, and between the control module and the processor; Detect the level states of the first signal, the second signal, the third signal, and the fourth signal; The system determines whether an anomaly has occurred based on the level states of the first, second, third, and fourth signals, as well as the state of the control module.

9. The anomaly detection method according to claim 8, characterized in that: When the first signal is detected to be at the first level and the control module is in the fourth state, it is determined that the memory has malfunctioned. or When the first signal is detected to be at the first level, and the control module is in the first state or the second state, it is determined that the control module has malfunctioned. or When the first signal is detected to be at the second level and the second signal is at the first level, and the control module is in the third state, it is determined that the control module has malfunctioned. or When the first signal and the second signal are both at the second level, the third signal is at the first level, and the control module is in the third state, it is determined that the control module has malfunctioned. or When the first signal, the second signal, and the third signal are all at the second level, and the fourth signal is at the first level, and the control module is in the third state, it is determined that the control module has malfunctioned.

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