Wireless clock synchronization method and system based on chirp spread spectrum

Abstract

A chirped spread spectrum-based wireless clock synchronization method and system overcomes the limitation of signal sampling rate on wireless clock synchronization accuracy through chirped spread spectrum modulation and demodulation, achieving arrival time estimation with oversampling period resolution. The clock difference between the client and server is measured using round-trip time delay measurement. A Kalman filter is used to optimally estimate the clock difference and clock speed. The FPGA's MMCM dynamically adjusts the clock phase, achieving higher resolution clock adjustment step sizes at lower clock frequencies, thus overcoming the limitation of system clock frequency on synchronization accuracy. This invention combines a high-precision arrival time estimation method and a high-precision clock adjustment method, and can be used for high-precision wireless clock synchronization in communication systems, radar systems, data acquisition systems, astronomical observation systems, and other systems, meeting the synchronization requirements of multiple distributed devices.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and more specifically relates to a chirped spread spectrum-based wireless clock synchronization method and system within the field of wireless communication technology. This invention can be used for high-precision wireless clock synchronization in systems such as communication systems, radar systems, data acquisition systems, and astronomical observation systems, meeting the synchronization requirements of multiple distributed devices. Background Technology

[0002] Currently, with the rapid development of science and technology, modern industry has increasingly higher requirements for clock synchronization accuracy, and many fields have higher requirements for the real-time performance and determinism of networks. Therefore, achieving high-precision and high-reliability time synchronization methods has received widespread attention. Clock synchronization can be classified into wireless and wired according to the transmission medium. Wireless clock synchronization has advantages over wired clock synchronization in terms of high flexibility, portability, mobility, and fault tolerance. IEEE has specified several standards related to wireless clock synchronization. Among them, the widely used ones are: IEEE 1588: also known as Precision Time Protocol (PTP). This standard was not specifically designed for wireless, but it provides a mechanism for achieving sub-microsecond time synchronization in local area networks (whether wired or wireless). Some wireless technologies have begun to adopt or are considering adopting PTP for time synchronization. IEEE 802.11: a standard widely used in Wi-Fi networks. Although this standard mainly focuses on the design of wireless local area networks, it also includes a time synchronization mechanism. IEEE 802.15.4: a standard for low-speed wireless personal area networks, especially for wireless sensor networks. The Time Synchronized Channel Hopping (TSCH) mode pays special attention to time synchronization.

[0003] Chengdu Aircraft Industry (Group) Co., Ltd. disclosed a method for synchronization and data transmission in a wireless network acquisition system in its patent application "A Synchronization Time Synchronization and Data Transmission Method for a Wireless Network Acquisition System" (Application No.: 202211144952.1, Publication No.: CN 115884352A). The method's implementation steps include: First, the ADAS control master system sends a timestamp to the Ethernet port of the ADAS interface control device via a message sending interface. Second, the ADAS interface control device parses the timestamp received from the master message sending interface at the physical layer of the Ethernet port. Third, the ADAS control interface device sends a synchronization message to the wireless network acquisition system via the wireless network; the wireless network acquisition node receives the message and records the timestamp. The node immediately returns an acknowledgment frame and records the timestamp; the ADAS interface control device receives the acknowledgment frame and records the timestamp. Fourth, by repeating this process, the wireless network acquisition node calculates the time error and network latency. Fifth, the ADAS interface control device processes and packages the sensor data received from the wireless network acquisition system and uploads the data to the ADAS control master system or host computer via a wireless communication protocol. The shortcomings of this method are as follows: First, the wireless synchronization system lacks clock offset correction for different device nodes, and the cumulative clock offset will lead to a decrease in synchronization stability; Second, the wireless synchronization system requires three communication processes: synchronization message, acknowledgment frame, and follow message. The follow message communication process is redundant, reducing the utilization rate of communication resources; Third, its clock synchronization accuracy depends on the system master frequency recorded by the timestamp, and can only reach the nanosecond level at most, but cannot reach the sub-nanosecond level.

[0004] Xi'an Yuanfang Aviation Technology Development Co., Ltd. disclosed an airborne wireless clock synchronization method, system, aircraft, and storage medium in its patent application "An Airborne Wireless Clock Synchronization Method, System, Aircraft, and Storage Medium" (Application No.: 202310465042.1, Publication No.: CN 116723564A). The device includes a first synchronization device and at least one second synchronization device. The clock of the first synchronization device is synchronized with a GPS clock and includes a first communication chip. The second synchronization device also includes a second communication chip. The shortcomings of this device are that the clock correction device uses a crystal oscillator control unit and a voltage-controlled crystal oscillator for clock correction, which has a limited adjustment range. Long-term drift of the crystal oscillator can lead to inaccuracies exceeding the voltage-controlled adjustment range. With increasing service life, it may become unable to achieve synchronization. Furthermore, it requires a GPS module and cannot be used in situations where the GNSS system denies functionality. The implementation steps of the patented method include: first, the first synchronization device sends a message to the second synchronization device using the first communication chip, and the second synchronization device receives the message using the second communication chip. Second, the second synchronization device corrects its own clock based on the message's transmission and reception times to achieve clock synchronization with the first synchronization device. Third, to achieve clock synchronization, the second synchronization device can use a crystal oscillator control unit and a voltage-controlled crystal oscillator for clock correction. Fourth, during communication, the first and second communication chips communicate using short energy pulse sequences, expanding the pulses to a frequency range through orthogonal frequency division modulation or direct sequencing. Fifth, by changing the amplitude, time, and phase of the pulses, the information to be transmitted is loaded, thereby achieving information transmission and providing a precise hardware timestamp. Another drawback of this method is that the communication waveform for wireless synchronization uses pulse signals, which are susceptible to interference during transmission, affecting synchronization accuracy. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the existing technologies mentioned above by providing a chirped spread spectrum-based wireless clock synchronization method and system. This method solves the problems of low synchronization accuracy, synchronization accuracy limited by the system's main frequency, redundancy in the communication process, poor stability caused by accumulated clock offset, narrow adjustment range of voltage-controlled crystal oscillators, susceptibility of wireless communication waveforms to interference, and complex circuit implementation in wireless clock synchronization methods and devices.

[0006] To achieve the above objectives, the present invention is based on the following approach: By using chirped spread spectrum modulation and demodulation, the present invention overcomes the limitation of signal sampling rate on the accuracy of wireless clock synchronization, achieving arrival time estimation with oversampling period resolution. Furthermore, the clock difference between the client and server is measured using round-trip delay measurement. Then, a Kalman filter is used to optimally estimate the clock difference and clock speed. Finally, the MMCM within the FPGA is used to dynamically adjust the clock phase, achieving a higher resolution clock adjustment step size at a lower clock frequency, thus overcoming the limitation of system clock frequency on synchronization accuracy.

[0007] To achieve the above objectives, the wireless clock synchronization device of the present invention includes a server and at least one client, wherein the modules in both the server and the client are built on an FPGA. The server includes a synchronization protocol control module, a chirped spread spectrum transmission module, a chirped spread spectrum reception module, a delay module, and a counter module. The client includes a synchronization protocol control module, a chirped spread spectrum transmission module, a chirped spread spectrum reception module, a counter module, an MMCM dynamic phase shifting module, and a Kalman filter module; wherein:

[0008] The synchronization protocol control module in the server is used to read the local clock; the chirped spread spectrum transmission module is used to encode the channel, perform chirped spread spectrum waveform modulation on the encoded modulation symbols, generate and send reply frames; the chirped spread spectrum reception module is used to capture the synchronization request sent by the client, receive the complete preamble through symbol synchronization and frequency synchronization, and output the preamble arrival flag at the same time; the delay module is used to perform delay operations; and the counter module is used to count the local clock.

[0009] The client-side synchronization protocol control module reads the local clock, calculates the clock deviation between the client and server using the time deviation formula, and corrects the counter module's count value and the MMCM dynamic phase shift module's clock phase. The chirped spread spectrum transmission module encodes the channel, modulates the encoded modulation symbols using chirped spread spectrum waveforms, generates and sends synchronization requests. The chirped spread spectrum reception module captures the server's reply message, and through symbol synchronization and frequency synchronization, receives the complete preamble while outputting a preamble arrival flag. The counter module counts the local clock. The MMCM dynamic phase shift module adjusts the local clock phase. The Kalman filter module filters the clock deviation to obtain the clock difference and clock speed.

[0010] The steps of the wireless clock synchronization method of the present invention include the following:

[0011] Step 1: While the client's synchronization protocol control module reads the local clock, the chirped spread spectrum transmission module encodes the channel, modulates the encoded modulation symbols into a chirped spread spectrum waveform, generates and sends a synchronization request.

[0012] Step 2: The server receives synchronization requests using linear chirped spread spectrum communication.

[0013] After the server's chirped spread spectrum receiver module captures the synchronization request sent by the client, it receives the complete preamble and outputs the preamble arrival flag while controlling the synchronization protocol module to read the local clock through symbol synchronization and frequency synchronization.

[0014] Step 3, the server sends a reply message:

[0015] After the server's delay module performs the delay operation, the synchronization protocol control module reads the local clock information, and the chirped spread spectrum transmission module modulates the encoded modulation symbols into a chirped spread spectrum waveform to generate and send a reply frame.

[0016] Step 4: The client receives the reply message in the same way as in Step 2.

[0017] After the client's chirped spread spectrum receiver module captures the reply message sent by the server, it receives the complete preamble while outputting the preamble arrival flag and using the synchronization protocol control module to read the local clock through symbol synchronization and frequency synchronization.

[0018] Step 5: The client's synchronization protocol control module uses the time deviation formula to calculate the clock deviation between the client and the server, and uses the Kalman filter of the Kalman filter module to filter the clock deviation to obtain the clock difference and clock speed.

[0019] Step 6: The client uses clock difference and clock speed to synchronize the protocol control module to correct the count value of the counter module and the clock phase of the MMCM dynamic phase shift module.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] First, the method of the present invention adopts linear chirped spread spectrum communication. The receiving end completes the arrival time estimation based on the signal preamble, without the need for tracking operation, and quickly completes the calculation of the signal arrival time. This overcomes the defect of the existing wireless clock synchronization communication waveform being susceptible to interference, enabling the present invention to obtain better resistance to noise interference and multipath effects.

[0022] Secondly, the method of this invention estimates the fractional part of the symbol offset of the communication waveform, achieving arrival time estimation with oversampling time resolution, which greatly improves the accuracy of arrival time estimation. This overcomes the limitation of existing technologies where arrival time estimation is restricted by the sampling frequency, enabling this invention to improve the accuracy of wireless clock synchronization.

[0023] Third, the method of the present invention addresses the situation where there is a difference in clock frequency between the local clocks of the client and the server. It uses a Kalman filter to optimally filter the clock deviation, calculates the clock difference and clock speed between the client and the server, and then corrects it. This overcomes the defect of existing technology where the cumulative clock offset leads to a decrease in the stability of clock synchronization, thus enabling the present invention to improve the stability of clock synchronization.

[0024] Fourth, the device of this invention enables the counter and MMCM dynamic phase shifting modules to adjust the counting period and clock phase, effectively improving clock adjustment accuracy and overcoming the limitation of system main frequency on clock adjustment accuracy. It overcomes the shortcomings of existing voltage-controlled crystal oscillator solutions, such as narrow error adjustment range and inability to achieve synchronous adjustment with increasing service life, thus avoiding the need for a voltage-controlled adjustment circuit and enhancing the stability of the wireless clock synchronization system. Attached Figure Description

[0025] Figure 1 This is a block diagram of the device of the present invention;

[0026] Figure 2 This is a flowchart of the method of the present invention.

[0027] Figure 3 This is a schematic diagram of the synchronous waveform output by the oscilloscope of the present invention. Detailed Implementation

[0028] The present invention will now be further described with reference to the accompanying drawings.

[0029] Reference Figure 1 The apparatus of the present invention will be further described below.

[0030] The wireless clock synchronization device comprises a server and at least one client, with modules in both the server and client built on an FPGA. The server includes a synchronization protocol control module, a chirped spread spectrum transmitter module, a chirped spread spectrum receiver module, a delay module, and a counter module. The client includes the same modules: a synchronization protocol control module, a chirped spread spectrum transmitter module, a chirped spread spectrum receiver module, a counter module, an MMCM dynamic phase shifter module, and a Kalman filter module.

[0031] The synchronization protocol control module in the server is used to read the local clock. The chirped spread spectrum transmission module is used to encode the channel, perform chirped spread spectrum modulation on the encoded modulation symbols, generate and send reply frames. The chirped spread spectrum reception module is used to capture synchronization requests sent by the client, receive the complete preamble through symbol synchronization and frequency synchronization, and output a preamble arrival flag. The delay module is used to perform delay operations. The counter module is used for counting the local clock.

[0032] The client-side synchronization protocol control module reads the local clock, calculates the clock deviation between the client and server using the time deviation formula, and corrects the counter module's count value and the clock phase of the MMCM dynamic phase shift module. The chirped spread spectrum transmission module encodes the channel, modulates the encoded modulation symbols using a chirped spread spectrum waveform, generates and sends a synchronization request. The chirped spread spectrum reception module captures the server's reply message, and through symbol and frequency synchronization, receives the complete preamble while outputting a preamble arrival flag. The counter module counts the local clock. The MMCM dynamic phase shift module adjusts the local clock phase. The Kalman filter module filters the clock deviation to obtain the clock difference and clock rate.

[0033] Reference Figure 2 The steps of the synchronization method of the present invention will be further described below.

[0034] Step 1: While the client's synchronization protocol control module reads the local clock, the chirped spread spectrum transmission module encodes the channel, modulates the encoded modulation symbols into a chirped spread spectrum waveform, and generates and sends a synchronization request.

[0035] If the chirped spread spectrum transmitter module is in the ready state, the synchronization protocol control module sends a latch signal to the counter module, reads the counter value and records it as T1, sets the client number in the chirped spread spectrum transmitter module to 0, sends a transmit start signal, and switches to the transmit state. If the chirped spread spectrum transmitter module is in the transmit state, the current transmit request signal is ignored.

[0036] The modulation of the chirped spread spectrum waveform is achieved by the following formula:

[0037]

[0038]

[0039] Where, x up (n; a) represents the amplitude of the nth signal sampling point in the chirped spread spectrum discrete waveform on the ath modulation symbol, x down (n; a) represents the amplitude of the nth signal sampling point in the chirped spread spectrum discrete waveform under the ath modulation symbol, e (·) The symbol represents an exponential operation with base e, j represents the imaginary unit sign, π represents pi, M represents the number of modulation symbols, B represents the bandwidth of the spread spectrum discrete waveform, and f represents the number of modulation symbols. s This indicates the sampling rate of the spread spectrum discrete waveform.

[0040] Step 2: The server uses linear chirped spread spectrum communication to receive synchronization requests.

[0041] After the server's chirped spread spectrum receiver module captures the synchronization request sent by the client, it receives the complete preamble and outputs the preamble arrival flag while controlling the synchronization protocol module to read the local clock through symbol synchronization and frequency synchronization.

[0042] The steps of the symbol synchronization and frequency synchronization method are as follows:

[0043] The first step is to multiply the upper-chirped spread spectrum discrete waveform of each modulation symbol by the lower-chirped spread spectrum discrete waveform of the zero modulation symbol to obtain the upper-chirped de-chewing signal waveform of that modulation symbol. The second step is to multiply the lower-chirped spread spectrum discrete waveform of each modulation symbol by the upper-chirped spread spectrum discrete waveform of the zero modulation symbol to obtain the lower-chirped de-chewing signal waveform of that modulation symbol.

[0044] The second step is to perform a Discrete Fourier Transform on the upper chirped descrambling signal waveform to obtain the upper chirped descrambling signal spectrum, and to perform a Discrete Fourier Transform on the lower chirped descrambling signal waveform to obtain the lower chirped descrambling signal spectrum.

[0045] The third step is to search for the maximum amplitude value in the upper-chirped descrambling signal spectrum of each modulation symbol, and use the coordinates of the position of the maximum amplitude value of this modulation symbol as the value of the upper-chirped demodulated symbol. Similarly, search for the maximum amplitude value in the lower-chirped descrambling signal spectrum of each modulation symbol, and use the coordinates of the position of the maximum amplitude value of this modulation symbol as the value of the lower-chirped demodulated symbol.

[0046] The fourth step is to synchronize the integer and fractional parts of the symbol offset and the frequency offset based on the values ​​of the upper and lower chirped demodulation symbols.

[0047] The preamble includes a capture head composed of a chirped spread spectrum waveform on the zero-modulation symbol, a synchronization head composed of a chirped spread spectrum waveform on the zero-modulation symbol and a chirped spread spectrum waveform on the zero-modulation symbol.

[0048] Due to signal transmission delay and the frequency difference of the RF inverter, the signal received by the spread spectrum receiver module will have symbol offset and frequency offset compared with the signal transmitted by the transmitter, as expressed below:

[0049] STO = L STO +λ STO

[0050] CFO = L CFO +λ CFO

[0051] Where STO represents the sign offset value, L STO The integer part representing the sign offset, λ STO The fractional part representing the sign offset, CFO representing the frequency offset, L CFO The integer part representing the frequency offset, λ CFOThe fractional part λ representing the frequency offset CFO .

[0052] The expression for the decimal part of the sign offset is as follows:

[0053]

[0054] in, Re represents the estimated value of the fractional part of the sign offset, Re[·] represents the floor function, i represents the coordinates of the position of the maximum amplitude of the chirped descrambled signal spectrum, and Y represents the position of the maximum amplitude of the chirped descrambled signal spectrum. i-1 Y represents the amplitude of the (i-1)th discrete frequency in the spectrum of the chirped descrambled signal. i Y represents the amplitude of the i-th discrete frequency in the spectrum of the chirped descrambled signal. i+1 This represents the amplitude of the (i+1)th discrete frequency in the spectrum of the chirped descrambled signal.

[0055] The expression for the fractional part of the frequency offset is as follows:

[0056]

[0057] in, Let f(·) represent the estimated value of the fractional part of the frequency offset, f(·) represent solving the phase angle function, ∑· represent the summation function, i represent the position coordinates of the maximum amplitude of the chirped descrambling signal spectrum, and p represent an integer value in the range of -2 ≤ p ≤ 2. This represents the amplitude of the (i+p)th discrete frequency in the l-th chirped spread spectrum waveform of the preamble. This represents the amplitude of the (i+p)th discrete frequency in the (l-1)th chirped spread spectrum waveform of the leader.

[0058] The expression for the integer part of the symbol offset is as follows:

[0059]

[0060] in, s represents the estimated value of the integer part of the sign offset. up It is the numerical value of the upper chirp demodulation symbol, s down It is the numerical value of the down-chirped demodulation symbol.

[0061] The expression for the integer part of the frequency offset is as follows:

[0062]

[0063] in, s represents the estimated value of the integer part of the sign offset. up It is the numerical value of the upper chirp demodulation symbol, s down It is the numerical value of the down-chirped demodulation symbol.

[0064] The steps of receiving the complete leader header, simultaneously outputting the leader header arrival flag, and using the synchronization protocol control module to read the local clock are as follows:

[0065] Upon receiving the complete preamble, the chirped spread spectrum receiver module outputs a preamble arrival flag. This flag is output after a one-symbol delay, following the receipt of the last sample of the last symbol of the preamble at the module's input. Simultaneously, the spread spectrum receiver module will incorporate the synchronization process estimation... Output. When the synchronization protocol control module receives the leader arrival signal and It will re-latch the count value in the counter module and add that value. T2 is obtained.

[0066] Step 3: The server sends a reply message.

[0067] After the server's delay module performs the delay operation, the synchronization protocol control module reads the local clock information, and the chirped spread spectrum transmission module modulates the encoded modulation symbols into a chirped spread spectrum waveform to generate and send a reply frame.

[0068] The server's delay module extends for a fixed period of time. The synchronization protocol control module reads the local clock information. Then, the chirped spread spectrum transmission module modulates the waveform using the modulation method in step 1 to generate a reply frame containing the client number, an integer value of T2, and a decimal value of T2. The chirped spread spectrum transmission module then switches to the transmitting state and transmits the reply frame.

[0069] Step 4: The client receives the reply message in the same way as in Step 2.

[0070] After the client's chirped spread spectrum receiver module captures the reply message sent by the server, it receives the complete preamble while outputting the preamble arrival flag and using the synchronization protocol control module to read the local clock through symbol synchronization and frequency synchronization.

[0071] The client-side chirped spread spectrum receiver module outputs a preamble arrival signal. This signal is received at the module input after the last sample of the last symbol of the preamble, delayed by one symbol length. Simultaneously, the module outputs the signal estimated during the synchronization process. Output. When the client clock synchronization transceiver interface module receives the preamble arrival signal, it will re-latch the count value in the counter module and increment that value. The obtained value is T4. The clock synchronization transceiver interface module receives the data reception completion signal and reads the client number, the integer value of T2, and the decimal value of T2.

[0072] Step 5: The client's synchronization protocol control module uses the time deviation formula to calculate the clock deviation between the client and the server, and uses the Kalman filter of the Kalman filter module to filter the clock deviation to obtain the clock difference and clock speed.

[0073] The time deviation formula is as follows:

[0074]

[0075] Among them, T offset This represents the clock deviation between the client and the server. T1 represents the clock value when the client first obtains the local clock value, T2 represents the clock value when the server first obtains the local clock value, T3 represents T2 plus the delay value of the server's delay operation, and T4 represents the clock value when the client obtains the local clock value for the second time.

[0076] The filtering steps of the Kalman filter include:

[0077] The first step is to initialize the system state estimates and the covariance matrix of the estimation error. This includes the initial estimates of the system state and the covariance matrix of the initial estimation error.

[0078] The second step is to use the state estimate and control input from the previous time step to predict the current state and its covariance matrix.

[0079] The third step is to obtain the actual observations and then compare them with the predicted state to calculate the Kalman gain. The Kalman gain determines the trade-off between the predicted state and the observations, and is used to update the state estimate and the state's covariance matrix.

[0080] Fourth, repeat steps two and three to predict and update the state based on the new observations and control inputs, recursively estimating the system state.

[0081] Step 6: The client uses clock difference and clock speed to synchronize the protocol control module to correct the count value of the counter module and the clock phase of the MMCM dynamic phase shift module.

[0082] The count value of the correction counter module and the clock phase of the MMCM dynamic phase shift module refer to the single correction of the count value in the counter module and the clock phase of the MMCM dynamic phase shift module using the clock difference value. The clock speed is used to continuously correct the count value of the counter module and the clock phase of the MMCM dynamic phase shift module.

[0083] The steps for correcting the clock phase of the MMCM dynamic phase shift module include:

[0084] The first step is to initialize the clock by configuring its frequency, phase parameters, and phase adjustment step size.

[0085] The second step is to use the clock difference and clock speed to obtain the phase shift value per second, and then divide this phase value by the clock cycle to obtain the phase shift value for each clock cycle.

[0086] The third step is to accumulate the phase offset value for each clock cycle to obtain the phase accumulation value. When the phase accumulation value is greater than the phase modulation step size, a phase adjustment operation is performed.

[0087] Fourth, repeat steps two and three to correct the clock phase of the MMCM dynamic phase shift module according to the new clock difference and clock speed.

[0088] Observe the local clock waveforms output by the client and server respectively using an oscilloscope, as follows: Figure 3 As shown. Figure 3 The horizontal axis represents time, and the vertical axis represents the amplitude of the output waveform. Figure 3 The yellow waveform represents the client clock, and the blue waveform represents the server clock. It can be seen that the difference between the rising edges of the two is less than one nanosecond, indicating that the synchronization accuracy of the present invention is in the sub-nanosecond range, and the clock synchronization function is normal.

Claims

1. A wireless clock synchronization system based on chirped spread spectrum, comprising a server and at least one client, wherein modules in both the server and client are built on an FPGA, characterized in that: The server includes a synchronization protocol control module, a chirped spread spectrum transmission module, a chirped spread spectrum reception module, a delay module, and a counter module. The client includes a synchronization protocol control module, a chirped spread spectrum transmission module, a chirped spread spectrum reception module, a counter module, an MMCM dynamic phase shifting module, and a Kalman filter module; wherein: The synchronization protocol control module in the server is used to read the local clock; the chirped spread spectrum transmission module is used to encode the channel, perform chirped spread spectrum waveform modulation on the encoded modulation symbols, generate and send reply frames; the chirped spread spectrum reception module is used to capture the synchronization request sent by the client, receive the complete preamble through symbol synchronization and frequency synchronization, and output the preamble arrival flag; the delay module is used to perform delay operations; and the counter module is used to count the local clock. The client-side synchronization protocol control module reads the local clock, calculates the clock deviation between the client and server using the time deviation formula, and corrects the counter module's count value and the MMCM dynamic phase shift module's clock phase. The chirped spread spectrum transmission module encodes the channel, modulates the encoded modulation symbols with a chirped spread spectrum waveform, generates and sends a synchronization request. The chirped spread spectrum reception module captures the server's reply message, and through symbol synchronization and frequency synchronization, receives the complete preamble while outputting a preamble arrival flag. The counter module counts the local clock. The MMCM dynamic phase shift module adjusts the local clock phase. The Kalman filter module filters the clock deviation to obtain the clock difference and clock rate.

2. A wireless clock synchronization method based on chirped spread spectrum for the synchronization system according to claim 1, characterized in that, A linear chirped spread spectrum communication method is adopted to estimate the fractional part of the communication waveform symbol offset, and a Kalman filter is used to optimally filter the clock deviation. The steps of this synchronization method are as follows: Step 1: While the client's synchronization protocol control module reads the local clock, the chirped spread spectrum transmission module encodes the channel, modulates the encoded modulation symbols into a chirped spread spectrum waveform, generates and sends a synchronization request. Step 2: The server receives synchronization requests using linear chirped spread spectrum communication. After the server's chirped spread spectrum receiver module captures the synchronization request sent by the client, it receives the complete preamble and outputs the preamble arrival flag while controlling the synchronization protocol module to read the local clock through symbol synchronization and frequency synchronization. Step 3, the server sends a reply message: After the server's delay module performs the delay operation, the synchronization protocol control module reads the local clock information, and the chirped spread spectrum transmission module modulates the encoded modulation symbols into a chirped spread spectrum waveform to generate and send a reply frame. Step 4: The client receives the reply message in the same way as in Step 2. After the client's chirped spread spectrum receiver module captures the reply message sent by the server, it receives the complete preamble while outputting the preamble arrival flag and using the synchronization protocol control module to read the local clock through symbol synchronization and frequency synchronization. Step 5: The client's synchronization protocol control module uses the time deviation formula to calculate the clock deviation between the client and the server, and uses the Kalman filter of the Kalman filter module to filter the clock deviation to obtain the clock difference and clock speed. Step 6: The client uses clock difference and clock speed to synchronize the protocol control module to correct the count value of the counter module and the clock phase of the MMCM dynamic phase shift module.

3. The wireless clock synchronization method based on chirped spread spectrum according to claim 2, characterized in that, The modulation of the chirped spread spectrum waveform described in steps 1 and 3 is achieved by the following formula: ； ； in, Indicates the first In the chirped spread spectrum discrete waveform of the modulation symbol, the first... The amplitude of each signal sampling point Indicates the first In the chirped spread spectrum discrete waveform under the modulation symbol, the first... The amplitude of each signal sampling point, e (.) Represented by natural constant Index-based operations. The symbol representing the imaginary unit. Represents pi (π). Indicates the number of modulation symbols. This represents the bandwidth of the spread spectrum discrete waveform. This indicates the sampling rate of the spread spectrum discrete waveform.

4. The wireless clock synchronization method based on chirped spread spectrum according to claim 3, characterized in that, The steps of the symbol synchronization and frequency synchronization method described in step 2 are as follows: The first step is to multiply the upper-chirped spread spectrum discrete waveform of each modulation symbol by the lower-chirped spread spectrum discrete waveform of the zero modulation symbol to obtain the upper-chirped de-skewing signal waveform of that modulation symbol. Multiply the discrete waveform of the lower chirped spread spectrum of each modulation symbol by the discrete waveform of the upper chirped spread spectrum of the zero modulation symbol to obtain the lower chirped descrambling signal waveform of that modulation symbol. The second step is to perform a Discrete Fourier Transform on the upper chirped descrambling signal waveform to obtain the upper chirped descrambling signal spectrum, and to perform a Discrete Fourier Transform on the lower chirped descrambling signal waveform to obtain the lower chirped descrambling signal spectrum. The third step is to search for the maximum amplitude in the spectrum of the upper chirped descrambling signal for each modulation symbol, and use the position coordinates of the maximum amplitude of the modulation symbol as the value of the upper chirped demodulation symbol; and to search for the maximum amplitude in the spectrum of the lower chirped descrambling signal for each modulation symbol, and use the position coordinates of the maximum amplitude of the modulation symbol as the value of the lower chirped demodulation symbol. The fourth step is to synchronize the integer and fractional parts of the symbol offset and the frequency offset based on the values ​​of the upper and lower chirped demodulation symbols.

5. The wireless clock synchronization method based on chirped spread spectrum according to claim 3, characterized in that, The preamble mentioned in steps 2 and 4 includes a capture head composed of a chirped spread spectrum waveform on the zero-modulation symbol, a synchronization head composed of a chirped spread spectrum waveform on the zero-modulation symbol and a chirped spread spectrum waveform on the lower part of the zero-modulation symbol.

6. The wireless clock synchronization method based on chirped spread spectrum according to claim 2, characterized in that, The time deviation formula mentioned in step 5 is as follows: ； in, This indicates the clock offset between the client and the server. This indicates that the client is obtaining the local clock value for the first time. This indicates the first time the server retrieves the local clock value. express Adding the latency value of server-side delayed operations, This indicates that the client is obtaining the local clock value for the second time.

7. The wireless clock synchronization method based on chirped spread spectrum according to claim 2, characterized in that, The correction of the counter module's count value and the MMCM dynamic phase shift module's clock phase mentioned in step 6 refers to: using the clock difference value to correct the counter module's count value and the MMCM dynamic phase shift module's clock phase once; and using the clock speed value to continuously correct the counter module's count value and the MMCM dynamic phase shift module's clock phase.

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