A register renaming method and device of a RISC-V matrix instruction

Abstract

Embodiments of the present application disclose a register renaming method and device for RISC-V matrix instructions. Embodiments of the present application obtain a busy table of a physical register, the busy table including a direction bit and a slice vector bit of the physical register; the direction bit representing a current slice operation direction of the physical register, and the slice vector bit representing a ready state of the plurality of slices of the physical register; in response to a source logical register of a matrix instruction being a two-dimensional register, a first physical register corresponding to the source logical register is determined; the direction bit and the slice vector bit of the first physical register are obtained in the busy table; in response to a slice operation direction of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, the slice vector bit of the first physical register is distributed to a launch queue. Through the above method, the launch delay and the execution period of the matrix instruction can be reduced, and the instruction per cycle (IPC) performance is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically to a register renaming method and apparatus for RISC-V matrix instructions. Background Technology

[0002] The fifth-generation Reduced Instruction Set Computer (RISC-V) combines the advantages of x86 and ARM instruction sets. RISC-V features simple instructions, fewer instruction lines, smaller code size, and lower power consumption. As a result, RISC-V is becoming increasingly widely used. Under these circumstances, the pipeline design of the CPU will affect the processing efficiency of RISC-V.

[0003] In existing technologies, there are many data dependencies between different instructions in a program. These dependencies are directly related to registers. In modern out-of-order superscalar general-purpose processors, hardware-managed register renaming techniques are typically used to eliminate these dependencies. In schemes using a unified physical register file for register renaming, each physical register's busy table has only one bit, which indicates whether the data in the entire physical register is ready. To meet the high computational demands of matrix operations in artificial intelligence applications, various mainstream instruction set architectures have added matrix instruction extensions. These extensions introduce matrix registers (i.e., two-dimensional registers). Compared to general-purpose registers, matrix registers contain both row and column dimensions, supporting read and write operations in both row and column directions in a slice manner. However, because each physical register's busy table only has one status bit to indicate the readiness of the entire register, the matrix register can only be used as a whole, failing to reflect the readiness status of individual slices. This can lead to longer instruction issuance times, increasing instruction issue latency and execution cycles, thus impacting processor performance.

[0004] In summary, reducing the issue latency and execution cycle of matrix instructions, and improving the IPC performance (instructions executed per cycle) is a problem that needs to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a register renaming method and apparatus for RISC-V matrix instructions, which can reduce the issue latency and execution cycle of matrix instructions and improve the IPC performance of instructions executed per cycle.

[0006] In a first aspect, embodiments of the present invention provide a register renaming method for RISC-V matrix instructions, the method comprising:

[0007] Obtain the busy table of the physical register, which includes the direction bit and slice vector bit of the physical register, wherein the physical register is a two-dimensional register including multiple slices; the direction bit indicates the direction of the current slice operation of the physical register, and the slice vector bit indicates the ready state of the multiple slices of the physical register;

[0008] In response to the source logic register of the matrix instruction being a two-dimensional register, the first physical register corresponding to the source logic register is determined; the direction bit and slice vector bit of the first physical register are obtained from the busy table; in response to the direction of the slice operation of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, the slice vector bit of the first physical register is distributed to the transmit queue, wherein the transmit queue includes at least one microcode of the matrix instruction, and each microcode carries one bit of the slice vector bit corresponding to the microcode;

[0009] In response to the matrix instruction, the destination logic register is a two-dimensional register, and an idle second physical register is determined and allocated to the destination logic register; the direction bit and slice vector bit of the second physical register in the busy table are changed according to the matrix instruction.

[0010] Optionally, after distributing the slice vector bits of the first physical register to the transmit queue, the method further includes:

[0011] In response to any bit in the slice vector bits of the first physical register indicating that the corresponding slice is ready, the microcode corresponding to any bit in the slice vector bits is transmitted in the transmit queue.

[0012] Optionally, the method further includes:

[0013] In response to the matrix instruction's slicing operation on the first physical register having a different direction than the direction bit of the first physical register, all slice vector bits of the first physical register are changed to an unready state.

[0014] The modified slice vector bits of the first physical register are distributed to the transmit queue.

[0015] Optionally, the method further includes:

[0016] Command to obtain matrix;

[0017] The matrix instructions are split according to the granularity of the slice to obtain at least one microcode; wherein the microcode is used to operate a slice of the physical register.

[0018] Optionally, determining the first physical register corresponding to the source logic register includes:

[0019] Obtain the renaming mapping table; wherein, the renaming mapping table includes the mapping relationship between logical registers and physical registers;

[0020] The first physical register corresponding to the source logical register is found in the renaming mapping table.

[0021] Optionally, the renaming mapping table includes the number of the physical register;

[0022] Determining the first physical register corresponding to the source logic register includes:

[0023] The number of the first physical register corresponding to the source logical register is found in the renaming mapping table; the direction bit and slice vector bit of the first physical register are obtained from the busy table according to the number.

[0024] Optionally, allocating the determined free second physical register to the destination logical register includes:

[0025] Get the register free list;

[0026] Select a free second physical register from the register free list and assign it to the destination logic register, and change the free status of the second physical register in the register free list.

[0027] Optionally, the method further includes:

[0028] During the write-back phase, the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode described in the busy table is set to the ready state;

[0029] In response to the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode being set to the ready state, the microcode is transmitted in the transmit queue.

[0030] In a second aspect, embodiments of the present invention provide a matrix instruction processing apparatus, the apparatus comprising:

[0031] The acquisition unit is used to acquire the busy table of a physical register, the busy table including the direction bit and the slice vector bit of the physical register, wherein the physical register is a two-dimensional register including multiple slices; the direction bit indicates the direction of the current slice operation of the physical register, and the slice vector bit indicates the ready state of the multiple slices of the physical register;

[0032] The determining unit, in response to the source logic register of the matrix instruction being a two-dimensional register, is used to determine the first physical register corresponding to the source logic register; obtains the direction bit and slice vector bit of the first physical register from the busy table; in response to the direction of the slice operation of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, distributes the slice vector bit of the first physical register to the transmit queue, wherein the transmit queue includes at least one microcode of the matrix instruction, and each microcode carries one bit of the slice vector bit corresponding to the microcode;

[0033] The determining unit is further configured to, in response to the matrix instruction's destination logic register being a two-dimensional register, determine an idle second physical register to allocate to the destination logic register; and modify the direction bit and slice vector bit of the second physical register in the busy table according to the matrix instruction.

[0034] Optionally, the device further includes: a transmission unit, which, in response to any bit in the slice vector bits of the first physical register indicating that the corresponding slice is in a ready state, transmits the microcode corresponding to any bit in the slice vector bits in the transmission queue.

[0035] Optionally, the device further includes a processing unit, which, in response to the matrix instruction's slicing operation on the first physical register being in a different direction than the direction bit of the first physical register, is used to change all the slice vector bits of the first physical register to an unready state; the processing unit is further used to distribute the changed slice vector bits of the first physical register to the transmit queue.

[0036] Optionally, the acquisition unit is further configured to:

[0037] Command to obtain matrix;

[0038] The processing unit is further configured to: split the matrix instructions according to the granularity of the slice to obtain at least one microcode; wherein the microcode is used to operate a slice of the physical register.

[0039] Optionally, the acquisition unit is specifically used for:

[0040] Obtain the renaming mapping table; wherein, the renaming mapping table includes the mapping relationship between logical registers and physical registers;

[0041] The first physical register corresponding to the source logical register is found in the renaming mapping table.

[0042] Optionally, the renaming mapping table includes the number of the physical register; the acquisition unit is specifically used for:

[0043] The number of the first physical register corresponding to the source logical register is found in the renaming mapping table; the direction bit and slice vector bit of the first physical register are obtained from the busy table according to the number.

[0044] Optionally, the acquisition unit is specifically used to: acquire a register free list;

[0045] Select a free second physical register from the register free list and assign it to the destination logic register, and change the free status of the second physical register in the register free list.

[0046] Optionally, the processing unit is further configured to: during the write-back phase, set the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode in the busy table to the ready state;

[0047] The transmitting unit is further configured to: transmit the microcode in the transmitting queue in response to the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode being set to a ready state.

[0048] Thirdly, embodiments of the present invention provide computer program instructions that, when executed by a processor, implement the method as described in the first aspect or any one of the possible methods described in the first aspect.

[0049] Fourthly, embodiments of the present invention provide a computer-readable storage medium having storage thereon.

[0050] The computer program instructions, when executed by a processor, implement the method as described in the first aspect or any one of the possibilities of the first aspect.

[0051] Fifthly, embodiments of the present invention provide a chip including a memory and a processing core, the memory being used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method as described in the first aspect or any one of the possible methods of the first aspect.

[0052] Sixthly, embodiments of the present invention provide a board card, the board card including the chip described in the fifth aspect.

[0053] In a seventh aspect, embodiments of the present invention provide a server, the server including the board from the sixth aspect.

[0054] This invention employs a busy table of physical registers, including a direction bit and a slice vector bit. The physical register is a two-dimensional register comprising multiple slices. The direction bit indicates the direction of the current slice operation, and the slice vector bit indicates the ready state of the multiple slices. Responding to the fact that the source logic register of a matrix instruction is a two-dimensional register, a first physical register corresponding to the source logic register is determined. The direction bit and slice vector bit of the first physical register are obtained from the busy table. Responding to the fact that the direction of the slice operation of the matrix instruction on the first physical register is the same as the direction bit of the first physical register, the slice vector bit of the first physical register is distributed to a launch queue. The launch queue includes at least one microcode of the matrix instruction, and each microcode carries one bit of the slice vector bit corresponding to the microcode. Responding to the fact that the destination logic register of the matrix instruction is a two-dimensional register, an idle second physical register is determined and allocated to the destination logic register. The direction bit and slice vector bit of the second physical register in the busy table are modified according to the matrix instruction. This method reduces the launch latency and execution cycle of matrix instructions, improving the IPC performance (instructions executed per cycle). Attached Figure Description

[0055] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0056] Figure 1 This is a schematic diagram of a microcode in the existing technology;

[0057] Figure 2 It is a busy indication intention in existing technology;

[0058] Figure 3 This is a schematic diagram of a launch queue in the prior art;

[0059] Figure 4 This is a flowchart of a register renaming method for RISC-V matrix instructions according to an embodiment of the present invention;

[0060] Figure 5 This is a busy representation of an embodiment of the present invention;

[0061] Figure 6 This is a flowchart of another RISC-V matrix instruction register renaming method according to an embodiment of the present invention;

[0062] Figure 7 This is a flowchart of another RISC-V matrix instruction register renaming method according to an embodiment of the present invention;

[0063] Figure 8This is a flowchart of another RISC-V matrix instruction register renaming method according to an embodiment of the present invention;

[0064] Figure 9 This is a schematic diagram of another RISC-V matrix instruction register renaming device according to an embodiment of the present invention. Detailed Implementation

[0065] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0066] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0067] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0068] In the description disclosed in this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description disclosed in this invention, unless otherwise stated, "a plurality of" means two or more.

[0069] In existing technologies, there are many data dependencies between different instructions of a program. These data dependencies are directly related to registers and include three types: anti-dependency (WAR), output dependency (WAW), and true dependency (RAW). Among them, anti-dependency and output dependency are related to register names.

[0070] Specifically, a specific example of the anticorrelation WAR is as follows:

[0071] Add R3, R4, R2

[0072] Load R2, (R1)

[0073] The above add instruction reads the values ​​from registers R4 and R2, then adds the read values ​​together and writes the result to register R3; the load instruction loads data from a register and writes it to register R2 (the memory address comes from register R1); the destination register R2 of the load instruction is the same as the source register R2 of the add instruction. If the load instruction is executed before the add instruction, it will cause the instruction calculation result to be incorrect. Therefore, there is a data dependency between the add and load instructions, and the load instruction must wait for the add instruction to complete before it can be executed.

[0074] The specific example of the output-related WAW is as follows:

[0075] sub R1, R2, R3

[0076] Add R1, R4, R5

[0077] The above sub instruction reads the values ​​from registers R2 and R3, then subtracts the read values ​​and writes the result to register R1; the add instruction reads the values ​​from registers R4 and R5, then adds the read values ​​and writes the result to register R1; the destination register R1 of the add instruction is the same as the destination register R1 of the sub instruction. If the above sub and add instructions are executed out of order, and the add instruction may be executed before the sub instruction, the final result in register R1 will be incorrect, resulting in a data conflict.

[0078] In modern out-of-order superscalar general-purpose processors, hardware-managed register renaming techniques are typically used to eliminate the two types of dependencies mentioned above. For example, in the specific example of output dependency mentioned above, the renamed instruction sequence becomes as follows:

[0079] sub R1, R2, R3

[0080] Add R6, R4, R5

[0081] Therefore, it can be seen that the WAW dependency between the above-mentioned sub and add instructions has been eliminated after renaming, and the above renaming method can also resolve WAR dependency.

[0082] In existing schemes that use a unified physical register file for register renaming, the actual number of registers (physical registers) in the processor is greater than the number of general-purpose registers (logical registers) defined in the instruction set. During the renaming phase, the processor can map logical registers from the instruction set to physical registers to resolve inverse and output dependencies. Furthermore, in schemes using a unified physical register file for register renaming, a renaming mapping table records the mapping relationship between logical and physical registers, a register free list records whether physical registers are idle, and a busy table records whether the data in the physical registers is ready. Moreover, each entry in the existing busy table for physical registers has only one bit, and this single bit indicates whether the data in the entire physical register is ready.

[0083] To meet the high computational demands of matrix operations in artificial intelligence applications, major instruction set architectures have successively added matrix instruction extensions. These extensions introduce matrix registers (i.e., two-dimensional registers). Compared to general-purpose registers, matrix registers contain both row and column dimensions, allowing instructions to perform read and write operations in slices along both rows and columns. However, because each physical register's Busy Table only has one status bit to indicate the readiness of the entire register, the matrix register can only be used as a whole, failing to reflect the readiness status of individual slices. This can lead to longer instruction issuance times, increasing instruction issue latency and execution cycle, ultimately impacting processor performance.

[0084] For example, matrix instruction A1 writes data to rows 1 and 2 of matrix register t0 in the row direction, and matrix instruction B1 reads data from row 5 of matrix register t0 in the row direction. If the Busy Table only has one status bit, then during the execution of matrix instruction A1, the status bit of matrix register t0 in the Busy Table is 1 (indicating that the data in matrix register t0 is not ready). At this time, although the data in matrix register t0 for matrix instruction B1 is ready, it cannot be issued for execution until the status bit of matrix register t0 in the Busy Table becomes 0 (indicating that the data in matrix register t0 is ready). Therefore, other instructions must wait for the entire register to become ready before they can be issued and executed, increasing the issue latency and instruction execution cycle of matrix instructions.

[0085] In summary, reducing the issue latency and execution cycle of matrix instructions, and improving the IPC performance (instructions executed per cycle) is a problem that needs to be solved.

[0086] In this embodiment of the invention, to solve the above problems, a register renaming method for RISC-V matrix instructions is proposed, specifically as follows: Figure 4 As shown, Figure 4 This is a flowchart of a register renaming method for RISC-V matrix instructions according to an embodiment of the present invention, specifically including:

[0087] Step 400: Obtain the busy table of the physical register, which includes the direction bit and slice vector bit of the physical register. The physical register is a two-dimensional register that includes multiple slices. The direction bit indicates the direction of the current slice operation of the physical register, and the slice vector bit indicates the ready state of the multiple slices of the physical register.

[0088] In this embodiment, the physical register is a two-dimensional register, and the acquired busy table includes the status information of multiple two-dimensional registers. Furthermore, the direction bits of the two-dimensional registers in the busy table can determine whether a row or column operation is currently being performed on that two-dimensional register, and the slice vector bits of the two-dimensional registers in the busy table can determine whether each slice of that two-dimensional register is ready. A slice of a two-dimensional register can consist of one or more rows of the two-dimensional register, or one or more columns of the two-dimensional register.

[0089] In one possible implementation, the direction bit is 1 bit. In this embodiment, the operation direction of the two-dimensional register includes both row and column directions. For example, it can be represented by setting the direction bit to 0 or 1 respectively. That is, when the direction bit is 0, it indicates that the current slice operation of the physical register is in the row direction, and when the direction bit is 1, it indicates that the current slice operation of the physical register is in the column direction. This is only an illustrative example, and the numerical representation of the direction bit can be determined according to the actual situation. This embodiment of the invention does not limit it.

[0090] The bit width of the slice vector bit in the physical register is the maximum value of the number of slices in the row and column directions of the two-dimensional register. For example, assuming the two-dimensional register has 4 slices in the row direction and 6 slices in the column direction, the bit width of the slice vector bit in the physical register is 6. When representing a row slice, only the lower 4 bits of the slice vector bit in the physical register are valid. If the slice data in the row and column directions of the physical register are the same, the bit width of the slice vector bit in the physical register can remain unchanged when representing the state of the row and column slices. Furthermore, each bit in the slice vector bit records the ready state of the corresponding slice. For example, 0 indicates that the data in the slice is ready; 1 indicates that the slice is waiting for the instruction to write back the execution result, and the data is not yet available. This is only an illustrative example; the numerical representation of the slice vector bit can be determined according to the actual situation, and this embodiment of the invention does not limit it.

[0091] In one possible implementation, the busy table also includes an identifier for a two-dimensional register to facilitate finding the corresponding information in the busy table. This identifier can be a name or a number, etc.

[0092] For example, such as Figure 5 As shown, assuming a certain two-dimensional register is numbered 1, the busy table includes a direction bit of the two-dimensional register numbered 1 that is 1, indicating that the two-dimensional register numbered 1 is sliced ​​according to the column direction; assuming this two-dimensional register includes 4 slices in the column direction, in the... Figure 5 In this context, the slice bit vector is 1100, indicating that the data for the two-dimensional register numbered 1 in column-direction slices 1 and 2 is ready, while the data in column-direction slices 3 and 4 is not ready. Therefore, from Figure 5 It can be seen that slices 1 and 2 in the column direction of the two-dimensional register numbered 1 are in a ready state, while slices 3 and 4 in the column direction are in a not ready state.

[0093] Step 401: In response to the source logic register of the matrix instruction being a two-dimensional register, determine the first physical register corresponding to the source logic register; obtain the direction bit and slice vector bit of the first physical register from the busy table; in response to the direction of the slice operation of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, distribute the slice vector bit of the first physical register to the issue queue, wherein the issue queue includes at least one microcode of the matrix instruction, and each microcode carries one bit of the slice vector bit corresponding to the microcode. Each bit of the slice vector bit of the physical register corresponds to a slice, and each microcode of the matrix instruction corresponds to a slice to be operated on. Therefore, after distributing the slice vector bit of the first physical register to the issue queue, each microcode of the matrix instruction carries the corresponding bit of the slice vector bit, so that the microcode determines the ready state of the slice to be operated on by the corresponding bit it carries. The issue queue is used to store instructions to be executed or microcodes of instructions.

[0094] Matrix instructions can operate on one or more slices of a two-dimensional register in both row and column directions. In this embodiment, if a matrix instruction operates on multiple slices of a two-dimensional register, it can be split into multiple micro-ops according to the granularity of the slice, with each micro-op corresponding to the operation of one slice.

[0095] Since the busy table records the ready state of each slice in the two-dimensional register, the corresponding microcode can be issued according to the ready state of each slice, without waiting for all slices corresponding to the matrix instruction to be in the ready state before issuing the matrix instruction, thus effectively reducing the issuance latency of the matrix instruction.

[0096] In one possible implementation, during the decoding stage, instruction-related information of the matrix instruction can be obtained, including: the direction of the instruction's operation on the two-dimensional register, source logic register, destination logic register, and other information.

[0097] In one possible implementation, determining the first physical register corresponding to the source logical register includes: obtaining a renaming mapping table; wherein the renaming mapping table includes a mapping relationship between logical registers and physical registers; and searching for the first physical register corresponding to the source logical register in the renaming mapping table.

[0098] In one possible implementation, the renaming mapping table includes the number of the physical register; determining the first physical register corresponding to the source logical register includes: searching for the number of the first physical register corresponding to the source logical register in the renaming mapping table; and obtaining the direction bit and slice vector bit of the first physical register in the busy table according to the number.

[0099] For example, suppose the renaming mapping table is shown in Table 1 below:

[0100]

[0101]

[0102] Assuming the source logic register is t2, the corresponding first physical register number is determined to be 2 according to the renaming mapping table, and the lookup is performed based on number 2. Figure 5 The busy table shown determines the direction bit and slice vector bit corresponding to number 2.

[0103] In one possible implementation, the transmit queue includes at least one microcode of the matrix instruction, each microcode carrying one bit from the slice vector corresponding to the microcode. For example, if the transmit queue includes four microcodes of the matrix instruction and the slice vector is 1100, then the first microcode carries the first 0 from the back to the front of the slice vector, the second microcode carries the second 0 from the back to the front of the slice vector, the third microcode carries the first 1 from the back to the front of the slice vector, and the fourth microcode carries the second 1 from the back to the front of the slice vector.

[0104] In one possible implementation, the method further includes: in response to the direction of the matrix instruction's slice operation on the first physical register being different from the direction bit of the first physical register, changing all slice vector bits of the first physical register to an unready state; and distributing the changed slice vector bits of the first physical register to the issue queue of the matrix instruction. If the direction of the matrix instruction's operation on the physical register is different from the direction of the current slice operation of the physical register, it will lead to slice overlap. Therefore, the matrix instruction can only be issued after all current operations are completed, that is, after all slices corresponding to the matrix instruction are ready. In this way, the data dependency problem caused by slice overlap between instructions can be avoided.

[0105] For example, suppose that 1 in the slice vector bit indicates that the slice is not ready and 0 indicates that the slice is ready. If the direction of the slice operation of the matrix instruction on the first physical register is row, but the direction bit of the first physical register is 1 (the 1 indicates that the current slice operation of the register is column), that is, the direction of the slice operation of the matrix instruction on the first physical register is different from the direction bit of the first physical register. If the original slice vector bit of the first physical register was 0001, then the updated slice vector bit of the first physical register is 1111. The changed slice vector bit of the first physical register 1111 is distributed to the issue queue of the matrix instruction, that is, each microcode is distributed with its corresponding slice vector bit 1.

[0106] Step 402: In response to the matrix instruction, the destination logic register is a two-dimensional register. An idle second physical register is determined and allocated to the destination logic register. The direction bit and slice vector bit of the second physical register in the busy table are changed according to the matrix instruction.

[0107] In one possible implementation, determining which free second physical register to allocate to the destination logical register includes: obtaining a register free list; selecting a free second physical register from the register free list to allocate to the destination logical register; and changing the free status of the second physical register in the register free list.

[0108] The register free list is used to record whether physical registers are in a free state. Assume that the register free list is as shown in Table 2 below:

[0109] Table 2

[0110] Physical registers Status indicator 1 idle 2 idle 3 Occupy 4 idle

[0111] In Table 2 above, physical registers 1, 2, and 4 are in an idle state. A second idle physical register is selected from the register free list and allocated to the destination logical register. For example, if physical register 1 is selected as the second physical register and allocated to the destination logical register, the status indicator of physical register 1 is updated to occupied. The updated register free list is shown in Table 3 below.

[0112] Table 3

[0113] Physical registers Status indicator 1 Occupy 2 idle 3 Occupy 4 idle

[0114] The busy table is used to record whether the data in the physical registers is ready. In one possible implementation, if physical register 1, physical register 2, and physical register 4 are currently idle, and only physical register 3 is occupied, then the busy table only contains the ready information for physical register 3, as shown in Table 4 below:

[0115] Table 4

[0116]

[0117]

[0118] In another possible implementation, the direction and slice bit vectors of the idle physical registers 1, 2 and 4 can also be set to empty in the busy table.

[0119] Furthermore, if, after allocating physical register 1 as the second physical register to the destination logical register of the matrix instruction, the status indicator of the physical register in the register free list is changed, and the direction bit and slice vector bit of physical register 1 in the busy table are changed according to the operation slice and operation direction of the matrix instruction on physical register 1 (i.e., the second physical register), for example, if the operation direction of the matrix instruction on physical register 1 is column-oriented (assuming 1 represents the direction of register operation as column), the slice data of physical register 1 in the column direction is 6, and the matrix instruction operates on column slice 1 and column slice 2 of physical register 1, then after allocating physical register 1 as the second physical register to the destination logical register, the changed busy table is shown in Table 5 below:

[0120] Table 5

[0121] Physical register identifier Direction Slice bit vector 3 0 1100 1 1 000011

[0122] In one possible implementation, after step 401 or 402, the following steps are further included, specifically as follows: Figure 6 As shown, Figure 6This is a flowchart of another RISC-V matrix instruction register renaming method according to an embodiment of the present invention, specifically including:

[0123] Step 403: In response to the slice being ready as indicated by any bit in the slice vector bits of the first physical register, transmit the microcode corresponding to any bit in the slice vector bits in the transmit queue.

[0124] Suppose that the decoding of matrix instruction A is: mop_h t1, t0, where m represents the matrix instruction, op represents the opcode, h represents the operation direction on the two-dimensional register, t1 represents the destination logic register, and t0 represents the source logic register, and t0 is a two-dimensional register; if matrix instruction A operates on the four slices of t0, then matrix instruction A is split into four micro-Ops, which operate on the four slices h_slice0 to h_slice3 of t0 respectively. The micro-Ops include:

[0125] mop_h t1_h_slice0, t0_h_slice0;

[0126] mop_h t1_h_slice1, t0_h_slice1;

[0127] mop_h t1_h_slice2, t0_h_slice2;

[0128] mop_h t1_h_slice3, t0_h_slice3.

[0129] In the Busy Table, 0 indicates a ready state and 1 indicates a not-ready state. Since t0 has 4 slices, the slice bit vector of t0 in the Busy Table is 1000, which means that slices h_slice0 to h_slice2 are currently ready, but h_slice3 is not ready. Therefore, the microcodes corresponding to h_slice0 to h_slice2 are transmitted in the transmission queue, and the microcode mop_h t1_h_slice3 corresponding to h_slice3 is transmitted temporarily. t0_h_slice3 is not transmitted for the time being.

[0130] In one possible implementation, before step 400, the following steps are further included, specifically as follows: Figure 7 As shown, Figure 7 This is a flowchart of another RISC-V matrix instruction register renaming method according to an embodiment of the present invention, specifically including:

[0131] Step 404: Obtain matrix instructions.

[0132] Specifically, the matrix instruction is a two-dimensional matrix instruction.

[0133] Step 405: The matrix instructions are split according to the granularity of the slice to obtain at least one microcode; wherein the microcode is used to operate a slice of the physical register.

[0134] For example, suppose the matrix instruction operates on four slices of a two-dimensional register. The matrix instruction can be split into four microcodes. Each microcode is used to operate on one slice of the physical register. The physical register is divided into four slices in total. This is only an illustrative example. The specific number of microcodes to be split into depends on the actual situation. This embodiment of the invention does not limit the specific number of microcodes.

[0135] In this embodiment of the invention, since the Busy Table includes direction bits and vector slice bits, the ready state of each slice in the matrix register can be distinguished. After a matrix instruction is split into multiple microcodes, each microcode can be issued and executed as soon as the slice it operates on is ready, without waiting for the entire register to be ready before issuing and executing the matrix instruction. This reduces the issue latency and instruction execution cycle of the matrix instruction, and improves the performance of the processor in executing matrix instructions.

[0136] In one possible implementation, after step 403, the following steps are further included, specifically as follows: Figure 8 As shown, Figure 8 This is a flowchart of another RISC-V matrix instruction register renaming method according to an embodiment of the present invention, specifically including:

[0137] Step 406: During the write-back phase, set the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode in the busy table to the ready state.

[0138] During the write-back phase, it indicates that the microcode has been executed completely. This means the data in the corresponding register slice has been processed, and the slice is now ready. Step 406 allows for real-time updates to the ready status of each slice in each register, enabling the timely issuance of other instructions or microcode for other commands.

[0139] For example, the corresponding bit of the vector slice bit in the second physical register corresponding to the microcode mop_h t1_h_slice3 and t0_h_slice3 in the busy table is changed from the unready state to the ready state, that is, the 1 corresponding to h_slice3 is changed to 0.

[0140] Step 407: In response to the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode being set to the ready state, the microcode is transmitted in the transmit queue.

[0141] Specifically, since the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode is set to the ready state, that is, the original "busy" state is changed to the "ready" state, the microcode is then transmitted in the transmission queue.

[0142] Figure 9 This is a schematic diagram of a register renaming device for RISC-V matrix instructions according to an embodiment of the present invention. Figure 9 As shown, the apparatus of this embodiment includes an acquisition unit 901 and a determination unit 902;

[0143] The acquisition unit 901 is used to acquire a busy table of physical registers, the busy table including a direction bit and a slice vector bit of the physical register, wherein the physical register is a two-dimensional register including multiple slices; the direction bit indicates the direction of the current slice operation of the physical register, and the slice vector bit indicates the ready state of the multiple slices of the physical register; the determination unit 902, in response to the source logic register of the matrix instruction being a two-dimensional register, is used to determine the first physical register corresponding to the source logic register; acquire the direction bit and slice vector bit of the first physical register from the busy table; in response to the direction of the slice operation of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, distribute the slice vector bit of the first physical register to the transmit queue, wherein the transmit queue includes at least one microcode of the matrix instruction, each microcode carrying one bit of the slice vector bit corresponding to the microcode; the determination unit 1702 is further used to, in response to the destination logic register of the matrix instruction being a two-dimensional register, determine an idle second physical register to allocate to the destination logic register; and change the direction bit and slice vector bit of the second physical register in the busy table according to the matrix instruction.

[0144] Furthermore, the device also includes a transmission unit, which, in response to any bit in the slice vector bits of the first physical register indicating that the corresponding slice is in a ready state, transmits the microcode corresponding to any bit in the slice vector bits in the transmission queue.

[0145] Furthermore, the device also includes a processing unit, which, in response to the matrix instruction's slicing operation on the first physical register having a different direction than the direction bit of the first physical register, is used to change all the slice vector bits of the first physical register to an unready state; the processing unit is also used to distribute the changed slice vector bits of the first physical register to the transmit queue.

[0146] Furthermore, the acquisition unit is also used for:

[0147] Command to obtain matrix;

[0148] The processing unit is further configured to: split the matrix instructions according to the granularity of the slice to obtain at least one microcode; wherein the microcode is used to operate a slice of the physical register.

[0149] Furthermore, the acquisition unit is specifically used for:

[0150] Obtain the renaming mapping table; wherein, the renaming mapping table includes the mapping relationship between logical registers and physical registers;

[0151] The first physical register corresponding to the source logical register is found in the renaming mapping table.

[0152] Furthermore, the renaming mapping table includes the physical register number; the acquisition unit is specifically used for:

[0153] The number of the first physical register corresponding to the source logical register is found in the renaming mapping table; the direction bit and slice vector bit of the first physical register are obtained from the busy table according to the number.

[0154] Furthermore, the acquisition unit is specifically used to: acquire the register free list;

[0155] Select a free second physical register from the register free list and assign it to the destination logic register, and change the free status of the second physical register in the register free list.

[0156] Furthermore, the processing unit is also configured to: during the write-back phase, set the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode in the busy table to the ready state;

[0157] The transmitting unit is further configured to: transmit the microcode in the transmitting queue in response to the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode being set to a ready state.

[0158] In this embodiment of the invention, a computer program instruction is also provided, which, when executed by a processor, implements the method described in any one of the above embodiments.

[0159] In this embodiment of the invention, a computer-readable storage medium is also provided, on which computer program instructions are stored, which, when executed by a processor, implement the method described in any one of the above embodiments.

[0160] This invention provides a chip including a memory and a processing core. The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method described in any of the above embodiments.

[0161] This invention provides a board card that includes the chip.

[0162] This invention provides a server, which includes the aforementioned board.

[0163] As those skilled in the art will recognize, various aspects of the embodiments of the present invention can be implemented as a system, method, or computer program product. Therefore, various aspects of the embodiments of the present invention can take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or an implementation combining software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, various aspects of the embodiments of the present invention can take the form of a computer program product implemented in one or more computer-readable media having computer-readable program code implemented thereon.

[0164] Any combination of one or more computer-readable media can be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, (but not limited to) an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media will include: an electrical connection having one or more wires, a portable computer floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable optical disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the context of embodiments of the present invention, a computer-readable storage medium can be any tangible medium capable of containing or storing a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0165] Computer-readable signal media may include propagated data signals having computer-readable program code implemented therein, such as in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and can communicate, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0166] Program code implemented on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination thereof.

[0167] Computer program code for performing operations relating to various aspects of embodiments of the present invention can be written in any combination of one or more programming languages, including: object-oriented programming languages ​​such as Java, Smalltalk, C++, etc.; and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code can be executed as a standalone software package entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet provided by an Internet service provider).

[0168] The flowchart illustrations and / or block diagrams of the methods, apparatus (systems), and computer program products according to embodiments of the present invention describe various aspects of the embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions (executed via the processor of the computer or other programmable data processing apparatus) create means for implementing the functions / actions specified in the flowchart and / or block diagram blocks or blocks.

[0169] These computer program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus or other means to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing that includes instructions that implement the functions / actions specified in or in flowchart and / or block diagram blocks.

[0170] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operable steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide for implementing the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0171] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A register renaming method for RISC-V matrix instructions, characterized in that, The method includes: Obtain the busy table of the physical register, which includes the direction bit and slice vector bit of the physical register, wherein the physical register is a two-dimensional register including multiple slices; the direction bit indicates the direction of the current slice operation of the physical register, and the slice vector bit indicates the ready state of the multiple slices of the physical register; In response to the source logic register of the matrix instruction being a two-dimensional register, the first physical register corresponding to the source logic register is determined; the direction bit and slice vector bit of the first physical register are obtained from the busy table; in response to the direction of the slice operation of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, the slice vector bit of the first physical register is distributed to the transmit queue, wherein the transmit queue includes at least one microcode of the matrix instruction, and each microcode carries one bit of the slice vector bit corresponding to the microcode; In response to the matrix instruction, the destination logic register is a two-dimensional register, and an idle second physical register is determined and allocated to the destination logic register; the direction bit and slice vector bit of the second physical register in the busy table are changed according to the matrix instruction.

2. The method as described in claim 1, characterized in that, After distributing the slice vector bits of the first physical register to the transmit queue, the method further includes: In response to any bit in the slice vector bits of the first physical register indicating that the corresponding slice is ready, the microcode corresponding to any bit in the slice vector bits is transmitted in the transmit queue.

3. The method as described in claim 1 or 2, characterized in that, The method also includes: In response to the matrix instruction's slicing operation on the first physical register having a different direction than the direction bit of the first physical register, all slice vector bits of the first physical register are changed to an unready state. The modified slice vector bits of the first physical register are distributed to the transmit queue.

4. The method according to any one of claims 1-3, characterized in that, The method also includes: Command to obtain matrix; The matrix instructions are split according to the granularity of the slice to obtain at least one microcode; wherein the microcode is used to operate a slice of the physical register.

5. The method according to any one of claims 1-4, characterized in that, Determining the first physical register corresponding to the source logic register includes: Obtain the renaming mapping table; wherein, the renaming mapping table includes the mapping relationship between logical registers and physical registers; The first physical register corresponding to the source logical register is found in the renaming mapping table.

6. The method as described in claim 5, characterized in that, The renaming mapping table includes the numbers of the physical registers; Determining the first physical register corresponding to the source logic register includes: The number of the first physical register corresponding to the source logical register is found in the renaming mapping table; the direction bit and slice vector bit of the first physical register are obtained from the busy table according to the number.

7. The method according to any one of claims 1-6, characterized in that, The allocation of the determined free second physical register to the destination logical register includes: Get the register free list; Select a free second physical register from the register free list and assign it to the destination logic register, and change the free status of the second physical register in the register free list.

8. The method according to any one of claims 1-7, characterized in that, The method also includes: During the write-back phase, the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode described in the busy table is set to the ready state; In response to the corresponding bit of the vector slice bit of the second physical register corresponding to the microcode being set to the ready state, the microcode is transmitted in the transmit queue.

9. A matrix instruction processing device, characterized in that, The device includes: The acquisition unit is used to acquire the busy table of a physical register, the busy table including the direction bit and the slice vector bit of the physical register, wherein the physical register is a two-dimensional register including multiple slices; the direction bit indicates the direction of the current slice operation of the physical register, and the slice vector bit indicates the ready state of the multiple slices of the physical register; The determining unit, in response to the source logic register of the matrix instruction being a two-dimensional register, is used to determine the first physical register corresponding to the source logic register; obtains the direction bit and slice vector bit of the first physical register from the busy table; in response to the direction of the slice operation of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, distributes the slice vector bit of the first physical register to the transmit queue, wherein the transmit queue includes at least one microcode of the matrix instruction, and each microcode carries one bit of the slice vector bit corresponding to the microcode; The determining unit is further configured to, in response to the matrix instruction's destination logic register being a two-dimensional register, determine an idle second physical register to allocate to the destination logic register; and modify the direction bit and slice vector bit of the second physical register in the busy table according to the matrix instruction.

10. A computer program product comprising computer program instructions, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-8.

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