Asymmetric three-stage gate metal oxide thin film transistor structure and method of manufacturing the same
By using an asymmetric three-segment gate metal-oxide-slim thin-film transistor structure, and by utilizing metal gate segments with different work functions and optimized length relationships, the leakage current problem of IGZO TFTs was solved, thus improving the performance of DRAM.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-11-17
- Publication Date
- 2026-07-24
AI Technical Summary
The leakage current problem of existing IGZO TFTs is difficult to solve effectively in traditional thermal annealing processes, resulting in shorter DRAM hold-up time and increased power consumption.
An asymmetric three-segment gate metal-oxide thin-film transistor structure is adopted, which uses metal gate segments with different work functions to form a three-segment gate layer, and reduces the leakage current of the device by optimizing the length and coverage relationship of the gate segments.
It significantly reduces device leakage current, improves DRAM hold time, reduces power consumption, and the manufacturing method is compatible with existing integration processes.
Smart Images
Figure CN117712179B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of transistors, and in particular to an asymmetric three-segment gate metal-oxide thin-film transistor structure and its manufacturing method. Background Technology
[0002] Dynamic Random Access Memory (DRAM) plays a crucial role in the development of cloud computing, edge computing, the Internet of Things (IoT), and artificial intelligence. In recent years, DRAM has faced the well-known "memory wall" problem, namely the performance difference between the CPU and the main memory. Simultaneously, with the miniaturization of feature sizes and chip areas, the size of transistors and capacitors in the traditional 1T1C DRAM architecture continues to shrink, leading to challenges such as increased leakage current, shortened hold time, and increased power consumption.
[0003] Indium gallium zinc oxide thin-film transistors (IGZO TFTs) possess characteristics such as low leakage current, high mobility, low-temperature large-area deposition, and low cost. Capacitorless 2T0C DRAMs composed of IGZO TFTs hold promise for solving the "memory wall" problem of traditional 1T1C DRAMs. To improve the hold time of DRAM devices, reducing the leakage current of IGZO TFTs has become a new challenge.
[0004] Currently, the most common process for reducing leakage current in IGZO TFTs is thermal annealing, which repairs material defects, but its effectiveness in reducing leakage current is nearing its limit.
[0005] Therefore, this invention is proposed. Summary of the Invention
[0006] The main objective of this invention is to provide an asymmetric three-segment gate metal oxide thin film transistor structure and its manufacturing method, which significantly reduces the leakage current problem of the device.
[0007] To achieve the above objectives, the present invention provides the following technical solutions.
[0008] A first aspect of the present invention provides an asymmetric three-segment gate metal-oxide thin-film transistor structure, comprising: Substrate; Stacked sequentially from bottom to top on the substrate are: a gate layer, a gate dielectric layer, and a channel layer; The source layer and drain layer are respectively disposed on the left and right sides of the upper surface of the channel layer; The gate layer comprises a first metal gate segment, a second metal gate segment, and a third metal gate segment sequentially spliced in a horizontal direction, and the work function of the first metal gate segment and the third metal gate segment is lower than that of the second metal gate segment.
[0009] Further improvements can be made based on this, as listed below.
[0010] Furthermore, the difference between the work function of the second metal gate segment and the work function of the first metal gate segment is 0.05V~1.5V, and the difference between the work function of the second metal gate segment and the work function of the third metal gate segment is 0.05V~1.5V.
[0011] Furthermore, the first metal gate segment is covered only by the source layer, the third metal gate segment is covered only by the drain layer, and the second metal gate segment is not covered by the source layer and the drain layer.
[0012] Furthermore, the length of the second metal gate segment is greater than the length of the first metal gate segment and the length of the third metal gate segment, and the length direction is along the splicing direction.
[0013] Furthermore, the first metal gate segment and the third metal gate segment use the same metal.
[0014] Furthermore, the lengths of the first metal gate segment and the third metal gate segment are different.
[0015] Furthermore, the channel layer is made of at least one of IGZO, IZO, ITO, InO, ZnO, and TiO. Furthermore, the source and drain layers are made of Mo.
[0016] Furthermore, the gate dielectric layer covers the upper surface and sidewalls of the gate layer, the channel layer covers the upper surface and sidewalls of the gate dielectric layer, and both the source layer and the drain layer cover the upper surface and sidewalls of the channel layer.
[0017] A second aspect of the present invention provides a method for manufacturing the asymmetric three-segment gate metal-oxide thin-film transistor structure of the first aspect, comprising: A gate layer is formed on a substrate, the gate layer comprising a first metal gate segment, a second metal gate segment and a third metal gate segment sequentially spliced in a horizontal direction; A gate dielectric layer is formed to cover the gate layer; A channel layer is formed to cover the gate dielectric layer; A conductive layer is formed above the channel layer; The conductive layer is patterned to form a source layer and a drain layer, respectively; Preferably, the step of forming the gate layer includes: first forming a second metal gate segment, and then forming a first metal gate segment and a third metal gate segment on the left and right sides of the second metal gate segment, respectively.
[0018] Furthermore, the step of forming the gate layer includes: first forming a second metal gate segment, and then forming a first metal gate segment and a third metal gate segment on the left and right sides of the second metal gate segment, respectively.
[0019] In summary, compared with the prior art, the present invention achieves the following technical effects: (1) By splicing two or three metals with different work functions into a three-segment gate layer, the leakage current problem of the device can be reduced by utilizing the difference in work functions; (2) Placing a metal with a low work function in the overlapping part of the source / drain and gate will affect the electric field in the channel, thereby reducing the leakage current problem of the device; (3) Optimizing the difference between the work function of the first metal grid segment, the third metal grid segment and the work function of the second metal grid segment can further improve the leakage problem; (4) Optimizing the length difference of the three gate segments will affect the potential barrier in the channel and further improve the leakage problem; (5) The manufacturing method provided is simple and compatible with existing integrated processes. Attached Figure Description
[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.
[0021] Figure 1 A schematic diagram of the structure of the asymmetric three-segment gate metal-oxide thin-film transistor provided by the present invention; Figures 2 to 8 This is a schematic diagram of the structure obtained in each step of the manufacturing method provided by the present invention. Detailed Implementation
[0022] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0023] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0024] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0025] This invention provides a method such as Figure 1 The asymmetric three-segment gate metal-oxide thin-film transistor shown includes: a substrate (not shown); and a gate layer, a gate dielectric layer 2 and a channel layer 3 stacked sequentially from bottom to top on the substrate; a source layer 41 and a drain layer 42 are respectively disposed on the left and right sides of the upper surface of the channel layer 3.
[0026] The gate layer comprises a first metal gate segment 11, a second metal gate segment 12, and a third metal gate segment 13, which are sequentially spliced in a horizontal direction. The work functions of the first and third metal gate segments are both lower than that of the second metal gate segment. Although Figure 1 The diagram only illustrates the structure where the first metal gate segment 1 is located on the left side, but this does not limit the scope of the invention. The splicing in this invention can be from left to right or from right to left. In other words, the first metal gate segment and the source layer can be on the same side, and the third metal gate segment and the drain layer can be on the same side; alternatively, the third metal gate segment and the source layer can be on the same side, and the first metal gate segment and the drain layer can be on the same side. Typically, to significantly reduce leakage current, the first metal gate segment is covered by only one of the source and drain layers, and the third metal gate segment is covered by only the other.
[0027] Therefore, this invention, by using at least two metals with different work functions to form a three-segment gate, can reduce the leakage current problem of the device, thus compensating for the shortcomings of traditional thermal annealing processes. Furthermore, the structure of this invention can be further integrated with thermal annealing processes; this invention is not limited in this regard.
[0028] exist Figure 1 In the transistor shown, the substrate can be any substrate commonly used in semiconductor devices. It can be a silicon-based substrate, such as one of bulk silicon, SOI, strained silicon, GeSi, or silicon oxide, or a substrate made of group III-V materials.
[0029] The first metal gate segment 11, the second metal gate segment 12, and the third metal gate segment 13 can be independently selected from TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu, and RuOx, as long as the selection of the three meets the requirement of work function difference. Meanwhile, the first metal gate segment 11 and the third metal gate segment 13 can be made of the same or different metals. Using different metals can further reduce leakage current, while using the same metal simplifies the fabrication process.
[0030] In some implementations, the difference between the work function of the second metal gate segment 12 and the work function of the first metal gate segment 11 is 0.05V to 1.5V.
[0031] In some implementations, the difference between the work function of the second metal gate segment 12 and the work function of the third metal gate segment 13 is 0.05V to 1.5V.
[0032] In some implementations, the second metal gate segment 12 is made of Mo, while the first metal gate segment 11 and the third metal gate segment 13 are both made of Al.
[0033] The gate dielectric layer 2 can be one or more of the following materials stacked together: aluminum oxide, silicon oxide, silicon oxynitride, tantalum oxide, hafnium oxide, silicon nitride, tantalum oxide, or zirconium oxide.
[0034] The channel layer 3 can be at least one of IGZO, IZO, ITO, InO, ZnO, and TiO to obtain higher field-effect mobility and better electrical stability.
[0035] The source layer 41 and drain layer 42 can be made of conductive materials such as metals or doped semiconductors, for example, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu, and RuOx. The materials of the source layer and drain layer can be the same or different.
[0036] In some implementations, such as Figure 1As shown, the first metal gate segment 11 is covered only by the source layer 41, the third metal gate segment 13 is covered only by the drain layer 42, and the second metal gate segment 12 is not covered by either the source layer 41 or the drain layer 42. In other words, the second metal gate segment 12 is located directly below the isolation segment between the source layer 41 and the drain layer 42.
[0037] In some embodiments, the length of the second metal gate segment is greater than the length of the first metal gate segment and the length stated therein, and the length direction is along the splicing direction.
[0038] This size difference can be used to further reduce leakage problems. For example... Figure 1 As shown, the lengths of the first metal gate segment 11, the second metal gate segment, and the third metal gate segment are L1, L2, and L3, respectively, with L2 > L1 and L2 > L3.
[0039] In some implementations, the lengths of the first metal gate segment and the third metal gate segment are different, i.e., L1 ≠ L3. For example, it can be as follows: Figure 1 The L1 shown is greater than L3, or in another embodiment, L1 is less than L3. This asymmetric overlap length can affect the potential barrier in the channel, thereby further reducing device leakage current.
[0040] In some implementations, the gate layer, gate dielectric layer 2, channel layer 3, and source layer 41 / drain layer 42 are stacked in a "wrap-around" shape, for example... Figure 1 As shown, the gate dielectric layer 2 covers the upper surface and sidewalls of the gate layer, the channel layer 3 covers the upper surface and sidewalls of the gate dielectric layer 2, and the source layer 41 and the drain layer 42 both cover the upper surface and sidewalls of the channel layer 3.
[0041] In some implementations, the source layer 41 and the drain layer 42 can be isolated by a suitable dielectric material. Figure 1 It is not shown in the middle.
[0042] The present invention also provides Figure 1 The method for manufacturing the transistor shown is simple and mainly includes the following steps: A gate layer is formed on a substrate, the gate layer comprising a first metal gate segment, a second metal gate segment and a third metal gate segment sequentially spliced in a horizontal direction; A gate dielectric layer is formed to cover the gate layer; A channel layer is formed to cover the gate dielectric layer; A conductive layer is formed above the channel layer; The conductive layer is patterned to form a source layer and a drain layer, respectively.
[0043] In this invention, the specific steps for forming the gate layer differ for the two cases where the first metal gate segment and the third metal gate segment use the same or different metal materials. The following description takes the case where the first metal gate segment and the third metal gate segment use the same metal material as an example.
[0044] Step S1: Form a second metal gate segment 12 on the substrate using sputtering or other means.
[0045] Step S2: A low work function metal layer 11' is formed on the second metal gate segment 12. The low work function metal layer 11' covers the upper surface and sidewalls of the second metal gate segment, that is, sidewalls are formed on the left and right sidewalls of the second metal gate segment, such as... Figure 3 As shown.
[0046] Step S3: Etch the isolation dielectric layer 11'. Taking the first and third metal gate segments as examples of different lengths, this achieves asymmetric sidewall retention while exposing the upper surface of the second metal gate segment. At this point, the first metal gate segment 11 and the third metal gate segment 13 of different lengths are formed on the left and right sides of the second metal gate segment, respectively. These three segments constitute the gate layer, as shown below. Figure 4 As shown.
[0047] Step S4, form gate dielectric layer 2, cover the gate layer, as shown. Figure 5 As shown.
[0048] Step S5, forming the channel layer 3, covering the gate dielectric layer 2, as shown. Figure 6 As shown.
[0049] Step S6: A conductive layer 4 is formed above the channel layer 3. The conductive layer is made of various permitted materials used to form the source and drain, such as... Figure 7 As shown.
[0050] Step S7: Pattern the conductive layer 4 to form the source layer 41 and drain layer 42, as shown below. Figure 8 As shown.
[0051] If the first metal grid segment and the third metal grid segment are made of different metal materials, the first metal grid segment and the third metal grid segment can be formed in steps, and the order of their formation can be interchanged.
[0052] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. An asymmetric three-segment gate metal-oxide thin-film transistor structure, characterized in that, include: Substrate; Stacked sequentially from bottom to top on the substrate are: a gate layer, a gate dielectric layer, and a channel layer; The source layer and drain layer are respectively disposed on the left and right sides of the upper surface of the channel layer; The gate layer comprises a first metal gate segment, a second metal gate segment, and a third metal gate segment sequentially spliced in the horizontal direction, and the work function of the first metal gate segment and the third metal gate segment is lower than that of the second metal gate segment. The first metal gate segment is covered only by the source layer, the third metal gate segment is covered only by the drain layer, and the second metal gate segment is not covered by either the source layer or the drain layer; the lengths of the first metal gate segment and the third metal gate segment are different.
2. The asymmetric three-segment gate metal-oxide thin-film transistor structure according to claim 1, characterized in that, The difference between the work function of the second metal gate segment and the work function of the first metal gate segment is 0.05V~1.5V, and the difference between the work function of the second metal gate segment and the work function of the third metal gate segment is 0.05V~1.5V.
3. The asymmetric three-segment gate metal-oxide thin-film transistor structure according to claim 1, characterized in that, The length of the second metal gate segment is greater than the length of the first metal gate segment and the length of the third metal gate segment, and the length direction is along the splicing direction.
4. The asymmetric three-segment gate metal-oxide thin-film transistor structure according to claim 1, wherein the first metal gate segment and the third metal gate segment are made of the same metal.
5. The asymmetric three-segment gate metal-oxide thin-film transistor structure according to any one of claims 1-4, characterized in that, The channel layer is made of at least one of IGZO, IZO, ITO, InO, ZnO, and TiO.
6. The asymmetric three-segment gate metal-oxide thin-film transistor structure according to any one of claims 1-4, characterized in that, The source and drain layers are made of Mo.
7. The asymmetric three-segment gate metal-oxide thin-film transistor structure according to any one of claims 1-4, characterized in that, The gate dielectric layer covers the upper surface and sidewalls of the gate layer, the channel layer covers the upper surface and sidewalls of the gate dielectric layer, and both the source layer and the drain layer cover the upper surface and sidewalls of the channel layer.
8. A method for manufacturing the asymmetric three-segment gate metal-oxide thin-film transistor structure according to any one of claims 1-7, characterized in that, include: A gate layer is formed on a substrate, the gate layer comprising a first metal gate segment, a second metal gate segment and a third metal gate segment sequentially spliced in a horizontal direction; A gate dielectric layer is formed to cover the gate layer; A channel layer is formed to cover the gate dielectric layer; A conductive layer is formed above the channel layer; The conductive layer is patterned to form a source layer and a drain layer, respectively.
9. The manufacturing method according to claim 8, characterized in that, The steps for forming the gate layer include: first forming a second metal gate segment, and then forming a first metal gate segment and a third metal gate segment on the left and right sides of the second metal gate segment, respectively.