Display panel and display device

Abstract

The display panel comprises a substrate, a first common electrode bus, a second common electrode bus and a conductive connection layer which are arranged in layers on the substrate, the substrate comprises a display area and a peripheral area surrounding the display area, the first common electrode bus comprises a main body part and a branch part extending from an end of the main body part to a side away from the display area, the main body part extends along a first direction, at least a part of the branch part connected with the main body part extends along a second direction, the first direction and the second direction intersect, the second common electrode bus extends along the second direction to the side away from the display area, a first end of the second common electrode bus and an end of the main body part and the branch part are opposite, in the peripheral area, the conductive connection layer is electrically connected with the branch part of the first common electrode bus through a first via structure, and the conductive connection layer is electrically connected with the first end of the second common electrode bus through a second via structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display panel and a display device. Background Technology

[0002] Liquid Crystal Displays (LCDs) are among the most widely used flat panel displays. They offer advantages such as thinness, wide color gamut, low power consumption, and portability, and are currently widely used in display products such as televisions, monitors, and laptops. An LCD panel is a non-emissive image display device, comprising a color filter substrate, an array substrate on which thin-film transistors are disposed, and a liquid crystal layer formed by injection between the color filter substrate and the array substrate. Because the liquid crystal molecules in the liquid crystal layer are anisotropic, LCD panels can display images by utilizing differences in light transmittance.

[0003] A liquid crystal display panel includes a liquid crystal panel (LCD) and a driving circuit for driving the LCD. Pixel cells on the LCD are arranged in a matrix, and gate lines and data lines on the LCD define pixel areas. A liquid crystal cell is disposed within the pixel area. The LCD also includes a common electrode and pixel electrodes that provide an electric field to each liquid crystal cell. Each pixel electrode is connected to the data line via a source or drain lead of a thin-film transistor (TFT) that acts as a switching element, and the gate lead of the TFT is connected to the gate line. The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a common voltage generator for driving the common electrode. The gate driver sequentially sends gate signals to the gate lines to sequentially drive the liquid crystal cells on the LCD. Therefore, the liquid crystal display panel can adjust the transmittance of each liquid crystal cell according to the electric field applied between the pixel electrode and the common electrode in response to the data voltage signal, thereby displaying an image. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display panel and a display device. In the display panel, a conductive connection layer in the peripheral region is connected through a first via structure and a branch of a first common electrode bus. The conductive connection layer is electrically connected through a second via structure and a first end of the second common electrode bus. This structural design of the display panel allows for an increase in the number of first and second via structures, reducing the resistance in the circuit structure and preventing the first and second via structures from burning out, which would reduce the product yield and shorten the lifespan of the display panel. Furthermore, when the display panel is a liquid crystal display panel, placing the first and second via structures far away from the display area can also prevent the heat dissipated from the first and second via structures from raising the temperature of the liquid crystal layer in the display area of ​​the liquid crystal display panel, thus avoiding the problem of liquid crystal clearing points.

[0005] At least one embodiment of this disclosure provides a display panel, the display panel comprising: a substrate including a display area and a peripheral area surrounding the display area; a first common electrode bus, a second common electrode bus, and a conductive connection layer stacked on the substrate, wherein the first common electrode bus includes a main body portion and a branch portion extending from an end of the main body portion toward a side away from the display area, the main body portion extending along a first direction, and at least a portion of the branch portion connected to the main body portion extending along a second direction, the first direction and the second direction intersecting; the second common electrode bus extending along the second direction toward a side away from the display area, a first end of the second common electrode bus facing the end of the main body portion and the branch portion; in the peripheral area, the conductive connection layer is electrically connected to the branch portion of the first common electrode bus through a first via structure, and the conductive connection layer is electrically connected to the first end of the second common electrode bus through a second via structure.

[0006] For example, in a display panel provided in at least one embodiment of this disclosure, on a plane parallel to the main surface of the substrate, the branch portion includes at least a first bent portion away from the display area, and the orthographic projection of the first via structure on the substrate and the orthographic projection of the first bent portion on the substrate at least partially overlap.

[0007] For example, in a display panel provided in at least one embodiment of this disclosure, on a plane parallel to the main surface of the substrate, the first end extends into the opening region defined by the first bend, and the orthographic projection of the second via structure on the substrate and the orthographic projection of the first end on the substrate at least partially overlap.

[0008] For example, in a display panel provided in at least one embodiment of this disclosure, the first bending portion includes a first sub-bending portion extending along the second direction and a second sub-bending portion extending along the first direction toward a side close to the second common electrode bus. The extension direction of the second common electrode bus is parallel to the second direction. The orthographic projection of the first sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate have an overlapping portion, and the orthographic projection of the second sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate also have an overlapping portion.

[0009] For example, in a display panel provided in at least one embodiment of this disclosure, the first bending portion includes a first sub-bending portion extending along the second direction and a second sub-bending portion extending along the first direction toward a side close to the second common electrode bus. The extension direction of the second common electrode bus is parallel to the second direction. The orthographic projection of the first sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate have an overlapping portion, and the orthographic projection of the second sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate do not have an overlapping portion.

[0010] For example, in a display panel provided in at least one embodiment of this disclosure, the first bending portion includes a first sub-bending portion extending along the second direction and a second sub-bending portion extending along the first direction toward a side close to the second common electrode bus. The extension direction of the second common electrode bus is parallel to the second direction. The orthographic projection of the first sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate do not overlap, while the orthographic projection of the second sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate overlap.

[0011] For example, in a display panel provided in at least one embodiment of this disclosure, on a plane parallel to the main surface of the substrate, the branch portion further includes a second bending portion away from the display area. The second bending portion includes a third sub-bending portion extending along the second direction and a fourth sub-bending portion extending along the first direction. The second sub-bending portion and the fourth sub-bending portion are connected so that the overall shape of the first bending portion and the second bending portion is "U"-shaped, and the second common electrode bus extends into the opening of the "U" shape.

[0012] For example, in a display panel provided in at least one embodiment of this disclosure, the orthographic projection of the third sub-bent portion on the substrate and the orthographic projection of the first via structure on the substrate overlap, and the orthographic projection of the fourth sub-bent portion on the substrate and the orthographic projection of the first via structure on the substrate overlap.

[0013] For example, in a display panel provided in at least one embodiment of this disclosure, the orthographic projection of the third sub-bent portion on the substrate and the orthographic projection of the first via structure on the substrate have an overlapping portion, while the orthographic projection of the fourth sub-bent portion on the substrate and the orthographic projection of the first via structure on the substrate do not have an overlapping portion.

[0014] For example, in a display panel provided in at least one embodiment of this disclosure, the main body of the first common electrode bus is disposed in a direction parallel to the first direction on a plane parallel to the main surface of the substrate, the main body is provided with a third via structure, and the main body is electrically connected to the conductive connection layer through the third via structure.

[0015] For example, in a display panel provided in at least one embodiment of this disclosure, the minimum distance between the first via structure and the second via structure and the display area is greater than 500 micrometers.

[0016] For example, in a display panel provided in at least one embodiment of this disclosure, the first via structure is configured as a plurality of multiple via structures, the second via structure is configured as a plurality of multiple via structures, and the total number of the first via structure and the second via structure is greater than or equal to 150.

[0017] For example, in a display panel provided in at least one embodiment of this disclosure, the first via structure and the second via structure are arranged in a matrix, the first direction is the row direction, the second direction is the column direction, the sum of the number of the first via structure and the second via structure in a row along the first direction is greater than 15, the sum of the number of the first via structure and the second via structure in a column along the second direction is greater than 10, and the sum of the number of the first via structure and the second via structure in a row along the first direction is greater than the sum of the number of the first via structure and the second via structure in a column along the second direction.

[0018] For example, in a display panel provided in at least one embodiment of this disclosure, the first via structure and the second via structure are arranged in a matrix, the first direction is the row direction, the second direction is the column direction, the sum of the number of the first via structure and the second via structure in a row along the first direction is greater than 10, the sum of the number of the first via structure and the second via structure in a column along the second direction is greater than 15, and the sum of the number of the first via structure and the second via structure in a row along the first direction is less than the sum of the number of the first via structure and the second via structure in a column along the second direction.

[0019] For example, in a display panel provided in at least one embodiment of this disclosure, the maximum size of the first via structure and the second via structure on the motherboard surface parallel to the substrate is in the range of 4 micrometers to 6 micrometers.

[0020] For example, at least one embodiment of the present disclosure provides a display panel that further includes: a thin-film transistor and a first electrode disposed on the substrate and in the display area, wherein the thin-film transistor includes a gate, an active layer and a source / drain electrode layer stacked together, the source / drain electrode layer includes a source and a drain disposed opposite to each other, a first common electrode bus and the gate are disposed on the same layer, a second common electrode bus and the source and the drain are disposed on the same layer, the conductive connection layer and the first electrode are disposed on the same layer and spaced apart from each other, and the first electrode is electrically connected to the drain through a fourth via structure.

[0021] For example, in a display panel provided in at least one embodiment of this disclosure, a gate insulating layer is provided on the side of the gate away from the substrate, and a passivation layer is provided on the side of the source / drain electrode layer away from the substrate. The first via structure passes through the passivation layer and the gate insulating layer in sequence, and the second via structure and the fourth via structure both pass through the passivation layer.

[0022] For example, in a display panel provided in at least one embodiment of this disclosure, on a plane parallel to the main surface of the substrate, and in one display panel, two second common electrode buses are configured, and the two second common electrode buses are disposed opposite to each other on both sides of the main body portion of the first common electrode bus along the first direction; the display panel further includes a third common electrode bus disposed opposite to the first common electrode bus in the second direction, the third common electrode bus is parallel to the main body portion of the first common electrode bus, and the third common electrode bus is disposed in the same layer as the first common electrode bus, the two second common electrode buses, the first common electrode bus and the third common electrode bus surround the display area; the two second common electrode buses respectively include a second end and a third end away from the first common electrode bus in the first direction, and the conductive connection layer is electrically connected to the second end and the third end through a fifth via structure; the third common electrode bus includes a fourth end opposite to the second end and a fifth end opposite to the third end, and the conductive connection layer is electrically connected to the fourth end and the fifth end through a sixth via structure.

[0023] For example, in a display panel provided in at least one embodiment of this disclosure, the portion of the third common electrode bus between the fourth end and the fifth end is electrically connected to the conductive connection layer via a seventh via structure.

[0024] At least one embodiment of this disclosure also provides a display device, which includes the display panel in any of the above examples. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0026] Figure 1 This is a schematic diagram of a planar structure of a display panel;

[0027] Figure 2 A schematic diagram of the planar structure of a display panel provided for at least one embodiment of this disclosure;

[0028] Figure 3 A magnified planar structural schematic diagram of a first bent portion provided for at least one embodiment of the present disclosure;

[0029] Figure 4 A magnified planar structural schematic diagram of another first bending portion provided in at least one embodiment of the present disclosure;

[0030] Figure 5 A magnified planar structural schematic diagram of another first bent portion provided in at least one embodiment of the present disclosure;

[0031] Figure 6 This is a schematic diagram of an enlarged planar structure of a branch provided in at least one embodiment of the present disclosure;

[0032] Figure 7 A further enlarged planar structural diagram of a branch provided in at least one embodiment of the present disclosure;

[0033] Figure 8 A schematic diagram of an enlarged planar structure of a branch provided in at least one embodiment of this disclosure;

[0034] Figure 9 A circuit diagram at a first via structure and a second via structure provided for at least one embodiment of this disclosure; and

[0035] Figure 10 This is a schematic cross-sectional view of a display panel provided for at least one embodiment of the present disclosure. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0038] With the continuous development of flat panel display technology, display devices have been successfully applied to display equipment such as laptops, monitors, televisions, and advertising screens. Thin-film transistor (TFT) displays are one type of display. Each pixel on a TFT display is driven by a field-effect thin-film transistor integrated behind it, enabling the acquisition of information from a high-brightness, high-contrast display screen. Since GOA (Gate-on-Area) driving circuits can replace gate-driven chip-on-film (COF) films, and the manufacturing cost of GOA driving circuits is lower than that of gate-driven COF films, the use of GOA driving circuits can save production costs. This allows for the mass production and use of such display devices in the display field while reducing production costs.

[0039] For example, display panels typically include multiple electronic components, such as thin-film transistors, signal lines, and electrode patterns. These electronic components are distributed across different layers. During the actual manufacturing process of display panels, based on requirements such as wiring design and layout, it is often necessary to electrically connect conductive patterns located on different layers to meet product requirements.

[0040] For example, in display panel design, such as in large-size display panels for televisions, laptops, monitors, and advertising screens, conductive patterns on different layers are typically connected to the electrical connection layer through multiple via structures. That is, two conductive patterns on different layers are electrically connected to the electrical connection layer through corresponding via structures, thus achieving electrical connection between conductive patterns on different layers. Display panels are also widely used in small-size display panels such as gaming monitors. With the continuous expansion of the gaming market, similar to large-size display panels, two conductive patterns on different layers in small-size display panels are also electrically connected to the electrical connection layer through corresponding via structures. Professional gaming monitors have an increasing demand for ultra-high refresh rates, with refresh rates evolving from 60Hz to 120Hz, 144Hz, 165Hz, 240Hz, or even 480Hz. Higher frequencies generate more heat.

[0041] The inventors of this disclosure have noted that in current medium-to-large-sized and small-sized display panels, the resistance values ​​at the electrical connection layers and conductive pattern connections are relatively high, meaning that the resistance at the via structures is high and the current withstand value is low. Under the same current, the via structures dissipate more heat, resulting in higher heat generation. Especially in liquid crystal display panels, not only is the resistance at the via structures high, but the via structures are also close to the display area, causing the temperature of the liquid crystal layer in the display area to rise. When the temperature of the liquid crystal layer exceeds the clearing point of the liquid crystal molecules, the liquid crystal layer becomes transparent, affecting the display area and resulting in a poor display image. It should be noted that the aforementioned display area refers to the area corresponding to the effective pixels. In some embodiments, the pixels of the display panel include effective pixels and dummy pixels, and the display area is the area corresponding to the effective pixels. The distance between the via structure and the display area refers to the minimum distance between the via structure and the effective pixels. In some cases, the via structures are also prone to burning out, leading to a decrease in the product yield and a shorter lifespan of the liquid crystal display panel. For example, Figure 1 This is a schematic diagram of a planar structure of a display panel, such as... Figure 1As shown, a vertical common electrode bus 012 is provided on the right side of the display area 011, and a horizontal common electrode bus 013 is provided below the display area 011. A first via 014 is provided above the horizontal common electrode bus 013, and a second via 015 is provided above the vertical common electrode bus 012. A conductive connection layer 016 is provided above the first via 014 and the second via 015. The conductive connection layer 016 is electrically connected to the horizontal common electrode bus 013 through the first via 014, and to the vertical common electrode bus 012 through the second via 015, thereby electrically connecting the horizontal common electrode bus 013 and the vertical common electrode bus 012. However, in Figure 1 In the structure shown, the area directly opposite the vertical common electrode bus 012 and the horizontal common electrode bus 013 is relatively small, which makes the area where the first via 014 and the second via 015 can be arranged relatively small. This results in fewer first vias 014 and the second via 015, fewer parallel circuits, and higher resistance in the entire circuit. Consequently, more heat is released at the first vias 014 and the second via 015, which can easily lead to the first vias 014 and the second via 015 being burned out, reducing the product yield of the display panel and shortening the lifespan of the display panel. When the display panel is a liquid crystal display panel, the first via 014 and the second via 015 are relatively close to the display area 011. This can easily lead to the problem that the heat emitted from the first via 014 and the second via 015 raises the temperature of the liquid crystal layer in the display area 011 of the liquid crystal display panel, thus causing the liquid crystal to clear. Therefore, it is advisable to increase the number of the first via 014 and the second via 015 and place the first via 014 and the second via 015 further away from the display area 011 to reduce the impact of the heat emitted from the first via 014 and the second via 015 on the display area 011.

[0042] At least one embodiment of this disclosure provides a display panel, comprising: a substrate and a first common electrode bus, a second common electrode bus, and a conductive connection layer stacked on the substrate. The substrate includes a display area and a peripheral area surrounding the display area. The first common electrode bus includes a main body and a branch extending from an end of the main body toward a side away from the display area. The main body extends along a first direction, and at least a portion of the branch connected to the main body extends along a second direction, with the first and second directions intersecting. The second common electrode bus extends along the second direction toward a side away from the display area, with a first end of the second common electrode bus facing the end of the main body and the branch. In the peripheral area, the conductive connection layer is connected to the branch of the first common electrode bus via a first via structure, and electrically connected to the first end of the second common electrode bus via a second via structure. This display panel design allows for an increase in the number of first and second via structures, reducing resistance in the circuit structure and preventing the first and second via structures from burning out, which could lead to reduced product yield and shorter lifespan of the display panel. Furthermore, when the display panel is a liquid crystal display panel, setting the first and second via structures far away from the display area can also avoid the problem of heat dissipated from the first and second via structures causing the temperature of the liquid crystal layer in the display area of ​​the liquid crystal display panel to rise, thus achieving the problem of clearing the liquid crystal.

[0043] For example, Figure 2 This is a schematic diagram of a planar structure of a display panel according to at least one embodiment of the present disclosure. The display panel 100 includes: a substrate 101 and a first common electrode bus 102, a second common electrode bus 103, and a conductive connection layer 104 stacked on the substrate 101. The substrate 101 includes a display area 105 and a peripheral area 106 surrounding the display area 105. The first common electrode bus 102 includes a main body portion 102a and a branch portion 102b extending from an end portion 102a' of the main body portion toward a side away from the display area 105. For example, the main body portion 102a extends along a first direction X, the branch portion 102b includes at least an elongated portion, and at least a portion of the branch portion 102b connected to the main body portion 102a extends along a second direction Y, and the first direction X and the second direction Y intersect.

[0044] For example, in one example, such as Figure 2As shown, the branch 102b includes two parts that form a step shape. The first end 103a of the second common electrode bus 103 extends to face the lateral platform of the step. The portion of the branch 102b connected to the main body 102a extends along the second direction Y to form a step-shaped vertical portion. Of course, the embodiments of this disclosure are not limited to this. Alternatively, the branch 102b may only include an elongated portion connected to the main body 102a and extending along the second direction Y, or the branch 102b may include multiple step-shaped portions.

[0045] For example, in one example, such as Figure 2 As shown, the second common electrode bus 103 extends along the second direction Y towards the side away from the display area 105. The first end 103a of the second common electrode bus 103 and the end 102a' and branch 102b of the main body are all directly opposite each other. In the peripheral area 106, the conductive connection layer 104 is connected to the branch 102b of the first common electrode bus 102 through the first via structure 107, and the conductive connection layer 104 is electrically connected to the first end 103a of the second common electrode bus 103 through the second via structure 108. For example, the second via structure 108 is only provided at the positions corresponding to the first end 103a and the branch 102b. It should be noted that a via structure is also provided at the position corresponding to the first end 103a and the end 102a' of the main body. The size, shape, distribution density, etc. of the via structure at this position may be different from the second via structure 108. For example, the maximum size of the via structure at the position corresponding to the first end 103a and the end 102a' of the main body on the main surface parallel to the substrate 101 is greater than the maximum size of the second via structure 108, and the distribution density is less than the distribution density of the second via structure 108.

[0046] For example, in Figure 2In the structure shown, the display panel 100 further includes a third common electrode bus 126 disposed opposite to the first common electrode bus 102 in the second direction Y. The third common electrode bus 126 is parallel to the main body 102a of the first common electrode bus 102 and is disposed on the same layer as the first common electrode bus 102. Second common electrode buses 103 are disposed on the left and right sides of the first common electrode bus 102 and the third common electrode bus 126. The first common electrode bus 102, the third common electrode bus 126, and the two second common electrode buses 103 are all located in the peripheral area 106. The two second common electrode buses 103, the first common electrode bus 102, and the third common electrode bus 126 surround the display area 105, forming a structure surrounding the display area 105. On the side of the third common electrode bus 126 away from the display area 105, and along a direction from the position close to the display area 105 to the position away from the display area 105, an anti-static structure 110 and an electrostatic discharge line 111 are sequentially disposed.

[0047] For example, such as Figure 2 As shown, on the side of the first common electrode bus 102 away from the display area 105, an anti-static structure 110 and a fan-out area 109 are sequentially provided in a direction from the position close to the display area 105 to the position away from the display area 105. The fan-out area 109 is configured to apply touch signals and / or display signals to the display area. For example, only at the two ends 102a' of the main body of the first common electrode bus 102 are branch portions 107 extending away from the display area 105. These branch portions 107 are where current converges, and the heat generated at these locations is significant, so it is necessary to position the branch portions 107 away from the display area 105. No branch portions 107 are provided at the ends of the third common electrode bus 126.

[0048] For example, such as Figure 2 As shown, a gate driving circuit 114 is provided on the side of the second common electrode bus 103 on the left, away from the display area 105, and a gate driving circuit 114 is also provided on the side of the second common electrode bus 103 on the right, away from the display area 105. The gate driving circuit 114 can apply a scan signal to the gate line. The display panel 100 also includes a common electrode line 115 extending from the display area 105, which is electrically connected to the second common electrode bus 103 and the conductive connection layer 104.

[0049] For example, the structural design of the display panel 100 allows the branch portion 107 to be positioned further away from the display area 105, thereby providing a larger area on the branch portion 107 where more via structures can be installed. This increases the number of first via structures 107 and second via structures 108, reducing resistance in the circuit structure and preventing the first via structures 107 and 108 from burning out, which would reduce the product yield and shorten the lifespan of the display panel 100. Furthermore, when the display panel is a liquid crystal display panel, positioning the first via structures 107 and 108 further away from the display area 105 also prevents the heat dissipated from the first via structures 107 and 108 from raising the temperature of the liquid crystal layer in the display area of ​​the liquid crystal display panel, thus avoiding the need for liquid crystal clearing.

[0050] For example, such as Figure 2 As shown, the minimum distance between the first via structure 107 and the second via structure 108 and the display area 105 is greater than 500 micrometers. In some examples, the minimum distance between the first via structure 107 and the display area 105 may be equal to the minimum distance between the second via structure 108 and the display area 105; the minimum distance between the first via structure 107 and the display area 105 may be greater than the minimum distance between the second via structure 108 and the display area 105; or the minimum distance between the first via structure 107 and the display area 105 may be less than the minimum distance between the second via structure 108 and the display area 105. The embodiments of this disclosure do not limit this. Figure 2 In the structure shown, the minimum distance D between the first via structure 107 and the display area 105 is less than the minimum distance between the second via structure 108 and the display area 105, and the minimum distance D between the first via structure 107 and the display area 105 is greater than 500 micrometers. This distance setting can avoid the problem that the heat emitted from the first via structure 107 and the second via structure 108 will cause the temperature of the liquid crystal layer in the display area of ​​the liquid crystal display panel to rise, thereby achieving the clearing point of the liquid crystal and causing a decrease in display quality.

[0051] For example, such as Figure 2 As shown, on a plane parallel to the main surface of the substrate 101, the branch 107 includes at least a first bend 112 away from the display area 105, and the orthographic projection of the first via structure 107 on the substrate 101 and the orthographic projection of the first bend 112 on the substrate 101 at least partially overlap. Figure 2In the structure shown, the branch 107 is the first bend 112 as a whole, excluding other structures. Of course, the branch 107 may also include other structures. For example, the branch 107 may also include more bends or elongated sections extending from the first bend 112 to the side away from the display area 105. The embodiments disclosed herein are not limited to this.

[0052] For example, such as Figure 2 As shown, on a plane parallel to the main surface of the substrate 101, the first end portion 103a extends into the opening region 113 defined by the first bend portion 112, and the orthographic projection of the second via structure 108 on the substrate 101 and the orthographic projection of the first end portion 103a on the substrate 101 at least partially overlap, that is, the orthographic projection of the first end portion 103a on the substrate 101 can overlap with all the orthographic projections of the second via structure 108 on the substrate 101, or it can overlap with a portion of the orthographic projections of the second via structure 108 on the substrate 101.

[0053] For example, such as Figure 2 As shown, on a plane parallel to the main surface of the substrate 101, the main body 102a of the first common electrode bus 102 is disposed in a direction parallel to the first direction X, that is, in Figure 2 The main body 102a of the first common electrode bus 102 extends laterally. A plurality of third via structures 116 are provided on the main body 102a, and the main body 102a is electrically connected to the conductive connection layer 104 through the plurality of third via structures 116.

[0054] It should be noted that the main body 102a has multiple parallel branches. Although the multiple third via structures 116 are close to the display area 105, the resistance of the multiple parallel branches is very small, and the current does not converge here, so the heat generated is very small and will not affect the display of the display area.

[0055] For example, Figure 3 This is a magnified planar structural diagram of a first bent portion provided in at least one embodiment of the present disclosure, as shown below. Figure 3As shown, the first bending portion 112 includes a first sub-bending portion 112a extending along the second direction Y and a second sub-bending portion 112b extending along the first direction X towards the side near the second common electrode bus 103. The overall planar shape of the first sub-bending portion 112a and the second sub-bending portion 112b is "L" shaped. The extension direction of the second common electrode bus 103 is parallel to the second direction Y. The orthographic projection of the first sub-bending portion 112a on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 overlap, and the orthographic projection of the second sub-bending portion 112b on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 also overlap. The overall shape of the first via structure 107 is also "L" shaped. Figure 3 In the structure shown, the orthographic projection of a portion of the first sub-bent portion 112a onto the substrate 101 overlaps with the orthographic projection of the first via structure 107 onto the substrate 101. Similarly, the orthographic projection of a portion of the second sub-bent portion 112b onto the substrate 101 overlaps with the orthographic projection of the first via structure 107 onto the substrate 101. The orthographic projection of a portion of the first end portion 103a onto the substrate 101 overlaps with the orthographic projection of the second via structure 108 onto the substrate 101. The structure of the first bend portion 112 is simple and can meet the requirements for a plurality of first via structures 107 and a plurality of second via structures 108, simplifying the manufacturing process. Furthermore, this design allows for the presence of first via structures 107 on both the first sub-bent portion 112a and the second sub-bent portion 112b, ensuring that the first via structures 107 corresponding to the second and second via structures 108 are distributed as evenly as possible, thereby making the connection between the second common electrode bus 103 and the first common electrode bus 102 more stable.

[0056] For example, although in Figure 3 In the structure shown, the orthographic projection of the conductive connection layer 104 on the substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the substrate 101. However, in the actual product, the conductive connection layer 104 is arranged around the display area 105. That is, the orthographic projection of the conductive connection layer 104 on the substrate 101 covers the orthographic projection of the first common electrode bus 102 on the substrate 101, the orthographic projection of the third common electrode bus 126 on the substrate 101, and the orthographic projections of the two second common electrode buses 103 on the substrate 101.

[0057] For example, Figure 4 This is an enlarged planar structural schematic diagram of another first bending portion provided in at least one embodiment of the present disclosure, as shown below. Figure 4As shown, the first bending portion 112 includes a first sub-bending portion 112a extending along the second direction Y and a second sub-bending portion 112b extending along the first direction X towards the side near the second common electrode bus 103. The overall planar shape of the first sub-bending portion 112a and the second sub-bending portion 112b is "L" shaped. The extension direction of the second common electrode bus 103 is parallel to the second direction Y. The orthographic projection of the first sub-bending portion 112a on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 have an overlapping portion, while the orthographic projection of the second sub-bending portion 112b on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 do not have an overlapping portion. The overall shape of the arrangement of the first via structure 107 is also linear, and the linear arrangement of the first via structure 107 and the linear arrangement of the second via structure 108 are directly opposite each other. The linear arrangement of the first via structure 107 and the linear arrangement of the second via structure 108, while meeting the requirement for the number of multiple first via structures 107 and multiple second via structures 108, also simplifies the process of forming the first via structure 107 and allows the width of the second sub-bent portion 112b in the second direction Y to be set as small as possible, thereby reducing the width of the lower border and making the lower border narrower.

[0058] For example, although in Figure 4 In the structure shown, the orthographic projection of the conductive connection layer 104 on the substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the substrate 101. However, in the actual product, the conductive connection layer 104 is arranged around the display area 105. That is, the orthographic projection of the conductive connection layer 104 on the substrate 101 covers the orthographic projection of the first common electrode bus 102 on the substrate 101, the orthographic projection of the third common electrode bus 126 on the substrate 101, and the orthographic projections of the two second common electrode buses 103 on the substrate 101.

[0059] For example, Figure 5 This is an enlarged planar structural schematic diagram of another first bent portion provided in at least one embodiment of the present disclosure, as shown below. Figure 5As shown, the first bending portion 112 includes a first sub-bending portion 112a extending along the second direction Y and a second sub-bending portion 112b extending along the first direction X towards the side near the second common electrode bus 103. The overall planar shape of the first sub-bending portion 112a and the second sub-bending portion 112b is "L" shaped. The extension direction of the second common electrode bus 103 is parallel to the second direction Y. The orthographic projection of the first sub-bending portion 112a on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 do not overlap, while the orthographic projection of the second sub-bending portion 112b on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 do overlap. The structure of the first bending portion 112 is simple, and it can meet the requirements of multiple first via structures 107 and multiple second via structures 108, thus simplifying the manufacturing process. Furthermore, this design allows the first via structure 107 to be present only on the second sub-bend portion 112b, thereby increasing the distance between the first via structure 107 and the display area 105, and thus reducing the impact of heat dissipated from the first via structure 107 on the display area 105.

[0060] For example, although in Figure 5 In the structure shown, the orthographic projection of the conductive connection layer 104 on the substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the substrate 101. However, in the actual product, the conductive connection layer 104 is arranged around the display area 105. That is, the orthographic projection of the conductive connection layer 104 on the substrate 101 covers the orthographic projection of the first common electrode bus 102 on the substrate 101, the orthographic projection of the third common electrode bus 126 on the substrate 101, and the orthographic projections of the two second common electrode buses 103 on the substrate 101.

[0061] For example, Figure 6 This is a schematic diagram of an enlarged planar structure of a branch provided in at least one embodiment of the present disclosure, as shown below. Figure 6As shown, on a plane parallel to the main surface of the substrate 101, the branch 107 includes a first bent portion 112 away from the display area 105 and a second bent portion 113 away from the display area 105. The first bent portion 112 includes a first sub-bent portion 112a extending along the second direction Y and a second sub-bent portion 112b extending along the first direction X towards the side near the second common electrode bus 103. The overall planar shape of the first sub-bent portion 112a and the second sub-bent portion 112b is "L". The second bend 113 includes a third sub-bend 113a extending along the second direction Y and a fourth sub-bend 113b extending along the first direction X. The second sub-bend 112b and the fourth sub-bend 113b are connected so that the overall shape of the first bend 112 and the second bend 113 is "U". The extension direction of the second common electrode bus 103 is parallel to the second direction Y, and the second common electrode bus 103 extends into the opening of the "U". It should be noted that... Figure 6 The edges of the second sub-bend portion 112b and the fourth sub-bend portion 113b shown are right-angled. Although the shape of the final branch is not strictly "U", it can be equivalent to "U". In another example, the edges of the second sub-bend portion 112b and the fourth sub-bend portion 113b can also be arc-shaped so that the cross-sectional shape of the final branch is "U".

[0062] For example, such as Figure 6 As shown, the orthographic projection of a portion of the first sub-bending portion 112a on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101. The orthographic projection of a portion of the second sub-bending portion 112b on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101. The orthographic projection of the third sub-bending portion 113a on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101. The orthographic projection of the fourth sub-bending portion 113b on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101. This makes the arrangement shape of the first via structure 107 also "U" shaped, so that the first end 103a of the second common electrode bus 103 is connected to the first common electrode bus 102 at as many positions as possible.

[0063] For example, such as Figure 6As shown, the orthographic projection of a portion of the first end 103a of the second common electrode bus 103 on the substrate 101 overlaps with the orthographic projection of the second via structure 108 on the substrate 101. This structure allows the first via structure 107 to be provided at the corresponding positions of the first sub-bend portion 112a and the third sub-bend portion 113a of the "U"-shaped branch. The first sub-bend portion 112a is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104, and the third sub-bend portion 113a is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. This allows the first end 103a of the second common electrode bus 103 to be electrically connected to both the first sub-bend portion 112a and the third sub-bend portion 113a, thereby forming more parallel circuits and further reducing resistance to reduce heat dissipation. This structure provides first via structures 107 at corresponding positions of the second sub-bend portion 112b and the fourth sub-bend portion 113b at the bottom of the "U" shape. The second sub-bend portion 112b is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. The fourth sub-bend portion 113b is also electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. This allows the first end 103a of the second common electrode bus 103 to also be electrically connected to the second sub-bend portion 112b and the fourth sub-bend portion 113b, resulting in more parallel circuits and further reducing resistance to further reduce heat dissipation.

[0064] For example, although in Figure 6 In the illustrated structure, the orthographic projection of the conductive connection layer 104 on the substrate 101 overlaps with the orthographic projection of a portion of the second common electrode bus 103 on the substrate 101. However, in actual products, the conductive connection layer 104 is arranged around the perimeter of the display area 105, meaning the orthographic projection of the conductive connection layer 104 on the substrate 101 covers the orthographic projections of the first common electrode bus 102, the third common electrode bus 126, and the two second common electrode buses 103 on the substrate 101. For example, Figure 7 This is a schematic diagram of an enlarged planar structure of another branch provided in at least one embodiment of the present disclosure, as shown below. Figure 7As shown, the orthographic projection of a portion of the first sub-bending portion 112a on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101; the orthographic projection of a portion of the second sub-bending portion 112b on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101; the orthographic projection of the third sub-bending portion 113a on the substrate 101 overlaps with the orthographic projection of the first via structure 107 on the substrate 101; and the orthographic projection of the fourth sub-bending portion 113b on the substrate 101 does not overlap with the orthographic projection of the first via structure 107 on the substrate 101. The first sub-bend portion 112a is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. The third sub-bend portion 113a is also electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. This allows the first end 103a of the second common electrode bus 103 to be electrically connected to both the first sub-bend portion 112a and the third sub-bend portion 113a, resulting in more parallel circuits and further reducing resistance to decrease heat dissipation. This structure also includes a first via structure 107 at the position corresponding to the second sub-bend portion 112b at the bottom of the "U" shape. The second sub-bend portion 112b is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. However, the fourth sub-bend portion 113b does not have the first via structure 107. This allows the first via structure 107 to be provided at all positions of the "U"-shaped structure that are directly opposite the first end 103a of the second common electrode bus 103. Furthermore, while ensuring the required number of first via structures 107 is met, the first via structure 107 can be omitted as much as possible at positions that are not directly opposite the first end 103a of the second common electrode bus 103, i.e., on the fourth sub-bend portion 113b, to simplify the process.

[0065] For example, although in Figure 7 In the structure shown, the orthographic projection of the conductive connection layer 104 on the substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the substrate 101. However, in the actual product, the conductive connection layer 104 is arranged around the display area 105. That is, the orthographic projection of the conductive connection layer 104 on the substrate 101 covers the orthographic projection of the first common electrode bus 102 on the substrate 101, the orthographic projection of the third common electrode bus 126 on the substrate 101, and the orthographic projections of the two second common electrode buses 103 on the substrate 101.

[0066] For example, Figure 8This is a schematic diagram of an enlarged planar structure of a branch provided in at least one embodiment of the present disclosure, as shown below. Figure 8 As shown, the orthographic projection of a portion of the first sub-bending portion 112a on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 do not overlap; the orthographic projection of the second sub-bending portion 112b on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 do not overlap; the orthographic projection of the third sub-bending portion 113a on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 overlap; and the orthographic projection of the fourth sub-bending portion 113b on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 overlap. The third sub-bend portion 113a is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. The fourth sub-bend portion 113b is electrically connected to the first end 103a of the second common electrode bus 103 through the first via structure 107 and the conductive connection layer 104. This allows the first end 103a of the second common electrode bus 103 to be electrically connected to both the third sub-bend portion 113a and the fourth sub-bend portion 113b, resulting in more parallel circuits and further reducing resistance to decrease heat dissipation. Furthermore, the third and fourth sub-bend portions 113a and 113b are farther from the display area 105. The first via structure 107 on the third and fourth sub-bend portions 113a and 113b can further reduce the impact of heat dissipated from the first via structure 107 on the display area 105.

[0067] For example, although in Figure 8 In the structure shown, the orthographic projection of the conductive connection layer 104 on the substrate 101 overlaps with the orthographic projection of part of the second common electrode bus 103 on the substrate 101. However, in the actual product, the conductive connection layer 104 is arranged around the display area 105. That is, the orthographic projection of the conductive connection layer 104 on the substrate 101 covers the orthographic projection of the first common electrode bus 102 on the substrate 101, the orthographic projection of the third common electrode bus 126 on the substrate 101, and the orthographic projections of the two second common electrode buses 103 on the substrate 101.

[0068] It should be noted that, in other examples, the orthographic projections of a portion of the first sub-bent portion 112a on the substrate 101 and the orthographic projections of the first via structure 107 on the substrate 101 may overlap; the orthographic projections of a portion of the second sub-bent portion 112b on the substrate 101 and the orthographic projections of the first via structure 107 on the substrate 101 may not overlap; the orthographic projections of the third sub-bent portion 113a on the substrate 101 and the orthographic projections of the first via structure 107 on the substrate 101 may overlap; and the orthographic projections of the fourth sub-bent portion 113b on the substrate 101 and the orthographic projections of the first via structure 107 on the substrate 101 may not overlap. Alternatively, the orthographic projection of a portion of the first sub-bending portion 112a on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 may not overlap; the orthographic projection of a portion of the second sub-bending portion 112b on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 may overlap; the orthographic projection of the third sub-bending portion 113a on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 may overlap; and the orthographic projection of the fourth sub-bending portion 113b on the substrate 101 and the orthographic projection of the first via structure 107 on the substrate 101 may not overlap. The embodiments disclosed herein are not limited in this respect.

[0069] For example, combining Figures 2-8 As shown, there are multiple first via structures 107 and multiple second via structures 108, and the total number of first via structures 107 and second via structures 108 is greater than or equal to 150. This design of the number of first via structures 107 and second via structures 108 ensures that the heat generated by professional e-sports monitors at high refresh rates such as 240Hz or 480Hz will not affect the normal display of the display panel.

[0070] It should be noted that, in Figures 2-8 The structure shown only shows a portion of the first via structure 107 and the second via structure 108; a large number of the first via structures 107 and the second via structures 108 are omitted.

[0071] For example, combining Figures 2-8As shown, the first via structure 107 and the second via structure 108 are arranged in a matrix, with the first direction X being the row direction and the second direction Y being the column direction. Along the first direction X, the sum of the number of the first via structure 107 and the second via structure 108 in a row is greater than or equal to 15, and along the second direction Y, the sum of the number of the first via structure 107 and the second via structure 108 in a column is greater than or equal to 10. Furthermore, the sum of the number of the first via structure 107 and the second via structure 108 in a row along the first direction X is greater than the sum of the number of the first via structure 107 and the second via structure 108 in a column along the second direction Y. For example, in one example, the sum of the number of first via structures 107 and second via structures 108 in each row is greater than or equal to 1.5 times the sum of the number of first via structures 107 and second via structures 108 in each column. This allows the sum of the number of first via structures 107 and second via structures 108 to reach 150, and the first via structures 107 and second via structures 108 to be evenly arranged, minimizing the resistance of the parallel circuit and thus minimizing heat dissipation. Furthermore, this design allows for a narrower width of the conductive connection layer 104 in the second direction Y, reducing the distance between the lower edge of the conductive connection layer 104 furthest from the display area 105 and the display area 105, thereby reducing the width of the lower bezel and making it narrower.

[0072] For example, combining Figures 2-8As shown, the first via structure 107 and the second via structure 108 are arranged in a matrix, with the first direction X being the row direction and the second direction Y being the column direction. Along the first direction X, the sum of the number of the first via structure 107 and the second via structure 108 in a row is greater than or equal to 10, and along the second direction Y, the sum of the number of the first via structure 107 and the second via structure 108 in a column is greater than or equal to 15. Furthermore, the sum of the number of the first via structure 107 and the second via structure 108 in a row along the first direction X is less than the sum of the number of the first via structure 107 and the second via structure 108 in a column along the second direction Y. For example, in one example, the sum of the number of first via structures 107 and second via structures 108 in each column is greater than or equal to 1.5 times the sum of the number of first via structures 107 and second via structures 108 in each row. This allows the sum of the number of first via structures 107 and second via structures 108 to reach 150, and the first via structures 107 and second via structures 108 to be evenly arranged, minimizing the resistance of the parallel circuit and thus minimizing heat dissipation. Furthermore, this design allows for a narrower width of the conductive connection layer 104 in the first direction X, reducing the distance between the edges of the left and right portions of the conductive connection layer 104 furthest from the display area 105 and the display area 105, thereby reducing the width of the left and right bezels and making them narrower.

[0073] For example, Figure 9 A circuit diagram of a display panel at a first via structure and a second via structure, provided for at least one embodiment of this disclosure, is shown below. Figure 9 As shown, R0 corresponds to the resistance of the conductive interconnect layer 104, R1 corresponds to the resistance of the first via structure 107 connecting the conductive interconnect layer 104 and the first common electrode bus 102, R2 corresponds to the resistance of the second via structure 108 connecting the conductive interconnect layer 104 and the second common electrode bus 103, and C1 corresponds to the resistance of the conductive interconnect layer 104 and the gate ( Figure 10 The coupling capacitance between the conductive connection layer 104 and the source / drain electrode layer (shown in the figure) is C2, which corresponds to the coupling capacitance between the conductive connection layer 104 and the source / drain electrode layer (shown in the figure). Figure 10 The coupling capacitance between the gate and source / drain electrode layers is shown in the figure. C0 corresponds to the coupling capacitance between the gate and source / drain electrode layers. Although only three resistors R0, R1 and R2 and three capacitors C0, C1 and C2 are shown, the number of resistors and capacitors can be more in the embodiments of this disclosure. The more circuits are connected in parallel, the smaller the final resistance and the less heat dissipated by the entire circuit.

[0074] For example, in one example, assuming the current is I at a frequency of 60Hz, and the heat at a frequency of 480Hz is 8 times that at 60Hz, and R1 equals R2, the resistance of the conductive connection layer 104 between adjacent first via structures, between adjacent first via structures and second via structures, or between adjacent second via structures and second via structures is 30 ohms, which is the resistance value of R0. The simulated resistance value of a 6μm*6μm via is about 80 ohms. At a frequency of 60Hz, in the arrangement of the first and second via structures with a 10*10 configuration, the three capacitors C0, C1, and C2 can be ignored, and the simulated combined resistance of 10*10 6μm*6μm vias of the same size is approximately 40 ohms. In the arrangement of the first and second via structures with a 10*30 configuration, the three capacitors C0, C1, and C2 can also be ignored, and the simulated combined resistance of 10*30 6μm*6μm vias of the same size is approximately 16 ohms, a reduction of 2.5 times. At a frequency of 480Hz, in the arrangement diagrams of the first and second via structures with a 10*10 configuration, the three capacitors C0, C1, and C2 can be ignored, and the simulated value of the combined resistance of 10*10 6μm*6μm vias of the same size is approximately 320 ohms. In the arrangement diagrams of the first and second via structures with a 10*30 configuration, the three capacitors C0, C1, and C2 can be ignored, and the simulated value of the combined resistance of 10*30 6μm*6μm vias of the same size is approximately 128 ohms.

[0075] For example, in a comparative example, assuming the current is I at a frequency of 60Hz, and the heat at a frequency of 165Hz is 2.75 times that at 60Hz, with R1 equal to R2 and both R1 and R2 being 400 ohms, the resistance of the conductive connection layer 104 between adjacent first via structures, between adjacent first and second via structures, or between adjacent first and second via structures is 30 ohms, which is the resistance value of R0. The simulated resistance of a 24μm*24μm via is approximately 400 ohms. In a 2*2 arrangement of first and second via structures at a frequency of 60Hz, the three capacitors C0, C1, and C2 can be ignored, and the simulated combined resistance of two 24μm*24μm vias of the same size is approximately 130 ohms. In the 2*2 arrangement of the first and second via structures at a frequency of 165Hz, the three capacitors C0, C1 and C2 can be ignored. The simulated combined resistance of the two 24μm*24μm vias of the same size is about 357.5 ohms.

[0076] As can be seen from the above examples, the resistance R1 of the first via structure with a size of 24μm*24μm is 5 times that of the first via structure with a size of 6μm*6μm, and the resistance R2 of the second via structure with a size of 24μm*24μm is 5 times that of the second via structure with a size of 6μm*6μm. The 6μm*6μm via size is the smallest size that can be achieved by current in-house equipment. In some embodiments of this disclosure, 6μm*6μm vias are selected, and the smaller the size of the first via structure 107 and the second via structure 108, the smaller the corresponding resistances R1 and R2.

[0077] For example, combining Figures 2-8 The maximum size of the first via structure 107 and the second via structure 108 on the main board surface parallel to the substrate 101 ranges from 4 micrometers to 6 micrometers. For example, in one example, the first via structure 107 and the second via structure 108 have the same planar shape; both are rectangles of the same size, with the longer side of the rectangle having a dimension of 4 micrometers to 6 micrometers. In another example, the first via structure 107 and the second via structure 108 have the same planar shape, both being rectangles, but the dimensions of the planar shapes of the first via structure 107 and the second via structure 108 are different; the longer side of the rectangle corresponding to the first via structure 107 and the second via structure 108 has a dimension of 4 micrometers to 6 micrometers. In another example, the first via structure 107 and the second via structure 108 have the same planar shape, both being circular. However, the dimensions of the planar shapes of the first via structure 107 and the second via structure 108 are different. The diameter of the larger circular shape corresponding to the first via structure 107 and the second via structure 108 is 4 micrometers to 6 micrometers. In yet another example, the first via structure 107 and the second via structure 108 have the same planar shape, both being elliptical. However, the dimensions of the planar shapes of the first via structure 107 and the second via structure 108 are different. The major axis of the larger elliptical shape corresponding to the first via structure 107 and the second via structure 108 is 4 micrometers to 6 micrometers. The planar shapes of the first via structure 107 and the second via structure 108 can also be other shapes. For other shapes, comparisons are made according to similar rules, and the embodiments of this disclosure are not limited in this regard.

[0078] For example, combined with Figure 2On the main board surface parallel to the substrate 101, the planar shape of the third via structure 116 may be the same as or different from the planar shapes of the first via structure 107 and the second via structure 108. The maximum size of the planar shape of the third via structure 116 is greater than the maximum size of the planar shape of the first via structure 107 and also greater than the maximum size of the planar shape of the second via structure 108.

[0079] For example, Figure 10 This is a schematic cross-sectional view of a display panel provided in at least one embodiment of the present disclosure, as shown below. Figure 10 As shown, the display panel 100 also includes a thin-film transistor 117 and a first electrode 118 disposed on the substrate 101 and in the display area 105. The thin-film transistor 117 includes a gate 119, an active layer 120 and a source / drain electrode layer 121 stacked together. The source / drain electrode layer 121 includes a source electrode 121a and a drain electrode 121b disposed opposite to each other. A first common electrode bus 102 is disposed on the same layer as the gate 119. A second common electrode bus 103 is disposed on the same layer as the source electrode 121a and the drain electrode 121b. The conductive connection layer 104 is disposed on the same layer as the first electrode 118 and spaced apart from each other. The first electrode 118 is electrically connected to the drain electrode 121b through a fourth via structure 122.

[0080] For example, the thin-film transistor 117 can be a top-gate thin-film transistor, a bottom-gate thin-film transistor, or a dual-gate thin-film transistor, and the embodiments disclosed herein are not limited to this.

[0081] For example, in embodiments of this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same mask to form a single patterning process. Depending on the specific pattern, the sequential patterning process may include multiple exposure, development, or etching processes, and the specific pattern formed in the same layer may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0082] For example, such as Figure 10 As shown, a gate insulating layer 123 is provided on the side of the gate 119 away from the substrate 101, and a passivation layer 124 is provided on the side of the source / drain electrode layer 121 away from the substrate 101. A first via structure 107 passes through the passivation layer 124 and the gate insulating layer 123 in sequence, and a second via structure 108 and a fourth via structure 122 both pass through the passivation layer 124.

[0083] For example, combining Figure 2On a plane parallel to the main surface of the substrate 101, and in a display panel, the second common electrode bus 103 is configured as two, and the two second common electrode buses 103 are disposed opposite each other on both sides of the main body portion 102a of the first common electrode bus 102 along the first direction X. The display panel 100 also includes a fourth common electrode bus 125 disposed on the side of the third common electrode bus 126 away from the display area 105. The main body portion of the fourth common electrode bus 125 is parallel to the main body portion 102a of the first common electrode bus 102, and the fourth common electrode bus 125 and the first common electrode bus 102 are disposed on the same layer. Two second common electrode buses 103 respectively include a second end 103b and a third end 103c that are away from the first common electrode bus 102 in the first direction X. The conductive connection layer 104 is electrically connected to the second end 103b and the third end 103c through a fifth via structure 127. The fourth common electrode bus 125 includes a fourth end 125a opposite to the second end 103b and a fifth end 125b opposite to the third end 103c. The conductive connection layer 104 is electrically connected to the fourth end 125a and the fifth end 125b through a sixth via structure 128.

[0084] For example, such as Figure 2 As shown, the fourth common electrode bus 125 is disposed on the side of the electrostatic discharge line 111 away from the display area 105. The fourth common electrode bus 125, the third common electrode bus 126, and the second common electrode bus 103 are electrically connected through the conductive connection layer 104.

[0085] For example, combining Figure 2 The middle portion of the third common electrode bus 126 located at its two ends is electrically connected to the conductive connection layer 104 through the seventh via structure 129. The arrangement density, planar shape and size of the seventh via structure 129 can be the same as those of the third via structure 116, and will not be described in detail here.

[0086] At least one embodiment of this disclosure also provides a display device, which includes the display panel of any of the above embodiments. Since the display device includes the display panel of any of the above embodiments, the structural design of the display device can also allow the branches to be positioned further away from the display area, thereby allowing for a larger area on the branches to accommodate more via structures. This increases the number of first and second via structures, reducing the resistance in the circuit structure and preventing the first and second via structures from burning out, which would reduce the product yield and shorten the lifespan of the display device. Furthermore, when the display device is a liquid crystal display (LCD), positioning the first and second via structures far from the display area can also prevent the heat dissipated from the first and second via structures from raising the temperature of the liquid crystal layer in the display area of ​​the LCD panel, thus avoiding the problem of liquid crystal clearing. In other words, the resistance at the conductive connection layer bridging points in the display device is low, and the heat generation is low, resulting in better product performance and display effect.

[0087] For example, the display device can be a liquid crystal display device, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, or any other product or component with display function. The embodiments disclosed herein do not limit this.

[0088] The display panel and display device provided in at least one embodiment of this disclosure have at least one of the following beneficial technical effects:

[0089] (1) In the display panel provided by at least one embodiment of the present disclosure, in the peripheral area, the conductive connection layer is connected through a branch of the first via structure and the first common electrode bus, and the conductive connection layer is electrically connected through the first end of the second via structure and the second common electrode bus. This can increase the number of the first via structure and the second via structure, reduce the resistance in the circuit structure, and avoid the problem that the first via structure and the second via structure are burned out, resulting in a decrease in the product yield of the display panel and a short life of the display panel.

[0090] (2) The display panel provided in at least one embodiment of the present disclosure, when the display panel is a liquid crystal display panel, sets the first via structure and the second via structure far away from the display area, which can also avoid the problem that the heat emitted from the first via structure and the second via structure causes the temperature of the liquid crystal layer in the display area of ​​the liquid crystal display panel to rise, thereby achieving the clearing point of the liquid crystal.

[0091] The following points need to be explained:

[0092] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0093] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0094] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0095] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A display panel, comprising: A substrate, including a display area and a peripheral area surrounding the display area; In the surrounding area, a first common electrode bus, a second common electrode bus, and a conductive connection layer are stacked on the substrate, wherein, The first common electrode bus includes a main body and a branch extending from an end of the main body toward a side away from the display area. The main body extends along a first direction, and at least a portion of the branch connected to the main body extends along a second direction. The first direction and the second direction intersect. The second common electrode bus extends along the second direction toward the side away from the display area, with the first end of the second common electrode bus facing the end of the main body and the branch portion. In the surrounding area, the conductive connection layer is electrically connected to the branch of the first common electrode bus through a first via structure, and the conductive connection layer is electrically connected to the first end of the second common electrode bus through a second via structure. The orthographic projection of the first via structure on the substrate and the orthographic projection of the branch on the substrate at least partially overlap.

2. The display panel according to claim 1, wherein, On a plane parallel to the main surface of the substrate, the branch includes at least a first bend away from the display area, and the orthographic projection of the first via structure on the substrate and the orthographic projection of the first bend on the substrate at least partially overlap.

3. The display panel of claim 2, wherein, On a plane parallel to the main surface of the substrate, the first end extends into the opening region defined by the first bend, and the orthographic projection of the second via structure on the substrate and the orthographic projection of the first end on the substrate at least partially overlap.

4. The display panel according to claim 2, wherein, The first bending portion includes a first sub-bending portion extending along the second direction and a second sub-bending portion extending along the first direction toward a side close to the second common electrode bus. The extension direction of the second common electrode bus is parallel to the second direction. The orthographic projection of the first sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate have an overlapping portion, and the orthographic projection of the second sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate also have an overlapping portion.

5. The display panel according to claim 2, wherein, The first bending portion includes a first sub-bending portion extending along the second direction and a second sub-bending portion extending along the first direction toward a side close to the second common electrode bus. The extension direction of the second common electrode bus is parallel to the second direction. The orthographic projection of the first sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate have an overlapping portion, and the orthographic projection of the second sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate do not have an overlapping portion.

6. The display panel according to claim 2, wherein, The first bending portion includes a first sub-bending portion extending along the second direction and a second sub-bending portion extending along the first direction toward a side close to the second common electrode bus. The extension direction of the second common electrode bus is parallel to the second direction. The orthographic projection of the first sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate do not overlap, while the orthographic projection of the second sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate overlap.

7. The display panel according to any one of claims 4 to 6, wherein, On a plane parallel to the main surface of the substrate, the branch also includes a second bend away from the display area. The second bend includes a third sub-bend extending along the second direction and a fourth sub-bend extending along the first direction. The second sub-bend and the fourth sub-bend are connected so that the overall shape of the first bend and the second bend is "U"-shaped, and the second common electrode bus extends into the opening of the "U".

8. The display panel according to claim 7, wherein, The orthographic projection of the third sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate overlap, and the orthographic projection of the fourth sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate overlap.

9. The display panel according to claim 7, wherein, The orthographic projection of the third sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate overlap, while the orthographic projection of the fourth sub-bending portion on the substrate and the orthographic projection of the first via structure on the substrate do not overlap.

10. The display panel according to any one of claims 1 to 6, wherein, On a plane parallel to the main surface of the substrate, the main body of the first common electrode bus is disposed in a direction parallel to the first direction. A third via structure is disposed on the main body, and the main body is electrically connected to the conductive connection layer through the third via structure.

11. The display panel according to any one of claims 1 to 6, wherein, The minimum distance between the first via structure and the second via structure and the display area is greater than 500 micrometers.

12. The display panel according to any one of claims 1 to 6, wherein, The first via structure is configured in multiple ways, the second via structure is configured in multiple ways, and the total number of the first via structure and the second via structure is greater than or equal to 150.

13. The display panel according to claim 12, wherein, The first via structure and the second via structure are arranged in a matrix, with the first direction being the row direction and the second direction being the column direction. Along the first direction, the sum of the number of the first via structures and the second via structures in a row is greater than 15, and along the second direction, the sum of the number of the first via structures and the second via structures in a column is greater than 10. Furthermore, the sum of the number of the first via structures and the second via structures in a row along the first direction is greater than the sum of the number of the first via structures and the second via structures in a column along the second direction.

14. The display panel according to claim 12, wherein, The first via structure and the second via structure are arranged in a matrix, with the first direction being the row direction and the second direction being the column direction. Along the first direction, the sum of the number of the first via structures and the second via structures in a row is greater than 10, and along the second direction, the sum of the number of the first via structures and the second via structures in a column is greater than 15. Furthermore, along the first direction, the sum of the number of the first via structures and the second via structures in a row is less than the sum of the number of the first via structures and the second via structures in a column along the second direction.

15. The display panel according to any one of claims 1 to 6, wherein, The maximum size of the first via structure and the second via structure on the motherboard surface parallel to the substrate ranges from 4 micrometers to 6 micrometers.

16. The display panel according to any one of claims 1 to 6, further comprising: A thin-film transistor and a first electrode are disposed on the substrate and in the display area. The thin-film transistor includes a gate, an active layer and a source / drain electrode layer stacked together. The source / drain electrode layer includes a source and a drain disposed opposite to each other. A first common electrode bus and the gate are disposed on the same layer. A second common electrode bus, the source and the drain are disposed on the same layer. A conductive connection layer and the first electrode are disposed on the same layer and spaced apart from each other. The first electrode is electrically connected to the drain through a fourth via structure.

17. The display panel according to claim 16, wherein, A gate insulating layer is provided on the side of the gate away from the substrate, and a passivation layer is provided on the side of the source / drain electrode layer away from the substrate. The first via structure passes through the passivation layer and the gate insulating layer in sequence, and the second via structure and the fourth via structure both pass through the passivation layer.

18. The display panel according to claim 17, wherein, On a plane parallel to the main surface of the substrate, and in a display panel, the second common electrode bus is configured as two, and the two second common electrode buses are disposed opposite to each other on both sides of the main body portion of the first common electrode bus along the first direction; The display panel further includes a third common electrode bus disposed opposite to the first common electrode bus in the second direction. The third common electrode bus is parallel to the main body of the first common electrode bus and is disposed on the same layer as the first common electrode bus. Two second common electrode buses, the first common electrode bus and the third common electrode bus surround the display area. Two second common electrode buses are respectively included at a second end and a third end that are away from the first common electrode bus in the first direction, and the conductive connection layer is electrically connected to the second end and the third end through a fifth via structure; The third common electrode bus includes a fourth end opposite to the second end and a fifth end opposite to the third end, and the conductive connection layer is electrically connected to the fourth end and the fifth end through a sixth via structure.

19. The display panel according to claim 18, wherein, The portion of the third common electrode bus between the fourth end and the fifth end is electrically connected to the conductive connection layer via a seventh via structure.

20. A display device comprising a display panel according to any one of claims 1 to 19.

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