A method and system for synchronous sampling of a harmonic standard table

Abstract

The application belongs to the technical field of electric power measurement, and discloses a synchronous sampling method and system of a harmonic standard meter, the method comprising: acquiring analog voltage signals and analog current signals corresponding to the number of analog voltage signals to form multiple analog electric signals, and inputting the multiple analog electric signals into AD sampling modules corresponding to the multiple analog electric signals, and sending a synchronous sampling start signal to the AD sampling modules by a master MCU module; starting the AD sampling modules by starting conversion pins of the AD sampling modules to synchronously sample the multiple analog electric signals into digital electric signals; and inputting the sampled digital electric signals into the master MCU module by a transmission mode of direct register access DMA through a SPI communication bus. The application samples multiple harmonic signals by using the characteristics of the master MCU module multi-SP I-DMA channel interlocking type chain pointer, thereby improving the accuracy of harmonic electric energy measurement.

Description

Technical Field

[0001] This invention belongs to the field of power metering technology, specifically relating to a synchronous sampling method and system for a harmonic standard meter. Background Technology

[0002] The three-phase harmonic standard meter is a standardized instrument used for harmonic energy measurement. The electrical signals input to the three-phase harmonic standard meter include six electrical signals consisting of three voltage signals and three current signals. When measuring harmonic energy, the higher the synchronization of the voltage and current signal sampling and the higher the sampling frequency, the higher the measurement accuracy of the three-phase harmonic standard meter.

[0003] Currently, there are three sampling methods for three-phase harmonic standard meters: The first method is to use a multi-channel sampling chip to synchronously sample multiple signals, or to use two chips to synchronously sample voltage and current signals respectively; the second method is to use multiple analog circuits associated with a single-channel chip for synchronous sampling; the third method is to use a separate chip for each electrical signal to synchronously sample each electrical signal, for example, by combining a microprocessor with a programmable logic device and a digital signal processor to achieve synchronous sampling control and data processing.

[0004] However, synchronous sampling of harmonic standard meters using multi-channel and single-channel sampling chips suffers from time errors due to the cyclic operation of analog switches, and the sampling frequency is relatively low, failing to meet the high accuracy requirements of harmonic standard meters. While sampling methods combining microprocessors, programmable logic devices, and digital signal processors offer higher synchronization, their production costs are high, and the increased sampling frequency leads to a larger data volume, potentially causing data loss during transmission and processing. Therefore, ensuring that the sampling frequency of three-phase harmonic standard meters is increased without data loss, thereby improving the accuracy of harmonic energy metering, is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] This invention provides a synchronous sampling method and system for a harmonic standard meter, which solves the technical problem of how to improve the accuracy of harmonic energy metering.

[0006] In a first aspect, the present invention provides a synchronous sampling method for a harmonic standard table, the method comprising:

[0007] The system acquires analog voltage signals and analog current signals corresponding to the number of analog voltage signals to form multiple analog electrical signals, and inputs the multiple analog electrical signals into the AD sampling modules corresponding to each analog electrical signal. The main control MCU module sends a synchronous sampling start signal to each AD sampling module.

[0008] The start conversion pin of each AD sampling module starts the AD sampling module and synchronously samples the analog electrical signals into digital electrical signals.

[0009] The sampled digital electrical signals are input to the main control MCU module via the SPI communication bus using the direct register access DMA transfer mode.

[0010] Preferably, the start-up conversion pin of each AD sampling module starts the AD sampling module and synchronously samples the analog electrical signals into digital electrical signals, including:

[0011] The signal input unit in the AD sampling module synchronously samples each analog electrical signal into a digital electrical signal, and inputs each digital electrical signal to the signal receiving unit of the main control MCU module through the SPI communication bus;

[0012] The signal selection unit in the main control MCU module sends the synchronous sampling start signal to the start conversion pin of the AD sampling module, and at the same time sends the clock signal in the clock output unit to the clock input unit of the AD sampling module.

[0013] Preferably, the clock signal in the clock output unit is the main phase-locked loop clock signal.

[0014] Preferably, the start-up conversion pin of each AD sampling module starts the AD sampling module and synchronously samples the analog electrical signals into digital electrical signals, further comprising:

[0015] Connect the start-up conversion pin units of the analog voltage signal in the AD sampling module in parallel, and connect the start-up conversion pin units of the parallel analog voltage signal to the output pin unit of the first channel of the main control MCU timer;

[0016] Connect the start-up conversion pin units of the analog current signal in the AD sampling module in parallel, and connect the start-up conversion pin units of the parallel analog current signal to the output pin unit of the second channel of the main control MCU timer;

[0017] The outputs of the first channel and the second channel of the main control MCU timer are pulse width modulated, and the outputs of the first channel and the second channel of the main control MCU timer are pulse waveforms with the same frequency.

[0018] Preferably, the sampled digital electrical signals are input to the main control MCU module via the SPI communication bus using a direct register access (DMA) transfer method, including:

[0019] Create the receive buffer and transmit buffer for the first DMA channel, and initialize the target buffer address and source buffer address for the first DMA channel;

[0020] Configure the first DMA channel as a data transmission channel for the first digital electrical signal, and configure the trigger mode of the first DMA channel as an automatic event trigger mode;

[0021] The channels of the sampled N digital electrical signals are configured as an array of N chain pointer structures in a chained mode, and the data source address of the N chain pointer structures is configured as the starting address of the transmit buffer of the first channel of the DMA, where N represents the number of channels of digital electrical signals.

[0022] Configure data registers for the data target addresses of the N chain pointer structure arrays respectively, and set the corresponding bit of the status code of the data register to 1;

[0023] The storage structure of the array of N chain pointer structures of the first DMA channel is configured as a circular linked list storage structure, and the second DMA channel to the Mth DMA channel are configured as the data receiving channels of the sampled N digital electrical signals, where M = N + 1, and M represents the number of DMA channels.

[0024] Preferably, the method further includes: the DMA second channel to the DMA Mth channel buffers the received data in a dual-buffer mode.

[0025] Preferably, the DMA second channel to the DMA Mth channel buffer the received data using a dual-buffering mode, including:

[0026] Create a first and a second receive buffer for the DMA second channel to the DMA M channel, and create first and second index data for the chain pointer structure array of the DMA second channel to the DMA M channel;

[0027] Set the data source address register of the chain pointer structure array from the second DMA channel to the Mth DMA channel as the data address register of each channel of the SPI communication bus;

[0028] Set the data target address register of the first index data of the chain pointer structure array from the second DMA channel to the Mth DMA channel to the address of the second receive buffer, and set the chain pointer register to the starting address of the second index data;

[0029] Set the data target address register of the second index data of the chain pointer structure array from the second channel of DMA to the Mth channel of DMA to the address of the first receive buffer, and set the chain pointer register to the starting address of the first index data.

[0030] Secondly, the present invention also provides a synchronous sampling system for a harmonic standard meter, the system comprising an AD sampling module and a main control MCU module;

[0031] The AD sampling module is used to synchronously sample multiple analog electrical signals into digital electrical signals, and input the sampled digital electrical signals to the main control MCU module through each SPI communication bus in the direct register access DMA transmission mode.

[0032] The main control MCU module sends a synchronous sampling start signal to the start conversion pin of each AD sampling module;

[0033] The start-up conversion pin of each AD sampling module is used to start each AD sampling module to synchronously sample each analog electrical signal.

[0034] Preferably, the AD sampling module includes a signal input unit, a chip select unit, and a clock input unit, and the main control MCU module includes a signal receiving unit, a signal selection unit, and a clock output unit;

[0035] The signal input unit in the AD sampling module is used to synchronously sample each analog electrical signal into a digital electrical signal, and input each digital electrical signal to the signal receiving unit of the main control MCU module through the SPI communication bus;

[0036] The signal selection unit in the main control MCU module is used to send the synchronous sampling start signal to the start conversion pin unit of the AD sampling module;

[0037] The clock output unit in the main control MCU module is used to send the clock reference signal to the clock input unit of the AD sampling module.

[0038] Preferably, the timer channel of the main control MCU module includes a first timer channel and a second timer channel;

[0039] The analog voltage signal start-up conversion pin units in the AD sampling module are connected in parallel, and the parallel analog voltage signal start-up conversion pin units are connected to the output pin units of the first channel of the timer.

[0040] The analog current signal start-up conversion pin units in the AD sampling module are connected in parallel, and the parallel analog current signal start-up conversion pin units are connected to the output pin units of the second channel of the timer.

[0041] The outputs of the first channel and the second channel of the main control MCU timer are pulse width modulation outputs, and the first and second channels of the main control MCU timer output pulse waveforms of the same frequency.

[0042] Compared with the prior art, the present invention provides a synchronous sampling method and system for a harmonic standard meter. The sampled digital electrical signals from the AD sampling module are input to the main control MCU module through the SPI communication buses. The main control MCU module utilizes the interlocking chain pointer characteristic of multiple SPI-DMA channels to sample multiple harmonic signals. Furthermore, the DMA receiving channel adopts a double-buffered mode to buffer the received data, effectively ensuring the continuity and integrity of the synchronous sampling of each analog electrical signal by the AD sampling module within a calculation cycle, and further improving the accuracy of harmonic energy metering. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and not all embodiments. For those skilled in the art, other drawings obtained from these drawings without creative effort are all within the scope of protection of the present invention.

[0044] Figure 1 A flowchart illustrating a synchronous sampling method for a harmonic standard table provided in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram illustrating the data transmission process between an AD sampling module and a main control MCU module via DMA, as provided in an embodiment of the present invention.

[0046] Figure 3 This is a schematic diagram of a DMA dual-buffer mode for caching data, provided in an embodiment of the present invention.

[0047] Figure 4 A flowchart of a signal synchronization sampling method using the SPI-DAM dual-buffering method is provided for an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the hardware structure of a synchronous sampling system for a harmonic standard table provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram illustrating the connection between an AD sampling module and a main control MCU module according to an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the output of synchronous sampling electrical signals by various AD sampling modules provided in an embodiment of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0052] To provide a more detailed and complete description of the present invention, illustrative descriptions of its implementation methods and specific embodiments are provided below; however, these are not the only forms of implementing or utilizing the specific embodiments of the present invention. The implementation methods cover features of multiple specific embodiments, as well as the methods, steps, and their order for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and sequence of steps. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.

[0053] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0054] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The word "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" means two or more. Other quantifiers should be understood similarly. The preferred embodiments described herein are only for illustrating and explaining the present invention and are not intended to limit the present invention. Furthermore, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0055] To address the problem of improving the accuracy of harmonic energy metering, this invention provides a synchronous sampling method for harmonic standard meters. Please refer to... Figure 1 This is a flowchart illustrating a synchronous sampling method for a harmonic standard table provided in an embodiment of the present invention. The method specifically includes the following steps:

[0056] S101. Acquire analog voltage signals and analog current signals corresponding to the number of analog voltage signals to form multiple analog electrical signals, and input the multiple analog electrical signals into the AD sampling modules corresponding to each analog electrical signal, and the main control MCU module sends a synchronous sampling start signal to each AD sampling module.

[0057] Specifically, in this embodiment of the invention, a three-phase harmonic standard meter can be used to measure harmonic energy. The three analog voltage signals and three analog current signals from the three harmonic standard meters enter the AD sampling module. Each channel in the AD sampling module is an independent AD sampling chip. Each AD sampling module is connected to the main control MCU module via an SPI communication bus. The main control MCU module sends a synchronous sampling start signal to the start conversion pin of the six AD sampling modules to synchronously sample the analog electrical signals into digital electrical signals.

[0058] S102. The start-up conversion pin of each AD sampling module starts each AD sampling module, synchronously sampling each analog electrical signal into a digital electrical signal. Specifically, in this embodiment of the invention, the AD sampling module converts each analog electrical signal into a digital electrical signal, thereby performing digital signal processing, storage, and transmission.

[0059] S103. The sampled digital electrical signals are input to the main control MCU module via the SPI communication bus using the direct register access DMA transmission method.

[0060] Specifically, in this embodiment of the invention, the six independent AD sampling modules communicate with the main control MCU module through six independent SPI communication buses. The SPI communication buses employ a full-duplex communication mode, allowing simultaneous data transmission and reception, resulting in a high data transmission rate. The main control MCU module uses a pulse width modulation (PWM) sampling method to initiate a synchronous sampling start signal, enabling the six AD sampling modules to synchronously sample the six analog electrical signals. The frequency of the PWM wave is the frequency at which the AD sampling modules synchronously sample the six analog electrical signals in this embodiment. Furthermore, the AD sampling modules transmit data with the main control MCU module via Direct Register Access (DMA). During DMA data transmission, the MCU main control module can perform other tasks. The main processor's operation is only interrupted after the entire data block transmission is completed and the data needs to be processed, enabling the transmission of large amounts of data in a short time.

[0061] It should be noted that, in this embodiment of the invention, taking a 32-bit MCU chip with a main frequency of 240MHz and a core of ARM Cortex M4, and an 18-bit AD sampling chip with a conversion rate of 100kSPS and a model of SAR as examples, the hardware resources already meet the requirements for implementing this invention.

[0062] In this embodiment of the invention, the digital electrical signals in the AD sampling module are input to the main control MCU module through the SPI communication buses, which effectively ensures the continuity and integrity of the AD sampling module's synchronous sampling of the analog electrical signals within a calculation cycle, and further improves the accuracy of harmonic energy measurement.

[0063] In one implementation, the start-up conversion pin of each AD sampling module activates the AD sampling module to synchronously sample the analog electrical signals into digital electrical signals. This includes: the signal input unit in the AD sampling module synchronously samples the analog electrical signals into digital electrical signals and inputs the digital electrical signals to the signal receiving unit of the main control MCU module via the SPI communication bus; the signal selection unit in the main control MCU module sends the synchronous sampling start signal to the start-up conversion pin of the AD sampling module and simultaneously sends the clock signal from the clock output unit to the clock input unit of the AD sampling module. In this embodiment, when the main control MCU module and the AD sampling module communicate via the SPI communication bus, the MCU main control module acts as the master device to control the reception and transmission of the digital electrical signals, and the AD sampling module acts as the slave device to sample the analog electrical signals.

[0064] In one implementation, the clock signal in the clock output unit is the main phase-locked loop clock signal. In this embodiment of the invention, the clock signal of the clock output unit of the main control MCU module is configured as the main phase-locked loop clock signal PLLH, and each clock frequency is configured as a 64-fold frequency divider.

[0065] In one implementation, the start-up conversion pins of each AD sampling module activate each AD sampling module to synchronously sample the analog electrical signals into digital electrical signals. This further includes: connecting the start-up conversion pins of the analog voltage signals in the AD sampling modules in parallel, and connecting the parallel-connected start-up conversion pins of the analog voltage signals to the output pins of the first channel of the main control MCU timer; connecting the start-up conversion pins of the analog current signals in the AD sampling modules in parallel, and connecting the parallel-connected start-up conversion pins of the analog current signals to the output pins of the second channel of the main control MCU timer; the outputs of the first and second channels of the main control MCU timer are pulse-width modulated (PWM), and both output pulse waveforms have the same frequency. The output frequency of the PWM is configured to the required sampling frequency fs, and the width of the PWM is set according to the data conversion duration of the AD sampling chip in the AD sampling module.

[0066] In one implementation, the sampled digital electrical signals are isolated and input to the main control MCU module via the SPI communication bus using Direct Register Access (DMA) transmission. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 The present invention provides a schematic diagram of a data transmission process between an AD sampling module and a main control MCU module via DMA, which specifically includes the following steps:

[0067] S201. Create the receive buffer and transmit buffer of the first DMA channel, and initialize the target buffer address and source buffer address of the first DMA channel. Specifically, in this embodiment of the invention, the receive buffer of the first DMA channel is first created as RxBuf[1], the transmit buffer is created as TxBuf[1], the target buffer address of the first DMA channel is initialized as &RxBuf[0], and the source buffer address of the first DMA channel is &TxBuf[0].

[0068] S202. Configure the first DMA channel as a data transmission channel for a first electrical signal, and configure the trigger mode of the first DMA channel as an automatic event trigger mode. Specifically, in this embodiment of the invention, after creating the receive buffer and transmit buffer of the first DMA channel, the first DMA channel is configured as a data transmission channel for a first electrical signal, and the trigger mode of the first DMA channel is configured as the automatic event trigger mode AOS_SetTriggerEventSrc.

[0069] S203. Configure the channels of the sampled N digital electrical signals as an array of N chain pointer structures in a cascading mode, and configure the data source address of the N chain pointer structures as the starting address of the transmit buffer of the first channel of the DMA, where N represents the number of channels of the digital electrical signals. Specifically, a three-phase harmonic standard meter can be used to measure harmonic energy. The adopted digital electrical signals are 6 digital electrical signals. In this embodiment of the invention, the channels of the sampled 6 digital electrical signals can be configured as an array of 6 chain pointer structures in a cascading mode as stcLlpSesc[6]. The array length is 6, corresponding to a total of 6 channels of voltage and current. The structure includes a data source address register SARx, a data target address register DARx, a data control register DTCTLx, a chain pointer register LLPx, and a channel control register DMA_CHCTLx. In addition, the data source address SARx of stcLlpSesc[] of the six chain pointer structure arrays of the first channel of DMA1 is uniformly configured as the first address of the transmit buffer of the first channel of DMA1 &TxBuf[0], that is, they share a common transmit buffer. According to the DMA data transmission principle, the transmit channel of DMA sends a signal first, and then the receive channel of DMA starts to receive data from the SPI bus. Using the same first address of the transmit buffer can realize the synchronization of data reception of the six electrical signal channels.

[0070] S204. Configure data registers for the data target addresses of the N chain pointer structure arrays respectively, and set the corresponding bit of the status code of the data register to 1. Specifically, in this embodiment of the invention, the data target address DARx of the six chain pointer structure arrays stcLlpSesc[x] of the first DMA channel can be configured as &SPIx_UNIT->DR, where SPIx_UNIT->DR represents the data register of the x-th SPI channel, x = 1, 2, 3, 4, 5, 6. At the same time, write 1 to the corresponding bit of the data control register DTCTLx of the six chain pointer structure arrays stcLlpSesc[] of the first DMA channel.

[0071] S205. Configure the storage structure of the array of N chain pointer structures of the first DMA channel as a circular linked list storage structure, and configure the second DMA channel to the Mth DMA channel as the data receiving channels of the sampled N electrical signals, where M = N + 1, and M represents the number of DMA channels. Write the chain pointer register LLPx of the chain pointer structure array stcLlpSesc[0] of the first DMA channel to the first address of &stcLlpSesc[1], write the chain pointer register LLPx of stcLlpSesc[1] to the first address of &stcLlpSesc[2], and so on. Write the chain pointer register LLPx of stcLlpSesc[4] to the first address of &stcLlpSesc[5], and finally write the chain pointer register LLPx of stcLlpSesc[5] to the first address of &stcLlpSesc[0] to form a circular linked list storage structure, and configure the second to seventh DMA channels as the data receiving channels for the 6 digital electrical signals after sampling.

[0072] In this embodiment of the invention, the AD sampling module transmits data with the main control MCU module through the Direct Register Access (DMA) transmission method. During the DMA data transmission process, the MCU main control module can perform other tasks. The operation of the main processor will only be interrupted when the data needs to be processed after the entire data block transmission is completed, which can realize the transmission of a large amount of data in a short time.

[0073] As one implementation, the method further includes: the received data is buffered via a dual-buffering mode from the second DMA channel to the Mth DMA channel. Please refer to [link / reference]. Figure 3 , Figure 3 This is a schematic diagram of a DMA dual-cache mode for caching data, provided in an embodiment of the present invention.

[0074] S301. Create the first and second receive buffers from the second DMA channel to the Mth DMA channel, and create the first and second index data of the chain pointer structure array from the second DMA channel to the Mth DMA channel. Specifically, in this embodiment of the invention, firstly, create the dual receive buffers RxBuf1[n] and RxBuf2[n] from the second DMA channel to the seventh DMA channel, where n is the data length of one sample, and create the chain pointer structure array stcLlpDesc_ch1[2] from the second DMA channel to the Mth DMA channel, with an array length of 2, corresponding to dual buffers.

[0075] S302. Set the data source address register of the chain pointer structure array from the second DMA channel to the Mth DMA channel as the data address register of each channel of the SPI communication bus. Specifically, in this embodiment of the invention, the data source address registers SARx of the chain pointer structure arrays stcLlpDesc_ch1[0] and stcLlpDesc_ch1[1] from the second DMA channel to the Mth DMA channel are all written to the data register &SPI1_UNIT->DR of the first SPI channel.

[0076] S303. Set the data target address register of the first index data of the chain pointer structure array from the second DMA channel to the Mth DMA channel to the address of the second receive buffer, and set the chain pointer register to the starting address of the second index data. Specifically, in this embodiment of the invention, set the data target address register DARx of the first index data stcLlpDesc_ch1[0] of the chain pointer structure array from the second DMA channel to the seventh DMA channel to the address &RxBuf2[0] of the second receive buffer, and set the chain pointer register LLPx to the starting address of the second index data &stcLlpDesc_ch1[1].

[0077] S304. Set the data target address register of the second index data of the chain pointer structure array from the second DMA channel to the Mth DMA channel to the address of the first receive buffer, and set the chain pointer register to the starting address of the first index data. Specifically, in this embodiment of the invention, set the data target address register DARx of the second index data stcLlpDesc_ch1[1] of the chain pointer structure array from the second DMA channel to the Mth DMA channel to the address &RxBuf1[0] of the first receive buffer, and set the chain pointer register LLPx to the starting address of the first index data &stcLlpDesc_ch1[1].

[0078] In this embodiment of the invention, the interrupt method for the DMA second channel to the DMA Mth channel includes: creating a data storage array and an interrupt flag for the DMA second channel to the DMA Mth channel, and initializing the interrupt flag for the DMA second channel to the DMA Mth channel; when the first receive buffer of the DMA second channel to the DMA Mth channel is full of data, a DMA interrupt event is generated, the interrupt flag of the DMA second channel to the DMA Mth channel is set to 1, and the data in the first receive buffer is stored in the data storage array; when the second receive buffer of the DMA second channel to the DMA Mth channel is full of data, a DMA interrupt event is generated, the interrupt flag of the DMA second channel to the DMA Mth channel is set to 2, and the data in the second receive buffer is stored in the data storage array; when the data in the second receive buffer is stored in the data storage array, the interrupt flag of the DMA second channel to the DMA Mth channel is set to 0.

[0079] In this embodiment of the invention, the AD sampling module transmits data with the main control MCU module via Direct Register Access (DMA) transmission, and the DMA employs a dual-buffer mode to buffer the received data. Please refer to [link / reference]. Figure 4 , Figure 4 This invention provides a flowchart of a signal synchronous sampling method using SPI-DAM dual buffering. In this embodiment, when performing harmonic sampling, only one more DMA channel resource than the number of channels for digital electrical signals is used to achieve synchronous sampling of multiple signals. The dual buffering ensures that during the interruption processing time of the first DMA channel, the second buffer of the DMA can continue to receive data from the SPI communication bus. The principle is simple, and the DMA resource utilization is small, which can ensure that data is not lost when the sampling frequency is increased.

[0080] This invention provides a synchronous sampling method for a harmonic standard meter. The method includes: acquiring an analog voltage signal and an analog current signal corresponding to the number of analog voltage signals to form multiple analog electrical signals; inputting the multiple analog electrical signals into an AD sampling module corresponding to each analog electrical signal; and the main control MCU module sending a synchronous sampling start signal to each AD sampling module; the start conversion pin of each AD sampling module starts the AD sampling module to synchronously sample the analog electrical signals into digital electrical signals; and the sampled digital electrical signals are input to the main control MCU module via an SPI communication bus using a direct register access (DMA) transmission method. The synchronous sampling method for harmonic standard meters provided by this invention inputs the sampled digital electrical signals from the AD sampling module to the main control MCU module through the SPI communication buses. It utilizes the interlocking chain pointer characteristic of the multi-SPI-DMA channels of the main control MCU module to sample the six harmonic signals. Furthermore, the DMA receiving channel adopts a dual-buffering mode to buffer the received data, effectively ensuring the continuity and integrity of the synchronous sampling of the analog electrical signals by the AD sampling module within one calculation cycle, and further improving the accuracy of harmonic energy metering.

[0081] Based on the above-described synchronous sampling method for harmonic standard tables, this invention provides a synchronous sampling system for harmonic standard tables. Please refer to [link / reference]. Figure 5 , Figure 5 This is a schematic diagram of the hardware structure of a synchronous sampling system for a harmonic standard table, provided in an embodiment of the present invention.

[0082] The system includes an AD sampling module and a main control MCU module. The AD sampling module is used to synchronously sample multiple analog electrical signals into digital electrical signals, and input the sampled digital electrical signals to the main control MCU module through each SPI communication bus in a direct register access DMA transmission mode. The main control MCU module sends a synchronous sampling start signal to the start conversion pin of each AD sampling module. The start conversion pin of each AD sampling module is used to start each AD sampling module to synchronously sample the analog electrical signals.

[0083] Specifically, in this embodiment of the invention, a three-phase harmonic standard meter can be used to measure harmonic energy. The digital electrical signals of each channel in the AD sampling module are input to the main control MCU module through each SPI communication bus, and are also input to the main control MCU module through the register access DMA transmission method. This effectively ensures the continuity and integrity of the AD sampling module's synchronous sampling of each analog electrical signal within a calculation cycle, and further improves the accuracy of harmonic energy measurement.

[0084] As one implementation method, please refer to Figure 6 , Figure 6 This invention provides a schematic diagram of the connection between an AD sampling module and a main control MCU module. The AD sampling module includes a signal input unit, a chip select unit, and a clock input unit. The main control MCU module includes a signal receiving unit, a signal selection unit, and a clock output unit. The signal input unit in the AD sampling module is used to synchronously sample each analog electrical signal into a digital electrical signal and input each digital electrical signal to the signal receiving unit of the main control MCU module via an SPI communication bus. The signal selection unit in the main control MCU module is used to send the synchronous sampling start signal to the signal start pin of the AD sampling module. The clock output unit in the main control MCU module is used to send a clock reference signal to the clock input unit of the AD sampling module.

[0085] Specifically, in this embodiment of the invention, the master control MCU module is the master device, and the AD sampling module is the slave device. Each SPI channel of the master control MCU module is configured with three functional pins, including a MISO pin for signal reception, an SS pin for signal selection, and an SCK pin for clock output. The AD sampling module includes an SDout pin for signal input, a CS pin for signal selection, and an SCLK pin for clock input. The SS pin of the master control MCU module is connected to the chip select CS pin of the AD sampling module, the SCK pin of the master control MCU module is connected to the SCLK pin of the AD sampling module, and the MISO pin of the master control MCU module is connected to the SDout pin of the AD sampling module. Furthermore, in this embodiment of the invention, the SPI clock signal source of the main control MCU module is configured as a phase-locked loop clock signal, and the clock frequency division of each SPI unit is configured as a 64-fold frequency division; the SPI data bit length of the main control MCU module is configured as 24 bits, and the SPI transmission mode is configured as full-duplex mode; the SPI pin working mode of the main control MCU module is configured as follows: in the idle state, the SCK pin outputs low, the MISO pin data is valid at even edges, and the MISO pin data changes and updates at odd edges.

[0086] As one implementation method, please refer to Figure 7 , Figure 7This invention provides a schematic diagram of the synchronous sampling output of electrical signals by various AD sampling modules. A three-phase harmonic energy meter can be used to measure harmonic energy. The timer channel of the main control MCU module includes a first timer channel and a second timer channel. The start-up conversion pins of three analog voltage signals in the AD sampling module are connected in parallel, and these three parallel start-up conversion pins are connected to the output pins of the first timer channel. Similarly, the start-up conversion pins of three analog current signals in the AD sampling module are connected in parallel, and these three parallel start-up conversion pins are connected to the output pins of the second timer channel. The outputs of the first and second timer channels of the main control MCU are pulse width modulation (PWM) outputs, and both output pulse waveforms of the same frequency. In this embodiment, the use of pulse width modulation output allows for precise control of the output level of each circuit signal by adjusting the pulse width and period.

[0087] The synchronous sampling system for a harmonic standard table provided in this embodiment of the invention can execute the technical solution of the synchronous sampling method for a harmonic standard table in any of the above embodiments. Its implementation principle and beneficial effects are similar to those of the synchronous sampling method for a harmonic standard table. For details, please refer to the implementation principle and beneficial effects of the synchronous sampling method for a harmonic standard table, which will not be repeated here.

[0088] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0089] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units. The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

[0090] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A synchronous sampling method for a harmonic standard table, characterized in that, include: The system acquires analog voltage signals and analog current signals corresponding to the number of analog voltage signals to form multiple analog electrical signals, and inputs the multiple analog electrical signals into the AD sampling modules corresponding to each analog electrical signal. The main control MCU module sends a synchronous sampling start signal to each AD sampling module. The start conversion pin of each AD sampling module starts the AD sampling module and synchronously samples the analog electrical signals into digital electrical signals. The sampled digital electrical signals are input to the main control MCU module via the SPI communication bus using Direct Register Access (DMA) transfer mode, including: Create the receive buffer and transmit buffer for the first DMA channel, and initialize the target buffer address and source buffer address for the first DMA channel; Configure the first DMA channel as a data transmission channel for the first digital electrical signal, and configure the trigger mode of the first DMA channel as an automatic event trigger mode; The channels of the sampled N digital electrical signals are configured as an array of N chain pointer structures in a chained mode, and the data source address of the N chain pointer structures is configured as the starting address of the transmit buffer of the first channel of the DMA, where N represents the number of channels of digital electrical signals. Configure data registers for the data target addresses of the N chain pointer structure arrays respectively, and set the corresponding bit of the status code of the data register to 1; The storage structure of the array of N chain pointer structures of the first DMA channel is configured as a circular linked list storage structure, and the second DMA channel to the Mth DMA channel are configured as the data receiving channels of the sampled N digital electrical signals, where M=N+1, and M represents the number of DMA channels.

2. The synchronous sampling method for the harmonic standard table according to claim 1, characterized in that, The start-up conversion pin of each AD sampling module starts the AD sampling module and synchronously samples the analog electrical signals into digital electrical signals, including: The signal input unit in the AD sampling module synchronously samples each analog electrical signal into a digital electrical signal, and inputs each digital electrical signal to the signal receiving unit of the main control MCU module through the SPI communication bus; The signal selection unit in the main control MCU module sends the synchronous sampling start signal to the start conversion pin of the AD sampling module, and at the same time sends the clock signal in the clock output unit to the clock input unit of the AD sampling module.

3. The synchronous sampling method for the harmonic standard table according to claim 2, characterized in that, The clock signal in the clock output unit is the main phase-locked loop clock signal.

4. The synchronous sampling method for the harmonic standard table according to claim 3, characterized in that, The start-up conversion pin of each AD sampling module starts the AD sampling module and synchronously samples the analog electrical signals into digital electrical signals, and also includes: Connect the start-up conversion pin units of the analog voltage signal in the AD sampling module in parallel, and connect the start-up conversion pin units of the parallel analog voltage signal to the output pin unit of the first channel of the main control MCU timer; Connect the start-up conversion pin units of the analog current signal in the AD sampling module in parallel, and connect the start-up conversion pin units of the parallel analog current signal to the output pin unit of the second channel of the main control MCU timer; The outputs of the first channel and the second channel of the main control MCU timer are pulse width modulated, and the outputs of the first channel and the second channel of the main control MCU timer are pulse waveforms with the same frequency.

5. The synchronous sampling method for the harmonic standard table according to claim 1, characterized in that, The method further includes: the received data is buffered through a dual-buffer mode from the second DMA channel to the Mth DMA channel.

6. The synchronous sampling method for the harmonic standard table according to claim 5, characterized in that, The DMA second channel to the DMA Mth channel buffer the received data using a dual-buffer mode, including: Create a first and a second receive buffer for the DMA second channel to the DMA M channel, and create first and second index data for the chain pointer structure array of the DMA second channel to the DMA M channel; Set the data source address register of the chain pointer structure array from the second DMA channel to the Mth DMA channel as the data address register of each channel of the SPI communication bus; Set the data target address register of the first index data of the chain pointer structure array from the second DMA channel to the Mth DMA channel to the address of the second receive buffer, and set the chain pointer register to the starting address of the second index data; Set the data target address register of the second index data of the chain pointer structure array from the second channel of DMA to the Mth channel of DMA to the address of the first receive buffer, and set the chain pointer register to the starting address of the first index data.

7. A synchronous sampling system for a harmonic standard meter, characterized in that, The system is used to implement the synchronous sampling method of the harmonic standard table as described in any one of claims 1-6, and the system includes an AD sampling module and a main control MCU module; The AD sampling module is used to synchronously sample multiple analog electrical signals into digital electrical signals, and input the sampled digital electrical signals to the main control MCU module through each SPI communication bus in the direct register access DMA transmission mode. The main control MCU module sends a synchronous sampling start signal to the start conversion pin of each AD sampling module; The start-up conversion pin of each AD sampling module is used to start each AD sampling module to synchronously sample each analog electrical signal.

8. The synchronous sampling system for the harmonic standard table according to claim 7, characterized in that, The AD sampling module includes a signal input unit, a chip select unit, and a clock input unit; the main control MCU module includes a signal receiving unit, a signal selection unit, and a clock output unit. The signal input unit in the AD sampling module is used to synchronously sample each analog electrical signal into a digital electrical signal, and input each digital electrical signal to the signal receiving unit of the main control MCU module through the SPI communication bus; The signal selection unit in the main control MCU module is used to send the synchronous sampling start signal to the start conversion pin unit of the AD sampling module; The clock output unit in the main control MCU module is used to send the clock reference signal to the clock input unit of the AD sampling module.

9. The synchronous sampling system for the harmonic standard table according to claim 8, characterized in that, The timer channels of the main control MCU module include a first timer channel and a second timer channel; The analog voltage signal start-up conversion pin units in the AD sampling module are connected in parallel, and the parallel analog voltage signal start-up conversion pin units are connected to the output pin units of the first channel of the timer. The analog current signal start-up conversion pin units in the AD sampling module are connected in parallel, and the parallel analog current signal start-up conversion pin units are connected to the output pin units of the second channel of the timer. The outputs of the first channel and the second channel of the main control MCU timer are pulse width modulation outputs, and the outputs of the first channel and the second channel of the main control MCU timer are pulse waveforms with the same frequency.

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