Display Substrate, Preparation Method Thereof, and Display Device

Abstract

A display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a substrate (101) and at least one transistor (100) disposed on the substrate (101); the transistor (100) includes: an active layer pattern (2) disposed on the substrate (101); a first source-drain electrode (3) disposed on the substrate (101), the first source-drain electrode (3) being electrically connected to the active layer pattern (2); a first gate electrode (5) disposed on a side of the active layer pattern (2) away from the substrate (101), a positive projection of the first gate electrode (5) and the active layer pattern (2) on the substrate (101) overlapping and not contacting each other; a second source-drain electrode (4) disposed on a side of the active layer pattern (2) away from the substrate (101), the second source-drain electrode (4) including a first sub-electrode (41) and a second sub-electrode (42) connected to each other, the second sub-electrode (42) being located on a side of the first sub-electrode (41) close to the first gate electrode (5), the first sub-electrode (41) being electrically connected to the active layer pattern (2), and a positive projection of the second sub-electrode (42) and the active layer pattern (2) on the substrate (101) overlapping and not contacting each other.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and particularly to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] In recent years, low temperature poly-silicon thin film transistors (Low Temperature Poly-Silicon Thin Film Transistor, LTPS TFT for short) and oxide thin film transistors have received much attention in the display industry, each with its own advantages and comparable in performance. Low temperature poly-silicon thin film transistors have the advantages of high mobility and fast charging. Indium gallium zinc oxide (In-Ga-Zn-Oxide, IGZO) thin film transistors (i.e., IGZO-TFT) have become a research hotspot because their active layer (IGZO) has a high carrier mobility, as well as high thermal and chemical stability. Preparing high-performance and high-stability IGZO thin film transistors has become the focus and difficulty for various manufacturers.

[0003] With the increase in product pixel density and refresh rate, the parasitic capacitance in the extending direction of the data line has become the most important factor restricting the increase in pixel density and refresh rate of the display panel. At the same time, the size and current of the transistors in the pixel circuit are the key factors affecting the capacitance and power consumption of the driving circuit. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in the present disclosure. This overview is not intended to limit the scope of protection of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including: a substrate and at least one transistor disposed on the substrate; the transistor includes:

[0006] an active layer pattern disposed on the substrate;

[0007] a first source-drain electrode disposed on the substrate, the first source-drain electrode being electrically connected to the active layer pattern;

[0008] a first gate electrode disposed on a side of the active layer pattern away from the substrate, the first gate electrode and the active layer pattern overlapping in the orthographic projection on the substrate and not contacting each other;

[0009] The second source-drain electrode is disposed on a side of the active layer pattern away from the substrate. The second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other. The second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode. The first sub-electrode is electrically connected to the active layer pattern. There is an overlap between the second sub-electrode and the active layer pattern in the orthographic projection on the substrate, and they do not contact each other.

[0010] In an exemplary embodiment, the second source-drain electrode further includes a third sub-electrode. The third sub-electrode is located on a side of the first sub-electrode away from the first gate electrode. There is an overlap between the third sub-electrode and the active layer pattern in the orthographic projection on the substrate, and they do not contact each other.

[0011] In an exemplary embodiment, the first sub-electrode and the second sub-electrode are integrally formed.

[0012] In an exemplary embodiment, the first source-drain electrode includes a fourth sub-electrode and a fifth sub-electrode connected to each other. The fifth sub-electrode is located on a side of the fourth sub-electrode away from the first gate electrode. The fourth sub-electrode is electrically connected to the active layer pattern. There is an overlap between the fifth sub-electrode and the active layer pattern in the orthographic projection on the substrate, and they do not contact each other.

[0013] In an exemplary embodiment, the transistor further includes a first insulating layer. The first insulating layer is located between the active layer pattern and the first gate electrode. The first insulating layer covers the active layer pattern. The first source-drain electrode, the first gate electrode, and the second source-drain electrode are all located on a side of the first insulating layer away from the substrate. A first via hole and a second via hole are provided in the first insulating layer. The first source-drain electrode is electrically connected to the active layer pattern through the first via hole, and the second source-drain electrode is electrically connected to the active layer pattern through the second via hole.

[0014] In an exemplary embodiment, the transistor further includes a first insulating layer. The first insulating layer includes at least one insulating layer pattern. The insulating layer pattern covers a part of the active layer pattern, and there is a non-overlapping region between the insulating layer pattern and at least a part of the active layer pattern in the orthographic projection on the substrate. The first source-drain electrode, the first gate electrode, and the second source-drain electrode are all located on a side of the first insulating layer away from the substrate. The first source-drain electrode and the second source-drain electrode are respectively electrically connected to the non-overlapping regions of the active layer pattern.

[0015] In an exemplary embodiment, a pixel electrode is further provided on a side of the transistor away from the substrate. The pixel electrode is integrally formed with the second source-drain electrode.

[0016] In an exemplary embodiment, the first source-drain electrode is integrally formed with the active layer pattern.

[0017] In an exemplary embodiment, a signal line is further included, and the signal line is electrically connected to the first source-drain electrode.

[0018] In an exemplary embodiment, the signal line is located between the first source-drain electrode and the substrate. The display substrate further includes a buffer layer, the buffer layer is located between the signal line and the active layer pattern, a third via hole is provided in the buffer layer, and the first source-drain electrode is electrically connected to the signal line through the third via hole.

[0019] In an exemplary embodiment, the first source-drain electrode is integrally formed with the active layer pattern, the signal line is in electrical contact with the first source-drain electrode, the signal line is located on the side of the first source-drain electrode close to the substrate, or the signal line is located on the side of the first source-drain electrode away from the substrate.

[0020] In an exemplary embodiment, the material of the active layer pattern is an oxide semiconductor.

[0021] In an exemplary embodiment, the transistor is configured as a transistor in a gate driving circuit.

[0022] On the other hand, the present disclosure also provides a display device including the foregoing display substrate.

[0023] On the other hand, the present disclosure also provides a method for manufacturing a display substrate, including:

[0024] Forming an active layer pattern on a substrate;

[0025] Forming a first source-drain electrode on the substrate, and electrically connecting at least part of the first source-drain electrode to the active layer pattern;

[0026] Forming a first gate electrode on the side of the active layer pattern away from the substrate, so that the positive projection of the first gate electrode and the active layer pattern on the substrate overlaps and does not contact each other;

[0027] Forming a second source-drain electrode on the side of the active layer pattern away from the substrate, the second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other, the second sub-electrode is located on the side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, and the positive projection of the second sub-electrode and the active layer pattern on the substrate overlaps and does not contact each other.

[0028] Other aspects can be understood after reading and understanding the drawings and the detailed description. Description of the Drawings

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation to the technical solution of the present application.

[0030] Figure 1a It is a schematic diagram of the structure of a transistor in a display substrate according to an embodiment of the present disclosure;

[0031] Figure 1b It is a first cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0032] Figure 2 It is the circuit symbol of a transistor in a display substrate according to an embodiment of the present disclosure;

[0033] Figure 3a It is a first equivalent circuit diagram of a transistor in a display substrate according to an embodiment of the present disclosure;

[0034] Figure 3b It is the equivalent circuit of a transistor in a display substrate according to an embodiment of the present disclosure Figure 2 ;

[0035] Figure 4a It is a first curve graph of the drain-source current of a transistor in a display substrate during charging according to an embodiment of the present disclosure;

[0036] Figure 4b It is a first curve graph of the drain-source current of a transistor in a display substrate during discharging according to an embodiment of the present disclosure;

[0037] Figure 4c It is the curve of the drain-source current of a transistor in a display substrate during charging according to an embodiment of the present disclosure Figure 2 ;

[0038] Figure 4d It is the curve of the curve graph of the drain-source current of a transistor in a display substrate during discharging according to an embodiment of the present disclosure Figure 2 ;

[0039] Figure 5 It is the curve graph of the drain-source current of a transistor in a display substrate under voltage in the related art;

[0040] Figure 6 It is the cross-sectional view of a transistor in a display substrate in the related art;

[0041] Figure 7a It is the schematic diagram of the structure of a transistor in a display substrate according to an embodiment of the present disclosure Figure 2 ;

[0042] Figure 7b It is the cross-section of a display substrate according to an embodiment of the present disclosure Figure 2 ;

[0043] Figure 8aSchematic diagram III of the structure of a transistor in the display substrate according to an embodiment of the present disclosure;

[0044] Figure 8b Cross-sectional view III of the display substrate according to an embodiment of the present disclosure;

[0045] Figure 9a Schematic diagram IV of the structure of a transistor in the display substrate according to an embodiment of the present disclosure;

[0046] Figure 9b Cross-sectional view IV of the display substrate according to an embodiment of the present disclosure;

[0047] Figure 10 Cross-sectional view of the display substrate according to an embodiment of the present disclosure. Detailed implementation manners

[0048] To make the objectives, technical solutions and advantages of the present disclosure more clear and understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the implementation manners can be implemented in multiple different forms. Those of ordinary skill in the art can easily understand the fact that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other arbitrarily.

[0049] In the accompanying drawings, sometimes for the sake of clarity, the sizes, thicknesses of layers or regions of the respective components are exaggerated. Therefore, one aspect of the present disclosure is not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one aspect of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0050] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of the components, rather than to limit in terms of quantity.

[0051] In this specification, for convenience, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the accompanying drawings, which are only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, so it cannot be understood as a limitation to the present disclosure. The positional relationship of the components changes appropriately according to the directions describing the respective components. Therefore, it is not limited to the words described in the specification and can be replaced appropriately according to the situation.

[0052] In this specification, unless otherwise clearly defined or limited, the terms "installed", "connected", and "joined" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0053] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0054] In this specification, the first pole may be the drain electrode and the second pole may be the source electrode, or the first pole may be the source electrode and the second pole may be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" sometimes swap with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can swap with each other.

[0055] In this specification, "electrically connected" includes the case where components are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0056] In this specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0057] In this specification, "film" and "layer" can swap with each other. For example, sometimes the "conductive layer" can be changed to the "conductive film". Similarly, sometimes the "insulating film" can be changed to the "insulating layer".

[0058] "About" in this disclosure means not strictly defining the boundary and allowing values within the range of process and measurement errors.

[0059] Figure 5It is a graph showing the current between the drain and source of a transistor in a display substrate of related technologies under voltage. Through the research of the inventor of the present disclosure, it is found that the transistor is prone to transistor negative shift or DGS under voltage, resulting in the failure of the driving circuit. Figure 5 The horizontal axis represents the voltage Vg of the first gate electrode (unit: volt), and the vertical axis represents the current Ids between the drain and source (unit: ampere). As Figure 5 shown, the curve of the current between the drain and source before the transistor fails is a, and the curve of the current between the drain and source after the transistor fails is b. The reason for the transistor failure is that high voltage and high current density cause device attenuation.

[0060] The present disclosure embodiment provides a display substrate, including: a substrate and at least one transistor disposed on the substrate; the transistor includes:

[0061] An active layer pattern disposed on the substrate;

[0062] An active layer pattern disposed on the substrate;

[0063] A first source-drain electrode disposed on the substrate, the first source-drain electrode being electrically connected to the active layer pattern;

[0064] A first gate electrode disposed on a side of the active layer pattern away from the substrate, there is an overlap between the first gate electrode and the active layer pattern in the orthographic projection on the substrate, and they do not contact each other;

[0065] A second source-drain electrode disposed on a side of the active layer pattern away from the substrate, the second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, and there is an overlap between the second sub-electrode and the active layer pattern in the orthographic projection on the substrate, and they do not contact each other.

[0066] In the display substrate of the present disclosure embodiment, the first sub-electrode of the second source-drain electrode is electrically connected to the active layer pattern, and there is an overlap between the second sub-electrode of the second source-drain electrode and the active layer pattern in the orthographic projection on the substrate and they do not contact each other. On the one hand, when the transistor discharges, the first sub-electrode in the second source-drain electrode can be configured as the source-drain electrode, and the second sub-electrode in the second source-drain electrode can be configured as the second gate electrode, so that the transistor forms a double-gate structure, effectively reducing the leakage current I off , avoiding the impact of high current density on the transistor; on the other hand, when the transistor charges, the first sub-electrode and the second sub-electrode in the second source-drain electrode can both be configured as the source-drain electrode, so that the transistor forms a single-gate structure, accelerating the charging speed.

[0067] Figure 1a It is a schematic structural diagram one of the transistor in the display substrate of the present disclosure embodiment;Figure 1b This is a first cross-sectional view of the display substrate according to an embodiment of the present disclosure. Among them, Figure 1b is Figure 1a a cross-sectional view taken along A-A' in Figure 1a and Figure 1b As shown, in the direction perpendicular to the display substrate, the display substrate according to an embodiment of the present disclosure may include a substrate 101 and at least one transistor 100 disposed on the substrate 101. The transistor 100 includes a buffer layer 1, a semiconductor layer, a first insulating layer 6, a conductive layer, and a second insulating layer 7 disposed on the substrate 101; the semiconductor layer includes an active layer pattern 2; the conductive layer includes a first source / drain electrode 3, a second source / drain electrode 4, and a first gate electrode 5. In the direction parallel to the display substrate, the first source / drain electrode 3, the second source / drain electrode 4, and the first gate electrode 5 all extend along a second direction (for example, direction Y), the first source / drain electrode 3, the second source / drain electrode 4, and the first gate electrode 5 are arranged at intervals along a first direction (for example, direction X), and the first gate electrode 5 is located between the first source / drain electrode 3 and the second source / drain electrode 4. Among them, the first direction is different from the second direction. For example, the first direction is perpendicular to the second direction.

[0068] In an exemplary embodiment, the transistor 100 may be an oxide (Oxide) thin film transistor, and the active layer in the transistor is made of an oxide semiconductor material. For example, the active layer in the transistor may be indium gallium zinc oxide (IGZO).

[0069] In an exemplary embodiment, the transistor 100 may be a transistor in circuits such as a gate driving circuit, an input circuit, and a working voltage circuit.

[0070] In an exemplary embodiment, as Figure 1b shown, there is an overlap between the positive projection of the first gate electrode 5 and the active layer pattern 2 on the substrate 101, and the first gate electrode 5 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other.

[0071] In an exemplary embodiment, as Figure 1a and Figure 1b shown, a first via 61 and a second via 62 are provided in the first insulating layer 6. The first source / drain electrode 3 is electrically connected to the active layer pattern 2 through the first via 61. The second source / drain electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42 connected to each other. The second sub-electrode 42 is located on the side of the first sub-electrode 41 close to the first gate electrode 5; there is an overlap between the positive projection of the second sub-electrode 42 and the active layer pattern 2 on the substrate 101, and the second sub-electrode 42 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other. The first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via 62. Among them, the first insulating layer 6 may also be referred to as a gate insulation (GI) layer.

[0072] In an exemplary embodiment, the first sub - electrode 41 and the second sub - electrode 42 can be integrally formed to form a film structure. The first sub - electrode 41 and the second sub - electrode 42 can be prepared from the same material through the same preparation process.

[0073] In an exemplary embodiment, as Figure 1a and Figure 1b shown, the second source - drain electrode 4 further includes a third sub - electrode 43. The third sub - electrode 43 is located on the side of the first sub - electrode 41 away from the first gate electrode 5. And the orthographic projection of the third sub - electrode 43 and the active - layer pattern 2 on the substrate 101 overlaps, and they are separated from each other by the first insulating layer 6 and do not contact each other.

[0074] In an exemplary embodiment, as Figure 1a and Figure 1b shown, the first source - drain electrode 3 includes a fourth sub - electrode 31 and a fifth sub - electrode 32 connected to each other. The fifth sub - electrode 32 is located on the side of the fourth sub - electrode 31 away from the first gate electrode 5. The fourth sub - electrode 31 is electrically connected to the active - layer pattern 2. The orthographic projection of the fifth sub - electrode 32 and the active - layer pattern 2 on the substrate 101 overlaps, and they are separated from each other by the first insulating layer 6 and do not contact each other. Among them, the fourth sub - electrode 31 and the fifth sub - electrode 32 can be integrally formed to form a film structure. The fourth sub - electrode 31 and the fifth sub - electrode 32 can be prepared from the same material through the same preparation process.

[0075] Figure 2 This is the circuit symbol of the transistor in the display substrate of the embodiment of the present disclosure. In an exemplary embodiment, as Figure 2 shown, G is the gate, S is the source, and D is the drain. When the value of the gate - source voltage Vgs (i.e., Vg - Vs) is greater than the threshold voltage Vth, the transistor is cut off, and at this time, there is a leakage current I off . When the gate - source voltage Vgs is lower than the threshold voltage Vth, the transistor works, the source voltage is higher than the drain voltage, and holes flow from the source to the drain as carriers through the channel region.

[0076] Figure 3a This is the first equivalent circuit diagram of the transistor in the display substrate of the embodiment of the present disclosure; Figure 3b This is the equivalent circuit of the transistor in the display substrate of the embodiment of the present disclosure Figure 2 In an exemplary embodiment, as Figure 3a and Figure 3bAs shown, in the embodiments of the present disclosure, when the transistor in the substrate is discharging, a high-potential voltage Vg can be applied to the first gate electrode 5 of the transistor, a high-potential voltage Vd can be applied to the second source-drain electrode 4 of the transistor, and a low-potential voltage Vs can be applied to the first source-drain electrode 3 of the transistor, so that the first sub-electrode 41 in the second source-drain electrode 4 is configured as the source-drain electrode, and the second sub-electrode 42 in the second source-drain electrode 4 is configured as the second gate electrode, thereby forming a double-gate structure for the transistor; in the embodiments of the present disclosure, when the transistor in the substrate is charging, a high-potential voltage Vg can be applied to the first gate electrode 5 of the transistor, a low-potential voltage Vd can be applied to the second source-drain electrode 4 of the transistor, and a high-potential voltage Vs can be applied to the first source-drain electrode 3 of the transistor, so that both the first sub-electrode 41 and the second sub-electrode 42 in the second source-drain electrode 4 are configured as source-drain electrodes, thereby forming a single-gate structure for the transistor.

[0077] In an exemplary embodiment, the formula for calculating the current Ids between the source and drain of the transistor in the substrate when the transistor is discharging in the embodiments of the present disclosure is:

[0078] Ids = μ × CoxW1 / L1 × [(0 - Vth1) × Vm - 1 / 2 × Vm 2 = μ × CoxW2 / L2 × [(Vgs - Vm) × (Vd - Vm) - 1 / 2 × (Vd - Vm) 2

[0079] In an exemplary embodiment, the formula for calculating the current Ids between the source and drain of the transistor in the substrate when the transistor is charging in the embodiments of the present disclosure is:

[0080] Ids = μ × CoxW1 / L1 × [(Vd - Vm - Vth1) × (Vd - Vm) - 1 / 2(Vd - Vm) 2 = μ × Cox × W2 / L2 × [(Vgs - Vth2) × Vm - 1 / 2 × Vm 2

[0081] Wherein, Vm is a related variable, related to the specific transistor design and can be specifically calculated through the above formula; W1 is the length of the first gate electrode 5 in the first direction (such as direction X); L1 is the length of the first gate electrode 5 in the second direction (such as direction Y); Vth1 is the threshold voltage of the first gate electrode 5; W2 is the length of the second gate electrode in the first direction (such as direction X); L2 is the length of the second gate electrode in the second direction (such as direction Y); Vth2 is the threshold voltage of the second gate electrode.

[0082] Figure 4a This is Curve Graph 1 of the current between the source and drain of the transistor in the substrate when the transistor is charging in the embodiments of the present disclosure; Figure 4b ​​FIG. 1 is a graph showing the current between the drain and source of a transistor in a display substrate according to an embodiment of the present disclosure during discharge. Among them, Figure 4a and Figure 4b are both graphs of the current between the drain and source using the Figure 3a equivalent circuit shown. Figure 4a and Figure 4b In the horizontal axis is the voltage Vg of the first gate electrode (unit: volt), and the vertical axis is the current Ids between the drain and source (unit: ampere). As Figure 4a shown, when the transistor in the display substrate according to the embodiment of the present disclosure is charging, the transistor forms a single-gate structure, and the on-state current Ion changes greatly. As Figure 4b shown, when the transistor in the display substrate according to the embodiment of the present disclosure is discharging, the transistor forms a double-gate structure, which can effectively control the on-state current Ion and avoid the impact of high current density on the transistor. The display substrate according to the embodiment of the present disclosure can accelerate the charging speed during charging; during discharging, effectively reduce the leakage current I off . If the turn-on voltage of the display substrate according to the embodiment of the present disclosure is adjusted to more than 0.5V, the transistor can achieve reverse turn-off.

[0083] Figure 4c FIG. 2 is a curve of the current between the drain and source of a transistor in a display substrate according to an embodiment of the present disclosure during charging Figure 2 ; Figure 4d FIG. 3 is a curve of the graph of the current between the drain and source of a transistor in a display substrate according to an embodiment of the present disclosure during discharging Figure 2 . Among them, Figure 4c and Figure 4d are both graphs of the current between the drain and source using the Figure 3b equivalent circuit shown. Figure 4c and Figure 4d In the horizontal axis is the voltage Vg of the first gate electrode (unit: volt), and the vertical axis is the current Ids between the drain and source (unit: ampere). As Figure 4c shown, when the transistor in the display substrate according to the embodiment of the present disclosure is charging, the transistor forms a single-gate structure, and the on-state current Ion changes greatly. As Figure 4d shown, when the transistor in the display substrate according to the embodiment of the present disclosure is discharging, the transistor forms a double-gate structure, which can effectively control the on-state current Ion and avoid the impact of high current density on the transistor. The display substrate according to the embodiment of the present disclosure can accelerate the charging speed during charging; during discharging, effectively reduce the leakage current I off .

[0084] Figure 6 FIG. 4 is a cross-sectional view of a transistor in a display substrate of the related art. As Figure 6As shown, the transistor in the related display substrate may adopt a double-gate structure. The transistor includes an active layer pattern 2, a first source-drain electrode 3, a first gate electrode 5, a second gate electrode 8, and a second source-drain electrode 4 that are sequentially disposed on a substrate 101. The first gate electrode 5 and the second gate electrode 8 are disconnected and insulated from each other. Both the first gate electrode 5 and the second gate electrode 8 overlap with the orthographic projection of the active layer pattern 2 on the substrate 101. Both the first source-drain electrode 3 and the second source-drain electrode 4 are electrically connected to the active layer pattern 2.

[0085] In the display substrate according to an embodiment of the present disclosure, by using the second sub-electrode as the second gate electrode and disposing the second sub-electrode on the side of the first sub-electrode closer to the gate, compared with the double-gate structure of the transistor in the related display substrate, the distance between the second gate electrode and the second source-drain electrode in the display substrate according to the embodiment of the present disclosure is eliminated. By controlling the distance between the second sub-electrode and the first gate electrode, the resistance of the active layer pattern to be conductive is adjusted, and the adjustment of the threshold voltage Vth is achieved.

[0086] Figure 7a Schematic diagram of the structure of the transistor in the display substrate according to an embodiment of the present disclosure Figure 2 ; Figure 7b Cross-section view of the display substrate according to an embodiment of the present disclosure Figure 2 . Among them, Figure 7b is Figure 7a a cross-sectional view taken along line B-B' in Figure 7a and Figure 7b . In an exemplary embodiment, as shown in

[0087] Figure 8a Figure 7a and Figure 7b , in the direction perpendicular to the display substrate, the transistor 100 in the display substrate according to the embodiment of the present disclosure includes a buffer layer 1, a semiconductor layer, a first insulating layer 6, a conductive layer, and a second insulating layer 7 disposed on a substrate 101; the semiconductor layer includes an active layer pattern 2; the conductive layer includes a first source-drain electrode 3, a second source-drain electrode 4, and a first gate electrode 5. The first gate electrode 5 overlaps with the orthographic projection of the active layer pattern 2 on the substrate 101, and the first gate electrode 5 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other. A first via 61 and a second via 62 are provided in the first insulating layer 6. The first source-drain electrode 3 is electrically connected to the active layer pattern 2 through the first via 61. The second source-drain electrode 4 includes a first sub-electrode 41, a second sub-electrode 42, and a third sub-electrode 43 that are connected to each other. The first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via 62. The second sub-electrode 42 is disposed on the side of the first sub-electrode 41 closer to the first gate electrode 5; the third sub-electrode 43 is disposed on the side of the first sub-electrode 41 away from the first gate electrode 5; both the second sub-electrode 42 and the third sub-electrode 43 overlap with the orthographic projection of the active layer pattern 2 on the substrate 101, and both the second sub-electrode 42 and the third sub-electrode 43 are separated from the active layer pattern 2 by the first insulating layer 6 and do not contact each other.

[0087] Figure 8aFIG. 3 is a schematic structural diagram of a transistor in the display substrate according to an embodiment of the present disclosure; Figure 8b FIG. 4 is a cross-sectional view of the display substrate according to an embodiment of the present disclosure. Among them, Figure 8b is Figure 8a a cross-sectional view taken along C-C' in FIG. In an exemplary embodiment, as shown in Figure 8a and Figure 8b In the direction perpendicular to the display substrate, the transistor 100 in the display substrate according to an embodiment of the present disclosure includes a buffer layer 1, a semiconductor layer, a first insulating layer 6, a conductive layer, and a second insulating layer 7 provided on a substrate 101; the semiconductor layer includes an active layer pattern 2; the conductive layer includes a first source / drain electrode 3, a second source / drain electrode 4, and a first gate electrode 5. The first gate electrode 5 and the active layer pattern 2 have an overlap in the orthographic projection on the substrate 101, and the first gate electrode 5 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other. The first insulating layer 6 is provided with a first via 61 and a second via 62. The first source / drain electrode 3 includes a fourth sub-electrode 31 and a fifth sub-electrode 32 connected to each other. The fifth sub-electrode 32 is located on a side of the fourth sub-electrode 31 away from the first gate electrode 5. The fourth sub-electrode 31 is electrically connected to the active layer pattern 2. The fifth sub-electrode 32 and the active layer pattern 2 have an overlap in the orthographic projection on the substrate 101 and are separated from each other by the first insulating layer 6 and do not contact each other. The second source / drain electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42 connected to each other. The first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via 62. The second sub-electrode 42 is located on a side of the first sub-electrode 41 close to the first gate electrode 5; the second sub-electrode 4 and the active layer pattern 2 have an overlap in the orthographic projection on the substrate 101, and the second sub-electrode 42 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other.

[0088] Figure 9a FIG. 5 is a schematic structural diagram of a transistor in the display substrate according to an embodiment of the present disclosure; Figure 9b FIG. 6 is a cross-sectional view of the display substrate according to an embodiment of the present disclosure. Among them, Figure 9b is Figure 9a a cross-sectional view taken along D-D' in FIG. In an exemplary embodiment, as shown in Figure 9a and Figure 9bAs shown, in a direction perpendicular to the display substrate, the transistor 100 in the display substrate according to an embodiment of the present disclosure includes a buffer layer 1, a semiconductor layer, a first insulating layer 6, a conductive layer, and a second insulating layer 7 provided on a substrate 101; the semiconductor layer includes an active layer pattern 2; the conductive layer includes a first source-drain electrode 3, a second source-drain electrode 4, and a first gate electrode 5. The first gate electrode 5 and the active layer pattern 2 overlap in the orthographic projection on the substrate 101, and the first gate electrode 5 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other. A first via 61 and a second via 62 are provided in the first insulating layer 6, and the first source-drain electrode 3 is electrically connected to the active layer pattern 2 through the first via 61. The second source-drain electrode 4 includes a first sub-electrode 41 and a second sub-electrode 42 connected to each other. The first sub-electrode 41 is electrically connected to the active layer pattern 2 through the second via 62. The second sub-electrode 42 is located on a side of the first sub-electrode 41 close to the first gate electrode 5. The second sub-electrode 42 and the active layer pattern 2 overlap in the orthographic projection on the substrate 101, and the second sub-electrode 42 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other.

[0089] In an exemplary embodiment, the display substrate according to an embodiment of the present disclosure may be an LCD display substrate, a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.

[0090] Figure 10 It is a cross-sectional view of the display substrate according to an embodiment of the present disclosure. Taking the display substrate according to an embodiment of the present disclosure as an LCD display substrate as an example. In an exemplary embodiment, as Figure 10 shown, the display substrate according to an embodiment of the present disclosure includes: a substrate 101, and a first conductive layer, a buffer layer 1, a semiconductor layer, a first insulating layer 6, a second conductive layer, a third insulating layer 9, a third conductive layer, a second insulating layer 7, a planarization layer 10, a fourth conductive layer, a fourth insulating layer 11, and a fifth conductive layer sequentially provided on the substrate 101.

[0091] In an exemplary embodiment, as Figure 10 shown, the substrate 101 may be made of a transparent material, such as glass or quartz.

[0092] In an exemplary embodiment, as Figure 10As shown, the first conductive layer is disposed on the substrate 101. The first conductive layer includes a signal line 20 and a light-shielding layer 21. The signal line 20 can be a data signal line and is electrically connected to the first source-drain electrode 3. The signal line 20 is used to provide a driving signal to the first source-drain electrode 3. The light-shielding layer 21 overlaps with the positive projection of the active layer pattern 2 on the substrate 101, and the light-shielding layer 21 is used to block light. The materials of the signal line 20 and the light-shielding layer 21 can both adopt a laminated structure of molybdenum (Mo), aluminum (Al) and aluminum (Al), or a laminated structure of molybdenum-niobium alloy (MoNb) and copper (Cu), or a laminated structure of molybdenum-niobium alloy (MTD) and copper (Cu), or a laminated structure of molybdenum-niobium alloy (MoNb), copper (Cu) and molybdenum-niobium alloy (MTD). The thickness of the signal line 20 and the light-shielding layer 21 can be 1000 - 10000 Å.

[0093] In an exemplary embodiment, as Figure 10 shown, a buffer layer 1 is disposed on a side of the first conductive layer away from the substrate 101 and covers the signal line 20 and the light-shielding layer 21. A third via 50 is provided in the buffer layer 1, and the first source-drain electrode 3 is electrically connected to the signal line 20 through the third via 50. The material of the buffer layer 1 can adopt silicon oxide compound (SiOx), or a laminated structure of silicon nitride compound (SiNx) and silicon oxide compound (SiOx). The thickness of the buffer layer 1 can be 100 nm - 700 nm.

[0094] In an exemplary embodiment, as Figure 10 shown, a semiconductor layer is disposed on a side of the buffer layer 1 away from the substrate 101. The semiconductor layer includes an active layer pattern 2, and the thickness of the active layer pattern 2 can be 10 nm - 80 nm.

[0095] In an exemplary embodiment, as Figure 10 shown, a first insulating layer 6 is disposed on a side of the semiconductor layer away from the substrate 101 and covers the active layer pattern 2. A first via 61 and a second via 62 are provided in the first insulating layer 6. The material of the first insulating layer 6 can adopt silicon oxide compound (SiOx). The thickness of the first insulating layer 6 can be 600 Å - 2000 Å. Among them, the first via 61 and the third via 50 in the buffer layer 1 can be prepared by the same manufacturing process.

[0096] In an exemplary embodiment, as Figure 10As shown, the second conductive layer is disposed on a side of the first insulating layer 6 away from the substrate 101. The second conductive layer includes a first gate electrode 5. The first gate electrode 5 overlaps with the positive projection of the active layer pattern 2 on the substrate 101, and the first gate electrode 5 and the active layer pattern 2 are separated from each other by the first insulating layer 6 and do not contact each other. The material of the first gate electrode 5 may adopt a stacked structure of molybdenum niobium alloy (MoNb) and copper (Cu), or a stacked structure of molybdenum niobium alloy (MTD) and copper (Cu), or a stacked structure of molybdenum niobium alloy (MoNb), copper (Cu) and molybdenum niobium alloy (MTD). The thickness of the first gate electrode 5 may be 200 nm to 1200 nm.

[0097] In an exemplary embodiment, as Figure 10 shown, a third insulating layer 9 is disposed on a side of the second conductive layer away from the substrate 101 and covers the first gate electrode 5. The material of the third insulating layer 9 may adopt silicon oxide compound (SiOx), or a stacked structure of silicon nitride compound (SiNx) and oxygen silicon compound (SiOx). The thickness of the third insulating layer 9 may be 200 nm to 400 nm.

[0098] In an exemplary embodiment, as Figure 10 shown, a third conductive layer is disposed on a side of the third insulating layer 9 away from the substrate 101. The third conductive layer includes a first source-drain electrode 3 and a second source-drain electrode 4. The first source-drain electrode 3 is electrically connected to the active layer pattern 2 through a first via 61. The second source-drain electrode 4 includes a first sub-electrode 41, a second sub-electrode 42 and a third sub-electrode 43 which are connected to each other. The second sub-electrode 42 is located on a side of the first sub-electrode 41 close to the first gate electrode 5, and the third sub-electrode 43 is located on a side of the first sub-electrode 41 away from the first gate electrode 5. Both the second sub-electrode 42 and the third sub-electrode 43 overlap with the positive projection of the active layer pattern 2 on the substrate 101, and both the second sub-electrode 42 and the third sub-electrode 43 are separated from the active layer pattern 2 by the first insulating layer 6 and the third insulating layer 9 and do not contact each other. The first sub-electrode 41 is electrically connected to the active layer pattern 2 through a second via 62. The materials of both the first source-drain electrode 3 and the second source-drain electrode 4 may adopt a stacked structure of molybdenum (Mo), aluminum (Al) and aluminum (Al), or a stacked structure of molybdenum niobium alloy (MoNb) and copper (Cu), or a stacked structure of molybdenum niobium alloy (MTD) and copper (Cu), or a stacked structure of molybdenum niobium alloy (MoNb), copper (Cu) and molybdenum niobium alloy (MTD). The thickness of the first source-drain electrode 3 and the second source-drain electrode 4 may be 1000 - 10000 Å. Among them, the first source-drain electrode 3, the second source-drain electrode 4, the first gate 5 and the active layer pattern 2 form a transistor.

[0099] In an exemplary embodiment, as Figure 10As shown, the second insulating layer 7 is disposed on a side of the third conductive layer away from the substrate 101 and covers the first source-drain electrode 3 and the second source-drain electrode 4. The material of the second insulating layer 7 may be silicon oxide (SiOx), or a stacked structure of silicon nitride (SiNx) and silicon oxide (SiOx). The thickness of the second insulating layer 7 may be 200 nm to 400 nm.

[0100] In an exemplary embodiment, as Figure 10 shown, the planarization layer 10 is disposed on a side of the second insulating layer 7 away from the substrate 101. The material of the planarization layer 10 may be an organic material, and the thickness of the planarization layer 10 may be 2 μm to 3 μm.

[0101] In an exemplary embodiment, as Figure 10 shown, the fourth conductive layer is disposed on a side of the planarization layer 10 away from the substrate 101. The fourth conductive layer includes a common electrode 30. The material of the common electrode 30 may be indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), and the thickness of the common electrode 30 may be 400 Å to 1000 Å.

[0102] In an exemplary embodiment, as Figure 10 shown, the fourth insulating layer 11 is disposed on a side of the fourth conductive layer away from the substrate 101 and covers the common electrode 30. The material of the fourth insulating layer 11 may be silicon oxide (SiOx), or a stacked structure of silicon nitride (SiNx) and silicon oxide (SiOx). The thickness of the fourth insulating layer 11 may be 1000 Å to 3000 Å.

[0103] In an exemplary embodiment, as Figure 10 shown, the fifth conductive layer is disposed on a side of the fourth insulating layer 11 away from the substrate 101. The fifth conductive layer includes a pixel electrode 40. A fourth via 60 is provided in each of the second insulating layer 7, the planarization layer 10, and the fourth insulating layer 11. The pixel electrode 40 is electrically connected to the second source-drain electrode 4 through the fourth via 60. The material of the pixel electrode 40 may be indium tin oxide (ITO) or indium zinc oxide (IZO), and the thickness of the pixel electrode 40 may be 40 nm to 135 nm.

[0104] In some embodiments, in the display substrate of the present disclosure, the first insulating layer includes at least one insulating layer pattern. The insulating layer pattern covers a part of the active layer pattern and does not cover the other part of the active layer pattern, that is, there is a non-overlapping area between the insulating layer pattern and at least part of the active layer pattern in the orthographic projection on the substrate, exposing at least part of the active layer pattern. The first source-drain electrode, the first gate electrode, and the second source-drain electrode are all located on the side of the first insulating layer away from the substrate. The first sub-electrodes of the first source-drain electrode and the second source-drain electrode are respectively electrically connected to the non-overlapping areas of the active layer pattern. For example, there is a non-overlapping area between the insulating layer pattern and the edge areas on both sides of the active layer pattern in the orthographic projection on the substrate, exposing the edge areas on both sides of the active layer pattern. The first sub-electrodes of the first source-drain electrode and the second source-drain electrode are respectively electrically connected to the edge areas on both sides of the active layer pattern; this reduces the preparation processes of forming the first vias and the second vias in the first insulating layer in the preparation process of the display substrate of the present disclosure, simplifies the preparation process, and reduces the production cost.

[0105] In some embodiments, in the display substrate of the present disclosure, the first gate electrode and the first source-drain electrode can be prepared from the same material by the same preparation process; the second source-drain electrode and the pixel electrode can be integrally formed, and the second source-drain electrode and the pixel electrode can be prepared from the same material by the same preparation process; thus, the preparation process of the display substrate of the present disclosure is simplified, and the production cost is reduced.

[0106] In some embodiments, in the display substrate of the present disclosure, the first source-drain electrode and the active layer pattern can be integrally formed to form a single-layer film structure, and the first source-drain electrode and the active layer pattern can be prepared from the same material by the same preparation process; the second source-drain electrode and the pixel electrode can be integrally formed, and the second source-drain electrode and the pixel electrode can be prepared from the same material by the same preparation process; thus, the preparation process of the display substrate of the present disclosure is simplified, and the production cost is reduced.

[0107] In some embodiments, in the display substrate of the present disclosure, the first insulating layer includes at least one insulating layer pattern. The insulating layer pattern covers a part of the active layer pattern and does not cover the other part of the active layer pattern, that is, there is a non-overlapping area between the insulating layer pattern and at least part of the active layer pattern in the orthographic projection on the substrate, exposing at least part of the active layer pattern. The first source-drain electrode, the first gate electrode, and the second source-drain electrode are all located on the side of the first insulating layer away from the substrate. The first sub-electrodes of the first source-drain electrode and the second source-drain electrode are respectively electrically connected to the non-overlapping areas of the active layer pattern. The first gate electrode and the first source-drain electrode can be prepared from the same material by the same preparation process; the second source-drain electrode and the pixel electrode can be integrally formed, and the second source-drain electrode and the pixel electrode can be prepared from the same material by the same preparation process; thus, the preparation process of the display substrate of the present disclosure is simplified, and the production cost is reduced.

[0108] In some embodiments, in the display substrate of the present disclosure, the first insulating layer in the substrate includes at least one insulating layer pattern. The insulating layer pattern covers a part of the active layer pattern, and does not cover a part of the active layer pattern, that is, there is a non-overlapping area in the orthographic projection of the insulating layer pattern and at least part of the active layer pattern on the substrate, exposing at least part of the active layer pattern. The first source-drain electrode, the first gate electrode, and the second source-drain electrode are all located on the side of the first insulating layer away from the substrate. The first source-drain electrode can be integrally formed with the active layer pattern to form a film structure, and the first source-drain electrode and the active layer pattern can be prepared from the same material through the same preparation process. The second source-drain electrode can be integrally formed with the pixel electrode, and the second source-drain electrode and the pixel electrode can be prepared from the same material through the same preparation process. Thereby, the preparation process of the display substrate of the present disclosure is simplified, and the production cost is reduced.

[0109] In some embodiments, the buffer layer can be cancelled in the display substrate of the present disclosure. In the display substrate of the present disclosure, the first source-drain electrode can be integrally formed with the active layer pattern to form a film structure, and the first source-drain electrode and the active layer pattern can be prepared from the same material through the same preparation process. The signal line is located on the side of the first source-drain electrode close to the substrate, and the signal line can be in electrical contact with the first source-drain electrode. The second source-drain electrode and the pixel electrode can be prepared from the same material through the same preparation process. The preparation process of the display substrate of the present disclosure is as follows: First, form a signal line on the substrate, then form a semiconductor thin film on the signal line, so that the semiconductor thin film forms an integrally formed first source-drain electrode and active layer pattern, and the first source-drain electrode is located on the side of the signal line away from the substrate, and the first source-drain electrode is in electrical contact with the signal line. Finally, form a first insulating layer on the side of the first source-drain electrode and the active layer pattern away from the substrate, form a first gate on the side of the first insulating layer away from the substrate, and an integrally formed second source-drain electrode and pixel electrode, and the second source-drain electrode is electrically connected to the active layer pattern. Thereby, the preparation process of the display substrate of the present disclosure is simplified, and the production cost is reduced.

[0110] In some embodiments, the embodiments of the present disclosure show that the buffer layer can be cancelled in the substrate. The embodiments of the present disclosure show that the first source-drain electrodes in the substrate can be integrally formed with the active layer pattern to form a film structure. The first source-drain electrodes and the active layer pattern can be prepared from the same material through the same preparation process. The signal line is located on the side of the first source-drain electrode away from the substrate, and the signal line can be in electrical contact with the first source-drain electrode. The second source-drain electrodes and the pixel electrodes can be prepared from the same material through the same preparation process. The preparation process of the substrate of the embodiments of the present disclosure is as follows: First, a semiconductor thin film is formed on the substrate, so that the semiconductor thin film forms integrally formed first source-drain electrodes and an active layer pattern. Then, a signal line is formed on the side of the first source-drain electrode away from the substrate, and the signal line is in electrical contact with the first source-drain electrode. Finally, a first insulating layer is formed on the side of the signal line away from the substrate, a first gate electrode is formed on the side of the first insulating layer away from the substrate, and integrally formed second source-drain electrodes and pixel electrodes are formed. The second source-drain electrodes are electrically connected to the active layer pattern. Thereby, the preparation process of the display substrate of the present disclosure is simplified, and the production cost is reduced.

[0111] In the embodiments of the present disclosure, the display substrate reduces the capacitance between the signal line and the first source-drain electrode by electrically contacting the signal line with the first source-drain electrode, ensures the stability of the transistor operation, and reduces the power consumption.

[0112] The present disclosure also provides a method for preparing a display substrate, including:

[0113] Forming an active layer pattern on a substrate;

[0114] Forming first source-drain electrodes on the substrate, and electrically connecting at least part of the first source-drain electrodes to the active layer pattern;

[0115] Forming a first gate electrode on the side of the active layer pattern away from the substrate, so that the orthographic projection of the first gate electrode and the active layer pattern on the substrate overlaps and does not contact each other;

[0116] Forming second source-drain electrodes on the side of the active layer pattern away from the substrate. The second source-drain electrodes include a first sub-electrode and a second sub-electrode connected to each other. The second sub-electrode is located on the side of the first sub-electrode close to the first gate electrode. The first sub-electrode is electrically connected to the active layer pattern, and the orthographic projection of the second sub-electrode and the active layer pattern on the substrate overlaps and does not contact each other.

[0117] The present disclosure also provides a display device, including the display substrate of the foregoing exemplary embodiments. The display device can be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0118] The accompanying drawings in this disclosure only relate to the structures involved in this disclosure. For other structures, reference may be made to the general design. Without conflict, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments.

[0119] Those of ordinary skill in the art should understand that the technical solutions of this disclosure can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of this disclosure, and all should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A substrate and at least one transistor disposed on the substrate; the transistor includes: An active layer pattern disposed on the substrate; A first source / drain electrode disposed on the substrate, the first source / drain electrode being electrically connected to the active layer pattern; A first gate electrode disposed on a side of the active layer pattern away from the substrate, a positive projection of the first gate electrode and the active layer pattern on the substrate overlaps, and they do not contact each other; A second source / drain electrode disposed on a side of the active layer pattern away from the substrate, the second source / drain electrode includes a first sub-electrode and a second sub-electrode connected to each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, a positive projection of the second sub-electrode and the active layer pattern on the substrate overlaps, and they do not contact each other.

2. The display substrate according to claim 1, wherein, The second source / drain electrode further includes a third sub-electrode, the third sub-electrode is located on a side of the first sub-electrode away from the first gate electrode, and a positive projection of the third sub-electrode and the active layer pattern on the substrate overlaps, and they do not contact each other.

3. The display substrate according to claim 1, wherein, The first sub-electrode and the second sub-electrode are integrally formed.

4. The display substrate according to claim 1, wherein, The first source / drain electrode includes a fourth sub-electrode and a fifth sub-electrode connected to each other, the fifth sub-electrode is located on a side of the fourth sub-electrode away from the first gate electrode, the fourth sub-electrode is electrically connected to the active layer pattern, a positive projection of the fifth sub-electrode and the active layer pattern on the substrate overlaps, and they do not contact each other.

5. The display substrate according to any one of claims 1 to 4, wherein, The transistor further includes a first insulating layer, the first insulating layer is located between the active layer pattern and the first gate electrode, the first insulating layer covers the active layer pattern, the first source / drain electrode, the first gate electrode and the second source / drain electrode are all located on a side of the first insulating layer away from the substrate, a first via hole and a second via hole are provided in the first insulating layer, the first source / drain electrode is electrically connected to the active layer pattern through the first via hole, and the second source / drain electrode is electrically connected to the active layer pattern through the second via hole.

6. The display substrate according to any one of claims 1 to 4, wherein, The transistor further includes a first insulating layer, the first insulating layer includes at least one insulating layer pattern, the insulating layer pattern covers part of the active layer pattern, and there is a non-overlapping region between the insulating layer pattern and at least part of the positive projection of the active layer pattern on the substrate, the first source / drain electrode, the first gate electrode and the second source / drain electrode are all located on a side of the first insulating layer away from the substrate, and the first source / drain electrode and the second source / drain electrode are respectively electrically connected to the non-overlapping regions of the active layer pattern.

7. The display substrate according to any one of claims 1 to 4, further comprising a pixel electrode disposed on a side of the transistor away from the substrate, and the pixel electrode is integrally formed with the second source-drain electrode.

8. The display substrate according to any one of claims 1 to 4, wherein, The first source / drain electrode is integrally formed with the active layer pattern.

9. The display substrate according to any one of claims 1 to 4, further comprising a signal line, and the signal line is electrically connected to the first source-drain electrode.

10. The display substrate according to claim 9, wherein, The signal line is located between the first source / drain electrode and the substrate, the display substrate further includes a buffer layer, the buffer layer is located between the signal line and the active layer pattern, a third via hole is provided in the buffer layer, and the first source / drain electrode is electrically connected to the signal line through the third via hole.

11. The display substrate according to claim 9, wherein, The first source-drain electrode is integrally formed with the active layer pattern, the signal line is in electrical contact with the first source-drain electrode, and the signal line is located on a side of the first source-drain electrode close to the substrate, or the signal line is located on a side of the first source-drain electrode away from the substrate.

12. The display substrate according to any one of claims 1 to 4, wherein, The material of the active layer pattern is an oxide semiconductor.

13. The display substrate according to any one of claims 1 to 4, wherein, The transistor is configured as a transistor in a gate driving circuit.

14. A display device, comprising the display substrate according to any one of claims 1 to 13.

15. A method for manufacturing a display substrate, comprising: Form an active layer pattern on a substrate; Form a first source-drain electrode on the substrate such that at least a part of the first source-drain electrode is electrically connected to the active layer pattern; Form a first gate electrode on a side of the active layer pattern away from the substrate such that a positive projection of the first gate electrode and the active layer pattern on the substrate overlaps and they do not contact each other; Form a second source-drain electrode on a side of the active layer pattern away from the substrate, the second source-drain electrode includes a first sub-electrode and a second sub-electrode connected to each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected to the active layer pattern, and a positive projection of the second sub-electrode and the active layer pattern on the substrate overlaps and they do not contact each other.

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