Quantum circuit processing method, device and electronic equipment

Abstract

The present disclosure provides a quantum circuit processing method, device and electronic device, which relates to the field of quantum computing technology, and specifically to the field of quantum circuit technology. The specific implementation scheme is: obtain the first instruction list of the first quantum circuit and the exchangeable characteristics of each operation instruction in the first instruction list, and the exchangeable characteristics indicate the exchangeability of the operation instruction with other operation instructions; based on the exchangeable characteristics, take the operation instruction in the first instruction list as a node to construct a first directed acyclic graph of the first quantum circuit, in which the action quantum bits have an intersection, and there is no directed edge between the corresponding nodes of different exchangeable operation instructions; based on the first directed acyclic graph, the first quantum circuit is equivalently compiled to obtain the second instruction list of the second quantum circuit, and the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit processing method, device and electronic device. Background Art

[0002] Quantum computing uses the unique operating rules of the quantum world to provide a new and very promising way of information processing. In many specific problems, quantum algorithms can bring advantages over classical algorithms. For example, using Shor's algorithm, large integers can be efficiently decomposed, and using Grover's algorithm, data searches can be performed faster. With the development of quantum theory, new quantum algorithms are constantly being proposed. How to efficiently simulate these algorithms or run them on real quantum hardware has always been an important issue.

[0003] At present, the classical simulation or real machine operation of quantum algorithms is mainly limited by the number of quantum bits. In classical simulation, the length of the column vector describing the quantum state grows exponentially with the number of corresponding bits (for example, the length of the column vector of an n-bit quantum state is 2 n ), it is difficult for classical computers to simulate large-scale quantum algorithms. Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support the simulation of algorithms with dozens of quantum bits at most. Therefore, it is necessary to compile quantum circuits into dynamic quantum circuits to reduce the number of quantum bits used.

[0004] Currently, a directed acyclic graph of a quantum circuit is constructed based on the execution order of quantum operations in the quantum circuit, so as to realize equivalent compilation of the quantum circuit based on the constructed directed acyclic graph. Summary of the invention

[0005] The present disclosure provides a quantum circuit processing method, device and electronic device.

[0006] According to a first aspect of the present disclosure, a quantum circuit processing method is provided, comprising:

[0007] Acquire a first instruction list of a first quantum circuit and an exchangeable feature of each operation instruction in the first instruction list, wherein the exchangeable feature indicates exchangeability of the operation instruction with other operation instructions;

[0008] Based on the exchangeable feature, the operation instructions in the first instruction list are used as nodes to construct a first directed acyclic graph of the first quantum circuit, wherein the action quantum bits have an intersection in the first directed acyclic graph, and there are no directed edges between the nodes corresponding to different exchangeable operation instructions;

[0009] Based on the first directed acyclic graph, the first quantum circuit is equivalently compiled to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

[0010] According to a second aspect of the present disclosure, there is provided a quantum circuit processing device, comprising:

[0011] An acquisition module, configured to acquire a first instruction list of a first quantum circuit and an exchangeable feature of each operation instruction in the first instruction list, wherein the exchangeable feature indicates exchangeability of the operation instruction with other operation instructions;

[0012] A construction module is used to construct a first directed acyclic graph of the first quantum circuit based on the exchangeable feature and using the operation instructions in the first instruction list as nodes, wherein the action quantum bits in the first directed acyclic graph have an intersection, and there are no directed edges between the nodes corresponding to different exchangeable operation instructions;

[0013] An equivalent compilation module is used to perform equivalent compilation on the first quantum circuit based on the first directed acyclic graph to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

[0014] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0015] at least one processor; and

[0016] a memory communicatively connected to at least one processor; wherein,

[0017] The memory stores instructions that can be executed by at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any method in the first aspect.

[0018] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute any one of the methods in the first aspect.

[0019] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, which implements any one of the methods in the first aspect when executed by a processor.

[0020] The technology disclosed in the present invention solves the problem of relatively poor equivalent compilation effect of quantum circuits in related technologies, can improve the effect of equivalent compilation of quantum circuits, and reduce the number of quantum bits required for the compiled dynamic quantum circuits.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0023] Figure 1 is a flowchart of a quantum circuit processing method according to the first embodiment of the present disclosure;

[0024] Figure 2 This is a schematic diagram of the structure of an example static quantum circuit;

[0025] Figure 3 is a schematic diagram of the structure of a static quantum circuit of another example;

[0026] Figure 4 yes Figure 3 The schematic diagram of the structure of converting the static quantum circuit shown into a dynamic quantum circuit;

[0027] Figure 5(a) is Figure 3 A schematic diagram of the structure of the directed acyclic graph corresponding to the static quantum circuit shown;

[0028] FIG5( b ) is a schematic diagram of the structure of the directed acyclic graph after adding directed edges;

[0029] FIG6( a ) is a schematic diagram of a static quantum circuit including a swappable structure;

[0030] FIG6( b ) is a schematic diagram of a static quantum circuit equivalent to FIG6( a );

[0031] Figure 7 It is a directed acyclic graph constructed for the dependency of the execution order of quantum operations shown in Figure 6(a);

[0032] Figure 8 It is a directed acyclic graph constructed based on the quantum circuit shown in Figure 6(a) and considering the commutativity between quantum operations;

[0033] Fig. 9 It is a schematic diagram comparing the compilation effects of different schemes on the maximum cut QAOA circuit;

[0034] Fig.10 This is one of the schematic diagrams comparing the compilability factors of different schemes for IQP circuits;

[0035] Fig.11 This is the second diagram comparing the compilability factors of different schemes for IQP circuits;

[0036] Fig.12 is a schematic structural diagram of a quantum circuit processing device according to a second embodiment of the present disclosure;

[0037] Fig.13 is a schematic block diagram of an example electronic device for implementing an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0039] First embodiment

[0040] like Figure 1 As shown, the present disclosure provides a quantum circuit processing method, comprising the following steps:

[0041] Step S101: obtaining a first instruction list of a first quantum circuit and an exchangeable feature of each operation instruction in the first instruction list, wherein the exchangeable feature indicates exchangeability of an operation instruction with other operation instructions.

[0042] In this embodiment, the quantum circuit processing method relates to the field of quantum computing technology, and in particular to the field of quantum circuit technology, which can be widely used in classical simulation and real machine operation scenarios of quantum circuits. The quantum circuit processing method of the disclosed embodiment can be executed by the quantum circuit processing device of the disclosed embodiment. The quantum circuit processing device of the disclosed embodiment can be configured in any electronic device to execute the quantum circuit processing method of the disclosed embodiment.

[0043] Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can only support algorithms that simulate dozens of qubits at most. For example, a laptop can simulate about 20-30 qubits, and a large supercomputer and cluster can simulate up to 30-40 qubits. In real machine operation, the scalability problem of current quantum chips has not yet been solved, resulting in a very limited number of qubits that a quantum computer can provide. Therefore, quantum circuit optimization is a fundamental issue in the field of quantum computing.

[0044] Quantum circuit optimization is a process that uses certain technical means to simplify a given quantum circuit to reduce the requirements for classical simulation and real-machine operation, thereby accelerating the research of quantum algorithms and the implementation of quantum computing in practical scenarios.

[0045] The quantum circuit processing of this embodiment can be a quantum circuit optimization process, and its purpose is to optimize and compile the quantum circuit so that the compiled quantum circuit can greatly simplify the original quantum circuit in terms of the number of quantum bits. On the one hand, it can further improve the scale of classical simulation of quantum algorithms and enhance the verification ability of classical computers on quantum algorithms. On the other hand, it can also reduce the bit number requirements of quantum algorithms on real machines, making up for the shortcomings of the current quantum chip scalability problem.

[0046] More specifically, the purpose of this embodiment is to compile a given quantum circuit into a dynamic quantum circuit to reduce the number of quantum bits in the quantum circuit and lower the requirements for its classical simulation and real machine operation.

[0047] Among them, dynamic quantum circuits are able to integrate classical communication and computing into quantum circuits by introducing intermediate circuit measurements of quantum bits and the ability to reset quantum bits to their ground state during calculations. This feature will greatly increase the diversity of circuits running on quantum hardware and is also crucial for the development of error-corrected and fault-tolerant quantum computing. Therefore, dynamic quantum circuits are expected to become an important part of many quantum applications in the future. In a mathematical sense and without experimental constraints, static and dynamic quantum circuits have the same computing power, that is, any problem that can be expressed by a dynamic quantum circuit can also be expressed as a static problem, so dynamic quantum circuits provide the possibility of a trade-off between circuit depth and width.

[0048] In addition, since the qubits in a dynamic quantum circuit can be reset and continue to be used in subsequent calculations, compared with a static quantum circuit, when running the same quantum algorithm, a dynamic quantum circuit can effectively reduce the number of qubits required for a computing task, and in theory, computing power is not affected in any way. For example, the Berstein-Vazirani algorithm, which requires n qubits in a static quantum circuit, can be implemented with only 2 qubits in a dynamic quantum circuit.

[0049] The quantum circuit model is introduced in detail below.

[0050] The quantum circuit model is a commonly used quantum computing model. The evolution of the quantum state is completed by performing quantum gate operations on the initial quantum state, and the calculation results are extracted through quantum measurements. The quantum circuit diagram represents the entire process of quantum circuit model calculation.

[0051] Figure 2 This is a schematic diagram of the structure of an example static quantum circuit. Figure 2 As shown, a quantum bit system can be represented by a horizontal line, and the quantum bits are numbered from top to bottom, where the quantum bit numbers often start from zero.

[0052] The direction of time evolution in the quantum circuit diagram is from left to right. The leftmost end is the initial quantum state, where each quantum bit is usually initialized to the zero state, and then different quantum gate operations are applied to the initial state in sequence to complete the evolution of the quantum state. At the same time, quantum measurements can be performed on certain quantum bits to obtain measurement results.

[0053] If a quantum circuit does not have any quantum measurement or quantum state preparation operations in the middle of the circuit, then such a circuit is called a static quantum circuit. An example of a static quantum circuit diagram is as follows: Figure 2 shown.

[0054] The operations in a quantum circuit diagram are usually represented by an ordered list of instructions in the order in which they are used. Each element in the list represents an instruction operation. Specifically,

[0055] Each quantum state preparation (or initialization) operation is represented by a four-element instruction [Reset, qubit, None, None]. For example, [Reset, 2, None, None] means initializing qubit 2 to the zero state.

[0056] Each single-qubit gate (such as H, X, Y, Z, S, T, Rx, Ry, Rz, etc.) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is the quantum bit acted on by the quantum gate, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [Rx, 2, π, None] means to apply an Rx rotation gate to the quantum bit on qubit 2, with a rotation angle of π.

[0057] Each two-qubit gate (such as a controlled NOT gate, CNOT gate, SWAP gate) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is a list of qubits that the two-qubit gate acts on. For a controlled quantum gate, qubit is a list of control bits and controlled bits, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [SWAP, [1, 2], None, None] means to act on SWAP gates between qubits 1 and 2; and [CNOT, [1, 3], None, None] means to act on qubits 1 and 3, where 1 is the control bit and 3 is the controlled bit.

[0058] Each multi-qubit gate (such as CCX gate) is represented by an instruction containing four elements [name, qubit, parameters, condition]. Among them, name is the name of the quantum gate, qubit is a list of qubits that the multi-qubit gate acts on, parameters are the parameters of the quantum gate (if there is no parameter, the default is None), and condition indicates which qubit measurement result controls the quantum gate operation (if there is no parameter, the default is None). For example, [CCX, [1, 2, 3], None, None] means to act on the CCX gate between qubits 1, 2, and 3, where 1 and 2 are control bits and 3 is a controlled bit.

[0059] A measurement in a computational basis is represented by a four-element instruction [Measure, qubit, None, None]. For example, [Measure, 2, None, None] represents a computational basis measurement on qubit 2.

[0060] Figure 2The instruction list of the static quantum circuit shown is: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[SWAP,[1,2],None,None],[Rx,0,α,None],[Ry,1,β,None],[Rz,2,γ,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0061] In some application scenarios, it is allowed to measure some quantum bits in the middle of a quantum circuit, and reset these quantum bits to zero state after the measurement results are obtained, so that they can be used for subsequent calculations. A quantum circuit that includes intermediate measurements and reset operations is called a dynamic quantum circuit. Figure 3 The static quantum circuit shown is transformed into a dynamic quantum circuit. Figure 4 As shown, it can be seen that the dynamic circuit reduces the number of quantum bits by one, but the operating effects of the two quantum circuits are equivalent.

[0062] Figure 3 The instruction list of the static quantum circuit shown is: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[CNOT,[1,2],None,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]].

[0063] Figure 4The circuit instruction list of the dynamic quantum circuit obtained after the equivalent compilation shown is: dynamic_circuit = [[Reset,0,None,None],[Reset,1,None,None],[H,0,None,None],[H,1,None,None],[CNOT,[0,1],None,None],[Measure,0,None,None],[Reset,0,None,None],[H,0,None,None],[CNOT,[1,0],None,None],[Measure,0,None,None],[Measure,1,None,None]].

[0064] A given static quantum circuit can be compiled into an equivalent dynamic quantum circuit, so that the number of quantum bits required for the compiled quantum circuit is less than the number of quantum bits in the original quantum circuit. The compilation problem of static quantum circuits can be transformed into an equivalent graph optimization problem. To ensure the equivalence of quantum circuits before and after compilation, it is necessary to ensure that the order of operation instructions with execution restrictions in the original static quantum circuit is not changed during compilation.

[0065] In the implementation process, the execution order of quantum circuit operation instructions can be represented by a directed acyclic graph. Each operation instruction in the quantum circuit corresponds to a node in the graph, and the execution order of the quantum circuit operation instructions can be represented by a directed acyclic graph. i Point to v j The directed edge of v i The corresponding operation instruction must be in v j The corresponding operation instruction is executed before execution.

[0066] For example, Figure 3 The directed acyclic graph corresponding to the static quantum circuit in is shown in Figure 5(a). Figure 3 The same as the operation instruction number in Figure 5(a). Figure 4 The dynamic quantum circuit is to Figure 3 The initialization operation on the quantum bit corresponding to quantum bit 2 (numbered 2) is postponed until the measurement operation on the quantum bit corresponding to quantum bit 0 (numbered 8), which is equivalent to adding a directed edge from node 8 to node 2 to the graph in the corresponding graph representation. As shown in Figure 5(b), the directed acyclic graph after adding the directed edge corresponds to the compiled dynamic quantum circuit.

[0067] At the same time, considering the specific problems of circuit compilation, the following restrictions need to be met in the graph optimization process: Since the directed acyclic graph represents the timing relationship of the execution of the operation instructions of the quantum circuit, it is necessary to ensure that the entire graph is still acyclic after adding directed edges; a quantum bit can only be used to perform operations on other quantum bits starting from the initialization operation after the measurement is completed. Therefore, the directed edges in the graph can only be connected between the nodes corresponding to the measurement operation instructions (hereinafter referred to as output nodes) and the nodes corresponding to the quantum bit initialization and reset operation instructions (hereinafter referred to as input nodes); a quantum bit can only be re-occupied by one other quantum bit at the same time after the measurement is completed. Therefore, at most one edge is added to each input / output node.

[0068] The purpose of this embodiment is to transform the compilation problem of the static quantum circuit into an equivalent graph optimization problem, and to compile the static quantum circuit into an equivalent dynamic quantum circuit by searching for directed edges from the output node to the input node in the directed acyclic graph of the static quantum circuit for connection. The more directed edges from the connected output node to the input node, the better the effect of the equivalent compilation, that is, the fewer quantum bits of the obtained dynamic quantum circuit.

[0069] However, in many scenarios, the order of action of quantum operations in quantum circuits is not unique. For example, in the instantaneous quantum polynomial (IQP) circuit, the general form of the IQP circuit is Here, H represents the Hadamard gate, and D is composed of a series of quantum gates diagonalized in the computational basis. For example, Quantum gates are randomly selected for construction in D, so the operation order of each quantum gate in D can be modified arbitrarily.

[0070] Another example is the Quantum Approximate Optimization Algorithm (QAOA) circuit, where the execution order of many quantum gates in the circuit is interchangeable, and these circuits do not have a predetermined structure. In other words, the order of some quantum gate operations in these quantum circuits is interchangeable, and has no effect on the final circuit operation results.

[0071] FIG6(a) and FIG6(b) are equivalent quantum circuits. The quantum circuit shown in FIG6(b) is obtained by exchanging the execution order of CZ gates numbered 5 and 6 in the quantum circuit shown in FIG6(a).

[0072] It is worth noting that for quantum circuits with commutative structures, imposing execution dependencies between commutative quantum operations may limit the opportunities for qubit reuse, and commutative structures are an important feature in quantum applications. For example, all CZ gates in Figure 6(a) are commutative. If these commutative properties are ignored when constructing a directed acyclic graph representation of a quantum circuit, unnecessary execution dependencies will be introduced in the directed acyclic graph.

[0073] like Figure 7 As shown in FIG. 6( a ), it is a directed acyclic graph constructed for the dependency of the execution order of the quantum operations shown in FIG. 6( a ). The directed edges 701 and 702 are introduced according to the mandatory dependency of the quantum gates shown in FIG. 6( a ), which results in Figure 7 At most, only one directed edge 703 from the output node to the input node can be added, that is, only one quantum bit can be reduced.

[0074] The purpose of this embodiment is to fully utilize the commutativity between quantum operations in the commutative structure for a quantum circuit containing a commutative structure, construct a directed acyclic graph of the quantum circuit, and perform equivalent compilation of the quantum circuit based on the directed acyclic graph to improve the compilation effect of the quantum circuit.

[0075] Figure 8 It is a directed acyclic graph constructed by utilizing the interchangeability between quantum operations in the interchangeable structure 601 as shown in FIG6(a). The constructed directed acyclic graph contains flexible dependencies and does not limit the execution dependencies of quantum operations numbered 4, 5, and 6. Two directed edges can be added from the output node to the input node, namely directed edge 801 and directed edge 802. Therefore, the compiled quantum circuit can reduce two quantum bits, and its equivalent compilation effect is better, which can make the quantum circuit equivalent compilation reduce the number of quantum bits by a greater magnitude.

[0076] The first quantum circuit may be a static quantum circuit, which includes a quantum measurement operation and a quantum gate operation, and the quantum measurement operation is always located after the quantum gate operation.

[0077] The order of action of quantum operations in the first quantum circuit can be represented by an ordered instruction list, which is the first instruction list. The representation method has been described in detail in the above description and will not be repeated here.

[0078] The first instruction list of the first quantum circuit may be obtained by pre-storing, or the first instruction list of the first quantum circuit input by a user may be obtained, which is not specifically limited here.

[0079] The interchangeability feature of an operation instruction characterizes the interchangeability of the operation instruction with other operation instructions. It has two properties: the first is to characterize whether the operation instruction is an interchangeable operation, and the second is to characterize whether the operation instruction is interchangeable with other operation instructions. The interchangeability feature can be represented by a numerical value or a character, which is not specifically limited here.

[0080] The exchangeable features of each operation instruction can be stored in an additional list, or in the parameters of the operation instruction, such as the group_tag parameter newly added to the operation instruction. Quantum operations with the same group_tag parameter can be exchanged in any order, while quantum operations belonging to different groups cannot be exchanged.

[0081] For non-commutative operation instructions, such as reset or measure operations, the group_tag parameter can be set to None. All commutative CZ gates in Figure 6(a) can be identified by a string 'a', so that the quantum circuit can be represented as the following ordered instruction list: static_circuit = [[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[Reset,3,None,None],[CZ,[0,1],None,'a'],[CZ,[2,3],None,'a'],[CZ,[1,2],None,'a'],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None],[Measure,3,None,None]].

[0082] Among them, the same exchangeable features indicate that the operation instructions are exchangeable. For example, the instruction list obtained by exchanging the order of the operation instructions [CZ, [2, 3], None, 'a'] and [CZ, [1, 2], None, 'a'] corresponds to the quantum circuit shown in Figure 6(b).

[0083] The exchangeable features may be obtained by manual annotation or automatically by electronic devices, which is not specifically limited here.

[0084] Step S102: Based on the exchangeable feature, the operation instructions in the first instruction list are used as nodes to construct a first directed acyclic graph of the first quantum circuit, in which the action quantum bits have an intersection and there are no directed edges between the nodes corresponding to different exchangeable operation instructions.

[0085] The first directed acyclic graph includes nodes corresponding to instructions in the first instruction list and directed edges between the nodes. The directed edges between the nodes are used to characterize the timing relationship between different operation instructions in the first instruction list, and the path formed by the directed edges between the nodes does not include a directed loop.

[0086] In constructing the first directed acyclic graph, it is necessary to avoid adding directed edges between nodes corresponding to exchangeable operation instructions. In an optional implementation, the first instruction list can be traversed in the order of instruction arrangement from left to right, and the instruction sublist in the first instruction list that is sorted before the instruction currently traversed and the first qubit acted on by the instruction currently traversed are obtained; the instruction sublist is traversed in the order of instruction arrangement from right to left, and the operation instruction whose acted qubit and the first qubit have an intersection is obtained; the exchangeable feature of the operation instruction is compared with the exchangeable feature of the instruction currently traversed. If the comparison result indicates that the two are not exchangeable, the identifier of the operation instruction is used as the source node and the identifier of the instruction currently traversed is used as the target node to construct a directed edge; if the comparison result indicates that the two are exchangeable, the instruction sublist is continued to be traversed to search for an operation instruction that is not exchangeable with the instruction currently traversed, and a directed edge between the two is constructed. When the traversal of the first instruction list is completed, the first directed acyclic graph is obtained based on the constructed directed edge.

[0087] In another embodiment, optionally, step S102 specifically includes:

[0088] forwardly traverse the first instruction list according to the arrangement order of the operation instructions;

[0089] Taking the first operation instruction currently traversed as a node, and if the first list is not an empty list, based on the exchangeable characteristics of the operation instructions in the first list, constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction; the target operation instruction is not exchangeable with the first operation instruction, and the first list is a list corresponding to the quantum bits acted upon by the first operation instruction;

[0090] The first operation instruction is added to the end of the first list, and the first directed acyclic graph is obtained when the traversal of the first instruction list is completed.

[0091] In this way, by creating a list corresponding to each quantum bit to store its corresponding operation instructions in order, it is very convenient to find the predecessor operation instruction associated with each operation instruction, and search for the target operation instruction from the predecessor operation instruction to construct a directed edge between the target operation instruction and the operation instruction, so that the first directed acyclic graph can be constructed very quickly and at high speed.

[0092] Among them, the target operation instruction is not interchangeable with the first operation instruction, and it is the operation instruction that is closest to the position of the first operation instruction and is not interchangeable with the first operation instruction. That is, by comparing the interchangeable features of the operation instructions in the first list with the interchangeable features of the first operation instruction, the target operation instruction in the first list that is closest to the position of the first operation instruction and is not interchangeable with the first operation instruction can be searched to build a dependency relationship between the two and add a directed edge between the two. In this way, dependencies can be added only between non-interchangeable operation instructions, and it can be avoided to impose a forced dependency between the corresponding nodes of the operation instructions of the exchangeable structure in the directed acyclic graph, so that the dependency between the corresponding nodes of the operation instructions in the directed acyclic graph is more flexible, that is, the execution dependency between the exchangeable operation instructions is not limited in the directed acyclic graph, so that there are more candidate directed edges from the output node to the input node that can be added in the directed acyclic graph.

[0093] Afterwards, the first operation instruction is added to the end of the first list as a preceding operation instruction of the next traversal. Accordingly, when the traversal of the first instruction list is completed, the construction of the directed acyclic graph of the quantum circuit is completed, and the first directed acyclic graph can be obtained. In this way, the first directed acyclic graph with flexible dependencies can be constructed very quickly and at high speed.

[0094] Step S103: Based on the first directed acyclic graph, equivalently compile the first quantum circuit to obtain a second instruction list of a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is smaller than the number of quantum bits of the first quantum circuit.

[0095] Wherein, the step S103 specifically includes:

[0096] Adding a target directed edge from the output node to the input node in the first directed acyclic graph to obtain a second directed acyclic graph;

[0097] Based on the second directed acyclic graph, the second list consisting of the added target directed edges, and the first instruction list, the first quantum circuit is equivalently compiled to obtain a second instruction list for a second quantum circuit.

[0098] Based on the first directed acyclic graph, and the input node list and output node list of the first directed acyclic graph, a target directed edge from the output node to the input node can be added in the first directed acyclic graph to obtain a second directed acyclic graph, wherein the second directed acyclic graph includes the target directed edge and the directed edges in the first directed acyclic graph, and the path formed by the target directed edge and the directed edges in the first directed acyclic graph does not include a directed loop.

[0099] Among them, the input node list includes nodes corresponding to the reset operation instruction type in the first instruction list, the output node list includes nodes corresponding to the quantum measurement operation instruction type in the first instruction list, and in the second directed acyclic graph, each output node is connected to at most one input node, and different output nodes cannot be connected to the same input node.

[0100] In this step, since one quantum circuit is compiled into another quantum circuit, it is essentially to reset and recycle the measured quantum bits for use in subsequent instructions. Corresponding to the first directed acyclic graph, it is equivalent to adding directed edges from output nodes to input nodes to the graph as much as possible to indicate that the measured bits are reset and reused, which can reduce the number of quantum bits required in the quantum circuit.

[0101] In order to ensure the equivalence of the compiled quantum circuit with the original quantum circuit and to ensure the timing relationship between the instructions in the quantum circuit, the following constraints need to be met when adding directed edges:

[0102] 1) In order to make the entire graph still conform to the timing relationship of the circuit instructions, it is necessary to ensure that the entire graph is still acyclic after adding more directed edges. It should be noted that the direction of the directed edges in the graph represents the timing relationship of the instructions, and the ring structure will destroy this relationship. That is, after adding directed edges, there should still be no ring structure path in the graph (called a directed loop);

[0103] 2) Each output node can only be connected to one input node at most, indicating that after the output node is measured, the input node it points to continues to perform operations on the qubit;

[0104] 3) Different output nodes cannot be connected to the same input node.

[0105] Correspondingly, after adding the target directed edge that meets the above constraints to the first directed acyclic graph, a second directed acyclic graph can be obtained.

[0106] A brute force search method, a heuristic search method, or a combination of the two can be used to determine the target directed edge from the output node to the input node added in the first directed acyclic graph to obtain the second directed acyclic graph. In some embodiments, the target directed edge from the output node to the input node added in the first directed acyclic graph can be determined based on the candidate edge matrix of the first directed acyclic graph, and the candidate edge matrix is ​​used to characterize the connectivity of the output node to the input node in the first directed acyclic graph.

[0107] Afterwards, the first quantum circuit can be equivalently compiled based on the second directed acyclic graph, the second list consisting of the target directed edges, and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

[0108] After adding a directed edge from the output node to the input node, the timing relationship between the nodes can be determined based on the second directed acyclic graph, and the first instruction list can be reordered based on the timing relationship. Afterwards, the relationship between the input node and the output node in the second list can be used to equivalently compile instructions that act on other quantum bits (i.e., the quantum bits acted on by the instructions corresponding to the input nodes that are directionally connected to the output nodes corresponding to the measurement operation instruction) after the measurement operation instruction into instructions that act on the quantum bits acted on by the measurement operation instruction. In this way, equivalent compilation of the first quantum circuit can be achieved, and a second instruction list for a second quantum circuit equivalent to the first quantum circuit can be obtained, and the quantum bits required in the second quantum circuit are fewer than the quantum bits required in the first quantum circuit.

[0109] In this embodiment, by obtaining the exchangeable feature of each operation instruction in the first instruction list of the first quantum circuit, based on the exchangeable feature, the operation instruction in the first instruction list is used as a node to construct a first directed acyclic graph of the first quantum circuit, so that in the first directed acyclic graph, the action quantum bits have an intersection, and there is no directed edge between the nodes corresponding to different exchangeable operation instructions. In this way, dependencies can be added only between non-exchangeable operation instructions, and it can be avoided to impose a forced dependency between the nodes corresponding to the exchangeable operation instructions in the directed acyclic graph, so that the dependency between the nodes corresponding to the operation instructions in the directed acyclic graph is flexible, so that more directed edges from the output node to the input node can be added in the constructed directed acyclic graph, thereby improving the effect of quantum circuit equivalent compilation, reducing the number of quantum bits required for the compiled dynamic quantum circuit, and compared with the equivalent compilation of quantum circuits by directed acyclic graphs based on forced dependencies, the quantum circuit equivalent compilation can reduce the number of quantum bits by a larger magnitude.

[0110] Optionally, constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction based on the exchangeable feature of the operation instructions in the first list includes:

[0111] In the case where it is determined based on the exchangeable feature that the second operation instruction is not exchangeable, determining the second operation instruction as the target operation instruction; the second operation instruction is the operation instruction at the end of the first list;

[0112] Add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

[0113] In this embodiment, if the exchangeable feature of the second operation instruction at the end of the first list is None, it can be indicated that the second operation instruction is not exchangeable. At this time, the first operation instruction and the second operation instruction have an execution dependency relationship, and the second operation instruction can be added to the target directed edge of the first operation instruction, which will not introduce unnecessary dependencies and can ensure the accuracy of the dependencies between the quantum operations of the first quantum circuit represented by the constructed directed acyclic graph.

[0114] Optionally, constructing a directed edge from a node corresponding to a target operation instruction in the first list to a node corresponding to the first operation instruction based on the exchangeable feature of the operation instructions in the first list includes:

[0115] In the case where it is determined that the second operation instruction is exchangeable based on the exchangeable feature, comparing the exchangeable feature of the operation instruction in the first list with the exchangeable feature of the first operation instruction to obtain a comparison result;

[0116] Based on the comparison result, at least one target operation instruction of a previous group of the first operation instruction is obtained from the first list to obtain a first sub-list, wherein different target operation instructions in the same group are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction;

[0117] Add each target operation instruction corresponding node in the first sublist to the directed edge of the first operation instruction corresponding node.

[0118] In this embodiment, if the exchangeable feature of the second operation instruction at the end of the first list is not None, it can be indicated that the second operation instruction is exchangeable. In this scenario, the exchangeable feature of the operation instruction in the first list and the exchangeable feature of the first operation instruction can be compared to search for at least one target operation instruction of the previous group of the first operation instruction from the first list, and the directed edge of each target operation instruction corresponding node in the first sublist to the first operation instruction corresponding node is added accordingly to obtain the first directed acyclic graph.

[0119] When the operation instructions are non-interchangeable, they can form a group alone. When the exchangeable characteristics of two operation instructions are not None and are the same, the two belong to the same group. When the exchangeable characteristics of two operation instructions are different, the two belong to different groups.

[0120] The previous group of the first operation instruction refers to the group that is arranged before the first operation instruction and is closest to the position of the first operation instruction. For example, the exchangeable characteristics of the operation instructions in the first list are node 1: 'None', node 2: 'None', node 3: 'b', node 4: 'b', and their groups are two groups with exchangeable characteristics of 'None' and a group with exchangeable characteristics of 'b', respectively. The exchangeable characteristics of the first operation instruction are 'a' or 'None'. As the first instruction list is traversed, the preceding operation instruction associated with the first operation instruction is placed at the end of the first list. Therefore, the group with exchangeable characteristics of 'b' is closer to the first operation instruction in the first instruction list, and the previous group of the first operation instruction is the group with exchangeable characteristics of 'b'.

[0121] Among them, in some scenarios, the previous group may be a non-interchangeable group, which contains only one target operation instruction. In other scenarios, the previous group may be an interchangeable group different from the first operation instruction group, which may include at least one target operation instruction.

[0122] For example, the exchangeable characteristics of the operation instructions in the first list are node 1: 'None', node 2: 'None', node 3: 'a', node 4: 'a', and the exchangeable characteristic of the first operation instruction is 'a'. Then the previous group of the first operation instruction obtained from the first list only includes the target operation instruction corresponding to node 2.

[0123] For another example, the exchangeable characteristics of the operation instructions in the first list are node 1: 'None', node 2: 'None', node 3: 'b', node 4: 'b', and the exchangeable characteristic of the first operation instruction is 'a' or 'None', then the previous group of the first operation instruction obtained from the first list includes the target operation instruction corresponding to node 3 and the target operation instruction corresponding to node 4.

[0124] In an optional embodiment, by obtaining each group of operation instructions in the first list and the operation instructions of each group, the interchangeable characteristics of each group can be compared with the interchangeable characteristics of the first operation instruction, and an adjacent group that is different from the group of the first operation instruction and is located before the first operation instruction group is selected, and the adjacent group is the previous group of the first operation instruction.

[0125] In another optional implementation, at least one target operation instruction of the previous group of the first operation instruction may be obtained from the first list by traversing the first list in reverse and comparing the exchangeable features of its operation instructions with the exchangeable features of the first operation instruction.

[0126] All target operation instructions of the previous group of the first operation instruction may be obtained first, and then a directed edge from a node corresponding to each target operation instruction to a node corresponding to the first operation instruction may be added. Alternatively, each time a target operation instruction is obtained, a directed edge from a node corresponding to the target operation instruction to a node corresponding to the first operation instruction may be added until the directed edge is added.

[0127] In this way, by obtaining at least one target operation instruction of the previous group of the first operation instruction and adding the target operation instruction to the directed edge of the first operation instruction, it will not introduce unnecessary dependencies and can ensure the accuracy of the dependencies between the quantum operations of the first quantum circuit represented by the constructed directed acyclic graph.

[0128] Optionally, based on the comparison result, obtaining at least one target operation instruction of a previous group of the first operation instruction from the first list to obtain a first sub-list includes:

[0129] When the comparison result indicates that the exchangeable feature of the second operation instruction is the same as the exchangeable feature of the first operation instruction, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions;

[0130] In a case where the first target operation instruction is not exchangeable, obtaining the first sub-list, wherein the first sub-list only includes the first target operation instruction;

[0131] In the case that the first target operation instruction is exchangeable, other target operation instructions having the same exchangeable feature as the first target operation instruction are acquired to obtain the first sub-list.

[0132] In this embodiment, the second operation instruction is the operation instruction at the end of the first list. If the first operation instruction is exchangeable, and the exchangeable feature of the second operation instruction is the same as the exchangeable feature of the first operation instruction, it means that the second operation instruction and the first operation instruction belong to the same group of exchangeable groups, and at this time, a directed edge between the two cannot be added.

[0133] By traversing the first list in reverse, and comparing the exchangeable features of the operating instructions in the first list with the exchangeable features of the first operating instruction, a target operating instruction different from the exchangeable features of the first operating instruction can be searched. It is determined whether the target operating instruction is exchangeable. If not, the previous group of the first operating instruction only includes one target operating instruction. If it is exchangeable, it is necessary to continue the reverse traversal. If there are other operating instructions with the same exchangeable features as the target operating instruction, they are obtained and classified into the previous group of the first operating instruction. In this way, all target operating instructions in the previous group of the first operating instruction can be searched. In this way, all target operating instructions in the previous group of the first operating instruction can be quickly and accurately obtained.

[0134] Optionally, based on the comparison result, obtaining at least one target operation instruction of a previous group of the first operation instruction from the first list to obtain a first sub-list includes:

[0135] If the comparison result indicates that the exchangeable characteristic of the second operation instruction is different from the exchangeable characteristic of the first operation instruction, determining the second operation instruction as the target operation instruction;

[0136] Other target operation instructions having the same exchangeable characteristic as the second operation instruction are acquired to obtain the first sub-list.

[0137] In this embodiment, the second operation instruction is the last operation instruction in the first list. If the first operation instruction is exchangeable, and the exchangeability feature of the second operation instruction is different from the exchangeability feature of the first operation instruction, then the second operation instruction and the first operation instruction belong to different groups.

[0138] By traversing the first list in reverse, searching for other target operation instructions with the same interchangeable characteristics as the second operation instruction in the first list, all target operation instructions in the previous group of the first operation instruction can be searched. In this way, all target operation instructions in the previous group of the first operation instruction can be quickly and accurately obtained.

[0139] In one implementation, based on the exchangeable feature, the specific process of constructing a directed acyclic graph of a quantum circuit is as follows:

[0140] Input: static quantum circuit instruction list Static_Circuit, quantum circuit width n;

[0141] Output: directed acyclic graph Digraph, input node list Inputs, output node list Outputs.

[0142] Step 1: Initialize an empty directed acyclic graph Digraph; initialize a list Causal_Lists of length n, each element is initialized to an empty list; initialize two lists Inputs and Outputs of length n, each element is initialized to None;

[0143] Step 2: Loop through Static_Circuit, and set the element currently being traversed to be Instruction, i.e. the first operation instruction, and its index to be Index:

[0144] Step 2.1: Add a node Vertex to the directed acyclic graph Digraph, whose identifier is Index;

[0145] Step 2.2: If Instruction is a qubit reset operation, obtain the qubit qubit it acts on, and modify the value of qubit indexed in the Inputs list to Index; if Instruction is a qubit measurement operation, obtain the qubit qubit it acts on, and modify the value of qubit indexed in the Outputs list to Index;

[0146] Step 2.3: Record the group_tag parameter of the Instruction instruction as Group; obtain the qubit value in the Instruction instruction and traverse it, set the current element to q, find the list Causal_Lists[q], that is, the last element of the first list, and record it as PreVertex;

[0147] Step 2.3.1: If PreVertex is not an empty element, record the group_tag parameter of the operation instruction corresponding to PreVertex as PreGroup, and initialize the SameGroup list to an empty list;

[0148] Step 2.3.2: If PreGroup is None, add a directed edge from PreVertex to Vertex to the directed acyclic graph Digraph, and then execute step 3;

[0149] Step 2.3.3: If PreGroup is the same as Group, perform a reverse loop traversal of the Causal_Lists[q] list, set the currently traversed element as CurrentVertex, and record the group_tag parameter of the instruction corresponding to CurrentVertex as CurrentGroup; if CurrentGroup is the same as Group, continue to loop through the next element; if CurrentGroup is different from Group, perform operation a or operation b; where, operation a: if CurrentGroup is None, add a directed edge from CurrentVertex to Vertex to the directed acyclic graph Digraph, and then perform step 3; operation b: if CurrentGroup is not None, set the value of PreGroup to CurrentGroup; record all nodes in the Causal_Lists[q] list whose group_tag parameter is equal to PreGroup in the SameGroup list;

[0150] Step 2.3.4: If PreGroup is different from Group, reverse the loop of Causal_Lists[q] and record all nodes in Causal_Lists[q] whose group_tag parameter is equal to PreGroup into the SameGroup list;

[0151] Step 2.3.5: Add a directed edge pointing to Vertex for each node in SameGroup to the directed acyclic graph Digraph;

[0152] Step 3: Add Vertex to the end of the list Causal_Lists[q];

[0153] Step 4: Return Digraph, Inputs, Outputs as output.

[0154] It can be seen that for quantum operations with intersections of acting quantum bits, if the order can be interchanged, it is necessary to avoid adding execution dependencies between the two (i.e., adding directed edges). The operation instructions on each quantum bit can be saved through a list Causal_Lists, and the list indexed by q saves all the operation instructions on quantum bit q according to their relative order in the first instruction list. The instruction list of the static quantum circuit can be traversed, and each operation instruction corresponding node can be added in the directed acyclic graph. Traverse the quantum bits involved in the operation instruction, check the previous operation instruction on each quantum bit, and if the previous operation instruction is not interchangeable, just add a directed edge from the previous operation instruction corresponding node to the current operation instruction. If the previous quantum operation is interchangeable, it is necessary to check whether the previous operation instruction and the current operation instruction belong to the same group. If not, the group to which the previous operation instruction belongs in Causal_Lists is determined as the previous interchangeable group of the currently traversed operation instruction. If it belongs, reversely traverse the Casual_List of the quantum bit and determine the previous group of the currently traversed operation instruction. If the previous group is a non-commutative operation group, then only one directed edge needs to be added from the non-commutative operation instruction corresponding node to the current operation instruction corresponding node. Conversely, if the previous commutative group is determined, then all the operation instruction corresponding nodes on the qubit belonging to the previous commutative group need to be connected to the current operation instruction corresponding node.

[0155] Taking a method of heuristic search as an example, the step of adding a target directed edge from an output node to an input node in the first directed acyclic graph to obtain a second directed acyclic graph includes:

[0156] Determine target directed edges from the candidate directed edges of the first directed acyclic graph in sequence, and add the target directed edges in sequence until there is no directed edge from the output node to the input node in the directed acyclic graph obtained after adding the target directed edges, thereby obtaining a second directed acyclic graph;

[0157] Among them, the target directed edge is the candidate directed edge with the largest score value among the candidate directed edges based on the first directed acyclic graph, and the score value is used to characterize the total number of directed edges that can be connected from the output node to the input node in the third directed acyclic graph, and the third directed acyclic graph is obtained after adding the candidate directed edges to the first directed acyclic graph.

[0158] Optionally, the score value of the candidate directed edge is determined by:

[0159] Obtaining a candidate edge matrix of a first directed acyclic graph, wherein elements in the candidate edge matrix are used to characterize the connectivity from an output node to an input node in the first directed acyclic graph;

[0160] For the candidate directed edge corresponding to the target element in the candidate edge matrix, obtain the column index whose element value in the row corresponding to the target element is a first value to obtain a first set, and obtain the row index whose element value in the column corresponding to the target element is the first value to obtain a second set, wherein the first value indicates that the output node is not connectable to the input node;

[0161] Performing a Cartesian product on the second set and the first set to obtain a third list;

[0162] Update the first element in the candidate edge matrix to a first value to obtain a target matrix, wherein the first element includes the elements indicated by the third list, the target element, and each element indicated by a row corresponding to the row index of the target element and each element indicated by a column corresponding to the column index of the target element;

[0163] Based on the number of elements in the target matrix whose element values ​​are second values, a score value of the candidate directed edge corresponding to the target element is determined, wherein the second value indicates that the output node is connectable to the input node.

[0164] That is, in an optional implementation manner, the specific process of this embodiment is as follows:

[0165] Acquire a first instruction list of a first quantum circuit and an exchangeable feature of each operation instruction in the first instruction list, wherein the exchangeable feature indicates exchangeability of the operation instruction with other operation instructions;

[0166] Based on the exchangeable feature, the operation instructions in the first instruction list are used as nodes to construct a first directed acyclic graph of the first quantum circuit, wherein the action quantum bits have an intersection in the first directed acyclic graph, and there are no directed edges between the nodes corresponding to different exchangeable operation instructions;

[0167] Obtaining a candidate edge matrix of the first directed acyclic graph by using a graph search algorithm such as a depth-first search algorithm;

[0168] A heuristic search method is used to obtain all target directed edges from output nodes to input nodes that can be added to the first directed acyclic graph of the first quantum circuit;

[0169] According to the second directed acyclic graph after adding the target directed edge, the first quantum circuit is compiled into an equivalent second quantum circuit.

[0170] Obviously, due to the restrictions of the directed acyclic graph conditions, not all edges pointing from output nodes to input nodes can be added to the graph. For example, in Figure 5(a), adding an edge from node 9 to node 2 will introduce a loop structure of 2→5→7→9→2. In fact, after obtaining the graph representation of the static quantum circuit, all edges that do not directly introduce a loop structure can be obtained through a graph search algorithm. If there is no path between the input node with index i and the output node with index j in the directed acyclic graph corresponding to the static quantum circuit, that is, the input node i cannot reach the output node j, then connecting the output node with index j and the input node with index i will not directly introduce a loop in the graph, so such an edge is a candidate directed edge.

[0171] Assume that a static quantum circuit contains n input nodes and m output nodes. All candidate directed edges can be stored in an m×n matrix, called a candidate edge matrix. The jth row corresponds to the output node with index j, and the ith column corresponds to the input node with index i. The matrix element (j, i) = 1 indicates that the edge between the output node with index j and the input node with index i is a candidate directed edge; otherwise, the matrix element is 0.

[0172] The candidate edge matrix can be obtained based on the depth-first algorithm, and the process is as follows:

[0173] Input: directed acyclic graph Digraph, input node list Inputs, output node list Outputs;

[0174] Output: candidate edge matrix C.

[0175] Step 1: Get the length of the input and output node lists, denoted as n and m respectively;

[0176] Step 2: Initialize an m×n matrix C of all zeros;

[0177] Step 3: Loop through the input node list Inputs, and set the element currently being looped to be Input, and its index to be i;

[0178] Step 3.1: Loop through the output node list Outputs, set the element currently being looped to Output, and its index is j; search the Digraph using a depth-first algorithm or other algorithm to see if there is a path from Input to Output; if the path does not exist, set the matrix element (j,i) of the matrix C to 1; if the path exists, do not perform any operation and continue looping the next element;

[0179] Step 4: Return the candidate edge matrix C as output.

[0180] Since unnecessary dependencies between commutative quantum operations are avoided when constructing a directed acyclic graph, the generated directed acyclic graph actually contains more candidate directed edges, which helps to add more candidate directed edges to the directed acyclic graph, thereby improving the equivalent compilation effect of the quantum circuit.

[0181] For example, based on Figure 7 The candidate edge matrix generated by the directed acyclic graph shown is: based on Figure 8 The candidate edge matrix generated by the directed acyclic graph shown is: It can be seen that based on Figure 8 The generated candidate edge matrix is ​​relative to the Figure 7 The generated candidate edge matrix contains at most two candidate directed edges.

[0182] A greedy strategy can be used to determine and add a target directed edge from the output node to the input node in the first directed acyclic graph based on the candidate edge matrix. The specific process can be as follows:

[0183] Input: the directed acyclic graph Digraph (i.e., the first directed acyclic graph) corresponding to the static quantum circuit, the input node list Inputs and the output node list Outputs of the directed acyclic graph Digraph, and the candidate edge matrix C;

[0184] Output: Modified_Digraph, the directed acyclic graph after the target directed edge is added, and Added_Edges (the second list), the list of all target directed edges added to the directed acyclic graph.

[0185] Step 1: Get the length of the input and output node lists, denoted as n and m respectively;

[0186] Step 2: Initialize an empty list Added_Edges;

[0187] Step 3: When the candidate edge matrix is ​​not a zero matrix, perform the following operations;

[0188] Step 3.1: Initialize an m×n zero matrix S;

[0189] Step 3.2: Traverse the non-zero matrix elements of matrix C, set the currently traversed matrix element to (i, j); initialize a matrix C i,j =C; the matrix C i,j The column indices of all 0 elements in the i-th row are recorded as a set R i ; The matrix C i,j The row indices of all 0 elements in the jth column are recorded as a set T j ; Calculate the set T j and R iThe Cartesian product of is recorded as a Pairs list; traverse the Pairs list, and set the element currently traversed to (u, v); i,j Set the matrix elements (u,v) of i,j All matrix elements in row i and column j are set to 0; calculate the matrix C i,j The sum of all matrix elements is recorded as Score; the matrix element (i, j) of matrix S is set to Score+1;

[0190] Step 3.3: Get all matrix elements with the highest score in matrix S and record them as Max_Score;

[0191] Step 3.4: Randomly select a matrix element from Max_Score and record it as (t,r);

[0192] Step 3.5: Add the directed edge (Outputs[t], Inputs[r]) to Added_Edges;

[0193] Step 3.6: Update the matrix C to matrix C t,r ;

[0194] Step 4: Add all directed edges in Added_Edges to the Digraph;

[0195] Step 5: Return Modified_Digraph and Added_Edges as output.

[0196] In this way, the target directed edges are determined in sequence by a heuristic method and the maximum candidate edge greedy strategy, until there are no directed edges from the output node to the input node that can be added in the first directed acyclic graph. This improves the efficiency of the directed edge search while ensuring the superiority of the directed edge search.

[0197] After obtaining all the target directed edges that can be added to the directed acyclic graph, the directed acyclic graph corresponding to the compiled dynamic quantum circuit is obtained. In order to further compile it into a dynamic quantum circuit instruction list, a feasible dynamic quantum circuit instruction execution order can be obtained by topologically sorting the updated directed acyclic graph. The topological sorting of a directed acyclic graph refers to a linear arrangement of nodes in the graph, so that for all directed edges (u, v) in the graph, node u appears in front of node v. Since the directed acyclic graph contains the order of execution of circuit operation instructions, the topologically sorted list also corresponds to a feasible instruction execution order list. The topologically sorted list can be traversed, and the quantum bits corresponding to the operation instructions can be updated according to the added target directed edges, so that the second instruction list of the compiled dynamic quantum circuit can be obtained.

[0198] The process of equivalently compiling the first quantum circuit based on the second directed acyclic graph to obtain the dynamic quantum circuit, i.e., the second quantum circuit, is as follows:

[0199] Input: the instruction list Static_Circuit of the first quantum circuit, the directed acyclic graph Digraph after adding the target directed edge, i.e. the second directed acyclic graph, and the second list Added_Edges;

[0200] Output: The instruction list of the dynamic quantum circuit Dynamic_Circuit.

[0201] Step 1: Initialize two empty lists Topological_order and Dynamic_Circuit;

[0202] Step 2: Topologically sort the Digraph and store the results in the Topological_order list;

[0203] Step 3: Loop through the Topological_order list and set the currently traversed element as Vertex;

[0204] Step 3.1: Add the element with index Vertex in the Static_Circuit list to the end of the Dynamic_Circuit list;

[0205] Step 4: Loop through the Added_Edges list and set the currently looped element to Edge;

[0206] Step 4.1: Record the two nodes of Edge as Tail and Head respectively;

[0207] Step 4.2: Record the qubits acted upon by the instructions indexed as Head and Tail in the Static_Circuit list as q i and q j ;

[0208] Step 4.3: Loop through the Dynamic_Circuit list, set the currently traversed element to be Instruction; loop through the list of qubits that Instruction acts on, set the currently traversed element to be q; if q = q i , then update q to q j ;

[0209] Step 5: Return the Dynamic_Circuit list as output.

[0210] In this way, the second directed acyclic graph can be effectively utilized to easily implement equivalent compilation of the first quantum circuit.

[0211] For an input static quantum circuit, the complete dynamic quantum circuit compilation scheme is as follows:

[0212] Input: static quantum circuit instruction list Static_Circuit;

[0213] Output: dynamic quantum circuit instruction list Dynamic_Circuit;

[0214] Step 1: Get the input static quantum circuit width, denoted as n;

[0215] Step 2: Based on Static_Circuit and n, construct the directed acyclic graph Digarph of the static quantum circuit, the input node list Inputs and the output node list Outputs;

[0216] Step 3: Based on Digraph, Inputs and Outputs, obtain the candidate edge matrix C of the directed acyclic graph Digarph;

[0217] Step 4: Based on Digraph, Inputs, Outputs and C, obtain the directed acyclic graph Modified_Digraph after adding the target directed edge and the list Added_Edges consisting of all target directed edges added to the directed acyclic graph;

[0218] Step 5: Perform equivalent compilation of the static quantum circuit based on Static_Circuit, Modified_Digraph and Added_Edges to obtain the dynamic quantum circuit instruction list Dynamic_Circuit;

[0219] Step 6: Return the Dynamic_Circuit list as output.

[0220] In order to demonstrate the advantages of the equivalent compilation effect of this embodiment over related technologies, the equivalent compilation effects of different schemes on quantum circuits are compared through some numerical experiments of circuit compilation.

[0221] The quantum circuit compilation scheme of this embodiment and the quantum circuit equivalent compilation schemes of three related technologies can be compared to each other, and the compilation effects of the maximum cut QAOA circuit on the randomly generated 3-regular graph can be compared. Among them, the three related technologies do not consider the commutativity of quantum operations.

[0222] Each two-qubit ZZ gate in the maximum-cut QAOA circuit is commutative. For each initial circuit width, 20 different 3-regular graphs and their corresponding maximum-cut QAOA circuits are randomly generated, and the comparison schemes are used for equivalent compilation. Fig. 9 Each data in the horizontal axis and the vertical axis is the average value of the width of 20 random circuits after compilation, and the error bar 901 indicates the maximum and minimum values ​​of the circuit width after compilation of the 20 random circuits.

[0223] It can be seen that the quantum circuit compilation scheme of this embodiment has improved quantum circuit compilation effect (represented by histogram 902) compared with the quantum circuit compilation effect of the related art (represented by histogram 903, histogram 904 and histogram 905 respectively).

[0224] In order to further demonstrate the compilation effect of quantum circuits, the compilation effects of different equivalent compilation schemes on randomly generated IQP circuits can be compared. All qubit gates in the subcircuit D of the IQP circuit are interchangeable. The ratio of the number of two-qubit gates m and the number of qubits n in the quantum circuit can be fixed to {0.5, 1, 1.5, 2, 2.5, 3, 3.5}, and then a random input quantum circuit width is selected from 10 to 80. The IQP circuit is constructed by randomly generating two-qubit gates, and is equivalently compiled using different quantum circuit compilation schemes.

[0225] For each ratio of two-qubit gates to the number of qubits, 300 different circuit instances were tested. The compilability factor can be used to represent the effect of circuit compilation, which is defined as:

[0226] Among them, n is the width of the input static quantum circuit, and n' is the width of the output dynamic quantum circuit. It can be seen that the higher the r value, the better the circuit compilation effect. Fig.10 and Fig.11 The figures show the comparison of the compilability factors of the quantum circuit compilation scheme of this embodiment with those of the circuit compilation schemes of related technologies 1 and 2 for random IQP circuits. The horizontal axes of the two figures are the compilability factors of related technologies 1 and 2 for random IQP circuits, respectively, and the vertical axes are the compilability factors of the quantum circuit compilation scheme of this embodiment for random IQP circuits.

[0227] Fig.10 and Fig.11 The black auxiliary line in represents y=x. It can be seen that for all random IQP circuits, the data points fall within the auxiliary line and the area within the line. It can be seen that the compilation effect of the quantum circuit compilation scheme of this embodiment on the random IQP circuit is significantly better than the compilation effect of the related technology 1 and the related technology 2 on the random IQP circuit.

[0228] Second embodiment

[0229] like Fig.12 As shown, the present disclosure provides a quantum circuit processing device 1200, comprising:

[0230] An acquisition module 1201 is used to acquire a first instruction list of a first quantum circuit and an exchangeable feature of each operation instruction in the first instruction list, wherein the exchangeable feature indicates exchangeability between the operation instruction and other operation instructions;

[0231] A construction module 1202 is used to construct a first directed acyclic graph of the first quantum circuit based on the exchangeable feature, using the operation instructions in the first instruction list as nodes, wherein the action qubits in the first directed acyclic graph have an intersection, and there are no directed edges between the nodes corresponding to different exchangeable operation instructions;

[0232] The equivalent compilation module 1203 is used to perform equivalent compilation on the first quantum circuit based on the first directed acyclic graph to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

[0233] Optionally, the construction module 1202 includes:

[0234] A forward traversal submodule, used for forward traversing the first instruction list according to the arrangement order of the operation instructions;

[0235] A construction submodule, used to take the first operation instruction currently traversed as a node, and if the first list is not an empty list, based on the exchangeable characteristics of the operation instructions in the first list, construct a directed edge from the node corresponding to the target operation instruction in the first list to the node corresponding to the first operation instruction; the target operation instruction is not exchangeable with the first operation instruction, and the first list is a list corresponding to the quantum bits acted upon by the first operation instruction;

[0236] An adding submodule is used to add the first operation instruction to the end of the first list, and obtain the first directed acyclic graph when the traversal of the first instruction list is completed.

[0237] Optionally, the construction submodule includes:

[0238] a determining unit, configured to determine the second operation instruction as a target operation instruction when it is determined based on the exchangeable feature that the second operation instruction is not exchangeable; the second operation instruction is an operation instruction at the end of the first list;

[0239] The first adding unit is used to add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

[0240] Optionally, the construction submodule includes:

[0241] a comparing unit, configured to compare the exchangeable feature of the operation instruction in the first list with the exchangeable feature of the first operation instruction to obtain a comparison result when it is determined that the second operation instruction is exchangeable based on the exchangeable feature;

[0242] an instruction acquisition unit, configured to acquire, based on the comparison result, at least one target operation instruction of a previous group of the first operation instruction from the first list to obtain a first sub-list, wherein different target operation instructions in the same group are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction;

[0243] The second adding unit is used to add a directed edge from each target operation instruction corresponding node in the first sublist to the first operation instruction corresponding node.

[0244] Optionally, the instruction acquisition unit is specifically used to:

[0245] When the comparison result indicates that the exchangeable feature of the second operation instruction is the same as the exchangeable feature of the first operation instruction, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions;

[0246] In a case where the first target operation instruction is not exchangeable, obtaining the first sub-list, wherein the first sub-list only includes the first target operation instruction;

[0247] In the case that the first target operation instruction is exchangeable, other target operation instructions having the same exchangeable feature as the first target operation instruction are acquired to obtain the first sub-list.

[0248] Optionally, the instruction acquisition unit is specifically used to:

[0249] If the comparison result indicates that the exchangeable characteristic of the second operation instruction is different from the exchangeable characteristic of the first operation instruction, determining the second operation instruction as the target operation instruction;

[0250] Other target operation instructions having the same exchangeable characteristic as the second operation instruction are acquired to obtain the first sub-list.

[0251] The quantum circuit processing device 1200 provided in the present disclosure can implement each process implemented in the quantum circuit processing method embodiment and can achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0252] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0253] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0254] Fig.13 A schematic block diagram of an example electronic device that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0255] like Fig.13 As shown, the device 1300 includes a computing unit 1301, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1302 or a computer program loaded from a storage unit 1308 into a random access memory (RAM) 1303. In the RAM 1303, various programs and data required for the operation of the device 1300 can also be stored. The computing unit 1301, the ROM 1302, and the RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0256] A number of components in the device 1300 are connected to the I / O interface 1305, including: an input unit 1306, such as a keyboard, a mouse, etc.; an output unit 1307, such as various types of displays, speakers, etc.; a storage unit 1308, such as a disk, an optical disk, etc.; and a communication unit 1309, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1309 allows the device 1300 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0257] The computing unit 1301 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1301 performs the various methods and processes described above, such as the quantum circuit processing method. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 1308. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1300 via the ROM 1302 and / or the communication unit 1309. When the computer program is loaded into the RAM 1303 and executed by the computing unit 1301, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 1301 may be configured to execute the quantum circuit processing method in any other appropriate manner (for example, by means of firmware).

[0258] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0259] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0260] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0261] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0262] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0263] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0264] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0265] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A quantum circuit processing method, comprising: Acquire a first instruction list of a first quantum circuit and an exchangeable feature of each operation instruction in the first instruction list, wherein the exchangeable feature indicates exchangeability of the operation instruction with other operation instructions; forwardly traverse the first instruction list according to the arrangement order of the operation instructions; Taking the first operation instruction currently traversed as a node, and if the first list is not an empty list, constructing a directed edge from a node corresponding to the target operation instruction in the first list to a node corresponding to the first operation instruction based on the exchangeable feature of the operation instructions in the first list; The target operation instruction and the first operation instruction are not interchangeable, and the first list is a list corresponding to the quantum bits acted upon by the first operation instruction; Adding the first operation instruction to the end of the first list, and obtaining a first directed acyclic graph of the first quantum circuit when the first instruction list is traversed, wherein the action quantum bits in the first directed acyclic graph have an intersection, and there are no directed edges between nodes corresponding to different exchangeable operation instructions; Adding a target directed edge from the output node to the input node in the first directed acyclic graph to obtain a second directed acyclic graph; Based on the second directed acyclic graph, the second list consisting of the added target directed edges, and the first instruction list, the first quantum circuit is equivalently compiled to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit.

2. The method according to claim 1, wherein: The constructing, based on the exchangeable feature of the operation instructions in the first list, a directed edge from a node corresponding to the target operation instruction in the first list to a node corresponding to the first operation instruction includes: In the case where it is determined based on the exchangeable feature that the second operation instruction is not exchangeable, determining the second operation instruction as the target operation instruction; the second operation instruction is the operation instruction at the end of the first list; Add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

3. The method according to claim 1, wherein: The constructing, based on the exchangeable feature of the operation instructions in the first list, a directed edge from a node corresponding to the target operation instruction in the first list to a node corresponding to the first operation instruction includes: In the case where it is determined that the second operation instruction is exchangeable based on the exchangeable feature, comparing the exchangeable feature of the operation instruction in the first list with the exchangeable feature of the first operation instruction to obtain a comparison result; Based on the comparison result, at least one target operation instruction of a previous group of the first operation instruction is obtained from the first list to obtain a first sub-list, wherein different target operation instructions in the same group are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction; Add each target operation instruction corresponding node in the first sublist to the directed edge of the first operation instruction corresponding node.

4. The method according to claim 3, wherein: The step of acquiring, based on the comparison result, at least one target operation instruction of a previous group of the first operation instruction from the first list to obtain a first sub-list includes: When the comparison result indicates that the exchangeable feature of the second operation instruction is the same as the exchangeable feature of the first operation instruction, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions; In a case where the first target operation instruction is not exchangeable, obtaining the first sub-list, wherein the first sub-list only includes the first target operation instruction; In the case that the first target operation instruction is exchangeable, other target operation instructions having the same exchangeable feature as the first target operation instruction are acquired to obtain the first sub-list.

5. The method according to claim 3, wherein: The step of acquiring, based on the comparison result, at least one target operation instruction of a previous group of the first operation instruction from the first list to obtain a first sub-list includes: If the comparison result indicates that the exchangeable characteristic of the second operation instruction is different from the exchangeable characteristic of the first operation instruction, determining the second operation instruction as the target operation instruction; Other target operation instructions having the same exchangeable characteristic as the second operation instruction are acquired to obtain the first sub-list.

6. A quantum circuit processing device, comprising: An acquisition module, configured to acquire a first instruction list of a first quantum circuit and an exchangeable feature of each operation instruction in the first instruction list, wherein the exchangeable feature indicates exchangeability of the operation instruction with other operation instructions; A construction module is used to construct a first directed acyclic graph of the first quantum circuit based on the exchangeable feature and using the operation instructions in the first instruction list as nodes, wherein the action quantum bits in the first directed acyclic graph have an intersection, and there are no directed edges between the nodes corresponding to different exchangeable operation instructions; an equivalent compilation module, configured to perform equivalent compilation on the first quantum circuit based on the first directed acyclic graph to obtain a second instruction list for a second quantum circuit, wherein the number of quantum bits of the second quantum circuit is less than the number of quantum bits of the first quantum circuit; The building blocks include: A forward traversal submodule, used for forward traversing the first instruction list according to the arrangement order of the operation instructions; A construction submodule, used to take the first operation instruction currently traversed as a node, and if the first list is not an empty list, based on the exchangeable characteristics of the operation instructions in the first list, construct a directed edge from the node corresponding to the target operation instruction in the first list to the node corresponding to the first operation instruction; the target operation instruction is not exchangeable with the first operation instruction, and the first list is a list corresponding to the quantum bits acted upon by the first operation instruction; An adding submodule, used for adding the first operation instruction to the end of the first list, and obtaining the first directed acyclic graph when the traversal of the first instruction list is completed; Equivalent compilation modules, specifically for: Adding a target directed edge from the output node to the input node in the first directed acyclic graph to obtain a second directed acyclic graph; Based on the second directed acyclic graph, the second list consisting of the added target directed edges, and the first instruction list, the first quantum circuit is equivalently compiled to obtain a second instruction list for the second quantum circuit.

7. The device according to claim 6, wherein: The construction submodule includes: a determining unit, configured to determine the second operation instruction as a target operation instruction when it is determined based on the exchangeable feature that the second operation instruction is not exchangeable; the second operation instruction is an operation instruction at the end of the first list; The first adding unit is used to add a directed edge from the node corresponding to the target operation instruction to the node corresponding to the first operation instruction.

8. The device according to claim 6, wherein: The construction submodule includes: a comparing unit, configured to compare the exchangeable feature of the operation instruction in the first list with the exchangeable feature of the first operation instruction to obtain a comparison result when it is determined that the second operation instruction is exchangeable based on the exchangeable feature; an instruction acquisition unit, configured to acquire, based on the comparison result, at least one target operation instruction of a previous group of the first operation instruction from the first list to obtain a first sub-list, wherein different target operation instructions in the same group are interchangeable, and each target operation instruction is not interchangeable with the first operation instruction; The second adding unit is used to add a directed edge from each target operation instruction corresponding node in the first sublist to the first operation instruction corresponding node.

9. The device according to claim 8, wherein: The instruction acquisition unit is specifically used for: When the comparison result indicates that the exchangeable feature of the second operation instruction is the same as the exchangeable feature of the first operation instruction, obtaining a first target operation instruction obtained by reversely traversing the first list according to the arrangement order of the operation instructions; In a case where the first target operation instruction is not exchangeable, obtaining the first sub-list, wherein the first sub-list only includes the first target operation instruction; In the case that the first target operation instruction is exchangeable, other target operation instructions having the same exchangeable feature as the first target operation instruction are acquired to obtain the first sub-list.

10. The device according to claim 8, wherein: The instruction acquisition unit is specifically used for: If the comparison result indicates that the exchangeable characteristic of the second operation instruction is different from the exchangeable characteristic of the first operation instruction, determining the second operation instruction as the target operation instruction; Other target operation instructions having the same exchangeable characteristic as the second operation instruction are acquired to obtain the first sub-list.

11. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-5.

13. A computer program product, comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 5.

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