Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate comprises a plurality of sub-pixels, a plurality of data signal lines and transistors, the sub-pixels are arranged in an array, the data signal lines are used for providing data signal voltages for the sub-pixels, the sub-pixels comprise a target sub-pixel, the transistors are connected with the sub-pixels and the data signal lines, when the transistors are turned on, the transistors drive the sub-pixels to write the data signal voltages, the sub-pixels can emit light and display corresponding colors, when a double-color mixed-color picture is displayed, the opening sequence of the transistors is different from the arrangement sequence of the transistors, so that a target front sub-pixel of the target sub-pixel emits light, and the target front sub-pixel is a sub-pixel connected with the target sub-pixel to the same data signal line and turned on first. The array substrate of the application controls the target front sub-pixel of the target sub-pixel to emit light, so that the target sub-pixel emits light with high brightness, the brightness difference in the display process is avoided, and the phenomenon of vertical line defects is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display device, more particularly, to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the continuous progress of flat panel display technology, liquid crystal displays have been successfully applied to a variety of display devices. Dual Gate products can achieve a reduction in the number of chip on film (COF) to reduce costs, and are increasingly favored by panel manufacturers. Because the pixels are not fully charged, the data signal voltage of the previous pixel is used to pre-charge the pixel to ensure the display effect of the pixel. In the related art, due to the influence of the Dual Gate pixel architecture, under a blue screen (a double-color mixed screen with blue and green being bright and red not being bright), a charging difference occurs in different columns of green pixels or green pixels due to different pre-charging, and the charging difference can cause a brightness difference, thereby causing the occurrence of vertical stripes in the blue screen. SUMMARY

[0003] The embodiments of the present application provide an array substrate, a display panel and a display device.

[0004] The embodiments of the present application provide an array substrate, the array substrate comprising a plurality of sub-pixels, a plurality of data signal lines and transistors, the sub-pixels being arranged in an array; the data signal lines are used to provide data signal voltages to the sub-pixels, the sub-pixels comprising a target sub-pixel, the target sub-pixel being used to display a target color; the transistors connect the sub-pixels and the data signal lines, when the transistors are turned on, the transistors drive the sub-pixels to write the data signal voltages, so that the sub-pixels can emit light and display corresponding colors, the sub-pixels in the same row are driven by two rows of transistors, and the transistors in the same row are turned on at the same time; in the case of displaying a double-color mixed screen, the opening sequence of the transistors and the arrangement sequence of the transistors are different, so that a target previous sub-pixel of the target sub-pixel emits light, the target previous sub-pixel and the target sub-pixel are connected to the same data signal line, and in the opening sequence, the transistor corresponding to the target previous sub-pixel is located in the previous row of the transistor corresponding to the target sub-pixel.

[0005] Therefore, the sub-pixel can be pre-charged by the data signal voltage of the previous sub-pixel, and the previous sub-pixel connected to the same data signal line emits light due to the written data signal voltage. The data signal voltage written into the target sub-pixel is high, and thus the pre-charging of the target sub-pixel is more, and the light emitting brightness of the target sub-pixel is brighter. By controlling the light emitting brightness of each column of target sub-pixels of the display target color to be brighter, the brightness difference in the display process can be avoided, the vertical stripe defect phenomenon can be avoided, and the brightness is better, and a better display effect can be obtained.

[0006] In some embodiments, the array substrate further comprises a driving signal line, the transistor is connected to the driving signal line, one driving signal line is used to drive one row of the transistors to be turned on, the arrangement order of the transistors is the same as the arrangement order of the driving signal lines, the driving order of the driving signal lines is the same as the arrangement order of the driving signal lines, and the transistors and the driving signal lines are not connected according to the arrangement order, so that the turning-on order of the transistors is different from the arrangement order of the transistors.

[0007] Therefore, by connecting the transistors and the driving signal lines not according to the arrangement order, so that the turning-on order of the transistors is different from the arrangement order of the transistors, the target previous sub-pixels of the target sub-pixels all emit light, and the vertical stripe defect phenomenon is improved.

[0008] In some embodiments, the array substrate further comprises a driving signal line and an array gate driving unit, the transistor is connected to the driving signal line, one driving signal line is used to drive one row of the transistors to be turned on, one array gate driving unit is connected to one driving signal line, the array gate driving unit outputs a driving signal, the driving signal drives the transistor to be turned on through the driving signal line, the arrangement order of the array gate driving unit, the driving signal line and the transistor are connected one by one according to the arrangement order, the output driving signal order of the array gate driving unit is different from the arrangement order of the array gate driving unit, so that the turning-on order of the transistor driven by the driving signal line is different from the arrangement order of the driving signal line.

[0009] Therefore, by changing the output driving signal order of the array gate driving unit, so that the output driving signal order of the array gate driving unit is different from the arrangement order of the array gate driving unit, so that the turning-on order of the transistor driven by the driving signal line is different from the arrangement order of the driving signal line, and thus the target previous sub-pixels of all target sub-pixels emit light.

[0010] In some embodiments, the array substrate further comprises a clock signal line connected to the array gate driving units, the clock signal line is used to output a clock signal to the array gate driving units to control the sequence of the driving signals outputted by the array gate driving units, the sequence of the clock signal outputted by the clock signal line is different from the arrangement sequence of the array gate driving units connected to the clock signal line, so that the sequence of the driving signals outputted by the array gate driving units is different from the arrangement sequence of the array gate driving units.

[0011] In this way, by changing the sequence of the clock signal outputted by the clock signal line, the sequence of the clock signal outputted by the clock signal line is different from the arrangement sequence of the array gate driving units connected to the clock signal line, so that the sequence of the driving signals outputted by the array gate driving units is different from the arrangement sequence of the array gate driving units, thereby changing the turn-on sequence of the transistors, so that the target front sub-pixels of the target sub-pixel all emit light.

[0012] In some embodiments, the sub-pixels comprise a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, in the case of displaying a two-color mixed color picture, the first color sub-pixel does not emit light, and the second color sub-pixel and the third color sub-pixel emit light.

[0013] In this way, according to the arrangement sequence of the sub-pixels, the corresponding data signal voltage can be set to display the corresponding picture.

[0014] In some embodiments, the target sub-pixel is the second color sub-pixel, and the target front sub-pixel is the second color sub-pixel or the third color sub-pixel.

[0015] In this way, when displaying a two-color mixed color picture, the target front sub-pixel is the second color sub-pixel or the third color sub-pixel, so that the target front sub-pixel all emits light.

[0016] In some embodiments, the data signal voltage written to the target front sub-pixel is used to pre-charge the target sub-pixel, and the pre-charge voltage of all the target sub-pixels is greater than a set voltage.

[0017] In this way, by writing the data signal voltage of the previous sub-pixel connected to the same data signal line to the sub-pixel for pre-charging, the charging time of the sub-pixel can be improved, so that the display effect of the sub-pixel is better.

[0018] In some embodiments, each of the data signal lines is connected to at least two columns of the sub-pixels, and the sub-pixels and the data signal lines are connected in a Z inversion manner.

[0019] In this way, the sub-pixels and the data signal lines are connected in a Z inversion manner, so that the polarities of the sub-pixels connected to the same data signal line are the same, and thus the power consumption can be reduced.

[0020] The display panel provided by the embodiment of the present application comprises a cover plate and the array substrate of any one of the above embodiments, and the cover plate is arranged on the array substrate.

[0021] In this way, the sub-pixels can be pre-charged by the data signal voltage written into the previous sub-pixel, and since the previous sub-pixel connected to the same data signal line as the target sub-pixel emits light, the data signal voltage written into the previous sub-pixel is at a high level, so that the target sub-pixel is pre-charged more, and the light emitting brightness of the target sub-pixel is brighter; by controlling the light emitting brightness of each column of target sub-pixels displaying a target color to be brighter, the brightness difference in the display process can be avoided, the vertical stripe defect phenomenon is avoided, and the brightness is better, and a better display effect can be obtained.

[0022] The display device provided by the embodiment of the present application comprises a housing and the display panel of the above embodiment, and the display panel is arranged in the housing.

[0023] In this way, the sub-pixels can be pre-charged by the data signal voltage written into the previous sub-pixel, and since the previous sub-pixel connected to the same data signal line as the target sub-pixel emits light, the data signal voltage written into the previous sub-pixel is at a high level, so that the target sub-pixel is pre-charged more, and the light emitting brightness of the target sub-pixel is brighter; by controlling the light emitting brightness of each column of target sub-pixels displaying a target color to be brighter, the brightness difference in the display process can be avoided, the vertical stripe defect phenomenon is avoided, and the brightness is better, and a better display effect can be obtained.

[0024] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, taken in conjunction with the following drawings in which:

[0026] Figure 1 is a schematic view of an array substrate of an embodiment of the present application;

[0027] Figure 2 is a schematic view of an array substrate of an embodiment of the present application;

[0028] Figure 3 is a schematic view of an array substrate of an embodiment of the present application;

[0029] Figure 4 is a connection diagram of an array gate driving unit and a transistor according to an embodiment of the present application;

[0030] Figure 5 is a connection diagram of an array gate driving unit and a transistor according to a related art;

[0031] Figure 6 is a connection diagram of a clock signal line, an array gate driving unit and a transistor according to an embodiment of the present application;

[0032] Figure 7 is a timing chart of an array substrate according to an embodiment of the present application;

[0033] Figure 8 is a schematic diagram of an array substrate according to a related art;

[0034] Figure 9 is a timing chart of an array substrate according to a related art;

[0035] Figure 10 is a display brightness schematic diagram of an array substrate according to a related art;

[0036] Figure 11 is a schematic diagram of a process flow according to an embodiment of the present application;

[0037] Figure 12 is a circuit schematic diagram of a gate driving unit according to an embodiment of the present application;

[0038] Figure 13 is a timing chart of a gate driving unit according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] Embodiments of the present application are described in detail below with reference to the attached drawings, wherein like or similar elements are denoted by the same or similar reference numerals throughout the drawings. The embodiments described below are merely exemplary and are used to explain the present application, but are not to be understood as limiting the present application.

[0040] With the continuous progress of flat panel display technology, liquid crystal displays have been successfully applied to a variety of display devices. Dual Gate products can achieve a reduction in the number of chip on film (COF) to reduce costs, and are increasingly favored by panel manufacturers. Because the pixel is not fully charged, the data signal voltage of the previous pixel is used to pre-charge the pixel to ensure the display effect of the pixel. In the related art, due to the influence of the Dual Gate pixel architecture, under a blue screen (a double-color mixed screen with bright blue and green, and no bright red), different columns of blue pixels and different columns of green pixels exist charging differences due to different pre-charging, and the charging differences can cause brightness differences, resulting in the occurrence of blue screen vertical stripe defects.

[0041] Please refer to Figures 1 to 3 The embodiment of the present application provides an array substrate 1000, the array substrate 1000 includes a plurality of sub-pixels 100, a plurality of data signal lines 200 and transistors 300, the sub-pixels 100 are arranged in an array; the data signal line 200 is used for providing a data signal voltage to the sub-pixel 100, the sub-pixel 100 includes a target sub-pixel 100, the target sub-pixel 100 is used for displaying a target color; the transistor 300 is connected with the sub-pixel 100 and the data signal line 200, when the transistor 300 is turned on, the transistor 300 drives the sub-pixel 100 to write the data signal voltage, so that the sub-pixel 100 can emit light and display the corresponding color, the sub-pixels 100 in the same row are driven by two rows of transistors 300, and the transistors 300 in the same row are turned on at the same time; in the case of displaying a double-color mixed screen, the opening sequence of the transistor 300 and the arrangement sequence of the transistor 300 are different, so that a target front sub-pixel 100 of the target sub-pixel 100 emits light, the target front sub-pixel 100 is connected with the target sub-pixel 100 with the same data signal line 200, and in the opening sequence, the transistor 300 corresponding to the target front sub-pixel 100 is located in the previous row of the transistor 300 corresponding to the target sub-pixel 100.

[0042] Specifically, the target color can be one of the colors displayed when displaying a two-color mixed color picture, such as green when displaying a blue picture, and the sub-pixel 100 displaying green is the target sub-pixel. The transistor 300 can connect the sub-pixel 100 and the data signal line 200 through the source and the drain, and when the transistor 300 is turned on, the source and the drain of the transistor 300 are conductive, so that the transistor 300 connects the sub-pixel 100 and the data signal line 200, and the data signal voltage transmitted by the data signal line 200 can be written into the sub-pixel 100. The previous sub-pixel 100 connected to the same data signal line 200 as the target sub-pixel and writing the data signal voltage is the target previous sub-pixel of the target sub-pixel, and the opening sequence of the transistor 300 and the arrangement sequence of the transistor 300 are different, so that the target previous sub-pixel of the target sub-pixel emits light. In the case of pre-charging the sub-pixel 100 using the data signal voltage of the previous sub-pixel 100, since the target previous sub-pixel of the target sub-pixel emits light, the data signal voltage written into the target previous sub-pixel is high, so that the pre-charging effect of the target sub-pixel is good, and the display effect of the target sub-pixel is good, and the display brightness is high. Since all the target previous sub-pixels of the target sub-pixel emit light, the display brightness of all the target sub-pixels is high, so that the display effect of the sub-pixel 100 displaying green is good, and since the human eye is more sensitive to green, when displaying a blue picture, the human eye observes no vertical stripe defect phenomenon, thereby improving the vertical stripe defect problem.

[0043] In this way, the sub-pixel 100 can be pre-charged by the data signal voltage written into the previous sub-pixel 100, and since the previous sub-pixel 100 connected to the same data signal line 200 as the target sub-pixel 100 emits light, the data signal voltage written into the sub-pixel 100 is high, so that the target sub-pixel 100 is pre-charged more, and the light emitting brightness of the target sub-pixel 100 is brighter; by controlling the light emitting brightness of each column of target sub-pixels 100 displaying the target color to be brighter, the brightness difference in the display process can be avoided, the vertical stripe defect phenomenon is avoided, and the brightness is good, so that a good display effect can be obtained.

[0044] Please refer to Figure 4 In some embodiments, the array substrate 1000 further includes a driving signal line 400, and the transistor 300 is connected to the driving signal line 400. One driving signal line 400 is used to drive one row of transistors 300 to be turned on. The arrangement sequence of the transistor 300 is the same as the arrangement sequence of the driving signal line 400, the driving sequence of the driving signal line 400 is the same as the arrangement sequence of the driving signal line 400, and the transistor 300 and the driving signal line 400 are not connected according to the arrangement sequence, so that the opening sequence of the transistor 300 is different from the arrangement sequence of the transistor 300.

[0045] Specifically, the driving signal line 400 is used to transmit a driving voltage, when the driving voltage is high, the transistor 300 connected to the driving signal line 400 is turned on, so that the sub-pixel 100 connected to the transistor 300 works. One driving signal line 400 drives one row of transistors 300 to open, and the sub-pixels 100 in the same row are driven by two driving signal lines 400 and two rows of driving transistors 300, that is, in the mode of dual gate driving, so that one data signal line 200 can connect two sub-pixels 100 in the same row, saving the number of data signal lines 200, simplifying the circuit structure and reducing the cost. The array substrate 1000 further comprises an array gate driving unit 500 (GOA unit), the GOA unit outputs a driving signal and transmits it through the driving signal line 400, and the GOA unit and the driving signal line 400 are connected in one-to-one correspondence according to the arrangement order. Please refer to Figure 4 The arrangement order of the transistor 300 is the same as the arrangement order of the driving signal line 400, and the driving order of the driving signal line 400 transmitting the driving signal to drive the transistor 300 to open is the same as the arrangement order of the driving signal line 400, that is, the driving order of the driving signal line 400 transmitting the driving signal is the same as the arrangement order of the transistor 300. But the transistor 300 and the driving signal line 400 are not connected according to the arrangement order, in an embodiment, the third row of driving signal lines 400 is connected to the fourth row of transistors 300, the fourth row of driving signal lines 400 is connected to the third row of transistors 300, and the third row of driving signal lines 400 transmits the driving signal earlier than the fourth row of driving signal lines 400, so that the fourth row of transistors 300 opens earlier than the third row of transistors 300, so that the opening order of the transistor 300 is different from the arrangement order of the transistor 300, so that the target front sub-pixel of the target sub-pixel emits light, and the phenomenon of vertical stripe defect is improved. Please refer to Figure 4 and Figure 5 By changing the connection relationship between the driving signal line 400 and the transistor 300, the opening order of the transistor 300 is different from the arrangement order of the transistor 300, without changing the arrangement order of the GOA unit, the implementation is simple.

[0046] In this way, by connecting the transistor 300 and the driving signal line 400 not according to the arrangement order, so that the opening order of the transistor 300 is different from the arrangement order of the transistor 300, so that the target front sub-pixel of the target sub-pixel emits light, and the phenomenon of vertical stripe defect is improved.

[0047] Please refer to Figure 6In some embodiments, the array substrate 1000 further comprises a driving signal line 400 and an array gate driving unit 500, the transistor 300 is connected to the driving signal line 400, one driving signal line 400 is used to drive one row of transistors 300 to turn on; one array gate driving unit 500 is connected to one driving signal line 400, the array gate driving unit 500 outputs a driving signal, the driving signal drives the transistor 300 to turn on through the driving signal line 400, the array gate driving unit 500, the driving signal line 400 and the transistor 300 are connected in one-to-one correspondence according to the arrangement order, and the output driving signal sequence of the array gate driving unit 500 is different from the arrangement order of the array gate driving unit 500, so that the transistor 300 turning-on sequence of the driving signal line 400 is different from the arrangement order of the driving signal line 400.

[0048] Specifically, the GOA unit, the driving signal line 400 and the transistor 300 are connected in one-to-one correspondence according to the arrangement order, that is, the first GOA unit (not necessarily referring to GOA1) is connected to the first driving signal line 400 and connected to the first transistor 300, the second GOA unit is connected to the second driving signal line 400 and connected to the second transistor 300, and so on. But the output driving signal sequence of the GOA unit is different from the arrangement order of the GOA unit, that is, the driving sequence of the driving signal line 400 is different from the arrangement order of the driving signal line 400, so that the transistor 300 turning-on sequence is different from the arrangement order of the transistor 300, thereby making the target front sub-pixel of the target sub-pixel emit light. Please refer to Figure 5 and Figure 6 GOA1 to GOA4 are named according to the output driving signal sequence, that is, GOA1 outputs the first driving signal, and GOA4 outputs the fourth driving signal. In the related art (such as Figure 5 ), the output driving signal sequence of GOA1 to GOA4 is the same as the arrangement order, that is, GOA1 is arranged at the position of the first GOA unit, GOA2 is arranged at the position of the second GOA unit, GOA3 is arranged at the position of the third GOA unit, and GOA4 is arranged at the position of the fourth GOA unit. In an embodiment, the embodiments of the present application interchange the spatial positions of GOA3 and GOA4 (such as Figure 6), i.e. the arrangement order of GOA3 and GOA4 is exchanged, at this time GOA3 is arranged at the position of the fourth GOA unit and GOA4 is arranged at the position of the third GOA unit, so that the order of the third GOA unit and the fourth GOA unit outputting the driving signal is exchanged. GOA1 and GOA2 output the driving signal in order among the four GOA units, GOA3 unit outputs the driving signal thirdly, so that the fourth driving signal line 400 transmits the driving signal thirdly to make the fourth row transistor 300 (Gate4) open thirdly among all the row transistors 300; GOA4 outputs the driving signal fourthly, so that the third driving signal line 400 transmits the driving signal fourthly to make the third row transistor 300 (Gate3) open fourthly among all the row transistors 300, thereby changing the order of the target sub-pixel 100 writing the data signal voltage, so that all the target front sub-pixels of all the target sub-pixels emit light. In addition, the cascade relationship among the plurality of GOA units can be that the output of GOA1 is the input signal of GOA3, the output of GOA2 is the input signal of GOA4, the output of GOA4 is the reset signal of GOA1, i.e. the output of the nth GOA unit is the input signal of the n+2th GOA unit, and at the same time is the reset signal of the n-3th GOA unit.

[0049] In this way, by changing the order of the output driving signal of the array gate driving unit 500, the order of the output driving signal of the array gate driving unit 500 is different from the arrangement order of the array gate driving unit 500, so that the order of the transistor 300 of the driving signal line 400 opening is different from the arrangement order of the driving signal line 400, thereby making all the target front sub-pixels of all the target sub-pixels emit light.

[0050] Please refer to Figure 6 In some embodiments, the array substrate 1000 further comprises a clock signal line 600, the clock signal line 600 is connected with the array gate driving unit 500, the clock signal line 600 is used to output a clock signal to the array gate driving unit 500 to control the order of the array gate driving unit 500 outputting the driving signal, the order of the clock signal line 600 outputting the clock signal is different from the arrangement order of the array gate driving unit 500 connected with the clock signal line 600, so that the order of the array gate driving unit 500 outputting the driving signal is different from the arrangement order of the array gate driving unit 500.

[0051] Specifically, the clock signal line 600 and the array gate driving unit 500 are connected sequentially. When the array gate driving unit 500 receives the clock signal, it outputs a driving signal. The order in which the clock signal line 600 outputs the clock signal is different from the arrangement order of the array gate driving units 500 connected to it, thereby changing the order in which the array gate driving units 500 output the driving signals, making the order of the output driving signals different from the arrangement order of the array gate driving units 500. In one embodiment, the clock signal line 600 includes CLK1, CLK2, CLK3, and CLK4, and the GOA unit includes GOA1, GOA2, GOA3, and GOA4. CLK1 is connected to GOA1, CLK2 is connected to GOA2, CLK3 is connected to GOA3, and CLK4 is connected to GOA4. CLK4 is located between CLK2 and CLK3, and GOA4 is located between GOA2 and GOA3. That is, the order of the four clock signal lines 600 is CLK1, CLK2, CLK4, and CLK3, and the order of the four GOA units in space is GOA1, GOA2, GOA4, and GOA3. GOA4 is connected to the third row of transistors 300 (Gate3), and GOA3 is connected to the fourth row of transistors 300 (Gate4). Since CLK3 outputs its clock signal before CLK4, although GOA3 is positioned after GOA4, GOA3 outputs its drive signal before GOA4, thus driving the connected fourth-row transistor 300 (Gate4) to turn on before the third-row transistor 300 (Gate3). Furthermore, the cascading relationship between the multiple GOA units remains unchanged: the output of GOA1 serves as the input signal for GOA3, the output of GOA2 serves as the input signal for GOA4, and the output of GOA4 serves as the reset signal for GOA1.

[0052] Thus, by changing the order of the clock signals output by the clock signal line 600, the order of the clock signals output by the clock signal line 600 is different from the arrangement order of the array gate driving units 500 connected to the clock signal line 600. This makes the order of the output driving signals of the array gate driving units 500 different from the arrangement order of the array gate driving units 500, thereby changing the turn-on order of the transistors 300, so that the target sub-pixel in front of the target sub-pixel emits light.

[0053] In some implementations, sub-pixel 100 includes a first color sub-pixel 101, a second color sub-pixel 102, and a third color sub-pixel 103. When displaying a dual-color mixed image, the first color sub-pixel 101 does not emit light, while the second color sub-pixel 102 and the third color sub-pixel 103 emit light.

[0054] Specifically, please refer to Figure 2, the first color sub-pixel 101 can be a red sub-pixel 100, the second color sub-pixel 102 can be a green sub-pixel 100, and the third color sub-pixel 103 can be a blue sub-pixel 100. Denote the first color sub-pixel 101 as R, the second color sub-pixel 102 as G, and the third color sub-pixel 103 as B. In a pixel, the arrangement order of the sub-pixels 100 is RGB. Three sub-pixels 100 can form a pixel, and the pixels are arranged in a column. In each row of sub-pixels 100, the arrangement order of the sub-pixels 100 is RGBRGB.

[0055] In this way, the corresponding data signal voltage can be set according to the arrangement order of the sub-pixels 100 to display the corresponding picture.

[0056] In some embodiments, the target sub-pixel 100 is the second color sub-pixel 102, and the target front sub-pixel 100 is the second color sub-pixel 102 or the third color sub-pixel 103.

[0057] Specifically, when displaying a two-color mixed color picture, the second color sub-pixel 102 and the third color sub-pixel 103 emit light, and the target front sub-pixel emits light. Therefore, the target front sub-pixel is the second color sub-pixel 102 or the third color sub-pixel 103.

[0058] In this way, when displaying a two-color mixed color picture, the target front sub-pixel 100 is the second color sub-pixel 102 or the third color sub-pixel 103, so that the target front sub-pixel emits light.

[0059] In some embodiments, two driving signal lines 400 are connected to each row of sub-pixels 100, and six columns of sub-pixels 100 form a sub-pixel unit. The array substrate 1000 includes four driving signal lines 400 corresponding to the sub-pixel unit. The sub-pixels 100 are arranged in a cycle in the order of the first color sub-pixel 101, the second color sub-pixel 102, and the third color sub-pixel 103. The first column of sub-pixels 100 is the first color sub-pixel 101. In the first row of sub-pixels 100, the second column, the fourth column, and the sixth column of sub-pixels 100 are connected to the first driving signal line 400, and the first column, the third column, and the fifth column of sub-pixels 100 are connected to the second driving signal line 400. In the second row of sub-pixels 100, the first column, the third column, and the fifth column of sub-pixels 100 are connected to the third driving signal line 400, and the second column, the fourth column, and the sixth column of sub-pixels 100 are connected to the fourth driving signal line 400. The second column of sub-pixels 100 and the fifth column of sub-pixels 100 are target sub-pixels, and the target front sub-pixels of the second column of sub-pixels 100 and the fifth column of sub-pixels 100 are the second color sub-pixel 102 or the third color sub-pixel 103.

[0060] Specifically, please refer to Figure 2 andFigure 3 The TFT side connection relationship of the two-row six-column sub-pixel 100, the data signal line 200 and the driving signal line 400 can be: long-long-long-short-short-short. Figure 3 The vertical signal line in the middle is the data signal line 200, the transistor 300 far from the data signal line 200 is a long connection, and the transistor 300 close to the data signal line 200 is a short connection.

[0061] Wherein, the target color is green, please refer to Figure 2 and Figure 7 Based on the Z inversion connection and the double gate line driving of the two-row six-column sub-pixel 100, five data signal lines 200 and four driving signal lines 400 are connected, wherein the first row first column and the first row second column sub-pixel 100 are connected with the data signal line 200 (Data1), the data signal voltage transmitted by Data1 is 10111011; the first row third column, the first row fourth column, the second row first column and the second row second column sub-pixel 100 are connected with the data signal line 200 (Data2), the data signal voltage transmitted by Data2 is 01100; the first row fifth column, the first row sixth column, the second row third column and the second row fourth column sub-pixel 100 are connected with the data signal line 200 (Data3), the data signal voltage transmitted by Data3 is 11011101; the second row fifth column and the second row sixth column sub-pixel 100 are connected with the data signal line 200 (Data4), the data signal voltage transmitted by Data4 is the same as Data1, which is 10111011, and the following is repeated.

[0062] The second column of sub-pixels 100 are all G sub-pixels 100 for displaying green, that is, all target sub-pixels. The target front sub-pixel of the sub-pixel 100 in the first row and the second column is a G sub-pixel 100, and the target front sub-pixel emits light when displaying a blue picture. The data signal voltage written into the target front sub-pixel is high, and thus the pre-charge voltage of the sub-pixel 100 in the first row and the second column is high. The sub-pixel 100 in the first row and the second column displays a relatively high brightness when emitting light, and the sub-pixel 100 in the first row and the second column is marked as “good”. The target front sub-pixel of the sub-pixel 100 in the second row and the second column is a B sub-pixel 100 in the first row and the fourth column, and the target front sub-pixel emits light when displaying a blue picture. The data signal voltage written into the target front sub-pixel is high, and thus the pre-charge voltage of the sub-pixel 100 in the second row and the second column is high. The sub-pixel 100 in the second row and the second column displays a relatively high brightness when emitting light, and the sub-pixel 100 in the second row and the second column is marked as “good”. Similarly, the sub-pixels 100 in the fifth column display a relatively high brightness when emitting light, and are all marked as “good”. The third column of sub-pixels 100 are all B sub-pixels 100 for displaying blue. The front sub-pixel of the sub-pixel 100 in the first row and the third column is an R sub-pixel 100, and the front sub-pixel does not emit light when displaying a blue picture. The data signal voltage written into the front sub-pixel is low, and thus the pre-charge voltage of the sub-pixel 100 in the first row and the third column is low. The sub-pixel 100 in the first row and the second column displays a relatively low brightness when emitting light, and the sub-pixel 100 in the first row and the second column is marked as “poor”. Similarly, the sub-pixels 100 in the second row and the second column and the sub-pixels 100 in the second row and the sixth column display a relatively low brightness when emitting light, and are all marked as “poor”. All the sub-pixels 100 for displaying green are marked as “good”, and among the sub-pixels 100 for displaying blue, the first column is marked as “poor” and the second column is marked as “good” and “poor”. Since the human eye is more sensitive to green, the display brightness of the sub-pixels 100 for displaying green is relatively high, so that when the human eye observes a blue picture, there is no picture with vertical stripe defects, thereby improving the problem of vertical stripe defects.

[0063] In this way, by making the brightness of the target sub-pixels 100 displaying the target color relatively high, the phenomenon of vertical stripe defects can be improved.

[0064] In some embodiments, the data signal voltage written into the target front sub-pixel 100 is used to pre-charge the target sub-pixel 100, and the pre-charge voltage of all the target sub-pixels 100 is greater than a set voltage.

[0065] Specifically, since the charging time of the sub-pixel 100 is short in the case of a high refresh rate, it is difficult to obtain a good display effect, and therefore the data signal voltage of the front sub-pixel writing into the sub-pixel 100 is used to pre-charge the sub-pixel 100, so that the sub-pixel 100 can have a good working state. The front sub-pixel is set to be the same as the current sub-pixel connected to the same data signal line 200 and the sub-pixel 100 of the previous writing data signal voltage, the current sub-pixel of which the front sub-pixel does not emit light is the first sub-pixel, and the current sub-pixel of which the front sub-pixel emits light is the second sub-pixel, that is, the target sub-pixel is the first sub-pixel. Since the front sub-pixel of the first sub-pixel does not emit light, the data signal voltage written into the front sub-pixel of the first sub-pixel is low, so that the voltage for pre-charging the first sub-pixel is small, and the pre-charging effect of the first sub-pixel is poor. When the first sub-pixel displays light, the brightness of the first sub-pixel is dark; since the front sub-pixel of the second sub-pixel emits light, the data signal voltage written into the front sub-pixel of the second sub-pixel is high, so that the voltage for pre-charging the second sub-pixel is large, and the pre-charging effect of the second sub-pixel is good. When the second sub-pixel displays light, the brightness of the second sub-pixel is bright.

[0066] In the related art, please refer to Figures 8 to 10 , the pixel architecture is two rows and three columns as a period, and the timing diagram is as shown in Figure 9 . When displaying a blue picture, since the red sub-pixel does not emit light, the sub-pixel connected to the same data signal line as the red sub-pixel and writing the data signal voltage after the red sub-pixel is the first sub-pixel. The data signal voltage for pre-charging the first sub-pixel is low, and the pre-charging of the first sub-pixel is poor, so it is marked as “poor”; the sub-pixel connected to the same data signal line as the blue sub-pixel or the green sub-pixel and writing the data signal voltage after the sub-pixel is the second sub-pixel. The data signal voltage for pre-charging the second sub-pixel is high, so the pre-charging of the second sub-pixel is good, and it is marked as “good”. As shown in Figure 8 , the third column sub-pixel displaying green and the fourth column sub-pixel displaying blue are both “poor”, as shown in Figure 8 L1, the fifth column sub-pixel displaying green and the sixth column sub-pixel displaying blue are both “good”, as shown in Figure 8 L2, after the blue-green mixed color, the charging difference will cause the brightness difference, that is, the display brightness of the third column sub-pixel displaying green and the fourth column sub-pixel displaying blue mixed in L1 is low, and the display brightness of the fifth column sub-pixel displaying green and the sixth column sub-pixel displaying blue mixed in L2 is high, so the phenomenon of vertical stripe defect as shown in Figure 10 .

[0067] Therefore, the embodiment of the present application makes the sub-pixels 100 displaying green color all be the sub-pixels 100 with better pre-charging by controlling the turn-on sequence of the transistors 300 and the arrangement sequence of the transistors 300, i.e., the display effect of the sub-pixels 100 displaying green color is better. Since the sensitivity of human eyes to green color is higher, the embodiment of the present application better solves the problem of vertical stripes, please refer to Figure 7 , the data signal voltage writing time of the sub-pixel 100 is 1H, the time of maintaining high level of the driving signal line 400 is 3H, i.e., 2H of pre-charging time of the sub-pixel 100 is added.

[0068] In this way, the data signal voltage of the previous sub-pixel 100 connected with the same data signal line 200 is written to pre-charge the sub-pixel 100, which can improve the charging time of the sub-pixel 100, so that the display effect of the sub-pixel 100 is better.

[0069] Please refer to Figure 1 In some embodiments, each data signal line 200 is connected with at least two columns of sub-pixels 100, and the sub-pixels 100 and the data signal line 200 are connected in a Z inversion manner.

[0070] Specifically, in the related art, the polarities of the sub-pixels connected with the same data signal line are arranged in a positive-negative or negative-positive sequence, while the embodiment of the present application uses the Z inversion manner to connect, so that the sub-pixels 100 connected with the same data signal line 200 have the same polarity (positive polarity or negative polarity), which can achieve the effect of reducing power consumption by half. Each data signal line 200 can be arranged between at least two columns of sub-pixels 100, and the two adjacent rows of sub-pixels 100 include a first sub-pixel row and a second sub-pixel row, among the sub-pixels 100 connected with the same data signal line 200, the sub-pixels 100 of the first sub-pixel row are connected on one side of the data signal line 200, and the sub-pixels 100 of the second sub-pixel row are connected on the other side of the data signal line 200, to form a Z inversion connection manner. In one embodiment, the sub-pixels 100 of the first sub-pixel row are connected on the left side of the data signal line 200, and the sub-pixels 100 of the second sub-pixel row are connected on the right side of the data signal line 200.

[0071] In this way, the sub-pixels 100 and the data signal line 200 are connected in a Z inversion manner, so that the polarities of the sub-pixels 100 connected with the same data signal line 200 are the same, thereby reducing power consumption.

[0072] Please refer to Figure 1In some embodiments, the two sub-pixels 100 connected to the same data signal line 200 in two adjacent rows form a period unit 700, and in the period unit 700, two sub-pixels 100 are connected to the first side of the data signal line 200, and two sub-pixels 100 are connected to the second side of the data signal line 200.

[0073] Specifically, in the pixel architecture based on Dual Gate and Z inversion, the number of sub-pixels 100 connected to the same data signal line 200 in each row is two, and in two adjacent rows, the two sub-pixels 100 connected to the same data signal line 200 in the first row are connected to the first side of the data signal line 200, and the two sub-pixels 100 connected to the same data signal line 200 in the second row are connected to the second side of the data signal line 200, and the four sub-pixels 100 form a period unit 700. In an embodiment, please refer to Figure 1 , the two sub-pixels 100 connected to Data2 in the first row are connected to the right side of Data2, and the two sub-pixels 100 connected to Data2 in the second row are connected to the left side of Data2, and the four sub-pixels 100 can form a period unit 700; the two sub-pixels 100 connected to Data2 in the third row are connected to the right side of Data2, and the two sub-pixels 100 connected to Data2 in the fourth row are connected to the left side of Data2.

[0074] In this way, by using the pixel architecture based on Dual Gate and Z inversion, the number of data signal lines 200 can be reduced, and the power consumption and cost can be reduced.

[0075] In some embodiments, when the data signal voltage written into the sub-pixel 100 is low, the sub-pixel 100 does not emit light; when the data signal voltage written into the sub-pixel 100 is high, the sub-pixel 100 emits light.

[0076] Specifically, please refer to Figure 7 , where 1 represents high level and 0 represents low level, when the driving signal line 400 outputs high level, the transistor 300 is turned on, and the turning on of the transistor 300 enables the data signal voltage of the data signal line 200 to be written into the sub-pixel 100, if the data signal voltage written into the sub-pixel 100 is 1, the sub-pixel 100 emits light; if the data signal voltage written into the sub-pixel 100 is 0, the sub-pixel 100 does not emit light. In an embodiment, a blue picture is displayed, and the data signals written into the sub-pixels 100 displaying red are all 0, so that the sub-pixels 100 displaying red do not emit light; and the data signals written into the sub-pixels 100 displaying blue or green are 1, so that the sub-pixels 100 displaying blue or green emit light.

[0077] In this way, by controlling the data signal voltage transmitted through the data signal line 200 to be high or low, it is possible to control whether the sub-pixel 100 to which the data signal voltage is written emits light or not.

[0078] In some embodiments, the array substrate 1000 can be obtained by setting a process flow.

[0079] Specifically, referring to Figure 11 , the process flow of the array substrate 1000 is 1 st ITO→Gate→SSM→PVX→2 nd ITO, wherein 1 st ITO is the Vcom electrode, 2 nd ITO is the pixel electrode, 1 st There is no insulating layer between the ITO and the Gate. The steps of setting the process flow are as follows:

[0080] 1. Make 1 st ITO layer: the material is ITO, the thickness is 700A, and the desired pattern (mainly the Vcom electrode) is formed by the process of plating, exposure, development, and wet etching. It can be a whole piece in the array substrate 1000.

[0081] 2. Make the Gate layer: the material is Mo / Al / Mo, the thickness is 150 / 3000 / 800, and the desired pattern (mainly the gate line) is formed by the process of plating, exposure, development, and wet etching. There is also a metal Vcom line formed under the gate line. After the fabrication is completed, a whole layer of GI insulating layer (thickness of 4000A, material of SiNx) is laid.

[0082] 3. Make the SSM layer: form the TFT and the SD metal. First, deposit an active layer (semiconductor layer) with a thickness of 1700A, then deposit an SD metal (form the source and drain of the TFT and the Matrix formed by the SD layer metal) with a thickness of 150 / 3000 / 800. Then use the SSM process (4Mask process) to form the source and drain of the TFT and the channel and Tx line by dry etching and wet etching once. The first wet etching etches away the SD metal to form the source and drain and the Tx line. Then, the second dry etching etches to expose the channel (the Tx line and the Data line are made in the same layer, which can be understood as parallel). Among them, the 4Mask process is to deposit the active layer and the SD layer at the same time. Compared with the traditional 5Mask, the 4Mask is to deposit the active layer and the SD layer together, coat PR glue, and only perform one Mask. Then, use SSM to form partial exposure in the channel area; first etch out the Source line, and then expose the channel by ashing.

[0083] 4. PVX Mask: deposit the uppermost layer of PVX, thickness of 4000A, material of SiNx, through the process of exposure, development, etching, dry etching of the unnecessary insulating layer, exposing the via, mainly the via place, such as the connection via of the pixel electrode and the half via formed by the patent.

[0084] 5. 2 nd ITO Mask: material of ITO, thickness of 700A, forming the desired pattern (mainly the pixel electrode) and the ITO connection part used for via connection through the process of plating, exposure, development, wet etching.

[0085] In this way, the array substrate 1000 can be obtained by setting the process flow.

[0086] The display panel provided by the embodiment of the present application comprises a cover plate and the array substrate 1000 of any one of the above embodiments, and the cover plate is arranged on the array substrate 1000.

[0087] Specifically, the driving unit comprises a gate driving (GOA) circuit, and the driving signal line 300 is connected to the gate driving circuit and the sub-pixel 100. Please refer to Figure 12 The GOA circuit can be a 19T1C structure, and one GOA circuit corresponds to one row of sub-pixels 100. When STV1 is high, the GOA circuit starts to work, M1 is opened by Input, so that VGH can charge the PU point, and the clock signal CLK1 is low at this time; when CLK1 becomes high, the potential of PU becomes higher due to the action of the capacitor C, so as to open M3 and M13, and M3 and M13 output CLK high level respectively, at this time, GOUT and GOUTC output high level, wherein GOUTC is an input signal Input of the GOA circuit of the next row, so that the GOA circuit outputs in turn to realize the function of shift register, and GOUT is the gate driving signal transmitted by the driving signal line 300, that is, the driving signal line 300 outputs high level at this time; wherein VDD1 and VDD2 are staggered (VDD1 is high and VDD2 is low, and VDD2 is high and VDD1 is low), so as to control the PD point, so that the PD point can reduce noise when the PU point is low, so as to make PU lower and not affect the output, so as to avoid damage of the TFT (thin film transistor) due to long time keeping high level.

[0088] In one embodiment, the display size is FHD (1920x1080), due to the Dual Gate design, the number of gate signal lines is 2160, the GOA is set to 4CLK, that is, Gate1 to Gate2160 are output in turn with 4CLK as one period, and the pre-charge time of 1H is increased, so that the high and low levels are 2H respectively, the time of writing data signal into the sub-pixel 100 is 1H, and the timing diagram is as followsFigure 13 As shown.

[0089] In this way, the sub-pixel 100 can be pre-charged by the data signal voltage written into the previous sub-pixel 100, and since the previous sub-pixel 100 connected to the same data signal line 200 emits light with the written data signal voltage, the data signal voltage written into the sub-pixel 100 is high, and thus the pre-charging of the target sub-pixel is more, and the light emitting brightness of the target sub-pixel is brighter; by controlling the light emitting brightness of each column of target sub-pixels displaying the target color to be brighter, the brightness difference in the display process can be avoided, the vertical stripe defect phenomenon is avoided, and the brightness is better, and a better display effect can be obtained.

[0090] The display device according to an embodiment of the present disclosure includes a housing and a display panel according to the above embodiment, and the display panel is disposed in the housing.

[0091] In this way, the sub-pixel 100 can be pre-charged by the data signal voltage written into the previous sub-pixel 100, and since the previous sub-pixel 100 connected to the same data signal line 200 emits light with the written data signal voltage, the data signal voltage written into the sub-pixel 100 is high, and thus the pre-charging of the target sub-pixel is more, and the light emitting brightness of the target sub-pixel is brighter; by controlling the light emitting brightness of each column of target sub-pixels displaying the target color to be brighter, the brightness difference in the display process can be avoided, the vertical stripe defect phenomenon is avoided, and the brightness is better, and a better display effect can be obtained.

[0092] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present specification, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0093] In addition, the term "connection" should be understood broadly, for example, it can include fixed connection, or detachable connection, or integral connection; it can include direct connection, or indirect connection through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0094] Furthermore, the terms "first", "second", etc. are used herein only to describe the different steps of the method and are not to be construed as indicating or implying relative importance or a specific order of the steps. Thus, a feature defined with "first", "second", etc. can implicitly or explicitly include at least one of the features.

[0095] Any process or method described in a flowchart or otherwise described herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for performing specific logic functions or steps in the process, and the various embodiments of the application include additional or fewer processes, steps, or modules, and the representation of the process or method in the flowcharts or otherwise described herein can be understood as being an abstraction of the actual code that can be structured differently. Additionally, the order in which a process or method is described is not necessarily the order in which the processes can be performed.

[0096] Although the embodiments of the present application have been shown and described above, it is to be understood that the above-described embodiments are merely exemplary, and the present application is not limited thereto, and changes, modifications, substitutions and variations can be made by those skilled in the art without departing from the scope of the present application.

Claims

1. An array substrate, characterized in that, The array substrate includes: Multiple sub-pixels, wherein the sub-pixels are arranged in an array; Multiple data signal lines are provided to supply data signal voltage to the sub-pixel, and the sub-pixel includes a target sub-pixel, which is used to display a target color. A transistor is connected to the sub-pixel and the data signal line. When the transistor is turned on, it drives the sub-pixel to write the data signal voltage so that the sub-pixel can emit light and display the corresponding color. Sub-pixels in the same row are driven by two rows of transistors, and the transistors in the same row are turned on simultaneously. When displaying a dual-color mixed image, the turn-on order of the transistors and the arrangement order of the transistors are different, so that the target sub-pixel in front of the target sub-pixel emits light. The target sub-pixel in front of the target sub-pixel is connected to the same data signal line as the target sub-pixel. In terms of the turn-on order, the transistor corresponding to the target sub-pixel in front of the target sub-pixel is located in the row before the transistor corresponding to the target sub-pixel. A drive signal line is provided, wherein the transistor is connected to the drive signal line, and one drive signal line is used to drive a row of transistors to turn on. The arrangement order of the transistors is the same as the arrangement order of the drive signal lines, and the driving order of the drive signal lines is the same as the arrangement order of the drive signal lines. The transistors and the drive signal lines are not connected in the arrangement order, so that the turn-on order of the transistors is different from the arrangement order of the transistors.

2. The array substrate according to claim 1, characterized in that, The array substrate further includes: A drive signal line, wherein the transistor is connected to the drive signal line, and one drive signal line is used to drive a row of transistors to turn on; An array gate driving unit is provided, wherein each array gate driving unit is connected to a driving signal line. The array gate driving unit outputs a driving signal, which drives the transistor to turn on through the driving signal line. The array gate driving units are arranged in a one-to-one correspondence with the driving signal line and the transistor. The order of the output driving signals of the array gate driving units is different from the arrangement order of the array gate driving units, so that the order in which the driving signal line drives the transistor to turn on is different from the arrangement order of the driving signal line.

3. The array substrate according to claim 2, characterized in that, The array substrate further includes: A clock signal line is connected to the array gate driving unit. The clock signal line is used to output a clock signal to the array gate driving unit to control the order of the output driving signals of the array gate driving unit. The order of the clock signals output by the clock signal line is different from the arrangement order of the array gate driving units connected to the clock signal line, so that the order of the output driving signals of the array gate driving unit is different from the arrangement order of the array gate driving units.

4. The array substrate according to claim 1, characterized in that, The sub-pixel includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. When displaying a dual-color mixed image, the first color sub-pixel does not emit light, while the second color sub-pixel and the third color sub-pixel emit light.

5. The array substrate according to claim 4, characterized in that, The target sub-pixel is the second color sub-pixel, and the sub-pixel before the target is either the second color sub-pixel or the third color sub-pixel.

6. The array substrate according to claim 1, characterized in that, The data signal voltage written to the target sub-pixel is used to pre-charge the target sub-pixel, and the pre-charge voltage of all target sub-pixels is greater than a set voltage.

7. The array substrate according to claim 1, characterized in that, Each of the data signal lines connects to at least two columns of the sub-pixels, and the sub-pixels and the data signal lines are connected in a Z-reversed manner.

8. A display panel, characterized in that, The display panel includes a cover plate and an array substrate as described in any one of claims 1-7, wherein the cover plate is disposed on the array substrate.

9. A display device, characterized in that, The display device includes a housing and a display panel as described in claim 8, wherein the display panel is disposed within the housing.

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