Systems and methods for configuring display devices and display systems

Abstract

The displays, systems, and methods can be used in applications including, but not limited to, projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as headsets or other near-eye devices or systems. According to the invention, the tileable or tilable displays and methods provide displays of different sizes, such that the tileable or tilable displays are configured to accommodate the display sizes required by various wearable and mobile devices that need or include displays.

Description

[0001] Priority requirements

[0002] This patent application claims the benefit of priority to U.S. Application Serial No. 63 / 229,642, filed August 5, 2021, the entire contents of which are incorporated herein by application. Technical Field

[0003] This disclosure relates to displays, such as light-emitting diode (LED) displays, including LED displays and OLED displays, and microdisplays or micro-versions thereof (e.g., micro-LED and micro-OLED displays). More specifically, this disclosure relates to configurable LED displays. Background Technology

[0004] Typically, direct-view applications with medium-sized displays (i.e., not microdisplays, monitors, televisions, etc.) for portable, wearable, mobile, or handheld devices are made using transmissive LCD or OLED technology with a TFT backplane. OLED displays have short lifespans and limited brightness, while LCD displays require backlighting, consuming power per pixel regardless of whether the pixels are on or off. TFTs, while inexpensive, have excessive resistance (wasting power) and are too large to fabricate complex circuitry under each pixel, thus limiting them to driving schemes that sequentially drive each row of the display, where each pixel has a very short duty cycle, requiring high current density to achieve sufficient brightness. In contrast, while microLED displays offer long lifespans, microLED arrays coupled to silicon backplanes to form microLED displays often result in displays with random defects.

[0005] In constructing microLED displays with silicon backplanes for physically larger applications (i.e., not microdisplays, but direct-view displays, such as for VR headsets, wearable devices like watches, and smartphones, or even monitors and televisions), building various shapes and sizes often requires redesigning the display and manufacturing process for each new application. As display sizes increase, yields decrease, making some applications prohibitively expensive or at least uncompetitive. Summary of the Invention

[0006] According to embodiments of this disclosure, the display can be used in applications including, but not limited to, projectors, head-up displays, and augmented reality (AR), mixed reality (MR), and virtual reality (VR) systems or devices, such as headsets or other near-eye devices or systems. According to embodiments of this disclosure, the tileable or tilable display and method provide displays of different sizes, such that the tileable or tilable display is configured to accommodate the display size required by various wearable and mobile devices that need or include the display. Attached Figure Description

[0007] Figure 1 An array of tiles for a circular watch display according to an embodiment of the present disclosure is shown.

[0008] Figure 2 A block with seams is shown according to an embodiment of the present disclosure.

[0009] Figure 3 This illustrates the conversion of operating dies (e.g., backplane dies) according to embodiments of the present disclosure into a form that can be almost seamlessly adjacent.

[0010] Figure 4 A cross-section of a block on a PCB according to an embodiment of the present disclosure is shown.

[0011] Figure 5 The back side of a block according to an embodiment of this disclosure is shown.

[0012] Figure 6 The diagram illustrates the connection of blocks for forming an array according to an embodiment of the present disclosure.

[0013] Figure 7 A block backplane circuit system according to an embodiment of the present disclosure is shown.

[0014] Figure 8 A single pixel circuit system according to an embodiment of the present disclosure is shown.

[0015] Figure 9 It is a serial stream format according to the embodiments of this disclosure. Detailed Implementation

[0016] Detailed embodiments are disclosed herein as needed. It must be understood that the disclosed embodiments are merely examples of various alternative forms. As used herein, the term "exemplary" is widely used to refer to embodiments used as illustrations, specimens, models, or patterns. The drawings are not necessarily drawn to scale, and some features may be enlarged or reduced to show details of specific components. In other instances, well-known components, systems, materials, or methods known to those skilled in the art have not been described in detail to avoid obscuring the scope of this disclosure. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but are merely intended as the basis for the claims and as a representative basis for teaching those skilled in the art.

[0017] This disclosure utilizes displays composed of independently manufactured and tested "tiles" (addressing production limitations because they are smaller, tested during manufacturing, and can be repaired before the manufacturing process is complete, thus increasing yield). Furthermore, different wearable or mobile device manufacturers attempt to differentiate themselves through industrial design, resulting in a wide variety of display sizes and shapes, which would require new designs for each customer. However, according to embodiments of this disclosure, the use of tiled or tileable displays and methods allows for the design or configuration of new displays by arranging tiles on a PCB (allowing for rapid design and manufacturing compared to creating new silicon dies and microLED arrays).

[0018] Figure 1 A pseudo-circular array of display tiles is shown. In embodiments of this disclosure, the tile array or display tile array approximates a circle and can be used in display devices that function as circular devices (e.g., LED display devices or LED panels). In embodiments of this disclosure, any number of tiles can be arranged in any shape. In embodiments of this disclosure, the lighting device (e.g., the tile) includes lighting dies (e.g., LED dies) and operating dies (e.g., backplane dies).

[0019] In embodiments of this disclosure, the lighting die (e.g., an LED die) includes lighting elements coupled to or integrated into a lighting substrate (e.g., a GaN substrate). In embodiments of this disclosure, an array of lighting elements, such as LEDs of any type or size, is formed on the lighting substrate. The lighting elements (e.g., LEDs) or lighting arrays (e.g., an array of lighting elements) and the lighting substrate (e.g., an LED substrate) are integrated and / or coupled together to form the lighting die (e.g., an LED die).

[0020] In embodiments of this disclosure, a pixel is formed when the lighting element of a lighting die is coupled (e.g., electrically coupled) to a circuitry system (including at least a pixel circuitry system) for controlling or operating (e.g., driving one or more corresponding lighting elements). In embodiments of this disclosure, the pixel circuitry system includes at least a driving circuitry system. In embodiments of this disclosure, the driving circuitry system includes at least a pixel logic circuitry system for determining the on / off state of the pixel based on time, and an input / output circuitry system for supplying current to the LED. In embodiments of this disclosure, each lighting element (e.g., an LED) has a set of pixel circuitry systems.

[0021] In embodiments of this disclosure, each lighting die (e.g., an LED die) is coupled (e.g., electrically coupled) to an operating die (e.g., a backplane die). The operating die (e.g., a backplane die) includes a backplane substrate and pixel circuitry and / or pixel-related circuitry.

[0022] In embodiments of this disclosure, it is then made of silicon and referred to as a silicon operating die (e.g., a backplane die). In embodiments of this disclosure, the operating die (e.g., a backplane die) includes circuit systems (e.g., pixel circuit systems) disposed on, coupled to, integrated into, formed in, deposited on, or embedded in a backplane substrate.

[0023] In embodiments of this disclosure, the circuit system (e.g., a pixel circuit system) or driving circuit system is at least divided into a pixel logic circuit system and an input / output circuit system. In embodiments of this disclosure, the pixel logic circuit system operates or is located in one or more portions of the backplane substrate, and the pixel logic circuit system operating or being located in one or more portions of the backplane substrate differs from the input / output circuit system operating or being located in one or more portions of the backplane substrate.

[0024] In embodiments of this disclosure, the pixel logic circuitry system operates or is located in one or more strips or stripes of the backplane substrate, which are different from the one or more strips or stripes of the backplane substrate in which the input / output circuitry system operates or is located.

[0025] In embodiments of this disclosure, each of the lighting elements is associated with a pixel circuitry (i.e., a driving circuit or driving circuitry system) that drives the lighting element (e.g., determines the grayscale output of the lighting element). In embodiments of this disclosure, each of the lighting elements is associated with its own pixel circuitry (i.e., a driving circuit or driving circuitry system) that drives the lighting element (e.g., determines the grayscale output of the lighting element). In embodiments of this disclosure, each of the lighting elements is associated with a pixel logic circuitry system or circuit and an input / output circuitry system or circuit. In embodiments of this disclosure, a combination of each lighting element (e.g., an LED) and its corresponding circuitry system (e.g., a pixel circuitry system), including but not limited to a driving circuitry system, forms the pixels of a block. In embodiments of this disclosure, there are electrical contact elements between the LED and the pixel circuitry system because they are located on different wafers before bonding. In embodiments of this disclosure, the electrical contact elements may be located on the wafer where the LED is located or on the wafer where the pixel circuitry system is located.

[0026] In embodiments of this disclosure, each lighting element (e.g., an LED) and its corresponding circuitry, such as combinations of each lighting element (e.g., an LED) and its corresponding circuitry (e.g., its corresponding pixel logic circuitry and its corresponding input / output circuitry), form pixels of a block.

[0027] In embodiments of this disclosure, the lighting element is a main lighting element. In embodiments of this disclosure, the main lighting element includes more than one lighting element (e.g., an LED). In embodiments of this disclosure, the main lighting element includes at least three (3) lighting elements, for example, a set of three (3) lighting elements (e.g., LEDs).

[0028] In embodiments of this disclosure, a pixel is formed when an illumination element (e.g., an LED) is coupled (e.g., electrically coupled) to a circuitry (e.g., a pixel circuitry) that drives each illumination element (e.g., an LED). In embodiments of this disclosure, a master pixel is formed when a master illumination element (e.g., a set or cluster of LEDs, such as three (3) LEDs) is coupled (e.g., electrically coupled) to a circuitry (e.g., a pixel circuitry) that drives each illumination element (e.g., an LED). In embodiments of this disclosure, the illumination elements (e.g., LEDs) are a set of three primary colors, and when LEDs are grouped into sets, gaps are present between them, achieving perceptually seamless adjacency. In embodiments of this disclosure, a patch includes more than one master pixel, e.g., a master pixel array. In embodiments of this disclosure, the pixel circuitry includes at least a driving circuitry. In embodiments of this disclosure, the driving circuitry includes at least a pixel logic circuitry and an input / output circuitry.

[0029] In embodiments of this disclosure, the blocks can be arranged in any pattern, for example, on a PCB. In embodiments of this disclosure, the blocks can be arranged in any pattern, for example, on a PCB to form a display. For the purpose of illustrating the use of the blocks, according to embodiments of this disclosure, Figure 1 The image shows a pseudo-circular array of tiles. For example, as shown... Figure 1As shown, a pseudo-circular array of display tiles is arranged on a printed circuit board (PCB) (not shown) and used for a dial display. In the example shown, according to an embodiment of this disclosure, 88 tiles—each 3.6mm × 3.6mm and containing 60 × 60 pixels—are arranged to form a dial, for example, with a diameter of 36mm. However, those skilled in the art will understand that the number of tiles, the number of pixels and / or main pixels per tile, the shape of the tiles, and / or the shape of the tile array can vary. In embodiments of this disclosure, the pattern or arrangement of tiles on the PCB can vary.

[0030] In the implementation of this disclosure, such as Figure 2 As shown, adjacent tiles are arranged on the PCB, with spaces, gaps, or seams between them. Figure 2 As shown, in embodiments of this disclosure, spaces, gaps, or seams exist between the sides or edges of two adjacent tiles (each tile having one or more master pixels or a set of three (3) lighting elements (e.g., LEDs and their associated pixel circuitry)). Those skilled in the art will understand that any reference to LED includes any type of LED (e.g., LED, OLED, microLED, or microOLED). Figure 2 As shown in the embodiments of this disclosure, gaps, spaces, or seams exist between adjacent tiles. Those skilled in the art will understand that the number and color of LEDs in a main lighting element or main pixel (e.g., an assembly of LEDs and / or a circuitry electrically coupled to each of the LEDs) can vary.

[0031] In embodiments of this disclosure, the spacing (i.e., the center-to-center distance between lighting elements (e.g., primary pixels, primary lighting elements, or a set of lighting elements (e.g., LEDs)) must be such that the space between lighting elements (e.g., primary pixels, primary lighting elements, pixels, or a set of lighting elements (e.g., LEDs)) is sufficient to account for gaps, seams, and spaces without interrupting the pixel spacing (i.e., the distance between the center of one lighting element (e.g., primary pixel or primary lighting element) and the center of another lighting element (e.g., primary pixel or primary lighting element)), while simultaneously maintaining the pixel spacing the same or substantially / approximately the same for all adjacent lighting elements (e.g., primary lighting elements or primary pixels) or at least some adjacent lighting elements (e.g., primary lighting elements or primary pixels). In embodiments of this disclosure, when the tile is a monochrome tile, the primary pixel and the pixel are identical.

[0032] Figure 3The diagram illustrates the difference between a conventional backplane die and a tileable or tilable operational die (e.g., a backplane die) according to embodiments of this disclosure, such as an operational die (e.g., a backplane die (such as a silicon backplane die)), which has a distinctly seamlessly adjacent tiled form because the spacing between the main illumination elements or main pixels is the same. The conventional die planar diagram has or includes I / O and logic circuitry regions (wherein the input region includes I / O buffers, and the buffers are used to convert between externally used logic levels and internal logic levels, and the logic region includes registers, state machines, and pixel drive circuitry, and is used to receive image data from the outside and assign it to pixels in the active region).

[0033] In conventional die designs, input and logic regions are located or positioned around the active regions of the display (i.e., the regions containing pixels that will generate, for example, images). In embodiments of the operating die, according to embodiments of this disclosure, the operating die (e.g., a tileable backplane die, such as a silicon backplane die) includes stripes of alternating pixel logic circuitry and I / O circuitry. In embodiments of this disclosure, the I / O circuitry includes I / O buffers, and the buffers are used to convert between externally used logic levels and internal logic levels. In embodiments of this disclosure, the logic regions include registers, state machines, and pixel driver circuitry, and are used to receive image data from the outside, allocate it to pixels in the active regions, and the wiring is arranged in rows and columns such that connections to LED pixels are maintained in the array. In embodiments of this disclosure, illumination elements such as LEDs may be positioned above the pixel logic circuitry or stripes, the I / O circuitry or stripes, or both. In embodiments of this disclosure, the circuitry strip is embedded in the backplane substrate of the operating die.

[0034] Traditional backplanes typically include peripheral bonding pads on a silicon die or bump / pillar connections on a silicon die to connect I / O buffers to a circuit board or package. Tile-out or tileable backplanes differ from traditional backplanes because, according to embodiments of this disclosure, they have through-silicon vias (TSVs) for connecting or electrically coupling one side or front side of an operating die (e.g., a backplane die such as a silicon backplane die) on which an illumination die (including, for example, an illumination element (e.g., an LED) or a main illumination element or an LED assembly forming a main pixel when coupled or electrically coupled to a pixel circuitry system) to the second side or back side of the operating die (e.g., a backplane die such as a silicon backplane die) and / or the circuitry of the PCB.

[0035] Figure 4A cross-section of a block on a PCB is shown. In embodiments of this disclosure, the block includes an operational die (e.g., a backplane die, such as a silicon backplane die or wafer) coupled (e.g., bonded and / or electrically coupled) to a lighting die (e.g., an LED chip or die) using bonding and connection methods known in the art.

[0036] In embodiments of the lighting die, according to embodiments of this disclosure, the LED is formed, integrated into, or fabricated in a substrate such as a GaN substrate. However, those skilled in the art will understand that the substrate material can vary; for example, the substrate can be any semiconductor material capable of forming a light-emitting structure. In embodiments of this disclosure, metal contacts are coupled to or integrated into the lighting die (e.g., the LED die) for electrically coupling the lighting die to an operating die (e.g., a backplane die, a silicon die, or a silicon operating die).

[0037] According to embodiments of this disclosure, an illumination device (e.g., a tile) includes vias (e.g., substrate vias or through-silicon vias (TSVs)) for connecting to a power supply and interface on a first or back side and a second or front side of an operating die (e.g., a silicon die) to provide power to the tile circuitry (e.g., I / O logic circuitry and / or stripes, pixel circuitry logic circuitry and / or stripes, and / or portions of conductive circuitry deposited, coupled to, or integrated into a PCB, such as copper deposits or other conductive elements). In embodiments of this disclosure, the vias (e.g., substrate vias or through-silicon vias (TSVs)) receive data voltage input at an I / O buffer and are used to connect power and grounding devices, components, and / or sources to the illumination die (e.g., an LED die) and / or the operating die (e.g., a backplane die).

[0038] In embodiments of this disclosure, the openings of substrate vias, such as through-silicon vias (TSVs), on the back side of an operating die (e.g., a silicon die) are wetted with solder or other conductive materials for attaching solder to an underlying PCB or the circuitry of the underlying PCB.

[0039] In embodiments of this disclosure, tile circuitry systems (e.g., I / O logic circuitry or circuitry stripes and pixel or driver circuitry logic stripes) are deposited, formed, embedded, or integrated into operating dies (e.g., backplane substrates, silicon operating dies, or backplane dies or silicon dies). In embodiments of this disclosure, lighting dies (e.g., LED dies) are at least electrically connected, coupled, and / or bonded to operating dies, and silicon dies are connected, coupled, electrically coupled, or connected and / or bonded to a PCB. In embodiments of this disclosure, connectivity exists between tiles or tile arrays via a PCB (i.e., the substrate housing the tiles or the substrate where the tiles are located, coupled, bonded, or positioned).

[0040] In embodiments of this disclosure, circuitry or one or more conductive elements are deposited, fabricated, or integrated into a PCB (e.g., on one or more sides of the PCB) and used, for example: (1) electrically connecting lighting dies (e.g., LED dies) and / or operating dies (e.g., backplane dies) to a power source or electrical source, a data source, a voltage source, and / or a current source, and / or (2) receiving data, voltage, or other input. In embodiments of this disclosure, the circuitry or conductive elements or deposits on the PCB are made of copper and may be referred to as multiple copper traces or copper traces. However, those skilled in the art will understand that conductive elements may be made of conductive materials other than copper. The PCB also serves as a structure providing support, rigidity, or a rigid surface to a tile array. In embodiments of this disclosure, the PCB may include one, two, or more layers of circuitry (e.g., any tile-related circuitry).

[0041] Figure 5 The back side of the tile is shown. In embodiments of this disclosure, such as... Figure 5 As shown, on the back or bottom of the block is an array of TSV openings for receiving, for example, input data or voltage, output data or voltage, or signals. In embodiments of this disclosure, the TSV openings can be used to electrically connect a lighting die (e.g., an LED die) to a circuit system on a PCB (e.g., the circuit system (1) electrically connects the LED die to a power source or electricity source, a data source, a voltage source, and / or a current source, and / or (2) receives data, voltage, or other inputs). In embodiments of this disclosure, the TSVs can be used to output data from the block.

[0042] Figure 5 The diagram illustrates, for example, a through-hole in an operating die (e.g., a silicon die) for making a power connection between a PCB (which may be connected to a voltage source or some other power source) and a lighting die (e.g., an LED die). Figure 5The embodiments of this disclosure also illustrate example I-layer wiring patterns of a PCB, such as wires or conductive elements deposited on or embedded in the PCB. In embodiments of this disclosure, a TSV labeled DI is used to transmit data from a controller (which...) Figure 6 The diagram shows (and may be referred to as a tile array controller, array controller, and / or master controller) with serial data inputs connected to the tiles. In embodiments of this disclosure, Figure 6 The controller shown is external to the blocks and / or block arrays. In embodiments of this disclosure, the controller (e.g., a block array controller or a main controller) is located on or coupled to a substrate such as a PCB, and the blocks are also coupled to or located on that substrate. In embodiments of this disclosure, the controller controls the operation of the blocks, each block in the block array, and / or the operation of the block array as units. In embodiments of this disclosure, the controller (e.g., a block array controller or a main controller) assigns data to the blocks and controls when they display new data. In embodiments of this disclosure, Figure 6 Arrows between controllers and Figure 6 The arrows between the blocks indicate information about the PCB. Figure 5 The serial data and clock tap transmission (“T”) line shown is a conductive element (e.g., a wired element such as a copper wire element).

[0043] The TSV labeled CK is used to connect the clock voltage output from the controller to the block to sample serial data and provide a clock to the block's logic circuitry. (See also: [link to relevant documentation]). Figure 6 As described, the block receives serial data (DI) and clock output (CK) from the controller.

[0044] In embodiments of this disclosure, at least one via is used to connect or deliver power to the pattern and / or lighting die (e.g., LED die) via power rails (e.g., conductive elements, grounding elements / components, cables, and / or other components coupled to, deposited in, embedded in, and / or integrated into the PCB) via, for example, via coupling or electrical connection to the operating die (e.g., backplane die or silicon operating die). As a result, according to embodiments of this disclosure, power is supplied to lighting devices (e.g., pattern and / or lighting die (e.g., LED die)).

[0045] In embodiments of this disclosure, lighting dies (e.g., LED dies) are coupled to operating dies (e.g., silicon operating dies or backplane dies). In embodiments of this disclosure, through-silicon vias (e.g., four TSVs) are used to connect the PCB to the power rails (i.e., VDD) of the lighting dies (e.g., LED dies) and / or the blocks, providing sufficient current carrying capacity and low resistance. Those skilled in the art will understand that the number of vias used to connect components of the operating die (e.g., backplane die) to the power supply, other components of the display system, the PCB, and / or other components of the PCB (or electrically coupled to the PCB) can vary.

[0046] In embodiments of this disclosure, a controller (e.g., a tile array controller, array controller, master controller, and / or master controller chip) broadcasts or transmits data to all tiles, or is used to broadcast or transmit data to all tiles or at least some tiles, and each tile (or at least some tiles) knows which portion of the data it reserves for itself based on its (i.e., the tile's) address or, for example, based on the connection method of the tile's address pins. In embodiments of this disclosure, the controller (e.g., an array controller) sends data to a first tile, and then the data is subsequently streamed or transmitted to the next tile in the tile array. In embodiments of this disclosure, as Figure 6 As shown, each block identifies and extracts data destined for it based on information in a header associated with data sent from a controller (e.g., an array controller, a main controller, or a main controller chip). In embodiments of this disclosure, each block can receive data (e.g., data represented as voltage waveforms or pulses) based on the block address identified in the address bits of data received from the controller (e.g., an array controller, a main controller, or a main controller chip) at the array. For example, in embodiments of this disclosure, each of the TSVs labeled A0 to A5 identifies a location within an LED or main pixel array and is electrically connected to a pixel, main pixel and / or LED, main illumination element, or LED in the main pixel array.

[0047] In the implementation of this disclosure, such as Figure 6 As shown, the tiles are assembled into a tile array and electrically interconnected (e.g., via a cable) via a serial bus consisting of, for example, data signals and an optional clock signal. In embodiments of this disclosure, as... Figure 6 As shown, the controller (e.g., array controller, master controller, or master controller chip) converts incoming image or video data in a format such as a standard format (e.g., MIPIDSI) into a custom serial format that the tiles can process.

[0048] Figure 6The first side or left side shows the tile array, and the second side or right side of the tiles (the side pointed to by the arrow) shows that the array consists of multiple tiles connected in series and is controlled by a controller (e.g., an array controller, a main controller, or a main controller chip) coupled to at least one of the series or multiple tiles.

[0049] In embodiments of this disclosure, a custom format is determined based on an implementation capable of distributing data to all tiles and allowing each tile to easily capture its own data portion. In embodiments of this disclosure, each tile has a predetermined position in the array, such as... Figure 5 The described data is stored and / or displayed when its address is identified or known, and it is known how the data on the serial data input is arranged as it travels along the bus associated with its address or its geographic location or a portion of the array (i.e., the entire array or at least a portion of the array). In embodiments of this disclosure, blocks ignore any data on the serial bus that is not associated with its address.

[0050] In embodiments of this disclosure, tapped transmission lines with terminations at their ends include transmission line segments, and according to an embodiment of a transmission line matching method (i.e., a method for providing a transmission path free from damage such as reflections and for matching the impedance between the transmission line and other components (e.g., electrical components) and / or blocks to which the transmission line is electrically connected, to provide a controlled transmission line impedance in conjunction with the input capacitance connected to the data input or data input pin on each block), each transmission line segment (i.e., a transmission line segment between two blocks in series) is tuned by adjusting its width.

[0051] In embodiments of this disclosure, when new data arrives at a tile from, for example, an image or video data source, data from the previous image or video frame is being displayed, and this allows for the transmission of new data or data from the next frame throughout the entire video frame period (i.e., the frame currently being displayed), which reduces the required data rate. For example, as Figure 1 As shown, the array (e.g., an array of main pixels or main illumination elements) in the embodiments of this disclosure provides, for example, 220,000 pixels and has 660,000 sub-illumination elements (e.g., sub-pixels (e.g., red LEDs, green LEDs, blue LEDs)), each requiring 8 bits of data to define its brightness. In the embodiments of this disclosure, support is provided. Figure 1 The implementation shown requires a serial data rate of 158.4 Mb / s at a refresh rate of 60 Hz.

[0052] Figure 7An embodiment of a backplane circuit system, such as an operating die (e.g., a silicon die or a tile backplane) circuit system, according to an embodiment of this disclosure is shown. In an embodiment of this disclosure, (1) the tile operating die (e.g., a backplane or backplane die) circuit system includes or is coupled to a receiver, logic circuit system, algorithm and / or software algorithm or module for DIN (i.e., data input / signal) and CLK input / signal (e.g., serial data and clock voltage input) to decode serial data received at the receiving logic circuit, circuit system or block, and (2) the tile operating die (e.g., a backplane or backplane die) circuit system determines when to load such serial data into the pixel circuit array and when to update the pixels to display the loaded data. In an embodiment of this disclosure, the pixel circuit (e.g., Figure 7 The pixel circuitry (as shown) is included in an operating die (e.g., backplane, backplane die, or silicon die) circuit system, and includes receiving and active storage devices (e.g., memory devices). Those skilled in the art will understand that the pixel circuitry can be driven using any modulation method. According to embodiments of this disclosure, the pixel structure will... Figure 8 Further details are provided below.

[0053] The tile controller logic circuit system and / or device extracts data from the serial data stream (e.g., represented by voltage waveforms) transmitted via a serial bus to the tile, places it on the data bus of the column for the pixel array (to which it should be written), and then loads it into the main pixel using the ROW-WRITE strobe.

[0054] The tile controller also generates a LOAD output control voltage for all primary pixels or primary illumination elements (or at least a subset thereof) within the tile, which controls the transfer of data from the receive memory to the active memory and outputs a time-varying value on the TVV bus, which will... Figure 8 Further details are provided below.

[0055] The tile control logic / circuit system / software / device also includes a time-varying value (TVV) generator that creates varying digital patterns for use by the pixels. In embodiments of this disclosure, the bias control circuitry, software, and / or device includes a luminance control register that provides digital values ​​to the DAC and a current DAC that converts the register values ​​into current. The current is then converted into a voltage suitable for biasing current sources electrically coupled to individual pixels or to pixel circuitry systems.

[0056] In embodiments of this disclosure, a configuration register may be written to data extracted from incoming serial data received by a deserializer and may be used to control the bias current set by a bias control circuitry and / or device. In embodiments of this disclosure, the configuration register may or may not store information about the X and Y pixel counts of the tiled display (i.e., the pixel count per row and the pixel count per column) and the activity state of the tiles (such as sleep or wake-up).

[0057] like Figure 8 As shown in the embodiments of this disclosure, each sub-pixel (one of a set of, for example, three, for each main pixel or main illumination element) includes an illumination element (e.g., an LED, microLED, OLED, or microLED device or component) electrically coupled to memory elements, such as two sets of memory elements, a logic circuit system having a latch (e.g., a final latch) to which it is electrically coupled, the final latch, and a current driver for supplying modulation current to the LED. Those skilled in the art will understand that the number of memory elements, latches, and current drivers can vary.

[0058] In embodiments of this disclosure, a receiving storage device (e.g., a memory device or a receiving pixel memory device) is loaded with image data or video data (e.g., image or video grayscale data) from a tile controller. The tile controller extracts data to be written to the tile from a serial data stream and places or transmits it to a data bus containing the column of the pixel to be written or the main pixel via a deserializer and decoder. The tile controller then outputs a ROWWRITE signal for the row of pixels to be written. Those skilled in the art will understand that other row-column scanning methods can be used to control the ROWWRITE operation.

[0059] Then, in embodiments of this disclosure, the tile controller outputs a LOAD output voltage or signal that initiates the transfer of data from a receiving storage device (e.g., a memory device or a receiving-storage memory device) to an active storage device (e.g., a memory or an active pixel memory device). Then, in embodiments of this disclosure, a display cycle begins. During this cycle, the tile controller provides a changing value or voltage on a time-varying value (TVV) bus, which, combined with a value (in the case of software) or a value represented by a voltage in an active storage device such as a memory, is combined with pixel logic hardware and / or software or pixel logic hardware devices or methods and / or software functions, algorithms, or modules to generate a time-varying voltage, such as a single-bit voltage, voltage pulse, or signal for modulating current. In embodiments of this disclosure, at each change in the TVV bus caused by the tile controller, a COMPUTE signal or output generated by a counter in the tile controller is determined or output to a logic function circuit system and / or latch to cause the calculation of a single-bit output or signal and latch it into a final latch, the output of which directly controls the on / off state of the current source. The modulation of the pixel logic hardware and / or software can be any of a variety of generated digital modes, such as PWM or binary weighted pulse width, used to change the brightness of each pixel based on data loaded into a storage device (e.g., memory).

[0060] In embodiments of this disclosure, the serial data stream from the tile array controller or main controller to the tiles is formatted into frames corresponding to the display's refresh rate in both duration and frequency. In embodiments of this disclosure, such as... Figure 9 As shown, each frame contains a Start of Frame (SOF) marker, which contains a unique pattern that the decoding logic circuitry of the tile controller can use to robustly detect the start of a frame (i.e., in the data received by the tile), followed by header information describing the content of the video data, such as the expected number of words in the data stream and the number of bits in each word, information about the number of pixels per row in the configured display, and also includes global (i.e., for the entire pixel array or a predetermined portion thereof) register updates such as brightness control or sleep / wake state.

[0061] In embodiments of this disclosure, the serial data stream transmitted from the tile controller or display controller to the tile can be encoded, for example, using 8b10b or 8b9b encoding, to provide robust transmission and reception, error detection, unique symbols for frame start, and other control purposes (e.g., tile power state control). Each tile stores its own data, indexed into the received pixel data using its address, and identifies the start and end of the data sent to that tile.

[0062] According to some embodiments of this disclosure, a display device includes an illumination die, wherein the illumination die includes at least one illumination element, said at least one illumination element being coupled to an illumination element substrate, formed on an illumination element substrate, or integrated into an illumination element substrate; and a backplane device coupled to the illumination die, wherein the backplane device includes a backplane substrate and a pixel circuit system, and the pixel circuit system being embedded in the backplane substrate, integrated into the backplane substrate, formed on the backplane substrate, or coupled to the backplane substrate, and wherein said pixel circuit system includes a pixel logic circuit system and an input / output logic circuit system.

[0063] In some embodiments, the pixel circuit system includes a driving circuit system. In some embodiments, at least one lighting element includes three lighting elements. The lighting element is an LED in some embodiments, and a micro LED in others. In some embodiments, the pixel circuit system is electrically coupled to at least one lighting element, and the pixel circuit system drives at least one lighting element. In some embodiments, the pixel circuit system is coupled to at least one lighting element via a conductive element, and the pixel circuit system drives at least one lighting element.

[0064] In some embodiments, the backplane assembly is made of a material including silicon or other semiconductors in which transistors can be formed. In some embodiments, the illumination elements have conductive portions, and the pixel circuitry includes conductive portions for electrically coupling the illumination elements to their respective pixel circuits. In some embodiments, the backplane assembly has a TSV, wherein the top side of the backplane assembly is connected to the back side of the backplane assembly via conductive material or means on the ends of the TSV. In some embodiments, the PCB is electrically coupled to the backplane assembly via conductive elements that couple the PCB and the backplane assembly using TSVs. In some embodiments, at least three illumination elements form a first main pixel. In some embodiments, the display device includes a second main pixel, wherein the second main pixel is electrically coupled to the first main pixel via conductive components or cables. In some embodiments, the first main pixel and the second main pixel form a tile.

[0065] In some embodiments, the display device includes a plurality of blocks, wherein each block includes an illumination die. The illumination die includes at least one illumination element, said at least one illumination element being coupled to, formed in, or integrated into an illumination element substrate; and a backplane device coupled to the illumination die, wherein the backplane device includes a backplane substrate and a pixel circuit system, and wherein the pixel circuit system is embedded in, integrated into, formed on, deposited on, or coupled to the backplane substrate. The pixel circuit system includes a pixel logic circuit system, an input / output logic circuit system, and a PCB. Multiple blocks are electrically coupled via: at least one circuit system that performs at least one of the following: embedded in a backplane substrate, integrated into a backplane substrate, formed on a backplane substrate, deposited on a backplane substrate, and coupled to a backplane substrate; and at least one circuit system that performs at least one of the following: embedded in a PCB, integrated into a PCB, formed on a PCB, deposited on a PCB, and coupled to a PCB.

[0066] In some embodiments, the pixel logic circuit system performs at least one of the following: disposed on a first strip region of a backplane substrate, embedded in a first strip region of a backplane substrate, integrated into a first strip region of a backplane substrate, formed on a first strip region of a backplane substrate, deposited on a first strip region of a backplane substrate, or coupled to a first strip region of a backplane substrate. In some embodiments, the input / output logic circuit system performs at least one of the following: disposed on a second strip region of a backplane, embedded in a second strip region of a backplane, integrated into a second strip region of a backplane, formed on a second strip region of a backplane, deposited on a second strip region of a backplane, or coupled to a second strip region of a backplane.

[0067] In some embodiments, the display system includes a tile controller that controls the operation of each tile in a tile array or a plurality of tiles and is included or integrated into the operating die of each of the tiles, and wherein each of the plurality of tiles has a tile address. A master controller is coupled to at least one tile in the plurality of tiles or a tile array, wherein the master controller sends data to the tile to which the master controller is coupled, and wherein the tile controller identifies tile data in the data received from the master controller, and wherein the tile data is a subset of the data sent from the master controller, and wherein the tile controller associated with the tile address stores the tile data in a memory unit in the tile or in a memory unit associated with the tile.

[0068] In some implementations, the data sent from the master controller includes the tile address in the header of the data sent from the master controller. In some implementations, the master controller receives data in a first format from the first device, and the master controller converts the data into a suitable second format or a second format that can be read or processed by the tile or a tile controller associated with the tile.

[0069] In some embodiments, the first device is a device for generating and / or outputting images or image data. In some embodiments, tiles in a plurality of tiles or an array of tiles are electrically connected in series. In some embodiments, image or video data is sent to the tiles while image or video data of the current frame is displayed on tiles for display in the next frame. In some embodiments, each tile includes an illumination element, and each illumination element is coupled to a first storage device and a second storage device.

[0070] In some embodiments, the display system further includes a logic function circuitry system electrically coupled to a latch, wherein the logic function circuitry system performs calculations or Boolean logic functions such as equivalent or comparison functions and generates an output received by the latch to which the logic function circuitry system is coupled, and wherein the latch stores the output of the logic function circuitry system, and wherein the latch is also electrically coupled to a current driver circuitry or component, and wherein the current driver circuitry or component is electrically coupled to an illumination element, and wherein the current driver circuitry or component supplies a modulation current to the illumination element, and wherein the current driver circuitry or component can supply a modulation current to the illumination element according to the output generated by the logic function circuitry system.

[0071] In some embodiments, the display system includes a pixel array of pixel elements, wherein each illumination element of a pixel in the pixel array or each illumination element of a main pixel is electrically coupled to a pixel circuit system, the pixel circuit system including: a first storage device or receiving pixel memory device; a second storage device or active pixel memory device electrically coupled to the receiving pixel memory device; a logic function circuit system coupled to the active pixel memory device; a latch coupled to the logic function circuit system; and a current driving device coupled to the latch, wherein the current driving device drives the operation of each pixel or main pixel in the pixel array. A tile controller includes a deserializer that receives incoming data from the receiving storage device. A decoder is electrically coupled to the deserializer, and the deserializer extracts image or video data from the data stream received at the deserializer of the tile controller based on or when the address of the tile is in the data stream, wherein the deserializer controls the writing of the extracted data to the first storage device or the receiving pixel memory device.

[0072] In some embodiments, the decoder decodes the extracted data after extracting data from the data stream, and wherein the tile controller instructs a control logic block to write the extracted and subsequently placed decoded data to a data bus corresponding to or associated with a column that includes or contains lighting elements, pixels, main pixels, LEDs, or sets of LEDs, which has been identified as the destination for writing the extracted and subsequently decoded data. In some embodiments, the tile controller outputs a ROW / WRITE output or signal to the row of lighting elements, pixels, main pixels, LEDs, or sets of LEDs that has been identified as receiving the extracted and subsequently decoded data.

[0073] In some embodiments, the display system further includes a control logic circuitry system for a tile controller that outputs a LOAD output voltage or signal to initiate the transfer of data from a receiving storage device to a second storage device or an active storage device. In some embodiments, the display system also includes a TVV (Time-Variable Value) generator, wherein a display cycle begins after data has been transferred to the second storage device or active storage device, wherein during the display cycle, the TVV generator provides a changing value or voltage on a time-varying value (TVV) bus, wherein pixel logic circuitry or pixel logic devices combine the changing value or voltage with a value or voltage in the second storage device or active storage device to generate a time-varying voltage for modulating a current driver circuitry or device electrically coupled to a main pixel or main illumination element.

[0074] In some implementations, at each change of the TVV bus caused by the TVV generator, a COMPUTE signal or output generated by a counter in the TVV generator of the tile controller reaches the logic function circuitry and / or latch of the pixel array, wherein the logic function circuitry calculates or performs Boolean logic functions and generates a single-bit output or signal and outputs it to the latch, wherein the output of the latch directly controls the on / off state of the current source, and thereby controls the on / off state of the pixel, main pixel, LED, or LED array.

[0075] The embodiments described above are merely illustrative examples of implementation methods proposed for a clear understanding of the principles. Variations, modifications, and combinations of the embodiments described above may be made without departing from the scope of the claims. All such variations, modifications, and combinations are included herein within the scope of this disclosure and the appended claims.

Claims

1. A display device, comprising: Multiple tiles, including: An illumination die, wherein the illumination die includes at least one illumination element and an illumination element substrate; and A backplane assembly coupled to the illumination die, wherein the backplane assembly includes a backplane substrate and a pixel circuit system, and wherein the pixel circuit system includes: Pixel logic circuit system, the pixel logic circuit system being located within the first strip area of ​​the backplane substrate; and Input / output logic circuit systems; and PCB, wherein the plurality of blocks are electrically coupled via: The circuit system of the backplane substrate; and The circuit system of the PCB.

2. The display device according to claim 1, wherein, The input / output logic circuit system is located in the second strip area of ​​the backplane substrate.

3. The display device according to claim 1, wherein, The at least one lighting element includes three lighting elements.

4. The display device according to claim 3, wherein, The three lighting elements form the first main pixel.

5. The display device according to claim 1, wherein, The at least one lighting element is at least one LED.

6. The display device according to claim 5, wherein, The at least one LED is at least one microLED.

7. A display system, comprising: A tile controller, wherein the tile controller controls the operation of each tile in a tile array or a plurality of tiles, and is included in the operation die of each of the tiles, and wherein each of the plurality of tiles has a tile address; and A master controller, coupled to at least one of the blocks in the plurality of blocks or block arrays, wherein the master controller sends data to the block to which it is coupled, the data having a header including a block address, and wherein the block controller identifies block data in the data received from the master controller, and wherein the block data is a subset of the data sent from the master controller, and wherein the block controller associated with the block address stores the block data in a memory component of the block or in a memory component associated with the block.

8. The display system according to claim 7, wherein, The main controller receives data in a first format from the first device, and wherein the main controller converts the data into a second format that can be read or processed by the tile or the tile controller associated with the tile.

9. The display system according to claim 8, wherein, The first device is an apparatus for generating and / or outputting images or image data.

10. The display system according to claim 7, wherein, The blocks in the plurality of blocks or block arrays are connected in series electrically.

11. The display system according to claim 10, wherein, When image or video data of the current frame is displayed on a tile for display in the next frame, the image or video data is sent to the tile.

12. The display system according to claim 7, wherein, Each tile includes a lighting element, and each lighting element is coupled to a first storage device and a second storage device.

13. A display system, comprising: A pixel array of pixels, wherein each illumination element of a pixel in the pixel array is electrically coupled to a pixel circuit system, the pixel circuit system comprising: Receive pixel memory device; An active pixel memory device electrically coupled to the receiving pixel memory device; The logic function circuit system coupled to the active pixel memory device; The latches coupled to the logic function circuit system; and A current driving device coupled to the latch, wherein the current driving device drives the operation of each pixel of the pixel array; and A tile controller, the tile controller comprising: A deserializer that receives the data stream; and The decoder is electrically coupled to the deserializer. Wherein, the deserializer: In response to the address of the tile being in the data stream, image or video data is extracted from the data stream, and Controlling the writing of the image or video data to the receiving pixel memory device The decoder extracts image or video data from the data stream and then decodes the image or video data. The tile controller instructs a control logic block to write the extracted and subsequently decoded image or video data to a data bus, the data bus corresponding to or associated with a column of a pixel array that has been identified as the destination for writing the extracted and subsequently decoded image or video data.

14. The display system according to claim 13, wherein, The tile controller outputs the ROW / WRITE output signal to the row of the pixel array that has been identified as receiving the extracted and subsequently decoded data.

15. The display system according to claim 14, further comprising: The control logic circuit system of the tile controller outputs a LOAD output signal, which initiates the transmission of data from the receiving pixel memory device to the active pixel memory device.

16. The display system according to claim 15, further comprising: A time-varying value generator, wherein a display cycle begins after the data has been transmitted to the active pixel memory device, wherein during the display cycle, the time-varying value generator provides a signal on a time-varying value bus, and pixel logic circuitry combines the signal with the value in the active pixel memory device to generate a time-varying voltage for modulating a current driver circuit electrically coupled to a main pixel or main illumination element.

17. The display system according to claim 16, wherein, Each time the time-varying value bus is changed due to the time-varying value generator, a COMPUTE output signal generated by the counter in the time-varying value generator of the tile controller reaches the logic function circuit system and / or latch of the pixel array, wherein the logic function circuit system calculates or executes Boolean logic functions and generates a single-bit output signal, and outputs the single-bit output signal to the latch, wherein the output of the latch directly controls the on / off state of the current source, and thereby controls the on / off state of the main pixel.

18. The display system according to claim 13, wherein, Each pixel or main pixel in the pixel array includes three illumination elements.

19. The display system according to claim 13, wherein, The lighting element is an LED.

20. The display system according to claim 19, wherein, The LED mentioned is a micro LED.

Images