Interleaved differential signaling loop system and method

Abstract

The application discloses an interlaced differential signal loop system and a method thereof. The TX+ pin and the RX+ pin and the TX- pin and the RX- pin in the first differential signal interface of the line conversion card are electrically connected to each other to form a loop. The line conversion card does not need to perform additional detection, and can provide a differential signal loop detection of a differential signal generated by a central processing unit of a to-be-tested circuit board. The TX+ pin and the RX+ pin and the TX- pin and the RX- pin are electrically connected to each other to avoid the situation that a signal short circuit cannot be detected. Therefore, the technical effect that the differential signal loop detection is realized by the line conversion card to improve the differential signal detection efficiency can be achieved.

Description

Technical Field

[0001] This invention relates to a loop system and method thereof, and more particularly to an interleaved differential signal loop system and method thereof, in which the TX+ pin and RX+ pin and the TX- pin and RX- pin are electrically connected to each other in an interleaved differential signal interface. Background Technology

[0002] The current differential signal detection method generally follows this approach: the differential signal interface of the circuit board under test is connected to the connection interface of the test card, the test card receives differential signal generation instructions from an external detection device to generate a differential signal, and the differential signal is used to detect the differential signal interface of the circuit board under test.

[0003] Existing differential signal detection methods require the additional design and manufacture of test cards to achieve differential signal detection of differential signal interfaces. In addition to the increased testing costs, the test cards also need to be tested. Otherwise, it will be impossible to correctly detect whether the problem lies with the differential signal interface of the circuit board under test or with the connection interface of the test card.

[0004] In summary, it is evident that existing technologies have long suffered from the problems of increased cost and the need for additional testing of the test card for differential signal detection. Therefore, it is necessary to propose improved technical methods to address this issue. Summary of the Invention

[0005] In view of the problems of increased cost and the need for additional testing of the test card in existing technologies for differential signal detection, the present invention discloses an interleaved differential signal loop system and method, wherein:

[0006] The present invention discloses an interleaved differential signal loop system according to a first embodiment, which includes: a line conversion card and a circuit board to be tested.

[0007] The line conversion card has a first differential signal interface, which has a first positive transmit (TX+) pin, a first negative transmit (TX-) pin, a first positive receive (RX+) pin, a first negative receive (RX-) pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, and multiple ground pins. The first TX+ pin and the second RX+ pin are electrically connected, the first TX- pin and the second RX- pin are electrically connected, the first RX+ pin and the second TX+ pin are electrically connected, and the first RX- pin and the second TX- pin are electrically connected.

[0008] The circuit board under test has a second differential signal interface and a central processing unit. The second differential signal interface is electrically connected to the central processing unit. The second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, a fifth RX- pin, a fifth RX- pin, and multiple ground pins.

[0009] When the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the fourth TX+ pin, the first TX+ pin, the second RX+ pin, and the fifth RX+ pin form a first positive differential signal line, and the fourth TX- pin, the first TX- pin, the second RX- pin, and the fifth RX- pin form a first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal. When the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the fourth RX+ pin, the first RX+ pin, the second TX+ pin, and the fifth TX+ pin form a second positive differential signal line, and the fourth RX- pin, the first RX- pin, the second TX- pin, and the fifth TX- pin form a second negative differential signal line. The second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal.

[0010] The interleaved differential signal loop system of the second embodiment disclosed in this invention includes: a line conversion card and a circuit board to be tested.

[0011] The line conversion card has a first differential signal interface, which has a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, a third TX+ pin, a third TX- pin, a third RX+ pin, a third RX- pin, and a third RX- pin, as well as multiple ground pins. The first TX+ pin and the third RX+ pin are electrically connected, the first TX- pin and the third RX- pin are electrically connected, the first RX+ pin and the second TX+ pin are electrically connected, the first RX- pin and the second TX- pin are electrically connected, the third TX+ pin and the second RX+ pin are electrically connected, and the third TX- pin and the second RX- pin are electrically connected.

[0012] The circuit board under test has a second differential signal interface and a central processing unit. The second differential signal interface is electrically connected to the central processing unit. The second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, a fifth RX- pin, a sixth TX+ pin, a sixth TX- pin, a sixth RX+ pin, a sixth RX- pin, a sixth RX- pin, and a sixth RX- pin, as well as multiple ground pins.

[0013] When the first differential signal interface and the second differential signal interface are electrically connected by mutual insertion, the fourth TX+ pin, the first TX+ pin, the third RX+ pin, and the sixth RX+ pin form the first positive differential signal line, and the fourth TX- pin, the first TX- pin, the third RX- pin, and the sixth RX- pin form the first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal. When the first differential signal interface and the second differential signal interface are electrically connected by mutual insertion, the fifth TX+ pin, the second TX+ pin, the first RX+ pin, and the fourth RX+ pin form the second positive differential signal line. The fifth TX-pin, the second TX-pin, the first RX-pin, and the fourth RX-pin form a second negative differential signal line, and the second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal; and when the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the sixth RX+ pin, the third RX+ pin, the second TX+ pin, and the fifth TX+ pin form a third positive differential signal line, and the sixth RX-pin, the third RX-pin, the second TX-pin, and the fifth TX-pin form a third negative differential signal line, and the third positive differential signal line and the third negative differential signal line provide the transmission of the third differential signal.

[0014] The interleaved differential signal loop method of the first embodiment disclosed in this invention includes the following steps:

[0015] First, the line conversion card has a first differential signal interface, which includes a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, and a second RX- pin, as well as multiple ground pins. Next, the first TX+ pin is electrically connected to the second RX+ pin, the first TX- pin is electrically connected to the second RX- pin, the first RX+ pin is electrically connected to the second TX+ pin, and the first RX- pin is electrically connected to the second TX- pin. Next, the circuit board under test has a second differential signal interface and a central processing unit (CPU), with the second differential signal interface electrically connected to the CPU. Finally, the second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, and a fifth RX- pin. The system consists of four differential signal interfaces: a first differential signal interface and a second differential signal interface; a second differential signal interface and a third differential signal interface; a third differential signal interface and a fourth differential signal interface; a fourth differential signal interface and a fifth differential signal interface; a fourth differential signal interface and a fifth differential signal interface; a fifth differential signal interface; a sixth differential signal interface and a fifth differential signal interface; a seventh differential signal interface and a fifth differential signal interface; a seventh differential signal interface and a fifth differential signal interface; a TX+ pin and a TX- pin; a TX+ pin and a TX+ pin; a TX+ pin and a TX+ pin; a TX- pin and a TX- ...

[0016] The interleaved differential signal loop method of the second embodiment disclosed in this invention includes the following steps:

[0017] First, the line conversion card has a first differential signal interface, which includes a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, a third TX+ pin, a third TX- pin, a third RX+ pin, a third RX- pin, and a third RX- pin, as well as multiple ground pins. Next, the first TX+ pin and the third RX+ pin are electrically connected, the first TX- pin and the third RX- pin are electrically connected, the first RX+ pin and the second TX+ pin are electrically connected, and the first RX- pin and the second TX- pin are electrically connected. Next, the third TX+ pin is electrically connected to the second RX+ pin, and the third TX- pin is electrically connected to the second RX- pin; then, the circuit board under test has a second differential signal interface and a central processing unit, with the second differential signal interface electrically connected to the central processing unit; then, the second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, a fifth RX- pin, a sixth TX+ pin, a sixth TX- pin, a sixth RX+ pin, a sixth RX- pin, a sixth RX- pin, and a plurality of ground pins; then, the first differential signal interface... When the first differential signal interface is electrically connected to the second differential signal interface, the fourth TX+ pin, the first TX+ pin, the third RX+ pin, and the sixth RX+ pin form a first positive differential signal line, and the fourth TX- pin, the first TX- pin, the third RX- pin, and the sixth RX- pin form a first negative differential signal line. The first positive and first negative differential signal lines provide the transmission of the first differential signal. Then, when the first differential signal interface and the second differential signal interface are electrically connected to each other, the fifth TX+ pin, the second TX+ pin, the first RX+ pin, and the fourth RX+ pin form a second positive differential signal line, and the fifth TX-... The first differential signal line, the second TX- pin, the first RX- pin, and the fourth RX- pin form the second negative differential signal line. The second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal. Finally, when the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the sixth RX+ pin, the third RX+ pin, the second TX+ pin, and the fifth TX+ pin form the third positive differential signal line. The sixth RX- pin, the third RX- pin, the second TX- pin, and the fifth TX- pin form the third negative differential signal line. The third positive differential signal line and the third negative differential signal line provide the transmission of the third differential signal.

[0018] The system and method disclosed in this invention are as described above. The difference between them and the prior art lies in the fact that the circuit formed by the interleaved electrical connection of the TX+ pin and RX+ pin and the TX- pin and RX- pin in the first differential signal interface of the line conversion card can provide the detection of the differential signal circuit generated by the central processing unit of the circuit board under test without the need for additional detection. Furthermore, the interleaved electrical connection of the TX+ pin and RX+ pin and the TX- pin and RX- pin avoids the situation where the signal is short-circuited and cannot be detected.

[0019] Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the differential signal detection efficiency by using a line conversion card to realize differential signal loop detection. Attached Figure Description

[0020] Figure 1 A system block diagram of a first embodiment of the interleaved differential signal loop system of the present invention is shown.

[0021] Figure 2 A system block diagram illustrating a second embodiment of the interleaved differential signal loop system of the present invention is shown.

[0022] Figure 3 A flowchart illustrating a first embodiment of the interleaved differential signal loop method of the present invention is shown.

[0023] Figure 4A as well as Figure 4B A flowchart illustrating a second embodiment of the interleaved differential signal loop method of the present invention is shown.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10 Line Converter Card

[0026] 20 Circuit boards to be tested

[0027] 21 Central Processing Units

[0028] 30 First Differential Signal Interface

[0029] 311 First TX+ pin

[0030] 312 First TX pin

[0031] 313 First RX+ pin

[0032] 314 First RX pin

[0033] 321 Second TX+ pin

[0034] 322 Second TX-pin

[0035] 323 Second RX+ pin

[0036] 324 Second RX Pin

[0037] 331 Third TX+ pin

[0038] 332 Third TX-pin

[0039] 333 Third RX+ pin

[0040] 334 Third RX-pin

[0041] 40 Second Differential Signal Interface

[0042] 411 Fourth TX+ pin

[0043] 412 Fourth TX pin

[0044] 413 Fourth RX+ pin

[0045] 414 Fourth RX pin

[0046] 421 Fifth TX+ pin

[0047] 422 Fifth TX pin

[0048] 423 Fifth RX+ pin

[0049] 424 Fifth RX Pin

[0050] 431 Sixth TX+ pin

[0051] 432 Sixth TX Pin

[0052] 433 Sixth RX+ pin

[0053] 434 Sixth RX Pin

[0054] 50 Detection Device

[0055] GND ground pin Detailed Implementation

[0056] The following will describe in detail the implementation of the present invention with reference to the accompanying drawings and embodiments, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0057] The following describes the interleaved differential signal loop system according to the first embodiment of the present invention, and please refer to... Figure 1 As shown, Figure 1 A system block diagram of a first embodiment of the interleaved differential signal loop system of the present invention is shown.

[0058] The present invention discloses an interleaved differential signal loop system according to a first embodiment, which includes: a line conversion card 10 and a circuit board 20 to be tested.

[0059] The line conversion card 10 has a first differential signal interface 30, which has a first positive transmit (TX+) pin 311, a first negative transmit (TX-) pin 312, a first positive receive (RX+) pin 313, a first negative receive (RX-) pin 314, a second TX+ pin 321, a second TX- pin 322, a second TX+ pin 323, a second TX- pin 324, and multiple ground pins GND.

[0060] The first TX+ pin 311 is electrically connected to the second RX+ pin 323, the first TX- pin 312 is electrically connected to the second RX- pin 324, the first RX- pin 313 is electrically connected to the second TX+ pin 321, and the first RX- pin 314 is electrically connected to the second TX- pin 322. Figure 1 In order to illustrate the connection of the pins, the pins are shown with a certain distance between them, but in reality the pins are close to each other.

[0061] The circuit board under test 20 has a second differential signal interface 40 and a central processing unit 21. The second differential signal interface 40 is electrically connected to the central processing unit 21. The second differential signal interface 40 has a fourth TX+ pin 411, a fourth TX- pin 412, a fourth RX+ pin 413, a fourth RX- pin 414, a fifth TX+ pin 421, a fifth TX- pin 422, a fifth RX+ pin 423, a fifth RX- pin 424 and multiple ground pins GND.

[0062] When the first differential signal interface 30 and the second differential signal interface 40 are plugged into each other to form an electrical connection, the fourth TX+ pin 411, the first TX+ pin 311, the second TX+ pin 323 and the fifth RX+ pin 423 form the first positive differential signal line, and the fourth TX- pin 412, the first TX- pin 312, the second TX- pin 324 and the fifth RX- pin 424 form the first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal.

[0063] When the first differential signal interface 30 and the second differential signal interface 40 are plugged into each other to form an electrical connection, the fourth RX+ pin 413, the first TX- pin 313, the second TX+ pin 321 and the fifth TX+ pin 421 form a second positive differential signal line, and the fourth RX- pin 414, the first RX- pin 314, the second TX- pin 322 and the fifth TX- pin 422 form a second negative differential signal line. The second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal.

[0064] The detection device 50 is electrically connected to the line conversion card 10. The detection device 50 provides differential signal generation instructions to the central processing unit 21 through the line conversion card 10. The central processing unit 21 generates a first differential signal and / or a second differential signal according to the differential signal generation instructions, so as to detect the differential signal through the first positive differential signal line and the first negative differential signal line and / or the second positive differential signal line and the second negative differential signal line.

[0065] The following describes the interleaved differential signal loop system according to the second embodiment of the present invention, and please refer to [reference needed]. Figure 2 As shown, Figure 2 A system block diagram of a second embodiment of the interleaved differential signal loop system of the present invention is shown.

[0066] The present invention discloses a second embodiment of an interleaved differential signal loop system, which includes: a line conversion card 10 and a circuit board 20 to be tested.

[0067] The line conversion card 10 has a first differential signal interface 30, which has a first TX+ pin 311, a first TX- pin 312, a first TX- pin 313, a first RX- pin 314, a second TX+ pin 321, a second TX- pin 322, a second TX+ pin 323, a second TX- pin 324, a third TX+ pin 331, a third TX- pin 332, a third RX+ pin 333, a third RX- pin 334, and multiple ground pins GND.

[0068] The first TX+ pin 311 is electrically connected to the third RX+ pin 333; the first TX- pin 312 is electrically connected to the third RX- pin 334; the first RX+ pin 313 is electrically connected to the second TX+ pin 321; the first RX- pin 314 is electrically connected to the second TX- pin 322; the third TX+ pin 331 is electrically connected to the second RX+ pin 323; and the third TX- pin 332 is electrically connected to the second RX- pin 324. Figure 2 In order to illustrate the connection of the pins, the pins are shown with a certain distance between them, but in reality the pins are close to each other.

[0069] The circuit board 20 under test has a second differential signal interface 40 and a central processing unit 21. The second differential signal interface 40 is electrically connected to the central processing unit 21. The second differential signal interface 40 has a fourth TX+ pin 411, a fourth TX- pin 412, a fourth RX+ pin 413, a fourth RX- pin 414, a fifth TX+ pin 421, a fifth TX- pin 422, a fifth RX+ pin 423, a fifth RX- pin 424, a sixth TX+ pin 431, a sixth TX- pin 432, a sixth RX+ pin 433, a sixth RX- pin 434 and multiple ground pins GND.

[0070] When the first differential signal interface 30 and the second differential signal interface 40 are plugged into each other to form an electrical connection, the fourth TX+ pin 411, the first TX+ pin 311, the third RX+ pin 333 and the sixth RX+ pin 433 form the first positive differential signal line, and the fourth TX- pin 412, the first TX- pin 312, the third RX- pin 334 and the sixth RX- pin 434 form the first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal.

[0071] When the first differential signal interface 30 and the second differential signal interface 40 are plugged into each other to form an electrical connection, the fifth TX+ pin 421, the second TX+ pin 321, the first TX- pin 313 and the fourth RX+ pin 413 form a second positive differential signal line, and the fifth TX- pin 422, the second TX- pin 322, the first RX- pin 314 and the fourth RX- pin 414 form a second negative differential signal line. The second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal.

[0072] When the first differential signal interface 30 and the second differential signal interface 40 are plugged into each other to form an electrical connection, the sixth RX+ pin 433, the third RX+ pin 333, the second TX+ pin 321 and the fifth TX+ pin 421 form the third positive differential signal line, and the sixth RX- pin 434, the third RX- pin 334, the second TX- pin 322 and the fifth TX- pin 422 form the third negative differential signal line. The third positive differential signal line and the third negative differential signal line provide the transmission of the third differential signal.

[0073] The detection device 50 is electrically connected to the line conversion card 10. The detection device 50 provides differential signal generation instructions to the central processing unit 21 through the line conversion card 10. The central processing unit 21 generates a first differential signal, a second differential signal, and / or a third differential signal according to the differential signal generation instructions, so as to detect the differential signal through the first positive differential signal line and the first negative differential signal line, the second positive differential signal line and the second negative differential signal line, and / or the third positive differential signal line and the third negative differential signal line.

[0074] Next, the operation method of the first embodiment of the present invention will be described below, and please refer to the following: Figure 3 As shown, Figure 3 A flowchart illustrating a first embodiment of the interleaved differential signal loop method of the present invention is shown.

[0075] The interleaved differential signal loop method of the first embodiment disclosed in this invention includes the following steps:

[0076] First, the line conversion card has a first differential signal interface, which includes a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, and a plurality of ground pins (step 601). Next, the first TX+ pin and the second RX+ pin are electrically connected, the first TX- pin and the second RX- pin are electrically connected, the first RX+ pin and the second TX+ pin are electrically connected, and the first RX- pin and the second TX- pin are electrically connected (step 602). Next, the circuit board under test has a second differential signal interface and a central processing unit (CPU), with the second differential signal interface electrically connected to the CPU (step 603). Next, the second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, and a fifth RX- pin. The first differential signal interface and the second differential signal interface are connected to form an electrical connection. The fourth TX+ pin, the first TX+ pin, the second RX+ pin, and the fifth RX+ pin form a first positive differential signal line, and the fourth TX- pin, the first TX- pin, the second RX- pin, and the fifth RX- pin form a first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal (step 605). Finally, when the first differential signal interface and the second differential signal interface are connected to form an electrical connection, the fourth RX+ pin, the first RX+ pin, the second TX+ pin, and the fifth TX+ pin form a second positive differential signal line, and the fourth RX- pin, the first RX- pin, the second TX- pin, and the fifth TX- pin form a second negative differential signal line. The second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal (step 606).

[0077] Next, the operation method of the second embodiment of the present invention will be described below, and please refer to the following: Figure 4A as well as Figure 4B As shown, Figure 4A as well as Figure 4B A flowchart illustrating a second embodiment of the interleaved differential signal loop method of the present invention is shown.

[0078] The interleaved differential signal loop method of the second embodiment disclosed in this invention includes the following steps:

[0079] First, the line conversion card has a first differential signal interface, which has a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, a third TX+ pin, a third TX- pin, a third RX+ pin, a third RX- pin, a third RX- pin, and a plurality of ground pins (step 701); then, the first TX+ pin and the third RX+ pin are electrically connected, the first TX- pin and the third RX- pin are electrically connected, the first RX+ pin and the second TX+ pin are electrically connected, the first RX- pin and the second TX- pin are electrically connected, and the third TX+ pin and the third RX- pin are electrically connected. The X+ pin is electrically connected to the second RX+ pin, and the third TX- pin is electrically connected to the second RX- pin (step 702); next, the circuit board under test has a second differential signal interface and a central processing unit, and the second differential signal interface is electrically connected to the central processing unit (step 703); next, the second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, a fifth RX- pin, a sixth TX+ pin, a sixth TX- pin, a sixth RX+ pin, a sixth RX- pin, and a plurality of ground pins (step 704); next, the first differential signal... When the first differential signal interface and the second differential signal interface are electrically connected, the fourth TX+ pin, the first TX+ pin, the third RX+ pin, and the sixth RX+ pin form a first positive differential signal line, and the fourth TX- pin, the first TX- pin, the third RX- pin, and the sixth RX- pin form a first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal (step 705). Next, when the first differential signal interface and the second differential signal interface are electrically connected, the fifth TX+ pin, the second TX+ pin, the first RX+ pin, and the fourth RX+ pin form a second positive differential signal line, and the fifth TX- pin... The second TX- pin, the first RX- pin, and the fourth RX- pin form a second negative differential signal line, and the second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal (step 706); finally, when the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the sixth RX+ pin, the third RX+ pin, the second TX+ pin, and the fifth TX+ pin form a third positive differential signal line, and the sixth RX- pin, the third RX- pin, the second TX- pin, and the fifth TX- pin form a third negative differential signal line, and the third positive differential signal line and the third negative differential signal line provide the transmission of the third differential signal (step 707).

[0080] In summary, the difference between this invention and the prior art lies in the fact that the circuit formed by the interleaved electrical connection of the TX+ pin and RX+ pin and the TX- pin and RX- pin in the first differential signal interface of the line conversion card allows the line conversion card to provide self-generated differential signal circuit detection of the differential signal generated by the central processing unit of the circuit board under test without additional detection. Furthermore, the interleaved electrical connection of the TX+ pin and RX+ pin and the TX- pin and RX- pin avoids the situation where the signal is short-circuited and cannot be detected.

[0081] This technology can solve the problems of increased cost and additional testing required for differential signal detection using test cards in existing technologies, thereby achieving the technical effect of improving differential signal detection efficiency by using a line conversion card to detect differential signal loops.

[0082] While the embodiments disclosed in this invention are as described above, the content is not intended to directly limit the scope of patent protection of this invention. Any person skilled in the art may make some modifications in form and detail without departing from the spirit and scope of this invention. The scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. An interleaved differential signal loop system, comprising: A line converter card has a first differential signal interface, which includes a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, and a plurality of ground pins. The first TX+ pin is electrically connected to the second RX+ pin, the first TX- pin is electrically connected to the second RX- pin, the first RX+ pin is electrically connected to the second TX+ pin, and the first RX- pin is electrically connected to the second TX- pin. The circuit board under test has a second differential signal interface and a central processing unit. The second differential signal interface is electrically connected to the central processing unit. The second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, a fifth RX- pin, and a plurality of ground pins. in, When the first differential signal interface and the second differential signal interface are electrically connected by mutual plugging, the fourth TX+ pin, the first TX+ pin, the second RX+ pin, and the fifth RX+ pin form a first positive differential signal line, and the fourth TX- pin, the first TX- pin, the second RX- pin, and the fifth RX- pin form a first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal. When the first differential signal interface and the second differential signal interface are electrically connected by mutual plugging, the fourth RX+ pin, the first RX+ pin, the second TX+ pin, and the fifth TX+ pin form a second positive differential signal line, and the fourth RX- pin, the first RX- pin, the second TX- pin, and the fifth TX- pin form a second negative differential signal line. The second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal. The interleaved differential signal loop system further includes a detection device, which is electrically connected to the line conversion card. The detection device provides differential signal generation instructions to the central processing unit through the line conversion card, and the central processing unit generates the first differential signal and / or the second differential signal according to the differential signal generation instructions.

2. An interleaved differential signal loop system, comprising: A line conversion card has a first differential signal interface, which includes a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, a third TX+ pin, a third TX- pin, a third RX+ pin, a third RX- pin, and a third RX- pin, as well as multiple ground pins. The first TX+ pin is electrically connected to the third RX+ pin, the first TX- pin is electrically connected to the third RX- pin, the first RX+ pin is electrically connected to the second TX+ pin, the first RX- pin is electrically connected to the second TX- pin, the third TX+ pin is electrically connected to the second RX+ pin, and the third TX- pin is electrically connected to the second RX- pin. The circuit board under test has a second differential signal interface and a central processing unit. The second differential signal interface is electrically connected to the central processing unit. The second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, a fifth RX- pin, a sixth TX+ pin, a sixth TX- pin, a sixth RX+ pin, a sixth RX- pin, and a sixth RX- pin, as well as multiple ground pins. in, When the first differential signal interface and the second differential signal interface are electrically connected by mutual insertion, the fourth TX+ pin, the first TX+ pin, the third RX+ pin, and the sixth RX+ pin form a first positive differential signal line, and the fourth TX- pin, the first TX- pin, the third RX- pin, and the sixth RX- pin form a first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal. When the first differential signal interface and the second differential signal interface are electrically connected by mutual insertion, the fifth TX+ pin, the second TX+ pin, the first RX+ pin, and the fourth RX+ pin form a second positive differential signal line. The fifth TX-pin, the second TX-pin, the first RX-pin, and the fourth RX-pin form a second negative differential signal line, and the second positive differential signal line and the second negative differential signal line provide the transmission of a second differential signal; and when the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the sixth RX+ pin, the third RX+ pin, the second TX+ pin, and the fifth TX+ pin form a third positive differential signal line, and the sixth RX-pin, the third RX-pin, the second TX-pin, and the fifth TX-pin form a third negative differential signal line, and the third positive differential signal line and the third negative differential signal line provide the transmission of a third differential signal; The interleaved differential signal loop system further includes a detection device, which is electrically connected to the line conversion card. The detection device provides differential signal generation instructions to the central processing unit through the line conversion card. The central processing unit generates the first differential signal, the second differential signal, and / or the third differential signal according to the differential signal generation instructions.

3. A method for interleaved differential signal loops, comprising the following steps: The line conversion card has a first differential signal interface, which has a first TX+ pin, a first TX- pin, a first RX+ pin, a first RX- pin, a second TX+ pin, a second TX- pin, a second RX+ pin, a second RX- pin, and multiple ground pins; The first TX+ pin is electrically connected to the second RX+ pin, the first TX- pin is electrically connected to the second RX- pin, the first RX+ pin is electrically connected to the second TX+ pin, and the first RX- pin is electrically connected to the second TX- pin. The circuit board under test has a second differential signal interface and a central processing unit, and the second differential signal interface is electrically connected to the central processing unit; The second differential signal interface has a fourth TX+ pin, a fourth TX- pin, a fourth RX+ pin, a fourth RX- pin, a fifth TX+ pin, a fifth TX- pin, a fifth RX+ pin, a fifth RX- pin, and a plurality of ground pins; When the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the fourth TX+ pin, the first TX+ pin, the second RX+ pin, and the fifth RX+ pin form a first positive differential signal line, and the fourth TX- pin, the first TX- pin, the second RX- pin, and the fifth RX- pin form a first negative differential signal line. The first positive differential signal line and the first negative differential signal line provide the transmission of the first differential signal; and When the first differential signal interface and the second differential signal interface are plugged into each other to form an electrical connection, the fourth RX+ pin, the first RX+ pin, the second TX+ pin, and the fifth TX+ pin form a second positive differential signal line, and the fourth RX- pin, the first RX- pin, the second TX- pin, and the fifth TX- pin form a second negative differential signal line. The second positive differential signal line and the second negative differential signal line provide the transmission of the second differential signal. in, The interleaved differential signal loop method further includes the steps of forming an electrical connection between a detection device and the line conversion card, the detection device providing differential signal generation instructions to the central processing unit through the line conversion card, and the central processing unit generating the first differential signal and / or the second differential signal according to the differential signal generation instructions.

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