Scan driving circuit and display panel

Abstract

This application discloses a scan driving circuit and a display panel, including n scan driving units for sequentially outputting corresponding scan signals. Each scan driving unit includes a pull-up module, an output control module, an auxiliary pull-down module, a pull-down module, a first node, and a second node. The pull-up module is connected to the first node to pull the first node up to a second potential. The output control module is connected to the first node; when the first node is at the second potential, the output control module controls the scan signal output terminal to output a scan signal. The auxiliary pull-down module is connected to the clock signal terminal and the second node, and controls the second node to be at either the first or second potential according to the clock signal. The pull-down module is connected to the second node, and when the second node is at the second potential, the pull-down module pulls the potential of the scan signal output terminal down to the first potential within a preset time. By setting the auxiliary pull-down module, the fall time of multiple scan signals is kept within a preset range.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to scanning drive circuits and display panels. Background Technology

[0002] Gate Driver Less (GDL) technology utilizes the existing array fabrication process of the display panel to fabricate the driving circuitry for the horizontal scan lines on the substrate surrounding the display area. This allows it to replace external integrated circuit (IC) boards to drive the horizontal scan lines. GDL technology reduces the soldering steps for external ICs, making the display panel more suitable for manufacturing narrow-bezel or bezel-less display products.

[0003] Currently, display panels need to recognize touch actions and execute touch commands while displaying images. When a user touches the display panel, the clock signal usually pauses output. At this time, the scan drive unit in the scan drive circuit needs to maintain the current potential to ensure that image display continues after the touch action ends. Because leakage often occurs when the scan drive unit maintains the current potential, the fall time of the output scan signal increases after the touch action ends. This causes inconsistencies in brightness between the row of pixels controlled by the scan signal and adjacent rows, resulting in horizontal lines on the display panel. Therefore, reducing the fall time of the scan signal to ensure consistency between adjacent scan signals is a pressing issue that needs to be addressed. Summary of the Invention

[0004] In view of the shortcomings of the prior art, this application provides a scanning drive circuit and a display panel that can effectively adjust the fall time of the scanning signal.

[0005] This application provides a scan driving circuit, including n scan driving units arranged sequentially, where n is an integer greater than 1. The n scan driving units sequentially output corresponding scan signals, which control pixel units to receive data signals for image display. Each scan driving unit includes a pull-up module, an output control module, an auxiliary pull-down module, a pull-down module, a first node, and a second node. The pull-up module is connected to the first node to pull it up from a first potential to a second potential. The output control module is connected to the first node, the scan signal output terminal, and the clock signal terminal. When the first node is at the second potential, the output control module receives a clock signal from the clock signal terminal and controls the scan signal output terminal to output a scan signal. The auxiliary pull-down module is connected to the clock signal terminal and the second node, controlling the second node to be at either the first or second potential according to the clock signal. The pull-down module is connected to the second node and the scan signal output terminal, pulling the potential of the scan signal output terminal down to the first potential within a preset time when the auxiliary pull-down module controls the second node to be at the second potential.

[0006] Optionally, the pull-up module includes a first switching transistor, and the output control module includes a second switching transistor. The gate of the first switching transistor is connected to the pull-up control terminal, the first end of the first switching transistor is connected to the first power supply terminal, and the second end of the first switching transistor is connected to the first node. It is used to conduct under the control of the pull-up control terminal to control the first power supply terminal to charge the first node, pulling the first node from a first potential to a second potential. The gate of the second switching transistor is connected to the first node, the first end of the second switching transistor is connected to the clock signal terminal, and the second end of the second switching transistor is connected to the scan signal output terminal. The second switching transistor is used to conduct when the first node is at the second potential, to receive the clock signal and output it as a scan signal from the scan signal output terminal.

[0007] Optionally, the auxiliary pull-down module includes a third switch and a fourth switch, and a fifth switch. The gate and first terminal of the third switch are connected to the second power supply terminal, and the second terminal of the third switch is connected to the second node. It is used to turn on according to the driving voltage output from the second power supply terminal and charge the second node, thereby pulling the second node up to the second potential. The gate of the fourth switch is connected to the clock signal terminal, the first terminal of the fourth switch is connected to the second node, and the second terminal of the fourth switch is connected to the first low-voltage terminal. It is used to turn on when the clock signal is output from the clock signal terminal to control the second node to drop to the first potential. The gate of the fifth switch is connected to the second node, the first terminal of the fifth switch is connected to the scan signal output terminal, and the second terminal of the fifth switch is connected to the first low-voltage terminal. When the second node is at the first potential, the fifth switch is off, and the scan signal output terminal outputs a scan signal. When the second node is at the second potential, the fifth switch is on to control the potential of the scan signal output terminal to drop to the first potential within a preset time.

[0008] Optionally, the scan drive circuit further includes a pull-up control module, a pull-down control module, a sustain module, and a third node. The pull-up control module is connected to the third node and is used to pull the third node up from the first potential to the second potential. The pull-down module is connected to the third node and is used to pull the third node down from the second potential to the first potential. The sustain module is connected to the first node and the third node and is used to control the first node to be at the first potential when the third node is at the second potential.

[0009] Optionally, the pull-up control module includes a sixth switch and a seventh switch. The gate and first terminal of the sixth switch are connected to the second power supply terminal, and the second terminal of the sixth switch is connected to the gate of the seventh switch. The first terminal of the seventh switch is connected to the second power supply terminal, and the second terminal of the seventh switch is connected to the third node. The sixth and seventh switches are used to conduct under the control of the second power supply terminal to pull the third node up to the second potential.

[0010] Optionally, the pull-down control module includes an eighth switch and a ninth switch. The gate of the eighth switch is connected to the first node, the first terminal of the eighth switch is connected to the gate of the seventh switch, and the second terminal of the eighth switch is connected to the first low-voltage terminal. This allows the eighth switch to conduct when the first node is at the second potential, thereby controlling the seventh switch to turn off and stopping the second power supply from charging the third node. The gate of the ninth switch is connected to the first node, the first terminal of the ninth switch is connected to the third node, and the second terminal of the ninth switch is connected to the first low-voltage terminal. This allows the ninth switch to conduct when the first node is at the second potential, thereby pulling the third node down to the first potential.

[0011] Optionally, the sustaining module includes a tenth switch, the gate of which is connected to the third node, the first end of which is connected to the first node, and the second end of which is connected to the first low-voltage terminal, for turning on when the third node is at the second potential, so as to pull the first node down to the first potential.

[0012] Optionally, the scan drive circuit further includes a first reset module and a second reset module. The first reset module is connected to the first node and is used to pull down the first node to the first potential after the scan signal output is completed. The second reset module is connected to the scan signal output terminal and is used to pull down the scan signal output terminal to the first potential simultaneously with the auxiliary pull-down module within a preset time after the scan signal output is completed.

[0013] Optionally, the first reset module includes an eleventh switch, and the second reset module includes a twelfth and a thirteenth switch. The gate of the eleventh switch is connected to a first reset terminal, the first terminal of the eleventh switch is connected to a first node, and the second terminal of the eleventh switch is connected to a second low-voltage terminal. It is used to turn on under the control of the first reset terminal after the scan signal is output, so as to pull the first node down to a first potential. The gate of the twelfth switch is connected to a second reset terminal, the first terminal of the twelfth switch is connected to the first node, and the second terminal of the twelfth switch is connected to a first low-voltage terminal. It is used to turn on under the control of the second reset terminal after the scan signal is output, so as to pull the first node down to a first potential. The gate of the thirteenth switch is connected to a third reset terminal, the first terminal of the thirteenth switch is connected to a scan signal output terminal, and the second terminal of the thirteenth switch is connected to a first low-voltage terminal. It is used to pull the scan signal output terminal down to a first potential within a preset time after the scan signal is output.

[0014] This application also provides a display panel, including a plurality of pixel units disposed in a display area and arranged in a matrix, a data driving circuit disposed in a non-display area, and the aforementioned scan driving circuit. The scan driving circuit is used to output a scan signal, and the scan signal is used to control the pixel units to receive the data signal output by the data driving circuit for image display.

[0015] Compared to existing technologies, by setting an auxiliary pull-down module in the scanning driver unit, the scanning signal is pulled down to the first potential within a preset time. This avoids the problem of increased fall time of the scanning signal output by the corresponding scanning driver unit when the display panel is touched. As a result, after the display panel is touched, the difference in fall time of multiple adjacent scanning signals is within a preset range, thereby eliminating the horizontal stripe problem caused by different fall edges of adjacent scanning signals. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a display device provided in the first embodiment of this application;

[0018] Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel;

[0019] Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the central display panel;

[0020] Figure 4 for Figure 3 A schematic diagram of the scanning drive circuit in the image;

[0021] Figure 5 for Figure 4 Equivalent circuit diagram of the scanning drive unit;

[0022] Figure 6 This is a schematic diagram showing the changes in clock signal and output control node voltage in touch mode;

[0023] Figure 7 A schematic diagram of an equivalent circuit of a scanning driving unit provided in the second embodiment of this application;

[0024] Figure 8 for Figure 7 A schematic diagram of the potential changes at the control node.

[0025] Explanation of reference numerals in the attached drawings: Display device-100, Display panel-10, Power supply module-20, Support frame-30, Display area-10a, Non-display area-10b, Timing control circuit-11, Data driving circuit-12, Scan driving circuit-13, Pixel unit-P, Backlight module-17, Array substrate-10c, Display medium layer-10e, Opposing substrate-10d, First direction-F1, Second direction-F2, m data lines-S1~Sm, n scan lines-G1~Gn, Clock signal-CLK, Start signal-STV, Reset signal-R, Scan driving unit-130, Low voltage terminal-VSS, Pull-up module-131, Output control module-132, Auxiliary pull-down module-133, Pull-down module-134, Pull-up control module-135, Pull-down control module-13 6. Maintenance Module - 137, First Reset Module - 138, Second Reset Module - 139, First Node - Q1, Second Node - Q2, Third Node - Q3, Pull-up Control Terminal - Vin, First Switch - T1, Second Switch - T2, Third Switch - T3, Fourth Switch - T4, Fifth Switch - T5, Sixth Switch - T6, Seventh Switch - T7, Eighth Switch - T8, Ninth Switch - T9, Tenth Switch - T10, Eleventh Switch - T11, First Power Supply Terminal - VDD1, Second Power Supply Terminal - VDD2, First Low Voltage Terminal - VSS1, Second Low Voltage Terminal - VSS2, Scan Signal Output Terminal - Gout, Touch Period - tc, First Duration - t1, Second Duration - t2, First Reset Terminal - R1, Second Reset Terminal - R2, Third Reset Terminal - R3. Detailed Implementation

[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0027] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.

[0029] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0031] Please see Figure 1 , Figure 1 This is a schematic diagram of a display device according to the first embodiment of this application. The display device 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is disposed on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images, and the support frame 30 provides fixation and protection for the display panel 10 and the power module 20.

[0032] In other embodiments of this application, the display device 100 may not require the support frame 30, for example, it may be a portable electronic device, such as a mobile phone or tablet computer.

[0033] Please see Figure 2 , Figure 2 for Figure 1 A schematic diagram of the side structure of the central display panel.

[0034] The display panel 10 includes an array substrate 10c and a counter substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the counter substrate 10d. Driving elements are disposed on the array substrate 10c and the counter substrate 10d to generate corresponding electric fields according to data signals, thereby driving the display medium layer 10e to emit light of corresponding brightness to perform image display. The display medium can be liquid crystal molecules, miniLED, Micro-LED, OLED, etc., and this application does not limit its use.

[0035] Taking a liquid crystal display panel as an example, the display medium in the display medium layer 10e is liquid crystal molecules. The display panel 10 also includes a back light module 17 (BM), wherein the back light module 17 is used to provide light for display to the display medium layer 10e. The liquid crystal molecules deflect relative angles according to the data signal so as to emit the light transmitted by the back light module 17 to the opposing substrate to perform image display.

[0036] Please refer to the following: Figure 3 , Figure 3 for Figure 2 A schematic diagram of the planar layout structure of the central display panel.

[0037] like Figure 3As shown, the display panel 10 also includes a timing control circuit 11, a data driving circuit 12, and a scan driving circuit 13. The timing control circuit 11, the data driving circuit 12, and the scan driving circuit 13 are disposed in the non-display area 10b of the display panel 10.

[0038] The display area 10a of the display panel 10 has m data lines (Source lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn arranged in a grid pattern. The m data lines S1 to Sm extend along a first direction F1, and the n scan lines G1 to Gn extend along a second direction F2. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units P are disposed at the intersections of the n scan lines G1 to Gn and the data lines S1 to Sm.

[0039] The timing control circuit 11 receives an image signal representing image information from an external signal source, obtains a clock signal CLK, a horizontal synchronization signal Hsyn, and a vertical synchronization signal Vsyn for synchronization, and outputs a gate output control signal Cg for controlling the scan drive circuit 13, a source output control signal Cs for controlling the data drive circuit 12, and a data signal representing image information. In this embodiment, the timing control circuit 11 performs data adjustment processing on the original data signal to obtain a data signal, and then transmits the data signal to the data drive circuit 12.

[0040] m data lines S1 to Sm are connected to the data driving circuit 12 and are used to receive data signals provided by the data driving circuit 12, which are stored and transmitted in the form of grayscale values. n scan lines G1 to Gn are connected to the scan driving circuit 13 and are used by the self-scanning driving circuit 13 to receive scan signals.

[0041] Under the control of n scan lines G1 to Gn, the pixel unit P receives the grayscale data voltage of the corresponding data signal provided by the data lines S1 to Sm within a predetermined time period, and drives the display medium layer 10e to deflect by a corresponding angle, thereby emitting light of corresponding brightness according to the corresponding deflection angle, so as to achieve image display by emitting light of corresponding brightness according to the image signal.

[0042] The scan drive circuit 13 receives the gate output control signal Cg from the timing control circuit 11 and outputs scan signals to each scan line G1 to Gn. The data drive circuit 12 receives the source output control signal Cs from the timing control circuit 11 and outputs data signals to each data line S1 to Sm for driving the elements in each pixel unit P in the display area 10a to perform image display. The data signals provided to the display panel 10 are analog grayscale voltages. The scan drive circuit 13 outputs scan signals to control the pixel unit P to receive the data signals output by the data drive circuit 12, thereby controlling the pixel unit P to display the corresponding image.

[0043] Please see Figure 4 , Figure 4 for Figure 3 The circuit structure diagram of the scanning drive circuit is shown in the figure.

[0044] like Figure 4 As shown, the scan drive circuit 13 includes n cascaded scan drive units 130, eight clock signals CLK1-CLK8, a start signal STV, a reset signal R, and a low-voltage terminal Vss, where n is an integer greater than or equal to 1.

[0045] In the exemplary embodiment, the clock signal can also be set to other quantities as needed, and this application does not impose any restrictions.

[0046] In the scanning drive circuit 13, each GDL unit outputs a scanning signal to a scanning line in the display area 10a. During the display of one frame of image, n GDL units output n scanning signals G(1) to G(n) in sequence.

[0047] Eight clock signals CLK1-CLK8 are used to provide scan drive timing for the scan signals output by the GDL unit. The start signal STV is the enable start signal for the first scan drive unit GDL1, and other scan drive units use the cascaded transmission signals output by the cascaded scan units as start signals. The low-voltage terminal VSS is used to provide low voltage to the nodes in the scan drive unit.

[0048] Please see Figure 5 , Figure 5 for Figure 4 A schematic diagram of the equivalent circuit of the scanning drive unit.

[0049] like Figure 5 As shown, the scan drive unit 130 includes a pull-up module 131, an output control module 132, and a first node Q1. The pull-up module 131 is connected to the first node Q1, and the output control module 132 is connected to the first node Q1 and the scan signal output terminal Gout. The pull-up module 131 is used to pull up the first node Q1 to a preset potential. When the first node Q1 is at the preset potential, the output control module 132 controls the scan signal output terminal Gout to output a scan signal.

[0050] The pull-up module 131 includes a first switching transistor T1, and the output control module 132 includes a second switching transistor T2 and a voltage regulator capacitor C. The gate of the first switching transistor T1 is connected to the pull-up control terminal Vin, the first terminal of the first switching transistor T1 is connected to the first power supply terminal, and the second terminal of the first switching transistor T1 is connected to the first node Q1. Under the control of the pull-up control terminal Vin, the first node Q1 is pulled up to a preset potential. The gate of the second switching transistor T2 is connected to the first node Q1, the first terminal of the second switching transistor T2 is connected to the clock signal terminal, and the second terminal of the second switching transistor T2 is connected to the scan signal output terminal Gout. When the first node Q1 is at the preset potential, the second switching transistor T2 is turned on to receive the clock signal from the clock signal terminal and output it as a scan signal from the scan signal output terminal Gout. The voltage regulator capacitor C is connected to the gate and the second terminal of the second switching transistor T2 to maintain the stability of the voltage between the gate and the second terminal of the second switching transistor T2.

[0051] The scan drive unit 130 also includes a pull-up control module 135, a pull-down control module 136, a sustaining module 137, a first reset module 138, a second reset module 139, and a third node Q3. The pull-up control module 135 is connected to the third node Q3 and is used to pull the third node Q3 from a first potential to a second potential. The pull-down control module 136 is connected to the first node Q1 and the third node Q3. When the first node Q1 is at a preset potential, the pull-down control module 136 pulls the third node Q3 from the second potential to the first potential.

[0052] The sustaining module 137 is connected to the first node Q1, the third node Q3 and the scan signal output terminal Gout. When the third node Q3 is at the second potential, the sustaining module 137 pulls down the first node Q1 to the first potential and at the same time pulls down the scan signal output terminal Gout to the first potential, that is, controls the scan signal output terminal Gout to output a low level signal.

[0053] The first reset module 138 is connected to the first node Q1 and is used to pull down the first node Q1 to the first potential. The second reset module 139 is connected to the scan signal output terminal Gout and the first node Q1 and is used to pull down the scan signal output terminal Gout and the first node Q1 to the first potential.

[0054] Before the output control module 132 controls the output of the scan signal, i.e., before the scan drive unit 130 outputs the scan signal, the pull-up control module 135 controls the third node Q3 to be at the second potential, thereby controlling the scan signal output terminal Gout to output a low-level signal through the sustain module 137, and controlling the first node Q1 to be at the first potential, i.e., a low potential, through the sustain module 137. When the pull-up module 131 pulls the first node Q1 up to the preset potential, the pull-down control module 136 pulls the third node Q3 down to the first potential, so that the scan signal output terminal Gout stops outputting a low-level signal through the sustain module 137. At the same time, the output control module 132 receives the clock signal and outputs it as the scan signal from the scan signal output terminal Gout. After the scan signal output is completed, the first reset module 138 and the second reset module 139 pull the first node Q1 and the scan signal output terminal Gout down to the first potential to clear the charge in the circuit.

[0055] Specifically, the pull-up control module 135 includes a third switch T3 and a fourth switch T4. The gate and first terminal of the third switch T3 are connected to the second power supply terminal VDD2. The second terminal of the third switch T3 is connected to the pull-down control module 136. The gate of the fourth switch T4 is connected to the second terminal of the third switch T3. The first terminal of the fourth switch T4 is connected to the second power supply terminal VDD2. The second terminal of the fourth switch T4 is connected to the third node Q3. The third switch T3 and the fourth switch T4 are turned on under the control of the driving voltage output from the second power supply terminal VDD2, and are used to pull up the third node Q3 to the second potential.

[0056] The pull-down control module 136 includes a fifth switch T5 and a sixth switch T6. The gate of the fifth switch T5 is connected to the first node Q1, the first terminal of the fifth switch T5 is connected to the second terminal of the third switch T3, and the second terminal of the fifth switch T5 is connected to the first low-voltage terminal VSS1. When the first node Q1 is at a preset potential, the fifth switch T5 is turned on, connecting the second terminal of the third switch T3 and the gate of the fourth switch T4 to the first low-voltage terminal VSS1, thereby controlling the fourth switch T4 to turn off, thus stopping the pull-up of the potential of the third node Q3, i.e., controlling the third node Q3 to drop to the first potential. The gate of the sixth switch T6 is connected to the first node Q1, the first terminal is connected to the third node Q3, and the second terminal is connected to the first low-voltage terminal VSS1. When the first node Q1 is at a preset potential, the sixth switch T6 is turned on, controlling the third node Q3 to be connected to the first low-voltage terminal VSS1, thereby conducting the charge of the third node Q3 to the first low-voltage terminal VSS1, thus pulling the third node Q3 down to the first potential.

[0057] The sustaining module 137 includes a seventh switch T7 and an eighth switch T8. The gate of the seventh switch T7 is connected to the third node Q3, its first terminal is connected to the first node Q1, and its second terminal is connected to the first low-voltage terminal VSS1. When the third node Q3 is at the second potential, the seventh switch T7 is turned on to control the first node Q1 to be connected to the first low-voltage terminal VSS1, thereby controlling the first node Q1 to be at the first potential. The gate of the eighth switch T8 is connected to the third node Q3, its first terminal is connected to the scan signal output terminal Gout, and its second terminal is connected to the first low-voltage terminal VSS1. When the third node Q3 is at the second potential, the eighth switch T8 is turned on to control the scan signal output terminal Gout to be connected to the first low-voltage terminal VSS1, thereby controlling the scan signal output terminal Gout to output a low-level signal.

[0058] The first reset module 138 includes a ninth switch transistor T9. The gate of the ninth switch transistor T9 is connected to the first reset terminal R1, the first terminal is connected to the first node Q1, and the second terminal is connected to the second low-voltage terminal VSS2. When the scan signal is output, the first reset terminal R1 outputs a reset signal to control the ninth switch transistor T9 to turn on, so as to control the first node Q1 to be connected to the second low-voltage terminal VSS2, which is used to conduct the charge of the first node Q1 to the second low-voltage terminal VSS2 and pull down the first node Q1 to the first potential.

[0059] The second reset module 139 includes a tenth switch transistor T10 and an eleventh switch transistor T11. The gate of the tenth switch transistor T10 is connected to the second reset terminal R2, its first terminal is connected to a voltage regulator capacitor and then to the first node Q1, and its second terminal is connected to the first low-voltage terminal VSS1. It is turned on under the control of the reset signal output from the second reset terminal R2, and is used to conduct the charge in the first node Q1 and the voltage regulator capacitor to the first low-voltage terminal VSS1. The gate of the eleventh switch transistor T11 is connected to the third reset terminal R3, its first terminal is connected to the scan signal output terminal Gout, and its second terminal is connected to the first low-voltage terminal VSS1. It is turned on under the control of the reset signal output from the third reset terminal R3, and is used to conduct the charge in the scan signal output terminal Gout to the first low-voltage terminal VSS1.

[0060] Please see Figure 6 , Figure 6 This is a schematic diagram showing the changes in clock signal and output control node voltage in touch mode.

[0061] like Figure 6As shown, when the display panel receives a touch signal for touch display, i.e., during the touch display period tc, the pixel unit P will stop charging, i.e., the clock signal CLK stops outputting. At this time, the time required for the first node Q1 in the scan drive unit 130 to maintain the preset voltage increases, resulting in leakage. That is, during the touch process, the potential of the first node Q1 will gradually decrease due to leakage. As the potential of the first node Q1 decreases, the conduction degree of the second switch T2 in the output control module 132 decreases, causing the falling edge time of the scan signal output by the scan drive unit 130 to increase, i.e., the time for the scan signal to fall to a low potential increases. During normal display, the falling edge duration of the scan signal is the first duration t1. At the end of the touch display period tc, the falling edge duration of the scan signal is the second duration t2, where the second duration t2 is greater than the first duration t1. This causes a difference in display brightness between the pixel units in this row and the pixel units in other rows, forming horizontal lines.

[0062] Please see Figure 7 , Figure 7 This is a schematic diagram of an equivalent circuit of a scanning drive unit provided in the second embodiment of this application.

[0063] like Figure 7 As shown, the scan drive unit 130 includes a pull-up module 131, an output control module 132, an auxiliary pull-down module 133, a pull-down module 134, a first node Q1, and a second node. The pull-up module 131 is connected to the first node Q1, and the output control module 132 is connected to the first node Q1, a clock signal terminal (not labeled), and a scan signal output terminal Gout. The pull-up module 131 is used to pull the first node Q1 from a first potential to a second potential. When the first node Q1 is at the second potential, the output control module 132 receives the clock signal CLK from the clock signal terminal and outputs the clock signal CLK as a scan signal from the scan signal output terminal Gout. An auxiliary pull-down module 133 is connected to the clock signal terminal and the second node Q2. It controls the second node Q2 to either a first or second potential based on the clock signal output from the clock signal terminal Gout. When the clock signal CLK is at the first potential, the auxiliary pull-down module 133 controls the second node Q2 to the second potential. When the clock signal CLK is at the second potential (i.e., the clock signal terminal outputs the clock signal CLK), the auxiliary pull-down module 133 controls the second node Q2 to the first potential. A pull-down module 134 is connected to the second node Q2 and the scan signal output terminal Gout. When the second node Q2 is at the second potential, the pull-down module 134 pulls the scan signal output terminal Gout down to the first potential within a preset time. When the second node Q2 is at the first potential, the pull-down module 134 stops pulling down the potential of the scan signal output terminal Gout, thus maintaining the output of the scan signal from the scan signal output terminal Gout.

[0064] The scan drive unit 130 also includes a pull-up control module 135, a pull-down control module 136, a sustaining module 137, a first reset module 138, a second reset module 139, and a third node Q3. The pull-up control module 135 is connected to the third node Q3 and is used to pull the third node Q3 from a first potential to a second potential. The pull-down control module 136 is connected to the first node Q1 and the third node Q3. When the first node Q1 is at a preset potential, the pull-down control module 136 is used to pull the third node Q3 from the second potential to the first potential.

[0065] The sustaining module 137 is connected to the first node Q1 and the third node Q3. When the third node Q3 is at the second potential, the sustaining module 137 pulls down the first node Q1 to the first potential.

[0066] The first reset module 138 is connected to the first node Q1 and is used to pull down the first node Q1 to a first potential. The second reset module 139 is connected to the scan signal output terminal Gout and the first node Q1 and is used to pull down the scan signal output terminal Gout and the first node Q1 to a first potential. The auxiliary pull-down module 133 works in conjunction with the second reset module 139 to pull down the potential of the scan signal output terminal Gout. This is used to control the fall time of the scan signal to be within a preset time after the touch display is completed, thereby eliminating the abnormal fall edge of the scan signal after the touch display and thus eliminating the problem of horizontal lines appearing on the display panel.

[0067] The specific output process of the scan signal is as follows: Before the output control module 132 controls the output of the scan signal, i.e., before the scan drive unit 130 outputs the scan signal, the pull-up control module 135 controls the third node Q3 to be at the second potential, thereby controlling the scan signal output terminal Gout to output a low-level signal through the auxiliary pull-down module 133, and controlling the first node Q1 to be at the first potential, i.e., a low potential, through the sustain module 137. When the pull-up module 131 pulls the first node Q1 up to the preset potential, the pull-down control module 136 pulls the third node Q3 down to the first potential under the control of the first node Q1, so as to control the sustain module 137 to stop pulling down the potential of the first node Q1. At the same time, the clock signal terminal outputs the clock signal CLK, and the auxiliary pull-down module 133 stops pulling down the potential of the scan signal output terminal Gout under the control of the clock signal. The output control module 132 receives the clock signal and outputs it as the scan signal from the scan signal output terminal Gout. After the scan signal is output, the first reset module 138 pulls down the first node Q1 to the first potential, and the auxiliary pull-down module 133, together with the second reset module 139, pulls down the scan signal output terminal Gout to the first potential within a preset time to clear the charge in the circuit.

[0068] Specifically, the pull-up module 131 includes a first switching transistor T1, and the output control module 132 includes a second switching transistor T2 and a voltage regulator capacitor C. The gate of the first switching transistor T1 is connected to the pull-up control terminal Vin, the first terminal of the first switching transistor T1 is connected to the first power supply terminal VDD1, and the second terminal of the first switching transistor T1 is connected to the first node Q1. It is used to conduct under the control of the pull-up control terminal Vin to pull the first node Q1 up to a preset potential. The gate of the second switching transistor T2 is connected to the first node Q1, the first terminal of the second switching transistor T2 is connected to the clock signal terminal, and the second terminal of the second switching transistor T2 is connected to the scan signal output terminal Gout. When the first node Q1 is at the preset potential, the second switching transistor T2 is turned on to receive the clock signal from the clock signal terminal and output it as a scan signal from the scan signal output terminal Gout. The voltage regulator capacitor C is connected to the gate and the second terminal of the second switching transistor T2 to maintain the stability of the voltage between the gate and the second terminal of the second switching transistor T2.

[0069] The auxiliary pull-down module 133 includes a third switch T3 and a fourth switch T4, and the pull-down module 134 includes a fifth switch T5. The gate and first terminal of the third switch T3 are connected to the second power supply terminal VDD, and the second terminal is connected to the second node Q2. It is used to conduct under the control of the second power supply terminal VDD to charge the second node Q2 and pull the second node Q2 to the second potential. The gate of the fourth switch T4 is connected to the clock signal terminal, the first terminal is connected to the second node Q2, and the second terminal is connected to the first low-voltage terminal. It is used to conduct when the clock signal is at the second potential to control the second node Q2 to be connected to the second low-voltage terminal. The gate of the fifth switch T5 is connected to the second node Q2, the first terminal is connected to the scan signal output terminal, and the second terminal is connected to the second low-voltage terminal. It is used to conduct when the second node Q2 is at the second potential to control the scan signal output terminal to be connected to the second low-voltage terminal, that is, to pull down the potential of the scan signal output terminal to the first potential. In other words, the third switch T3, under the control of the second power supply terminal VDD, pulls the second node Q2 up to the second potential, thereby controlling the fifth switch T5 to conduct, thus controlling the scan signal output terminal to be connected to the first low-voltage terminal, i.e., controlling the scan signal output terminal to be at the first potential. The fourth switch T4 is turned on under the control of the clock signal; that is, when the clock signal is at the second potential, the fourth switch T4 conducts, pulling the second node Q2 down to the first potential, thereby controlling the fifth switch T5 to be turned off, so that the scan signal output terminal is disconnected from the second low-voltage terminal, i.e., stopping the pull-down of the scan signal output terminal's potential.

[0070] The pull-up control module 135 includes a sixth switch T6 and a seventh switch T7. The gate and first terminal of the sixth switch T6 are connected to the second power supply terminal VDD2. The second terminal of the sixth switch T6 is connected to the pull-down control module 136. The gate of the seventh switch T7 is connected to the second terminal of the sixth switch T6. The first terminal of the seventh switch T7 is connected to the second power supply terminal VDD2. The second terminal of the seventh switch T7 is connected to the third node Q3. The sixth switch T6 and the seventh switch T7 are turned on under the control of the driving voltage output from the second power supply terminal VDD2, and are used to pull up the third node Q3 to the second potential.

[0071] The pull-down control module 136 includes an eighth switch T8 and a ninth switch T9. The gate of the eighth switch T8 is connected to the first node Q1, the first terminal of the eighth switch T8 is connected to the second terminal of the sixth switch T6, and the second terminal of the eighth switch T8 is connected to the first low-voltage terminal VSS1. When the first node Q1 is at a preset potential, the eighth switch T8 is turned on, connecting the second terminal of the sixth switch T6 and the gate of the seventh switch T7 to the first low-voltage terminal VSS1, thereby controlling the seventh switch T7 to turn off, thus stopping the pull-up of the potential of the third node Q3, i.e., controlling the third node Q3 to drop to the first potential. The gate of the ninth switch T9 is connected to the first node Q1, the first terminal is connected to the third node Q3, and the second terminal is connected to the first low-voltage terminal VSS1. When the first node Q1 is at a preset potential, the ninth switch T9 is turned on, controlling the third node Q3 to be connected to the first low-voltage terminal VSS1, thereby conducting the charge of the third node Q3 to the first low-voltage terminal VSS1, thus pulling the third node Q3 down to the first potential.

[0072] The sustaining module 137 includes a tenth switch transistor T10. The gate of the tenth switch transistor T10 is connected to the third node Q3, the first terminal is connected to the first node Q1, and the second terminal is connected to the first low-voltage terminal VSS1. When the third node Q3 is at the second potential, the tenth switch transistor T10 is turned on to control the first node Q1 to be connected to the first low-voltage terminal VSS1, thereby controlling the first node Q1 to be at the first potential.

[0073] The first reset module 138 includes a ninth switch transistor T9. The gate of the ninth switch transistor T9 is connected to the first reset terminal R1, the first terminal is connected to the first node Q1, and the second terminal is connected to the second low-voltage terminal VSS2. When the scan signal is output, the first reset terminal R1 outputs a reset signal to control the ninth switch transistor T9 to turn on, so as to control the first node Q1 to be connected to the second low-voltage terminal VSS2, which is used to conduct the charge of the first node Q1 to the second low-voltage terminal VSS2 and pull down the first node Q1 to the first potential.

[0074] The second reset module 139 includes a twelfth switch transistor T12 and a thirteenth switch transistor T13. The gate of the twelfth switch transistor T12 is connected to the second reset terminal R2, its first terminal is connected to a voltage regulator capacitor and then to the first node Q1, and its second terminal is connected to the first low-voltage terminal VSS1. It is turned on under the control of the reset signal output from the second reset terminal R2, and is used to conduct the charge in the first node Q1 and the voltage regulator capacitor to the first low-voltage terminal VSS1. The gate of the thirteenth switch transistor T13 is connected to the third reset terminal R3, its first terminal is connected to the scan signal output terminal Gout, and its second terminal is connected to the first low-voltage terminal VSS1. It is turned on under the control of the reset signal output from the third reset terminal R3, and is used to conduct the charge in the scan signal output terminal Gout to the first low-voltage terminal VSS1.

[0075] It is understood that the first switching transistor T1 through the thirteenth switching transistor T13 are all controllable switching transistors. These controllable switching transistors can be any of the following: metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gallium nitride transistors (GaN transistors), silicon carbide transistors (SiC transistors), bipolar transistors, or thyristors, etc. For MOSFETs, they can be N-type MOSFETs (NMOS) or P-type MOSFETs (PMOS). In this embodiment, the switching transistor is an NMOS, and the first terminal of the switching transistor can be the source, and the second terminal can be the drain. Please refer to [link to relevant documentation]. Figure 8 , Figure 8 for Figure 7 A schematic diagram of the potential change at the second node.

[0076] like Figure 8 As shown, when the clock signal is at the first potential (low potential), the second node Q2 is connected to the second power supply terminal VDD2 via the third switch T3, and is charged through the second power supply terminal VDD2 and located at the second potential. When the clock signal is at the second potential (high potential), the second node Q2 is connected to the first low-voltage terminal VSS1 via the fourth switch T4 to maintain the first potential.

[0077] When the clock signal is at a low potential, i.e., when the clock signal output stops, the control node is at the second potential. At this time, the fifth switch T5 is turned on, controlling the scan signal output terminal Gout to be connected to the first low-voltage terminal VSS1 via the fifth switch T5. Simultaneously, it is connected to the first low-voltage terminal VSS1 via the thirteenth switch T13 in the second reset module 139. By simultaneously pulling down the fifth switch T5 and the thirteenth switch T13, the fall time of the scan signal can be effectively shortened after the touch display is completed. This ensures that the difference between the fall time of the scan signal after touch display and the fall time of the scan signal without touch display is within a preset time, i.e., the difference between the first duration t1 and the second duration t2 is within a preset range. This eliminates the problem of horizontal lines appearing on the display panel due to the difference in fall time. When the difference between the first duration t1 and the second duration t2 is within the preset range, the human eye cannot perceive the horizontal lines caused by the difference in the fall time of the scan signal when the display panel is displaying an image.

[0078] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A scanning drive circuit, comprising n sequentially arranged scanning drive units, where n is an integer greater than 1, wherein the n scanning drive units are used to sequentially output corresponding scanning signals, and the scanning signals are used to control pixel units to receive data signals for image display and perform image display; Its features are, The scanning drive unit includes a pull-up module, an output control module, an auxiliary pull-down module, a pull-down module, a first node, and a second node. The pull-up module is connected to the first node to pull the first node from a first potential to a second potential. The output control module is connected to the first node, a scan signal output terminal, and a clock signal terminal. When the first node is at the second potential, the output control module receives a clock signal from the clock signal terminal and controls the scan signal output terminal to output the scan signal. When the display panel receives a touch signal during the touch period, the output of the scan signal is stopped. The auxiliary pull-down module is connected to the clock signal terminal and the second node, and is used to control the second node to be at the first potential or the second potential according to the clock signal. The pull-down module is connected to the second node and the scan signal output terminal. When the display panel receives the touch signal and performs image display recovery output of the clock signal, the auxiliary pull-down module stops pulling down the potential of the scan signal output terminal according to the clock signal, and the output control module outputs the scan signal according to the clock signal. When the clock signal is at the first potential, the auxiliary pull-down module controls the second node to be at the second potential. The pull-down module pulls down the potential of the scan signal output terminal to the first potential and stops outputting the scan signal within a preset time, so that the difference between the fall time of the scan signal output after touch display and the fall time of the scan signal when no touch display is performed is within the preset time.

2. The scanning drive circuit as described in claim 1, characterized in that, The pull-up module includes a first switching transistor, and the output control module includes a second switching transistor. The gate of the first switching transistor is connected to the pull-up control terminal, the first end of the first switching transistor is connected to the first power supply terminal, and the second end of the first switching transistor is connected to the first node. The first switching transistor is used to conduct under the control of the pull-up control terminal to control the first power supply terminal to charge the first node and pull the first node from the first potential to the second potential. The gate of the second switch is connected to the first node, the first end of the second switch is connected to the clock signal terminal, and the second end of the second switch is connected to the scan signal output terminal. The second switch is used to turn on when the first node is at the second potential, and is used to receive the clock signal and output it as the scan signal from the scan signal output terminal.

3. The scanning drive circuit as described in claim 2, characterized in that, The auxiliary pull-down module includes a third switch and a fourth switch, and the pull-down module includes a fifth switch. The gate and first terminal of the third switch are connected to the second power supply terminal, and the second terminal of the third switch is connected to the second node. It is used to turn on according to the driving voltage output by the second power supply terminal and charge the second node, thereby pulling the second node up to the second potential. The gate of the fourth switch is connected to the clock signal terminal, the first terminal of the fourth switch is connected to the second node, and the second terminal of the fourth switch is connected to the first low-voltage terminal. It is used to turn on when the clock signal is output at the clock signal terminal, so as to control the second node to drop to the first potential. The gate of the fifth switch is connected to the second node, the first end of the fifth switch is connected to the scan signal output terminal, and the second end of the fifth switch is connected to the first low-voltage terminal. When the second node is at the first potential, the fifth switch is turned off, and the scan signal output terminal outputs the scan signal. When the second node is at the second potential, the fifth switch is turned on to control the potential of the scan signal output terminal to drop to the first potential within the preset time.

4. The scanning drive circuit as described in claim 3, characterized in that, The scanning drive circuit further includes a pull-up control module, a pull-down control module, a sustaining module, and a third node. The pull-up control module is connected to the third node and is used to pull the third node up from a first potential to a second potential. The pull-down module is connected to the third node and is used to pull the third node down from the second potential to the first potential. The sustaining module is connected to the first node and the third node and is used to control the first node to be at the first potential when the third node is at the second potential.

5. The scanning drive circuit as described in claim 4, characterized in that, The pull-up control module includes a sixth switch and a seventh switch. The gate and first terminal of the sixth switch are connected to the second power supply terminal, and the second terminal of the sixth switch is connected to the gate of the seventh switch. The first terminal of the seventh switch is connected to the second power supply terminal, and the second terminal of the seventh switch is connected to the third node. The sixth and seventh switches are used to conduct under the control of the second power supply terminal to pull the third node up to the second potential.

6. The scanning drive circuit as described in claim 5, characterized in that, The pull-down control module includes an eighth switch and a ninth switch. The gate of the eighth switch is connected to the first node, the first end of the eighth switch is connected to the gate of the seventh switch, and the second end of the eighth switch is connected to the first low-voltage terminal. It is used to turn on when the first node is at the second potential, so as to control the seventh switch to turn off and control the second power supply terminal to stop charging the third node. The gate of the ninth switch is connected to the first node, the first end of the ninth switch is connected to the third node, and the second end of the ninth switch is connected to the first low-voltage terminal, for turning on when the first node is at the second potential, so as to pull the third node down to the first potential.

7. The scanning drive circuit as described in claim 6, characterized in that, The sustaining module includes a tenth switch, the gate of which is connected to the third node, the first end of which is connected to the first node, and the second end of which is connected to the first low-voltage terminal. The tenth switch is used to turn on when the third node is at the second potential, so as to pull the first node down to the first potential.

8. The scanning drive circuit as described in claim 4, characterized in that, The scanning drive circuit further includes a first reset module and a second reset module. The first reset module is connected to the first node and is used to pull down the first node to the first potential after the scanning signal is output. The second reset module is connected to the scan signal output terminal and is used to pull down the scan signal output terminal to the first potential simultaneously with the auxiliary pull-down module within a preset time after the scan signal output is completed.

9. The scanning drive circuit as described in claim 8, characterized in that, The first reset module includes an eleventh switch transistor, and the second reset module includes a twelfth switch transistor and a thirteenth switch transistor. The gate of the eleventh switch transistor is connected to a first reset terminal, the first terminal of the eleventh switch transistor is connected to the first node, and the second terminal of the eleventh switch transistor is connected to a second low-voltage terminal. It is used to turn on under the control of the first reset terminal after the scan signal is output, so as to pull the first node down to the first potential. The gate of the twelfth switch is connected to the second reset terminal, the first terminal of the twelfth switch is connected to the first node, and the second terminal of the twelfth switch is connected to the first low-voltage terminal. This is used to turn on the first node under the control of the second reset terminal after the scan signal is output, so as to pull the first node down to the first potential. The gate of the thirteenth switch is connected to the third reset terminal, the first terminal of the thirteenth switch is connected to the scan signal output terminal, and the second terminal of the thirteenth switch is connected to the first low voltage terminal, which is used to pull down the scan signal output terminal to the first potential within the preset time after the scan signal is output.

10. A display panel, characterized in that, The device includes a plurality of pixel units arranged in a matrix in the display area, a data driving circuit arranged in the non-display area, and a scan driving circuit as described in any one of claims 1-9. The scan driving circuit is used to output a scan signal, and the scan signal is used to control the pixel units to receive the data signal output by the data driving circuit for image display.

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