Ferroelectric memory array and method of making same, memory, electronic device

Abstract

The application provides a ferroelectric memory array and a preparation method thereof, a memory and an electronic device, relates to the technical field of semiconductors, and aims to improve the service life and durability of the memory. The ferroelectric memory array can be a two-dimensional structure or a three-dimensional structure. The ferroelectric memory array comprises a plurality of memory cells arranged in an array. Each memory cell comprises a ferroelectric capacitor and a transistor. The ferroelectric capacitor comprises oppositely arranged first and second electrodes, a ferroelectric layer and a protective layer. The ferroelectric layer is arranged between the first and second electrodes. At least one protective layer is arranged between the ferroelectric layer and the first electrode and / or between the ferroelectric layer and the second electrode. The material of the protective layer comprises a metal oxide, and the thickness of the protective layer is less than 0.1 nm. The ferroelectric memory array can be applied to a memory to realize reading and writing of data.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a ferroelectric memory array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] Currently, ferroelectric random access memory (FeRAM) has been widely used due to its low power consumption, non-volatile data storage, and fast access speed.

[0003] Typically, ferroelectric memories have multiple storage cells, each including a ferroelectric capacitor. The ferroelectric capacitor comprises two opposing electrodes and a ferroelectric thin film disposed between the two electrodes; that is, the ferroelectric capacitor has a metal-ferroelectric thin film-metal (MFM) structure. The ferroelectric thin film exhibits the ferroelectric effect, and its polarization direction can be changed by applying an electric field to it through the two electrodes. Ferroelectric memories utilize the ferroelectric effect of the ferroelectric thin film to store data.

[0004] However, as the electric field changes cyclically, oxygen in the ferroelectric thin film diffuses into the electrodes. Oxygen vacancies are formed in the ferroelectric thin film due to oxygen deficiency. As oxygen vacancies accumulate, they form conductive filaments, which increases the leakage current in the ferroelectric capacitor and can easily lead to breakdown of the ferroelectric capacitor. This, in turn, reduces the service life and durability of the ferroelectric memory. Summary of the Invention

[0005] This application provides a ferroelectric memory array and its fabrication method, memory, and electronic device, which can improve the service life and durability of ferroelectric memory.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a ferroelectric memory array is provided, which can be a two-dimensional structure or a three-dimensional structure. Furthermore, this ferroelectric memory array can be applied to ferroelectric memories, ferroelectric field-effect transistor memories, or ferroelectric tunnel junction memories to achieve data reading and writing.

[0008] The ferroelectric memory array comprises multiple memory cells arranged in an array. Each memory cell includes a ferroelectric capacitor and a transistor. The ferroelectric capacitor includes a first electrode and a second electrode disposed opposite to each other, a ferroelectric layer, and a protective layer, wherein the ferroelectric layer is disposed between the first electrode and the second electrode. At least one protective layer is disposed between the ferroelectric layer and the first electrode, and / or between the ferroelectric layer and the second electrode. The material of the protective layer includes a metal oxide, and the thickness of the protective layer is less than 0.1 nm.

[0009] The ferroelectric capacitor provided in the above embodiments of this application has a protective layer between the first electrode and the ferroelectric layer, or between the second electrode and the ferroelectric layer, or both between the first electrode and the ferroelectric layer, so that at least one of the first electrode and the second electrode does not directly contact the ferroelectric layer.

[0010] Furthermore, the protective layer is made of dense metal oxides, such as aluminum oxide and magnesium oxide, which can suppress the diffusion of oxygen ions from the ferroelectric layer into the electrodes (first electrode and / or second electrode), weaken the oxidation reaction between the electrode and oxygen ions, and prevent the formation of a "dead layer" of non-ferroelectric phase crystals on the side of the electrode near the ferroelectric layer and on the side of the ferroelectric layer near the electrode. This can increase the proportion of ferroelectric phase crystals in the ferroelectric layer and improve the accuracy of reading and writing data in the ferroelectric memory using this ferroelectric capacitor.

[0011] By suppressing the diffusion of oxygen ions from the ferroelectric layer into the electrodes through a protective layer, the number of oxygen vacancies formed due to oxygen ion movement in the ferroelectric layer can be reduced. This prevents the formation of conductive filaments from oxygen vacancies in the ferroelectric layer, thereby reducing leakage current in the ferroelectric capacitor, preventing capacitor breakdown, and improving the lifespan and durability of the ferroelectric memory. Furthermore, the reduction in oxygen vacancies in the ferroelectric layer can also mitigate polarization fatigue caused by oxygen vacancies, thus improving the accuracy of data reading and writing in the ferroelectric memory.

[0012] Furthermore, the protective layer is less than 0.1 nm thick, and its thinner thickness results in lower resistance, which can reduce the voltage division effect of the protective layer, decrease the proportion of voltage applied to the protective layer, and increase the proportion of voltage applied to the ferroelectric layer. According to the hysteresis loop diagram of the ferroelectric layer, the greater the voltage applied to the ferroelectric layer, the greater the polarization intensity of the ferroelectric layer, which can improve the distinction between the positive and negative polarization states of the ferroelectric layer, thereby improving the accuracy of reading and writing data in the ferroelectric memory.

[0013] In some embodiments, the material of the protective layer includes at least one of aluminum oxide and magnesium oxide.

[0014] In the above embodiments, both aluminum oxide and magnesium oxide are dense metal oxides, which enable the protective layer to suppress the diffusion of oxygen ions from the ferroelectric layer into the electrode.

[0015] In some embodiments, the thickness of the protective layer is less than the thickness of the first electrode, and / or the thickness of the protective layer is less than the thickness of the second electrode.

[0016] In the above embodiments, by setting the thickness of the protective layer to be less than the thickness of the first electrode and the second electrode, the protective layer is thinner and has lower resistance, which can weaken the voltage division effect of the protective layer, improve the distinction between the positive and negative polarization states of the ferroelectric layer, and thus improve the accuracy of reading and writing data in the ferroelectric memory.

[0017] In some embodiments, the thickness of the protective layer is less than the thickness of the ferroelectric layer.

[0018] In the above embodiments, by setting the thickness of the protective layer to be less than the thickness of the ferroelectric layer, the protective layer is thinner and has lower resistance, which can weaken the voltage division effect of the protective layer, improve the distinction between the positive and negative polarization states of the ferroelectric layer, and thus improve the accuracy of reading and writing data in the ferroelectric memory.

[0019] In some embodiments, the material of the first electrode and / or the second electrode includes at least one of TiN and TaN, and also includes at least one of aluminum oxide and magnesium oxide.

[0020] In the above embodiments, the first and second electrodes are doped with aluminum or magnesium. Aluminum and magnesium are easily oxidized to form dense aluminum oxide and magnesium oxide, which can inhibit the diffusion of oxygen ions from the ferroelectric layer into the electrode and inhibit the diffusion of oxygen ions in the electrode. This weakens the oxidation reaction between TiN and TaN and oxygen ions, and avoids the formation of a "dead layer" of non-ferroelectric phase crystal on the side of the electrode close to the ferroelectric layer, thereby improving the accuracy of reading and writing data in the ferroelectric memory.

[0021] Furthermore, it can reduce oxygen vacancies formed in the ferroelectric layer due to the movement of oxygen ions, thereby improving the lifespan, durability, and accuracy of reading and writing data in ferroelectric memory.

[0022] In some embodiments, the material of the first electrode and / or the second electrode includes TiN and is also doped with at least one of Si, La, Ce, Y, Sc, and Sr.

[0023] In the above embodiments, by doping the first electrode and the second electrode with one or more of Si, La, Ce, Y, Sc, and Sr, the doping elements can diffuse to the grain boundaries between the grains, reducing the disorder at the grain boundaries and weakening the energy and fluidity at the grain boundaries. This inhibits the diffusion of oxygen ions along the grain boundaries in the ferroelectric layer, weakens the oxidation reaction between TiN and oxygen ions, and avoids the formation of a "dead layer" of non-ferroelectric phase crystal on the side of the electrode near the ferroelectric layer, thereby improving the accuracy of reading and writing data in the ferroelectric memory.

[0024] Furthermore, it can reduce oxygen vacancies formed in the ferroelectric layer due to the movement of oxygen ions, thereby improving the lifespan, durability, and accuracy of reading and writing data in ferroelectric memory.

[0025] In some embodiments, the material of the first electrode and / or the second electrode includes at least one of TiN, TaN, TiAl, TiC, and TiSiC, and is also doped with an element whose valence state is greater than or equal to 5.

[0026] In the above embodiments, by doping the first and second electrodes with elements having a valence state greater than or equal to 5, i.e., doping with elements with higher valence states, the number of electrons in the first and second electrodes can be increased, the concentration of anion vacancies in the electrodes can be reduced, the diffusion of oxygen ions from the ferroelectric layer into the electrodes can be suppressed, and the diffusion of oxygen ions in the electrodes can be suppressed. This weakens the oxidation reaction between TiN, TaN, TiAl, TiC, TiSiC and oxygen ions, and avoids the formation of a "dead layer" of non-ferroelectric phase crystal on the side of the electrode close to the ferroelectric layer, thereby improving the accuracy of reading and writing data in the ferroelectric memory.

[0027] Furthermore, it can reduce oxygen vacancies formed in the ferroelectric layer due to the movement of oxygen ions, thereby improving the lifespan, durability, and accuracy of reading and writing data in ferroelectric memory.

[0028] In some embodiments, the higher valence element doped in the first electrode and / or the second electrode includes at least one of W, Mo, and Nb.

[0029] In some embodiments, the ferroelectric capacitor further includes at least one third electrode disposed on the side of the second electrode away from the ferroelectric layer, and / or on the side of the first electrode away from the ferroelectric layer. The coefficient of thermal expansion of the third electrode is different from that of the first electrode and / or the second electrode.

[0030] It is understandable that the fabrication of ferroelectric capacitors requires a high-temperature environment. Since the thermal expansion coefficient of the third electrode is different from that of the first and / or second electrodes, the volume expansion rate of the third electrode is different from that of the first and / or second electrodes. This generates stress in the ferroelectric capacitor. This stress acts on the ferroelectric layer, causing lattice distortion in the non-ferroelectric phase crystals in the ferroelectric layer, resulting in polarization intensity. This can improve the distinction between the positive and negative polarization states of the ferroelectric film and improve the accuracy of reading and writing data in the ferroelectric memory.

[0031] In some embodiments, the ferroelectric layer material includes at least one of HZO, La-doped HZO, Y-doped HZO, Sr-doped HZO, Gd-doped HZO, Gd and La co-doped HZO, Si-doped HfO2, Al-doped HfO2, La-doped HfO2, Y-doped HfO2, Gd-doped HfO2, and Sr-doped HfO2.

[0032] In some embodiments, both the first electrode and the second electrode are planar electrodes, and the first electrode, the ferroelectric layer, the protective layer, and the second electrode are stacked. That is, the structure of the ferroelectric capacitor is a two-dimensional planar structure, which is simple and easy to fabricate.

[0033] In some embodiments, the first electrode is a planar electrode, the second electrode is a columnar electrode, the second electrode penetrates through the first electrode, and the ferroelectric layer and the protective layer are disposed around the second electrode.

[0034] In the above embodiments, the ferroelectric capacitor adopts a three-dimensional vertical structure design, which can reduce its area occupied in the plane, thereby increasing the number of ferroelectric capacitors per unit area in the plane, so as to increase the number of storage units per unit area, which is beneficial to improving the storage density of the memory.

[0035] In some embodiments, both the first electrode and the second electrode are planar electrodes, and one of the first electrode and the second electrode is electrically connected to a transistor to form a memory cell. Alternatively, the first electrode is a planar electrode, the second electrode is a cylindrical electrode, and the second electrode is electrically connected to a transistor to form a memory cell.

[0036] Secondly, a method for fabricating a ferroelectric memory array is provided. The method includes sequentially forming a first electrode, a ferroelectric layer, and a second electrode. The method further includes forming at least one protective layer disposed between the ferroelectric layer and the first electrode, and / or between the ferroelectric layer and the second electrode. The protective layer is made of a metal oxide, and its thickness is less than 0.1 nm.

[0037] In some embodiments, during the formation of the first electrode, a metal element is doped. The metal element in the first electrode undergoes an oxidation reaction to form a metal oxide, resulting in a protective layer located between the ferroelectric layer and the first electrode.

[0038] In some embodiments, a metal element is doped during the formation of the second electrode. The metal element in the second electrode undergoes an oxidation reaction to form a metal oxide, resulting in a protective layer located between the ferroelectric layer and the second electrode.

[0039] The preparation method provided in the above embodiments of this application sequentially forms a first electrode, a ferroelectric layer, and a second electrode. During the formation of the first and second electrodes, easily oxidizable metal elements are doped. The metal elements undergo an oxidation reaction to generate dense metal oxides, thereby obtaining a protective layer located between the ferroelectric layer and the first electrode, and a protective layer located between the ferroelectric layer and the second electrode.

[0040] The protective layer can inhibit the diffusion of oxygen ions from the ferroelectric layer into the electrode, weaken the oxidation reaction between the electrode and oxygen ions, and reduce the oxygen vacancies formed in the ferroelectric layer due to the movement of oxygen ions, thereby improving the service life, durability, and accuracy of reading and writing data of the ferroelectric memory.

[0041] Furthermore, the above preparation methods employ atomic layer deposition, physical vapor deposition, or chemical vapor deposition processes, allowing for precise control over the chemical composition and thickness of the film, good process compatibility, and no damage to the ferroelectric layer (e.g., physical damage, corrosion, etc.), thus facilitating the preparation of ferroelectric memory with better performance and higher durability.

[0042] In some embodiments, the material of the first electrode and / or the second electrode includes Al-doped TiN to form the first electrode, and / or, to form the second electrode, includes: depositing TiN and in-situ doping AlN in the TiN, wherein the atomic ratio of Al to Ti is less than 3 / 7.

[0043] In some embodiments, a first electrode, a ferroelectric layer, and a second electrode are sequentially formed, including: forming a first electrode, a ferroelectric layer, and a second electrode stacked together to form a ferroelectric capacitor with a two-dimensional planar structure.

[0044] In some embodiments, forming a first electrode, a ferroelectric layer, and a second electrode sequentially includes: forming a first electrode; forming a via penetrating the first electrode; forming a ferroelectric layer on the sidewall of the via; and forming a second electrode inside the ferroelectric layer to form a three-dimensional vertical ferroelectric capacitor.

[0045] Thirdly, a memory is provided, which includes the ferroelectric memory array described in any of the above embodiments, and a controller electrically connected to the ferroelectric memory array.

[0046] Fourthly, an electronic device is provided, such as a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, or a communication electronics product. The electronic device includes a processor and a memory as described in the above embodiments, the memory being electrically connected to the processor.

[0047] It is understood that the beneficial effects of the memory and electronic device provided by the above embodiments of this application can be referred to the beneficial effects of the ferroelectric memory array mentioned above, and will not be repeated here. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0049] Figure 1 This is an architectural diagram of an electronic device according to some embodiments;

[0050] Figure 2 An exploded view of an electronic device according to some embodiments;

[0051] Figure 3 This is an architectural diagram of a ferroelectric memory according to some embodiments;

[0052] Figure 4 A circuit diagram of a memory cell according to some embodiments;

[0053] Figure 5 This is a structural diagram of a ferroelectric capacitor in related technologies;

[0054] Figure 6 A schematic diagram showing the generation of oxygen vacancies in the ferroelectric layer of a ferroelectric capacitor.

[0055] Figure 7 This is a hysteresis loop diagram of the ferroelectric layer of a ferroelectric capacitor.

[0056] Figure 8 A schematic diagram showing the conductive path created by oxygen vacancies in the ferroelectric layer of a ferroelectric capacitor.

[0057] Figures 9-11 Here are structural diagrams of various ferroelectric capacitors according to some embodiments;

[0058] Figures 12-14 Here are structural diagrams of various ferroelectric capacitors according to some embodiments;

[0059] Figures 15A to 15D The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments;

[0060] Figure 16 This is a three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments;

[0061] Figures 17A-17E The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments. Detailed Implementation

[0062] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0063] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this application.

[0064] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0065] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0066] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments claimed herein are not necessarily limited to the content of this document.

[0067] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0068] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0069] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0070] In the context of this application, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0071] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0072] The technical terms used in some embodiments of this application are as follows:

[0073] Grains: Grains are small, irregularly shaped crystals that make up a polycrystalline material.

[0074] Grain boundary: The contact interface between grains is called a grain boundary.

[0075] Crystal: A structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.

[0076] Crystal lattice: The atoms inside a crystal are arranged according to certain geometric rules, and the spatial framework of this atomic arrangement is called a crystal lattice.

[0077] Unit cell: The most basic geometric unit that makes up a crystal. Its shape and size are the same as the parallelepiped unit of the space lattice, and it retains all the characteristics of the entire crystal lattice.

[0078] Ferroelectric crystals: The structure of the unit cell causes the centers of positive and negative charges to not coincide, resulting in an electric dipole moment. This generates a non-zero polarization intensity, giving the crystal spontaneous polarization. Furthermore, the direction of the electric dipole moment can be changed by an external electric field, exhibiting characteristics similar to ferromagnetic materials.

[0079] Ferroelectric materials are materials that can maintain spontaneous polarization by applying an electric field to align their internal electric dipole moments, even when the externally applied electric field is removed. In other words, ferroelectrics are materials in which the polarization intensity (polarization) value (or electric field) is semi-permanently retained, even after a constant voltage is applied and the voltage is restored to zero volts.

[0080] Anionic vacancies: a type of defect in oxides. The lattice structure of oxides is formed by the alternating arrangement of metal cations and oxygen anions in stoichiometric ratios. If the ratio of metal to oxygen atoms in an oxide is greater than its stoichiometric ratio, anionic vacancies may appear at lattice sites that should be occupied by oxygen ions. Increased anionic vacancies can lead to faster oxygen migration through the oxide film, thus increasing the rate of metal oxidation.

[0081] Some embodiments of this application provide an electronic device, which may be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatch, smart bracelet), virtual reality (VR) terminal device, augmented reality (AR) terminal device, rechargeable small household appliances (e.g., soymilk maker, robot vacuum cleaner), drone, radar, aerospace equipment, and vehicle-mounted equipment, etc.; the electronic device may also be a network device such as a base station. The embodiments of this application do not impose special limitations on the specific form of the electronic device.

[0082] Figure 1 This is an architectural diagram of an electronic device according to some embodiments.

[0083] like Figure 1 As shown, electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will understand that... Figure 1 The architecture of the electronic device 1 shown does not constitute a limitation on the electronic device 1, which may include, for example... Figure 1 The components shown may have more or fewer components, or may be combined as follows: Figure 1 Some of the components shown, or those that can be combined with, for example Figure 1 The component arrangements shown are different.

[0084] The storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area. The program storage area stores and backs up the operating system and application programs required for at least one function (such as sound playback, image playback, etc.); the data storage area stores data created based on the use of the electronic device 1 (such as audio data, image data, phonebook, etc.). Furthermore, the storage device 11 includes an external memory 111 and an internal memory 112. Data stored in the external memory 111 and the internal memory 112 can be transferred between each other.

[0085] External storage 111 may include, for example, a hard disk, a USB flash drive, a floppy disk, etc. Internal storage 112 may include, for example, random access memory (RAM), read-only memory (ROM), resistive random access memory (RRAM), etc. RAM may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). ROM may include, for example, NAND flash memory.

[0086] Processor 12 is the control center of the electronic device 1. It connects various parts of the electronic device 1 via various interfaces and lines, and performs various functions and processes data by running or executing software programs and / or modules stored in storage device 11, and by calling data stored in storage device 11, thereby providing overall monitoring of the electronic device 1. Optionally, processor 12 may include one or more processing units. For example, processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Different processing units can be independent devices or integrated into one or more processors. For example, processor 12 may integrate an application processor and a modem processor, where the application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into processor 12. The application processor may, for example, be a central processing unit (CPU). Figure 1Taking processor 12 as an example (CPU), the CPU may include an arithmetic logic unit (ALU) 121 and a control unit 122. The ALU 121 retrieves data stored in the internal memory 112, processes the data stored in the internal memory 112, and the processed result is usually sent back to the internal memory 112. The control unit 122 can control the ALU 121 to process the data, and the control unit 122 can also control the external memory 111 and the internal memory 112 to read or write data.

[0087] Input device 13 is used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device. For example, input device 13 may include a touchscreen and other input devices. A touchscreen, also known as a touch panel, can collect touch operations performed by the user on or near the touchscreen (e.g., operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touchscreen) and drive corresponding connected devices according to a pre-set program. The controller 122 in the processor 12 can also control the input device 13 to receive or not receive input signals. Furthermore, the input numeric or character information received by input device 13 and the generated key signal inputs related to user settings and function control of the electronic device can be stored in internal memory 112.

[0088] Output device 14 is used to output signals corresponding to the input data of input device 13 and stored in internal memory 112. For example, output device 14 outputs audio signals or video signals. The controller 122 in the processor 12 can also control output device 14 to output signals or not output signals.

[0089] It should be noted that, Figure 1 The thick arrows in the diagram are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, a single arrow between input device 13 and internal memory 112 indicates that data received by input device 13 is transmitted to internal memory 112. As another example, a double arrow between arithmetic unit 121 and internal memory 112 indicates that data stored in internal memory 112 can be transmitted to arithmetic unit 121, and data processed by arithmetic unit 121 can be transmitted to internal memory 112. Figure 1 The thin arrows in the diagram indicate components that the controller 122 can control. For example, the controller 122 can control external memory 111, internal memory 112, arithmetic unit 121, input device 13, and output device 14, etc.

[0090] To facilitate further explanation of the structure of electronic device 1, the following description uses a mobile phone as an example.

[0091] Figure 2 An exploded view of an electronic device according to some embodiments.

[0092] See Figure 2 The electronic device 1 may also include a mid-frame 15, a rear housing 16, and a display screen 17. The rear housing 16 and the display screen 17 are located on opposite sides of the mid-frame 15, and the mid-frame 15 and the display screen 17 are disposed within the rear housing 16. The mid-frame 15 includes a support plate 150 for supporting the display screen 17, and a frame 151 surrounding the support plate 150.

[0093] See also Figure 2 The electronic device 1 may also include a circuit board 18, which is disposed on the side of the carrier plate 150 near the rear cover 16. The internal memory 112 in the electronic device 1 may be disposed on the circuit board 18 and is electrically connected to the circuit board 18.

[0094] Currently, ferroelectric memories, as a novel type of memory, are widely used in internal memory due to their characteristics such as non-volatility of stored data, fast access speed, low read / write voltage, low power consumption, small device size, good cycle performance, and radiation resistance. The internal memory 112 involved in this application can be a ferroelectric memory, a ferroelectric field-effect transistor (FeFET) memory, or a ferroelectric tunnel junction (FTJ) memory.

[0095] The following embodiments use the internal memory 112 as an example of a ferroelectric memory. Figure 3 This is an architectural diagram of a ferroelectric memory according to some embodiments.

[0096] See Figure 3 The internal memory 112 includes a ferroelectric memory array 210, a decoder 220, a driver 230, a controller (timing controller) 240, a register 250, and an input / output interface 260. The ferroelectric memory array 210 includes multiple memory cells 200 arranged in an array.

[0097] Figure 4 This is a circuit diagram of a memory cell according to some embodiments.

[0098] See Figure 4The memory cell 200 includes a circuit architecture based on a ferroelectric capacitor. The memory cell 200 has a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory cell 200 includes a transistor T and a ferroelectric capacitor C. The source of the transistor T is electrically connected to the bit line (BL), the drain is electrically connected to one electrode of the ferroelectric capacitor C, the gate is electrically connected to the word line (WL), and the other electrode of the ferroelectric capacitor C is electrically connected to the plate line (PL). The circuit architecture of the memory cell 200 in the embodiments of this application is not limited to this.

[0099] Based on this, the decoder 220 can decode the received address to determine the memory cell 200 in the ferroelectric memory array 210 that needs to be accessed. The driver 230 generates a control signal based on the decoding result output by the decoder 220. This control signal is transmitted via word line WL to the gate of transistor T in memory cell 200 to control transistor T to turn on or off, thereby enabling access to the specified memory cell 200. The buffer 250 receives the data signal output from memory cell 200 via board line PL and buffers the data signal, for example, using a first-in-first-out (FIFO) buffering method. The timing controller 240 controls the timing of the buffer 250 and controls the driver 230 to drive the ferroelectric memory array 210. The input / output interface 260 is used to transmit data signals, such as receiving or sending data signals.

[0100] The aforementioned ferroelectric memory array 210, decoder 220, driver 230, timing controller 240, buffer 250 and input / output interface 260 can be integrated into one chip or into multiple chips respectively.

[0101] The working principle of ferroelectric memory will be introduced below in conjunction with the structure of ferroelectric capacitors.

[0102] Figure 5 This is a structural diagram of a ferroelectric capacitor in related technologies; Figure 6 A schematic diagram showing the generation of oxygen vacancies in the ferroelectric layer of a ferroelectric capacitor. Figure 7 This is a hysteresis loop diagram of the ferroelectric layer of a ferroelectric capacitor. Figure 8 This is a schematic diagram illustrating the conductive pathway created by oxygen vacancies in the ferroelectric layer of a ferroelectric capacitor.

[0103] See Figure 5The ferroelectric capacitor C′ includes a first electrode 01′ and a second electrode 02′ disposed opposite to each other, and a ferroelectric film 03′ disposed between the first electrode 01′ and the second electrode 02′. The ferroelectric capacitor C′ has an MFM structure. The ferroelectric film 03′ comprises a ferroelectric material, which has spontaneous polarization characteristics.

[0104] Specifically, the ferroelectric material contains a ferroelectric phase crystal. When the first electrode 01′ and the second electrode 02′ receive voltage signals and generate an electric field, the electric field is applied to the ferroelectric film 03′. The central atoms of the orthorhombic phase unit cell in the ferroelectric material move along the electric field and stop in a low-energy state, which can be, for example, a "0" storage state.

[0105] It should be noted that a large number of central atoms move and couple within the unit cell to form ferroelectric domains, which will generate polarization charges under the influence of an electric field.

[0106] When the electric fields generated by the first electrode 01′ and the second electrode 02′ are reversed, the central atom moves in the unit cell along the direction of the electric field and stops in another low-energy state, which can be, for example, a "1" storage state, that is, the ferroelectric domains are oriented and flipped under the action of the reversed electric field.

[0107] It should be noted that the polarization charge energy formed by the ferroelectric domains before and after the electric field reversal is different. This positive and negative polarization state will cause the ferroelectric capacitor C′ to charge and discharge, which can be identified by the external sensing amplifier to determine whether the storage cell 200 is in the storage state of "0" or "1", thereby realizing the reading or writing of data by the ferroelectric memory.

[0108] However, as Figure 6 As shown, the material of the ferroelectric layer 03′ contains oxygen. At higher temperatures, oxygen ions in the ferroelectric layer 03′ will move and diffuse into the first electrode 01′ and the second electrode 02′. That is, the ferroelectric layer 03′ acts as an oxygen ion donor, and the first electrode 01′ and the second electrode 02′ act as oxygen ion acceptors, resulting in the generation of positively charged oxygen vacancies inside the ferroelectric layer 03′.

[0109] In the ferroelectric layer 03′, oxygen vacancies pin the domain walls of ferroelectric domains, causing polarization fatigue. Polarization fatigue refers to the phenomenon where the polarization intensity of ferroelectric domains decreases after multiple orientation flips. Specifically, ferroelectric memories perform numerous edit / erase operations during data reading and writing. The ferroelectric domains in ferroelectric layer 03′ continuously flip, and after multiple cycles, the residual polarization intensity of the ferroelectric domains in ferroelectric layer 03′ decreases, the coercive field increases, and the "0" or "1" states become increasingly similar. This reduces the distinguishability between the positive and negative polarization states of ferroelectric layer 03′, eventually making them difficult to differentiate, thus increasing the error rate of ferroelectric memory data reading and writing.

[0110] Figure 7 The diagram shows the hysteresis loop of the ferroelectric layer 03′ of the ferroelectric capacitor C′, where the horizontal axis represents the electric field strength E applied to the ferroelectric layer 03′; the vertical axis represents the polarization strength P of the ferroelectric layer 03′; curve “1” is the hysteresis loop of the ferroelectric layer 03′ without oxygen vacancies; and curve “2” is the hysteresis loop of the ferroelectric layer 03′ with oxygen vacancies.

[0111] It can be seen that, under the same electric field strength E, the polarization intensity P of the ferroelectric layer 03′ without oxygen vacancies is larger, while the polarization intensity P of the ferroelectric layer 03′ with oxygen vacancies is smaller. That is, the generation of oxygen vacancies leads to polarization fatigue in the ferroelectric layer 03′.

[0112] like Figure 8 As shown, with the cyclical changes in the electric field, oxygen vacancies gradually accumulate in the ferroelectric layer 03′, forming conductive filaments. This increases the leakage current in the ferroelectric capacitor C′, making it easier for the ferroelectric capacitor C′ to break down, which in turn reduces the lifespan and durability of the ferroelectric memory.

[0113] To address the aforementioned problems, some embodiments of this application provide a ferroelectric capacitor. Figures 9-11 This is a structural diagram of various ferroelectric capacitors according to some embodiments.

[0114] See Figures 9-11 The ferroelectric capacitor C includes a first electrode 01 and a second electrode 02 disposed opposite to each other, and a ferroelectric layer 03 and a protective layer 04 located between the first electrode 01 and the second electrode 02.

[0115] For example, the material of the ferroelectric layer 03 may include at least one of HZO (Hafnium Zirconium Oxide), La-doped HZO, Y-doped HZO, Sr-doped HZO, Gd-doped HZO, Gd and La co-doped HZO, Si-doped HfO2, Al-doped HfO2, La-doped HfO2, Y-doped HfO2, Gd-doped HfO2, and Sr-doped HfO2.

[0116] See Figure 9 At least one protective layer 04 is disposed between the ferroelectric layer 03 and the first electrode 01, which is equivalent to inserting the protective layer 04 between the ferroelectric layer 03 and the first electrode 01.

[0117] For example, a protective layer 04 is provided between the ferroelectric layer 03 and the first electrode 01.

[0118] like Figure 10 As shown, at least one protective layer 04 is disposed between the ferroelectric layer 03 and the second electrode 02, which is equivalent to inserting the protective layer 04 between the ferroelectric layer 03 and the second electrode 02.

[0119] For example, a protective layer 04 is provided between the ferroelectric layer 03 and the second electrode 02.

[0120] like Figure 11 As shown, at least one protective layer 04 is disposed between the ferroelectric layer 03 and the first electrode 01, and at least one protective layer 04 is disposed between the ferroelectric layer 03 and the second electrode 02. This is equivalent to inserting a protective layer 04 between the ferroelectric layer 03 and the first electrode 01, and also inserting a protective layer 04 between the ferroelectric layer 03 and the second electrode 02.

[0121] For example, a protective layer 04 is provided between the ferroelectric layer 03 and the first electrode 01, and a protective layer 04 is provided between the ferroelectric layer 03 and the second electrode 02.

[0122] The material of the aforementioned protective layer 04 includes metal oxides. For example, the material of the protective layer 04 may include aluminum oxide, magnesium oxide, or both.

[0123] Furthermore, the thickness of the protective layer 04 is less than 0.1 nm. For example, the thickness of the protective layer 04 can be 0.09 nm, 0.07 nm, 0.05 nm, 0.03 nm or 0.01 nm.

[0124] The ferroelectric capacitor C provided in the above embodiments of this application has a protective layer 04 between the first electrode 01 and the ferroelectric layer 03, or between the second electrode 02 and the ferroelectric layer 03, or both between the first electrode 01 and the ferroelectric layer 03 and between the second electrode 02 and the ferroelectric layer 03, so that at least one of the first electrode 01 and the second electrode 02 does not directly contact the ferroelectric layer 03.

[0125] Furthermore, the protective layer 04 is made of dense metal oxides, such as aluminum oxide and magnesium oxide, which allows the protective layer 04 to suppress the diffusion of oxygen ions from the ferroelectric layer 03 into the electrodes (first electrode 01 and / or second electrode 02). This reduces the oxidation reaction between the electrodes and oxygen ions, and prevents the formation of a "dead layer" of non-ferroelectric phase crystals on the side of the electrode near the ferroelectric layer 03 and on the side of the ferroelectric layer 03 near the electrode. This increases the proportion of ferroelectric phase crystals in the ferroelectric layer 03 and improves the accuracy of reading and writing data in the ferroelectric memory using the ferroelectric capacitor C.

[0126] By suppressing the diffusion of oxygen ions from the ferroelectric layer 03 into the electrode through the protective layer 04, the number of oxygen vacancies formed in the ferroelectric layer 03 due to oxygen ion movement can be reduced. This prevents the formation of conductive filaments from oxygen vacancies in the ferroelectric layer 03, thereby reducing leakage current in the ferroelectric capacitor C and preventing breakdown of the ferroelectric capacitor C, thus improving the lifespan and durability of the ferroelectric memory. The reduction in oxygen vacancies in the ferroelectric layer 03 also mitigates polarization fatigue caused by oxygen vacancies, thereby improving the accuracy of data reading and writing in the ferroelectric memory.

[0127] Furthermore, the thickness of the protective layer 04 is less than 0.1 nm. The thinner protective layer 04 has lower resistance, which reduces its voltage-dividing effect, lowers the voltage percentage applied to it, and increases the voltage percentage applied to the ferroelectric layer 03. (Reference) Figure 7 This can improve the polarization intensity of the ferroelectric layer O3, enhance the distinction between the positive and negative polarization states of the ferroelectric layer O3, and thus improve the accuracy of reading and writing data in the ferroelectric memory.

[0128] In some embodiments, see Figures 9-11 The thickness of the protective layer 04 is less than the thickness of the first electrode 01, or the thickness of the protective layer 04 is less than the thickness of the second electrode 02, or the thickness of the protective layer 04 is less than both the thickness of the first electrode 01 and the thickness of the second electrode 02.

[0129] For example, the thickness of the first electrode 01 is in the range of 1 nm to 100 nm, the thickness of the second electrode 02 is in the range of 1 nm to 100 nm, and the thickness of the protective layer 04 is less than 0.1 nm, which is less than the thickness of the first electrode 01 and the second electrode 02.

[0130] In the above embodiments, by setting the thickness of the protective layer 04 to be less than the thickness of the first electrode 01 and the second electrode 02, the protective layer 04 is thinner and has lower resistance, which can weaken the voltage division effect of the protective layer 04, improve the distinction between the positive and negative polarization states of the ferroelectric layer 03, and thus improve the accuracy of reading and writing data in the ferroelectric memory.

[0131] In some embodiments, see Figures 9-11 The thickness of the protective layer 04 is less than the thickness of the ferroelectric layer 03.

[0132] For example, the thickness of the ferroelectric layer 03 ranges from 1 nm to 100 nm, and the thickness of the protective layer 04 is less than 0.1 nm, which is less than the thickness of the ferroelectric layer 03.

[0133] In the above embodiments, by setting the thickness of the protective layer 04 to be less than the thickness of the ferroelectric layer 03, the protective layer 04 is thinner and has lower resistance, which can weaken the voltage division effect of the protective layer 04, improve the distinction between the positive and negative polarization states of the ferroelectric layer 03, and thus improve the accuracy of reading and writing data in the ferroelectric memory.

[0134] In some embodiments, see Figures 9-11 The material of the first electrode 01 includes at least one of TiN and TaN, and also includes at least one of aluminum oxide and magnesium oxide.

[0135] For example, the material of the first electrode 01 may include several combinations of TiN and aluminum oxide, TiN and magnesium oxide, TiN and aluminum oxide and magnesium oxide, TaN and aluminum oxide, TaN and magnesium oxide, and TaN and aluminum oxide and magnesium oxide.

[0136] See also Figures 9-11 The material of the second electrode 02 includes at least one of TiN and TaN, and also includes at least one of aluminum oxide and magnesium oxide.

[0137] Similarly, the material of the second electrode O2 can also include several combinations such as TiN and aluminum oxide, TiN and magnesium oxide, TiN and aluminum oxide and magnesium oxide, TaN and aluminum oxide, TaN and magnesium oxide, and TaN and aluminum oxide and magnesium oxide.

[0138] In the above embodiments, the first electrode 01 and the second electrode 02 are doped with aluminum or magnesium. Aluminum and magnesium are easily oxidized to form dense aluminum oxide and magnesium oxide, which can inhibit the diffusion of oxygen ions from the ferroelectric layer 03 into the electrode and inhibit the diffusion of oxygen ions in the electrode. This weakens the oxidation reaction between TiN and TaN and oxygen ions, and avoids the formation of a "dead layer" of non-ferroelectric phase crystal on the side of the electrode close to the ferroelectric layer 03, thereby improving the accuracy of reading and writing data in the ferroelectric memory.

[0139] Furthermore, it can reduce oxygen vacancies formed in the ferroelectric layer O3 due to oxygen ion movement, thereby improving the lifespan, durability, and accuracy of reading and writing data in the ferroelectric memory.

[0140] In some embodiments, see Figures 9-11 The material of the first electrode 01 includes TiN, and is also doped with at least one of Si, La, Ce, Y, Sc and Sr.

[0141] It is understood that the material of the first electrode 01 may include Si-doped TiN, La-doped TiN, Ce-doped TiN, Y-doped TiN, Sc-doped TiN, Sr-doped TiN, etc. Alternatively, the material of the first electrode 01 may include TiN co-doped with multiple elements selected from Si, La, Ce, Y, Sc, and Sr.

[0142] See also Figures 9-11 The material of the second electrode 02 includes TiN, and is also doped with at least one of Si, La, Ce, Y, Sc and Sr.

[0143] It is understood that the material of the second electrode 02 may include Si-doped TiN, La-doped TiN, Ce-doped TiN, Y-doped TiN, Sc-doped TiN, Sr-doped TiN, etc. Alternatively, the material of the second electrode 02 may include TiN co-doped with multiple elements selected from Si, La, Ce, Y, Sc, and Sr.

[0144] In the above embodiments, by doping the first electrode 01 and the second electrode 02 with one or more of Si, La, Ce, Y, Sc, and Sr, the doping elements can diffuse to the grain boundaries between the grains, reducing the disorder at the grain boundaries and weakening the energy and fluidity at the grain boundaries. This inhibits the diffusion of oxygen ions in the ferroelectric layer 03 along the grain boundaries, weakens the oxidation reaction between TiN and oxygen ions, and prevents the formation of a "dead layer" of non-ferroelectric phase crystal on the side of the electrode close to the ferroelectric layer 03, thereby improving the accuracy of reading and writing data in the ferroelectric memory.

[0145] Furthermore, it can reduce oxygen vacancies formed in the ferroelectric layer O3 due to oxygen ion movement, thereby improving the lifespan, durability, and accuracy of reading and writing data in the ferroelectric memory.

[0146] In some embodiments, see Figures 9-11 The material of the first electrode 01 includes at least one of TiN, TaN, TiAl, TiC, and TiSiC, and is also doped with an element whose valence state is greater than or equal to 5.

[0147] For example, the elements doped in the first electrode 01 include one or more of W, Mo, and Nb.

[0148] For example, the material of the first electrode 01 may include W-doped TiN, Mo-doped TiN, Nb-doped TiN, W-doped TaN, Mo-doped TaN, Nb-doped TaN, W-doped TiAl, Mo-doped TiAl, Nb-doped TiAl, W-doped TiC, Mo-doped TiC, Nb-doped TiC, W-doped TiSiC, Mo-doped TiSiC, Nb-doped TiSiC, etc.

[0149] See also Figures 9-11 The material of the second electrode 02 includes at least one of TiN, TaN, TiAl, TiC, and TiSiC, and is also doped with an element whose valence state is greater than or equal to 5.

[0150] For example, the elements doped in the second electrode O2 include one or more of W, Mo, and Nb.

[0151] For example, the material of the second electrode 02 may include W-doped TiN, Mo-doped TiN, Nb-doped TiN, W-doped TaN, Mo-doped TaN, Nb-doped TaN, W-doped TiAl, Mo-doped TiAl, Nb-doped TiAl, W-doped TiC, Mo-doped TiC, Nb-doped TiC, W-doped TiSiC, Mo-doped TiSiC, Nb-doped TiSiC, etc.

[0152] In the above embodiments, by doping the first electrode 01 and the second electrode 02 with elements having a valence state greater than or equal to 5, i.e., doping with elements with a higher valence state, the number of electrons in the first electrode 01 and the second electrode 02 can be increased, the concentration of anion vacancies in the electrodes can be reduced, the diffusion of oxygen ions from the ferroelectric layer 03 into the electrodes can be suppressed, and the diffusion of oxygen ions in the electrodes can be suppressed. This weakens the oxidation reaction between TiN, TaN, TiAl, TiC, TiSiC and oxygen ions, and avoids the formation of a "dead layer" of non-ferroelectric phase crystal on the side of the electrode close to the ferroelectric layer 03, thereby improving the accuracy of reading and writing data in the ferroelectric memory.

[0153] Furthermore, it can reduce oxygen vacancies formed in the ferroelectric layer O3 due to oxygen ion movement, thereby improving the lifespan, durability, and accuracy of reading and writing data in the ferroelectric memory.

[0154] Figures 12-14 This is a structural diagram of various ferroelectric capacitors according to some embodiments.

[0155] See Figure 12 The ferroelectric capacitor C also includes a third electrode 05, which is disposed on the side of the second electrode 02 away from the ferroelectric layer 03. The third electrode 05 and the second electrode 02 are connected in series to form the "top electrode" of the ferroelectric capacitor C.

[0156] See Figure 13 The third electrode 05 is disposed on the side of the first electrode 01 away from the ferroelectric layer 03, and the third electrode 05 and the first electrode 01 are connected in series to form the "bottom electrode" of the ferroelectric capacitor C.

[0157] See Figure 14 A third electrode 05 is disposed on the side of the second electrode 02 away from the ferroelectric layer 03, and another third electrode 05 is disposed on the side of the first electrode 01 away from the ferroelectric layer 03.

[0158] Specifically, the coefficient of thermal expansion of the third electrode 05 is different from that of the first electrode 01. Alternatively, the coefficient of thermal expansion of the third electrode 05 is different from that of the second electrode 02. Or, the coefficient of thermal expansion of the third electrode 05 is different from that of both the first electrode 01 and the second electrode 02.

[0159] It is understandable that the fabrication of the ferroelectric capacitor C needs to be carried out in a high-temperature environment. Since the thermal expansion coefficient of the third electrode 05 is different from that of the first electrode 01 and / or the second electrode 02, the volume expansion rate of the third electrode 05 is different from that of the first electrode 01 and / or the second electrode 02. Stress is generated in the ferroelectric capacitor C. This stress acts on the ferroelectric layer 03, causing lattice distortion in the non-ferroelectric phase crystals in the ferroelectric layer 03, resulting in polarization intensity. This can improve the distinction between the positive and negative polarization states of the ferroelectric film and improve the accuracy of reading and writing data in the ferroelectric memory.

[0160] The ferroelectric capacitor C provided in the embodiments of this application can have a two-dimensional planar structure, for example, see Figures 9-14 The first electrode 01 and the second electrode 02 are both planar electrodes. The first electrode 01, the ferroelectric layer 03, the protective layer 04 and the second electrode 02 are stacked. The structure of this ferroelectric capacitor C is simple and easy to manufacture.

[0161] For example, the memory cell 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 and the second electrode 02 of the ferroelectric capacitor C are both planar electrodes. In this case, one of the first electrode 01 and the second electrode 02 is electrically connected to the transistor T to form the memory cell 200.

[0162] Some embodiments of this application provide Figure 12 The method for preparing the ferroelectric capacitor C shown is as follows: Figures 15A to 15D The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments.

[0163] like Figure 15A As shown, the first electrode 01 is formed.

[0164] For example, during the formation of the first electrode 01, a metal element is doped, which is easily oxidized to form a dense metal oxide.

[0165] For example, the material of the first electrode 01 includes Al-doped TiN. In this case, atomic layer deposition (ALD) can be used to alternately deposit TiN and AlN to dope AlN in situ in TiN, forming an Al-doped TiN (TiAlN) thin film.

[0166] The atomic layer deposition process was carried out at a temperature of 400℃, with a deposition rate of [missing information]. In the first electrode 01, the atomic ratio of Al to Ti is less than 3 / 7.

[0167] like Figure 15B As shown, a ferroelectric layer 03 is formed.

[0168] For example, an atomic layer deposition process can be used to form a ferroelectric layer O3.

[0169] It is understandable that oxygen is introduced during the formation of the ferroelectric layer 03. The metal element in the first electrode 01 reacts with the oxygen element to form a metal oxide, resulting in a protective layer 04 located between the ferroelectric layer 03 and the first electrode 01. This protective layer 04 is very thin, for example, its thickness is less than 0.1 nm.

[0170] like Figure 15C As shown, the second electrode O2 is formed.

[0171] For example, during the formation of the second electrode O2, a metal element is doped, which is easily oxidized to form a dense metal oxide.

[0172] For example, the material of the second electrode O2 includes Al-doped TiN. In this case, an atomic layer deposition process can be used to alternately deposit TiN and AlN to dope AlN in situ in TiN, forming an Al-doped TiN (TiAlN) thin film.

[0173] The atomic layer deposition process was carried out at a temperature of 400℃, with a deposition rate of [missing information]. In the second electrode O2, the atomic ratio of Al to Ti is less than 3 / 7.

[0174] It is understandable that oxygen is introduced during the formation of the second electrode 02. The metal elements in the second electrode 02 react with the oxygen to form a metal oxide, resulting in a protective layer 04 located between the ferroelectric layer 03 and the second electrode 02. This protective layer 04 is very thin, for example, its thickness is less than 0.1 nm.

[0175] like Figure 15D As shown, the third electrode 05 is formed by atomic layer deposition, physical vapor deposition or chemical vapor deposition. The third electrode 05 is located on the side of the second electrode 02 away from the ferroelectric layer 03.

[0176] The preparation method provided in the above embodiments of this application sequentially forms a first electrode 01, a ferroelectric layer 03, and a second electrode 02. During the formation of the first electrode 01 and the second electrode 02, an easily oxidizable metal element is doped. The metal element undergoes an oxidation reaction to generate a dense metal oxide, thereby obtaining a protective layer 04 located between the ferroelectric layer 03 and the first electrode 01, and a protective layer 04 located between the ferroelectric layer 03 and the second electrode 02.

[0177] The protective layer 04 can inhibit the diffusion of oxygen ions from the ferroelectric layer 03 into the electrode, weaken the oxidation reaction between the electrode and oxygen ions, and reduce the oxygen vacancies formed in the ferroelectric layer 03 due to the movement of oxygen ions, thereby improving the service life, durability, and accuracy of reading and writing data of the ferroelectric memory.

[0178] Furthermore, in the above preparation methods, atomic layer deposition, physical vapor deposition, or chemical vapor deposition processes are used, which allows for precise control of the chemical composition and thickness of the film, good process compatibility, and no damage to the ferroelectric layer O3 (e.g., physical damage, corrosion, etc.), thus facilitating the preparation of ferroelectric memory with better performance and higher durability.

[0179] The ferroelectric capacitor C provided in the embodiments of this application can also have a three-dimensional vertical structure. Figure 16 This is a three-dimensional vertical structure diagram of a ferroelectric capacitor according to some embodiments.

[0180] See Figure 16 The first electrode 01 of the ferroelectric capacitor C is a planar electrode, and the second electrode 02 is a cylindrical electrode (the interior of the cylindrical electrode is hollow). The second electrode 02 penetrates the first electrode 01. The ferroelectric layer 03 and the protective layer 04 are arranged around the second electrode 02 to separate the first electrode 01 from the second electrode 02.

[0181] For example, the ferroelectric capacitor C also includes a third electrode 05, which is located inside the second electrode 02.

[0182] The ferroelectric capacitor C adopts the above-mentioned three-dimensional vertical structure design, which can reduce its occupied area in the XY plane, thereby increasing the number of ferroelectric capacitors C per unit area in the XY plane, so as to increase the number of storage units 200 per unit area, which is beneficial to improving the storage density of the ferroelectric memory.

[0183] For example, the memory cell 200 includes a ferroelectric capacitor C and a transistor T. The first electrode 01 of the ferroelectric capacitor C is a planar electrode and the second electrode 02 is a columnar electrode. In this case, the second electrode 02 is electrically connected to the transistor T, that is, the columnar electrode of the ferroelectric capacitor C is electrically connected to the transistor T to form the memory cell 200.

[0184] Some embodiments of this application provide Figure 16 The method for preparing the ferroelectric capacitor C shown is as follows: Figures 17A-17E The diagram shows the steps involved in preparing a ferroelectric capacitor according to some embodiments.

[0185] like Figure 17A As shown, a stacked layer D is formed, which includes alternating first electrodes 01 (planar electrodes) and a dielectric layer 06. The dielectric layer 06 can separate two adjacent first electrodes 01 along the Z direction to insulate between adjacent first electrodes 01.

[0186] like Figure 17BAs shown, a via H is formed that penetrates the stacked layer D, and the via H penetrates the first electrode 01 and the dielectric layer 06 in the stacked layer D.

[0187] like Figure 17C As shown, a ferroelectric layer 03 is formed on the sidewall of via H.

[0188] like Figure 17D As shown, a second electrode 02 is formed inside the ferroelectric layer 03.

[0189] For example, during the formation of the second electrode O2, a metal element is doped, which is easily oxidized to form a dense metal oxide.

[0190] For example, the material of the second electrode O2 includes Al-doped TiN. In this case, an atomic layer deposition process can be used to alternately deposit TiN and AlN to dope AlN in situ in TiN, forming an Al-doped TiN (TiAlN) thin film.

[0191] The atomic layer deposition process was carried out at a temperature of 400℃, with a deposition rate of [missing information]. In the second electrode O2, the atomic ratio of Al to Ti is less than 3 / 7.

[0192] It is understandable that oxygen is introduced during the formation of the second electrode 02. The metal elements in the second electrode 02 react with the oxygen to form metal oxides, resulting in a protective layer 04 located between the ferroelectric layer 03 and the second electrode 02.

[0193] like Figure 17E As shown, a third electrode 05 is formed inside the second electrode 02.

[0194] The above-described preparation method of this application forms a three-dimensional vertical ferroelectric capacitor C. During the formation of the second electrode 02, easily oxidizable metal elements are doped, thereby obtaining a protective layer 04 located between the ferroelectric layer 03 and the second electrode 02. The protective layer 04 can inhibit the diffusion of oxygen ions from the ferroelectric layer 03 into the electrode, weaken the oxidation reaction between the electrode and oxygen ions, and reduce oxygen vacancies formed in the ferroelectric layer 03 due to oxygen ion movement, thereby improving the service life, durability, and accuracy of data reading and writing of the ferroelectric memory.

[0195] Furthermore, in the above preparation methods, atomic layer deposition, physical vapor deposition, or chemical vapor deposition processes are used, which allows for precise control of the chemical composition and thickness of the film, good process compatibility, and no damage to the ferroelectric layer O3 (e.g., physical damage, corrosion, etc.), thus facilitating the preparation of ferroelectric memory with better performance and higher durability.

[0196] The memory and electronic device provided in some embodiments of this application, including the ferroelectric capacitor provided in any of the above embodiments, can achieve the same beneficial effects as the ferroelectric capacitor described above, and will not be repeated here.

[0197] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A ferroelectric memory array, characterized in that, It includes multiple memory cells arranged in an array, each memory cell comprising a ferroelectric capacitor and a transistor; The ferroelectric capacitor includes: The first and second electrodes are positioned relative to each other; A ferroelectric layer is disposed between the first electrode and the second electrode; At least one protective layer is disposed between the ferroelectric layer and the first electrode, and / or between the ferroelectric layer and the second electrode; along the thickness direction of the first electrode, the first electrode includes a portion facing the ferroelectric layer, the portion forming the protective layer, the material of the protective layer including a metal oxide, and the thickness of the protective layer being less than 0.1 nm.

2. The ferroelectric memory array according to claim 1, characterized in that, The material of the protective layer includes at least one of aluminum oxide and magnesium oxide.

3. The ferroelectric memory array according to claim 1 or 2, characterized in that, The thickness of the protective layer is less than the thickness of the first electrode; and / or, The thickness of the protective layer is less than the thickness of the second electrode.

4. The ferroelectric memory array according to any one of claims 1 to 3, characterized in that, The thickness of the protective layer is less than the thickness of the ferroelectric layer.

5. The ferroelectric memory array according to any one of claims 1 to 4, characterized in that, The material of the first electrode and / or the second electrode includes at least one of TiN and TaN, and also includes at least one of aluminum oxide and magnesium oxide.

6. The ferroelectric memory array according to any one of claims 1 to 4, characterized in that, The material of the first electrode and / or the second electrode includes TiN, and is also doped with at least one of Si, La, Ce, Y, Sc, and Sr.

7. The ferroelectric memory array according to any one of claims 1 to 4, characterized in that, The material of the first electrode and / or the second electrode includes at least one of TiN, TaN, TiAl, TiC, and TiSiC, and is also doped with an element whose valence state is greater than or equal to 5.

8. The ferroelectric memory array according to claim 7, characterized in that, The first electrode and / or the second electrode are doped with at least one of W, Mo, and Nb.

9. The ferroelectric memory array according to any one of claims 1 to 8, characterized in that, The ferroelectric capacitor further includes at least one third electrode disposed on the side of the second electrode away from the ferroelectric layer, and / or on the side of the first electrode away from the ferroelectric layer; The coefficient of thermal expansion of the third electrode is different from that of the first electrode and / or the second electrode.

10. The ferroelectric memory array according to any one of claims 1 to 9, characterized in that, The ferroelectric layer material includes at least one of HZO, La-doped HZO, Y-doped HZO, Sr-doped HZO, Gd-doped HZO, Gd and La co-doped HZO, Si-doped HfO2, Al-doped HfO2, La-doped HfO2, Y-doped HfO2, Gd-doped HfO2, and Sr-doped HfO2.

11. The ferroelectric memory array according to any one of claims 1 to 10, characterized in that, Both the first electrode and the second electrode are planar electrodes, and the first electrode, the ferroelectric layer, the protective layer and the second electrode are stacked.

12. The ferroelectric memory array according to any one of claims 1 to 10, characterized in that, The first electrode is a planar electrode, and the second electrode is a cylindrical electrode; The second electrode penetrates the first electrode, and the ferroelectric layer and the protective layer are disposed around the second electrode.

13. The ferroelectric memory array according to any one of claims 1 to 12, characterized in that, Both the first electrode and the second electrode are planar electrodes, and one of the first electrode and the second electrode is electrically connected to the transistor; or, The first electrode is a planar electrode, the second electrode is a cylindrical electrode, and the second electrode is electrically connected to the transistor.

14. A method for fabricating a ferroelectric memory array, characterized in that, include: The first electrode, the ferroelectric layer, and the second electrode are formed sequentially. The preparation method further includes: forming at least one protective layer; the at least one protective layer is disposed between the ferroelectric layer and the first electrode, and / or between the ferroelectric layer and the second electrode; The protective layer is made of metal oxide and has a thickness of less than 0.1 nm. During the formation of the first electrode, metal elements are doped; The metal elements in the first electrode undergo an oxidation reaction to form metal oxides, resulting in a protective layer located between the ferroelectric layer and the first electrode.

15. The preparation method according to claim 14, characterized in that, During the formation of the second electrode, metal elements are doped; The metal elements in the second electrode undergo an oxidation reaction to form metal oxides, resulting in a protective layer located between the ferroelectric layer and the second electrode.

16. The preparation method according to any one of claims 14-15, characterized in that, The material of the first electrode and / or the second electrode includes Al-doped TiN; The formation of the first electrode, and / or the formation of the second electrode, includes: TiN was deposited and AlN was in situ doped into the TiN; The ratio of Al to Ti atoms is less than 3 / 7.

17. The preparation method according to any one of claims 14 to 16, characterized in that, The sequential formation of the first electrode, the ferroelectric layer, and the second electrode includes: The first electrode, the ferroelectric layer, and the second electrode are formed in a stacked configuration.

18. The preparation method according to any one of claims 14 to 16, characterized in that, The sequential formation of the first electrode, the ferroelectric layer, and the second electrode includes: Form the first electrode; A via is formed that penetrates the first electrode; The ferroelectric layer is formed on the sidewall of the via; The second electrode is formed on the inner side of the ferroelectric layer.

19. A memory, characterized in that, include: Ferroelectric memory array as described in any one of claims 1 to 13; The controller is electrically connected to the ferroelectric storage array.

20. An electronic device, characterized in that, include: processor; The memory as described in claim 19 is electrically connected to the processor.

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