A random whitening enhanced PUF extraction system based on information sequence
The initial response and excitation of PUF are processed through a dynamic linear mapping structure, which solves the problem of insufficient number of excitation responses in weak PUF circuit systems, and realizes efficient utilization of FPGA board resources and reduces the difficulty of PUF deployment.
Patent Information
- Application Number
- CN202311428553.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-31
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2043-10-31
AI Technical Summary
In the existing weak PUF circuit systems and extraction methods, the excitation response is insufficient and the circuit resources consumed are high.
By using a dynamic linear mapping structure to obfuscate the initial response of the PUF and the excitation input of the upper computer, the number of excitation responses is increased and the small amount of excitation responses of weak PUFs is expanded.
The number of incentive responses has been greatly improved, the use of FPGA board resources has been reduced, and the deployment difficulty of PUF has been reduced.
Smart Images
Figure CN117806812B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of information security technology, and in particular to a random whitening enhanced PUF extraction system based on information sequence. Background Art
[0002] A physically unclonable function (PUF) is a function that inputs an excitation to a chip and outputs an unpredictable response function using the inevitable random process deviations in the chip manufacturing process. The PUF circuit is a hardware function implementation circuit that relies on chip characteristics. It has uniqueness and randomness. By extracting the process parameter deviations that are inevitably introduced during the chip manufacturing process, it realizes the function of the excitation signal and the response signal to uniquely correspond. Since the structure of the same type of PUF circuit is exactly the same, and the function of each PUF circuit is determined and unique after manufacturing, another significant feature of the PUF circuit is that it is unclonable. The above characteristics of the PUF circuit enable it to be used to build secure chips and defend against various attacks.
[0003] The existing weak PUF circuit system and extraction method extract an insufficient number of stimulus-response pairs from the weak PUF circuit and consume a high amount of circuit resources. Summary of the invention
[0004] To solve the above problems, the present invention provides a random whitening enhanced PUF extraction system based on information sequence, which confuses the initial response of the PUF and the stimulus input of the host computer to the FPGA board by utilizing a dynamic linear mapping structure, thereby greatly increasing the number of stimulus-response pairs and expanding a small number of stimulus-response pairs of weak PUF.
[0005] The present invention provides a random whitening enhanced PUF extraction system based on information sequence, and the specific technical scheme is as follows:
[0006] The system includes a host computer, a first interface module, a second interface module, a linear mapping module, a multiplexer module and a PUF unit module, wherein the linear mapping module includes an input mapping transformation module and an output mapping transformation module;
[0007] The output of the host computer is connected to the first interface module, the output of the first interface module is connected to the input mapping transformation module, and the excitation of the host computer is output to the dynamic input mapping transformation module through the first interface module;
[0008] The output of the input mapping transformation module is connected to the multiplexer module, and the input end of the multiplexer module is connected to the PUF unit module;
[0009] The output of the multiplexer module is connected to the output mapping transformation module, and the output mapping transformation module is connected to the input of the host computer through the second interface module, and the response after the dynamic random whitening enhancement processing of the output mapping transformation module is transmitted back to the host computer.
[0010] Furthermore, the multiplexer module includes at least one multiplexer, and the output of each multiplexer is connected to the input of the output mapping transformation module.
[0011] Furthermore, the multiplexer adopts a four-to-one structure multiplexer, including four input terminals, and each input terminal is correspondingly connected to one of the PUF units.
[0012] Furthermore, the linear mapping module is composed of a weight calculation module and a register module;
[0013] When the stimulus / response is different, the dynamic linear mapping module will process the stimulus / response differently;
[0014] The weight calculation module is used to output corresponding weight values for different input stimulus / response sequences, and the weight value is the number of times the register module is run.
[0015] Furthermore, the register module is composed of a plurality of registers cascaded with XOR gates, and the number of the registers is the same as the number of bits of the input stimulus.
[0016] Furthermore, the register module uses the longest linear feedback shift register sequence to generate a random sequence, and intercepts the sequence at a specific position through the weight calculation module and inputs it into the multiplexer module.
[0017] Furthermore, the operation structure of the linear feedback shift register is as follows:
[0018] S0=S1*g1⊙S2*g2⊙……⊙S n-2 *g n-2 ⊙S n-1 *g n-1 ⊙S n *g n
[0019] M0={S n-1 , S n-2 , S n-3 ,...,S3,S2,S1,S0}
[0020] Among them, {S1, S2, S3, ..., S n-1 , S n} is the initial value of n registers, {g1, g2, g3, ..., g n-1, g n} represents the tap selection of the register, the g value defined as the tap register is 1, and the rest are 0; S0 represents the value fed back to the end of the register group each time the linear feedback shift register runs, and M0 is the new sequence after the linear feedback shift register runs once.
[0021] Furthermore, the weight calculation process of the weight calculation module is as follows:
[0022] S1: After receiving n-bit stimulus data, the weight calculation module initializes the bit number parameter N=1 and the weight sum S=0;
[0023] S2: Determine whether the nth bit of the stimulus is 1. If it is 1, execute S=S+N, and iteratively increase the bit number parameter N by 1; otherwise, execute the next step;
[0024] S3: After looping through all the bits of the stimulus, the obtained weight and S as well as the n-bit stimulus data are transmitted to the register module.
[0025] Furthermore, the working process of the register module is as follows:
[0026] M1: After the n-bit stimulus data and S value are input into the register module, the n-bit data are stored in the n-bit register respectively;
[0027] M2: In each clock cycle, select a specific number of bits of data in the register for XOR, and shift the cascaded register data to the right. After the shift, the XOR value is stored in the leftmost register;
[0028] M3: Repeat step M2 according to the set first number of times, derive the data in all registers to obtain the excitation sequence, and input the n-bit excitation sequence to the selection terminals of the first n / 2 multiplexers;
[0029] M4: Repeat step M2 according to the set second number of times, export the data in all registers again to obtain a new excitation sequence, and input the n-bit excitation sequence to the selection ends of the next n / 2 multiplexers.
[0030] Furthermore, the first number is (n-1)*S, and the second number is S.
[0031] The beneficial effects of the present invention are as follows:
[0032] The present invention utilizes dynamic linear mapping transformation to process traditional weak PUF, solves the problem of insufficient stimulus-response pairs of traditional weak PUF, and increases the application scenarios of weak PUF. At the same time, based on the system structure of the present invention, a large number of stimulus-response pairs can be generated, which reduces the occupation of resources in the FPGA board card and the difficulty of PUF deployment compared with traditional strong PUF. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 It is a schematic diagram of the overall system architecture.
[0034] Figure 2 It is a schematic diagram of the architecture of the multiplexer module and the PUF unit module.
[0035] Figure 3 It is a schematic diagram of the register module architecture.
[0036] Figure 4 It is a schematic diagram of the execution flow of the weight calculation module. DETAILED DESCRIPTION
[0037] The following description clearly and completely describes the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0038] In the description of the embodiments of the present invention, it should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the invention product is usually placed when in use, or the orientation or positional relationship commonly understood by those skilled in the art, or the orientation or positional relationship in which the invention product is usually placed when in use, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0039] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0040] Example 1
[0041] Embodiment 1 of the present invention discloses a random whitening enhanced PUF extraction system based on information sequence, such as Figure 1 As shown, the details are as follows:
[0042] The system includes a host computer, a first interface module, a second interface module, a linear mapping module, a multiplexer module and a PUF unit module;
[0043] The first interface module and the second interface module are used for data exchange between the host computer and the FPGA board; specifically, the first interface module and the second interface module can use RS232 serial ports;
[0044] The linear mapping module, the multiplexer module and the PUF unit module are all integrated on the FPGA board.
[0045] The linear mapping module includes an input mapping transformation module and an output mapping transformation module;
[0046] The input mapping transformation module is used to process the stimulus sequence with small original differences, so as to enhance the randomness of the original sequence and expand the differences of the original sequence; the output mapping transformation module is used to increase the randomness of the response sequence.
[0047] In this embodiment, the linear mapping module is composed of a weight calculation module and a register module;
[0048] When the stimulus / response is different, the dynamic linear mapping module will process the stimulus / response differently.
[0049] The weight calculation module is used to output corresponding weight values for different input stimulus / response sequences, and the weight value is the number of times the register module is run.
[0050] In this embodiment, the register module is composed of 64 registers cascaded with XOR gates, and the number of the registers is the same as the number of bits of the input stimulus.
[0051] Specifically, the register module uses the longest linear feedback shift register sequence to generate a random sequence, and intercepts the sequence at a specific position through the weight calculation module and inputs it into the multiplexer module;
[0052] In this embodiment, the number of register bits selected is 64, 63, 61, and 60, and an XOR operation is performed on the values in these four-bit registers in each clock cycle.
[0053] Combination Figure 3 As shown, the operation structure of the linear feedback shift register is as follows:
[0054] S0=S1*g1⊙S2*g2⊙……⊙Sn-2 *g n-2 ⊙S n-1 *g n-1 ⊙S n *g n
[0055] M0={S n-1 , S n-2 , S n-3 ,...,S3,S2,S1,S0}
[0056] Among them, {S1, S2, S3, ..., S n-1 , S n} is the initial value of n registers, {g1, g2, g3, ..., g n-1 , g n} represents the tap selection of the register, the g value defined as the tap register is 1, and the rest are 0; S0 represents the value fed back to the end of the register group each time the linear feedback shift register runs, and M0 is the new sequence after the linear feedback shift register runs once.
[0057] The output of the host computer is connected to the first interface module, and the output of the first interface module is connected to the input mapping transformation module, and the excitation of the host computer is output to the dynamic input mapping transformation module through the first interface module;
[0058] The output of the input mapping transformation module is connected to the multiplexer module, and the input end of the multiplexer module is connected to the PUF unit module;
[0059] The output of the multiplexer module is connected to the output mapping transformation module, and the output mapping transformation module is connected to the input of the host computer through the second interface module, and the response after the dynamic random whitening enhancement processing of the output mapping transformation module is transmitted back to the host computer.
[0060] like Figure 2 As shown, in this embodiment, the multiplexer module includes at least one multiplexer, and the output of each of the multiplexers is connected to the input of the output mapping transformation module.
[0061] The multiplexer module is composed of n four-to-one multiplexers, each of which is composed of a 4-bit input terminal, a 1-bit output terminal, and a 2-bit selection terminal;
[0062] When the excitation signal received by the selection end of the multiplexer is 00, the PUF signal at the first input end of the multiplexer is output from the output port; when the excitation signal received by the selection end of the multiplexer is 01, the PUF signal at the second input end of the multiplexer is output from the output port; when the excitation signal received by the selection end of the multiplexer is 10, the PUF signal at the third input end of the multiplexer is output from the output port; when the excitation signal received by the selection end of the multiplexer is 11, the PUF signal at the fourth input end of the multiplexer is output from the output port.
[0063] In this embodiment, each input end of the multiplexer is correspondingly connected to one of the PUF units;
[0064] Specifically, the PUF unit module is used to generate an initial response, and the multiplexer module is composed of n*4 PUF units, wherein the PUF unit can be any weak PUF unit, including but not limited to butterfly PUF and SRAM PUF; the PUF units are independent of each other and will not affect each other.
[0065] Based on the register module structure of this embodiment, the working process of the system is described as follows:
[0066] First, the FPGA board is powered on and the PUF unit module generates an initial response;
[0067] The host computer inputs stimulus to the FPGA through the RS232 serial port, and dynamically inputs the stimulus input value to the mapping module through the serial port;
[0068] Combination Figure 4 As shown, 64-bit stimulus data is input into the weight calculation module, and the initialization bit number N=1 and the weight sum S=0;
[0069] Determine whether the nth bit of the stimulus is 1. If it is 1, execute S=S+N, and iteratively add 1 to the bit number parameter N, that is, execute N=N+1; if it is 0, keep the current weight and unchanged, and execute S=S, N=N+1;
[0070] The judgment logic of the previous step is repeated 64 times to obtain the weight and S, and the obtained weight and S and n bit stimulus data are transmitted to the register module.
[0071] After the 64-bit stimulus data and the S value are input into the register module, the 64-bit data are stored in the 64-bit registers respectively;
[0072] In each clock cycle, select the data of bits 64, 63, 61, and 60 in the register for XOR, and shift the cascaded register data to the right. After the shift, the XOR value is stored in the leftmost register.
[0073] Repeat the above register processing steps (n-1)*S times, that is, 63*S times, export the data in 64 registers to obtain the excitation sequence, and input the 64-bit excitation sequence to the selection end of the first 32 multiplexers;
[0074] Repeat the above register processing steps S times, export the data in the 64 registers again to obtain a new excitation sequence, and input the 64-bit excitation sequence to the selection end of the latter 32 multiplexers.
[0075] The present invention is not limited to the above-mentioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.
Claims
1. A random whitening enhanced PUF extraction system based on information sequence, characterized in that: The system includes a host computer, a first interface module, a second interface module, a linear mapping module, a multiplexer module and a PUF unit module, wherein the linear mapping module includes an input mapping transformation module and an output mapping transformation module; The linear mapping module is composed of a weight calculation module and a register module; when the stimulus / response is different, the linear mapping module will process the stimulus / response differently; The weight calculation module is used to output corresponding weight values for different input stimulus / response sequences, and the weight value is the number of times the register module is run; The output of the host computer is connected to the first interface module, the output of the first interface module is connected to the input mapping transformation module, and the stimulus of the host computer is output to the input mapping transformation module through the first interface module; The output of the input mapping transformation module is connected to the multiplexer module, and the input end of the multiplexer module is connected to the PUF unit module; The output of the multiplexer module is connected to the output mapping transformation module, and the output mapping transformation module is connected to the input of the host computer through the second interface module, and transmits the response after the random whitening enhancement processing of the output mapping transformation module back to the host computer.
2. The random whitening enhanced PUF extraction system based on information sequence according to claim 1 is characterized in that: The multiplexer module includes at least one multiplexer, and the output of each multiplexer is connected to the input of the output mapping transformation module.
3. The random whitening enhanced PUF extraction system based on information sequence according to claim 2 is characterized in that: The multiplexer adopts a four-to-one structure multiplexer, including four input terminals, and each input terminal is correspondingly connected to one of the PUF units.
4. The random whitening enhanced PUF extraction system based on information sequence according to claim 1 is characterized in that: The register module is composed of a plurality of registers cascaded with XOR gates, and the number of the registers is the same as the number of bits of the input stimulus.
5. The random whitening enhanced PUF extraction system based on information sequence according to claim 4 is characterized in that: The register module uses a linear feedback shift register sequence to generate a random sequence, and the sequence is intercepted by the weight calculation module and input to the multiplexer module.
6. The random whitening enhanced PUF extraction system based on information sequence according to claim 5 is characterized in that: The operation structure of the linear feedback shift register is as follows: S0=S1*g1⊙S2*g2⊙……⊙S n-2 *g n-2 ⊙S n-1 *g n-1 ⊙S n *g n M0={S n-1 ,S n-2 ,S n-3 ,……,S3,S2,S1,S0} Among them, {S1,S2,S3,……,S n-1 ,S n } is the initial value of n registers, {g1,g2,g3,……,g n-1 ,g n } represents the tap selection of the register, the g value defined as the tap register is 1, and the rest are 0; S0 represents the value fed back to the end of the register group each time the linear feedback shift register runs, and M0 is the new sequence after the linear feedback shift register runs once.
7. The random whitening enhanced PUF extraction system based on information sequence according to any one of claims 1 to 6, characterized in that: The weight calculation process of the weight calculation module is as follows: S1: After receiving n-bit stimulus data, the weight calculation module initializes the bit number parameter N=1 and the weight sum S=0; S2: Determine whether the nth bit of the stimulus is 1. If it is 1, execute S=S+N, and iteratively increase the bit number parameter N by 1; otherwise, execute the next step; S3: After looping through all the bits of the stimulus, the obtained weight and S as well as the n-bit stimulus data are transmitted to the register module.
8. The random whitening enhanced PUF extraction system based on information sequence according to claim 7 is characterized in that: The working process of the register module is as follows: M1: After the n-bit stimulus data and S value are input into the register module, the n-bit data are stored in the n-bit register respectively; M2: In each clock cycle, select the data of the set number of bits in the register for XOR, and shift the cascaded register data to the right. After the shift, the XOR value is stored in the leftmost register; M3: Repeat step M2 according to the set first number of times, derive the data in all registers to obtain the excitation sequence, and input the n-bit excitation sequence to the selection terminals of the first n / 2 multiplexers; M4: Repeat step M2 according to the set second number of times, export the data in all registers again to obtain a new excitation sequence, and input the n-bit excitation sequence to the selection ends of the next n / 2 multiplexers.
9. The random whitening enhanced PUF extraction system based on information sequence according to claim 8, characterized in that: The first number is (n-1)*S, and the second number is S.
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