Method of operation for visible-infrared image capture with an imaging system

Abstract

This application relates to a method of operation for visible-infrared image capture with an imaging system. A method of operating an imaging system is described. The method includes transferring first image charges accumulated during a long exposure period of a first image frame to respective floating diffusion regions of a first pixel and a second pixel, reading out long exposure image signals from the respective floating diffusion regions to a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel, transferring second image charges accumulated during a short exposure period of the first image frame to the respective floating diffusion regions of the first pixel and the second pixel, reading out short exposure image signals from a corresponding one of the floating diffusion regions to the second storage capacitor, and reading out storage charge signals from the first storage capacitor and the second storage capacitor to generate image data for the first image frame.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to CMOS image sensors and their applications. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of sub-devices, it is desirable to enhance the functionality, performance metrics, etc. of the image sensors in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through device architecture design as well as image acquisition processing.

[0003] A typical image sensor operates in response to image light reflected from an external scene incident on the image sensor. The image sensor includes an array of pixels having a photosensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and generates image charge upon absorption of the image light. The image charge photo-generated by a pixel can be measured as an analog output image signal on a column bitline that varies in accordance with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bitline as an analog image signal and converted to a digital value to produce a digital image (i.e., image data) representative of the external scene. SUMMARY

[0004] Embodiments of the present disclosure provide a method of operating an imaging system, the method comprising: transferring first image charge accumulated during a long exposure period of a first image frame to respective floating diffusion regions of a first pixel and a second pixel; reading out a long exposure image signal from the respective floating diffusion regions to a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel; transferring second image charge accumulated during a short exposure period of the first image frame to the respective floating diffusion regions of the first pixel and the second pixel; reading out a short exposure image signal from a corresponding one of the floating diffusion regions to the second storage capacitor; and reading out a storage charge signal from the first storage capacitor and the second storage capacitor to produce image data of the first image frame, wherein the image data is based on a corresponding one of the long exposure image signal associated with the first pixel and the short exposure image signal associated with the second pixel.

[0005] Another embodiment of the disclosure provides an imaging system comprising: an image sensor including a plurality of pixels arranged in a number of rows and a number of columns, wherein the plurality of pixels includes a first pixel and a second pixel each located within a first row included in the rows; a controller coupled to the image sensor, the controller including logic storing instructions that, when executed by the controller, cause the imaging system to perform operations comprising: transferring first image charges accumulated during a long exposure period of a first image frame to respective floating diffusion regions of the first pixel and the second pixel; reading out a long exposure image signal from the respective floating diffusion regions to a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel; transferring second image charges accumulated during a short exposure period of the first image frame to the respective floating diffusion regions of the first pixel and the second pixel; reading out a short exposure image signal from a corresponding one of the floating diffusion regions to the second storage capacitor; and reading out storage charge signals from the first storage capacitor and the second storage capacitor to generate image data for the first image frame, wherein the image data is based on a corresponding one of the long exposure image signal associated with the first pixel and the short exposure image signal associated with the second pixel. BRIEF DESCRIPTION OF DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein the like reference numerals refer to like elements unless otherwise specified. The drawings are in simplified form and are not drawn to precise scale. In some instances, details that are not directly related to the present disclosure have been omitted so as not to unnecessarily obscure the present disclosure.

[0007] Figure 1A An example imaging system including a sensor die and a logic die providing selective readout for visible-infrared image capture is illustrated in accordance with the teachings of this disclosure.

[0008] Figure 1B A cross-sectional view of a sensor die included in an imaging system in accordance with the teachings of this disclosure is illustrated. Figure 1A

[0009] Figure 1C A top view of a sensor die included in an imaging system in accordance with the teachings of this disclosure is illustrated. Figure 1A

[0010] Figure 1D An example pixel circuit for an individual pixel included in an imaging system illustrated in Figure 1A

[0011] An example pixel circuit for an individual pixel included in an imaging system illustrated in​​ Figure 1E FIG. illustrates an example pixel control line arrangement for a sensor die in accordance with the teachings of this disclosure. Figure 1A FIG. illustrates an example pixel control line arrangement for a sensor die in accordance with the teachings of this disclosure.

[0012] Figure 1F FIG. illustrates an example pixel control line arrangement for a logic die in accordance with the teachings of this disclosure. Figure 1A FIG. illustrates an example pixel control line arrangement for a sensor die in accordance with the teachings of this disclosure.

[0013] Figure 2A FIG. illustrates an example timing diagram for capturing visible-infrared image frames via selective readout during long and short exposure periods in accordance with the teachings of this disclosure.

[0014] Figure 2B FIG. illustrates an example timing diagram for capturing visible-infrared image frames via selective readout during short and long exposure periods in accordance with the teachings of this disclosure.

[0015] Figure 3A FIG. illustrates an example pixel cell circuit diagram for a sensor die in accordance with the teachings of this disclosure.

[0016] Figure 3B FIG. illustrates an example pixel cell circuit diagram for a logic die in accordance with the teachings of this disclosure.

[0017] Figures 3C to 3D FIG. illustrates an example timing diagram for capturing visible-infrared image frames via selective readout during long and short exposure periods in accordance with the teachings of this disclosure.

[0018] Figure 4 FIG. illustrates an example pixel control line arrangement for a logic die in accordance with the teachings of this disclosure.

[0019] Figure 5A FIG. illustrates an example pixel circuit for an imaging system in accordance with the teachings of this disclosure.

[0020] Figure 5B FIG. illustrates an example pixel control line arrangement for a sensor die in accordance with the teachings of this disclosure. Figure 5A FIG. illustrates an example pixel control line arrangement for a sensor die in accordance with the teachings of this disclosure.

[0021] Figure 5C FIG. illustrates an example pixel control line arrangement for a logic die in accordance with the teachings of this disclosure. Figure 5A FIG. illustrates an example pixel control line arrangement for a logic die in accordance with the teachings of this disclosure.

[0022] Figure 5D FIG. illustrates an example timing diagram for capturing image frames representing an external scene via selective readout during long and short exposure periods of the image frames in accordance with the teachings of this disclosure.

[0023] Figure 6 FIG. illustrates a block diagram of an imaging system that can selectively read out for visible-infrared image capture in accordance with the teachings of this disclosure. DETAILED DESCRIPTION

[0024] Embodiments of apparatuses, systems, and methods each related to image sensors that can selectively read out for visible-infrared image capture are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the specific aspects.

[0025] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0026] Throughout this specification, several technical terms are used. Such terms are to take on their ordinary meaning in the art unless otherwise specifically defined herein or the context of their use clearly dictates otherwise. It should be noted that throughout this document, element names and symbols can be used interchangeably (e.g., Si for silicon); however, both have the same meaning.

[0027] Embodiments of imaging systems that can selectively read out for visible-infrared image capture and methods thereof are described herein. In some embodiments, individual image sensors, which can have a stacked chip approach, are used to capture visible images (e.g., color) and non-visible images (e.g., near-infrared, infrared, short-wave infrared, far-infrared, or other frequency ranges outside the visible spectrum of electromagnetic radiation) of an external scene. This can be accomplished, at least in part, by an image sensor architecture that provides selective readout to storage nodes of the image sensor. Specifically, image frames can be captured using a plurality of exposure periods, including a long exposure period associated with visible image light and a short exposure period associated with non-visible image light (e.g., near-infrared, infrared, short-wave infrared, far-infrared, or other frequency ranges outside the visible spectrum of electromagnetic radiation). In some embodiments, storage control lines associated with storage nodes can be configured to provide independent readout to the storage nodes even when individual storage nodes are associated with a common row, such that each image frame captured by the image sensor can include image data associated with both the long exposure period and the short exposure period.

[0028] Advantageously, when capturing a given image frame with an image sensor or imaging system in conjunction with selective readout to a storage node, the long and short exposure periods allow for a reduction in cross-talk between visible and non-visible image data. In some embodiments, the duration of the short exposure period can be tailored based on the time taken for the non-visible light source to illuminate the external scene (or more specifically, the total time for the non-visible light to illuminate the external scene and reflect back onto the image sensor or imaging system), which can then be used to increase the duration of the long exposure period. In other words, the duration ratio of the long exposure period relative to the short exposure period can be increased to avoid sacrificing the sensitivity of the visible image data while maintaining a sufficient duration of the short exposure period to produce non-visible image data. It should be appreciated that the non-visible image data can be used to produce an illuminated image that does not interfere with the human eye or vision, a depth map of the external scene, and / or determine a distance of one or more pixels from the external scene. Thus, by reducing the duration of the short exposure period, the effect of ambient light on the non-visible image data can be reduced or otherwise mitigated. Still further, the increased ratio between the long and short exposure periods mitigates the blurring of flicker present in the external scene. This is particularly useful during video capture where image frames are captured consecutively and the non-visible image of the external scene is desired for each of the image frames.

[0029] While most of the embodiments described herein are discussed in the context of capturing image frames that include visible and non-visible image data, it should be appreciated that other embodiments can capture image frames with only visible image data and / or only non-visible image data over multiple exposure periods. In particular, the particular embodiments described herein can be used to capture a high dynamic range of visible or non-visible images using multiple exposure periods.

[0030] Figure 1A An example imaging system 100 including a sensor die 101 and a logic die 151 that provide for selective readout for visible-infrared image capture in accordance with the teachings of this disclosure is illustrated. The sensor die 101 includes a plurality of pixels 105, drivers 111, and an input / output (I / O) interface 109. The logic die 151 includes pixel circuitry 153, column circuitry 155, a v-scan 157, an I / O interface 159, and control circuitry 161. In the illustrated embodiment, the imaging system 100 includes a stacked complementary metal-oxide-semiconductor (CMOS) image sensor formed at least in part by the sensor die 101 (e.g., a first die) and the logic die 151 (e.g., a second die) stacked and coupled together (e.g., electrically and / or physically) in a stacked-chip arrangement. It should be appreciated that while the illustrated embodiment includes a stacked-chip arrangement, other embodiments can include a monolithic CMOS image sensor formed on a single die. In the illustrated embodiment, the sensor die 101 includes a plurality of pixels 105, drivers 111, and an I / O interface 109. The logic die 151 includes pixel circuitry 153, column circuitry 155, a v-scan 157, an I / O interface 159, and control circuitry 161. In the illustrated embodiment, the sensor die 101 and the logic die 151 are stacked in a stacked-chip arrangement. In other embodiments, the sensor die 101 and the logic die 151 can be formed on a single die. Figure 1AThe sensor die 101 and the logic die 151 are illustrated in the middle, but the stacked chip approach of the imaging system 100 can include additional dies that can be integrated into the stacked chip approach. Additionally, it should be appreciated that Figure 1A The views presented in the middle can omit particular elements of the imaging system 100 to avoid obscuring details of the disclosure (e.g., as Figure 6 The light source illustrated in the middle that emits electromagnetic radiation toward an external scene, Figure 6 Other components illustrated in the middle and / or other components not explicitly illustrated). In other words, not all elements of the imaging system 100 can be labeled, illustrated, or otherwise shown within Figure 1A It is further appreciated that, in some embodiments, the imaging system 100 can not necessarily include all of the elements shown.

[0031] Figure 1A The stacked chip approach illustrated in the middle distributes components of the imaging system 100 across multiple dies. Specifically, the sensor die 101 includes light-sensitive elements (e.g., photodiodes, pinned photodiodes, etc.) included in the plurality of pixels 105, while the logic die 151 includes pixel circuitry 153 associated with the plurality of pixels 105 (see, e.g., Figure 1D In other words, the logic die 151 offloads at least a portion of the circuitry associated with the plurality of pixels 105 of the sensor die 101, which advantageously provides additional space on the sensor die 101. The plurality of pixels 105 can be coupled to the pixel circuitry 153 through one or more hybrid bonds, through-silicon vias, combinations thereof, or other suitable circuit coupling techniques. In some embodiments, the space saved on the sensor die 101 by offloading circuitry to the logic die 151 can be repurposed to increase the size of individual photodiodes included in the plurality of pixels 105 to allow for increased pixel size, density, sensitivity, combinations thereof, and the like. Additionally or alternatively, functionality of the imaging system 100 can be facilitated because the logic die 151 can have space for additional components or circuitry that can not otherwise fit on an individual die or substrate containing both the plurality of pixels 105 and the pixel circuitry 153 without affecting performance and / or functionality of the imaging system 100.

[0032] In the illustrated embodiment, imaging system 100 includes a sensor wafer 101 and a logic wafer 151 coupled to sensor wafer 101. Sensor wafer 101 includes a plurality of pixels 105 including individual pixels arranged in a number of rows (e.g., R1, R2, R3,... RY) and a number of columns (e.g., C1, C2, C3,... CX) to form a pixel array. The plurality of pixels 105 can include any number of pixels, including at least a first pixel and a second pixel. In the same or other embodiments, the plurality of pixels 105 can further include a third pixel and a fourth pixel. Collectively, the first pixel, the second pixel, the third pixel, and the fourth pixel can form a minimum repeating unit of sensor wafer 101, or more specifically, the plurality of pixels 105. In some embodiments, the first pixel and the second pixel share a first common row (e.g., each of the first pixel and the second pixel can be arranged in a respective one of a number of rows, such as R1, R2, R3, or any other of the rows included therein). In the same or other embodiments, the third pixel and the fourth pixel share a second common row different from the first common row (e.g., each of the third pixel and the fourth pixel can be arranged in a respective one of a number of rows, such as R1, R2, R3, or any other of the rows included therein other than the first common row). In some embodiments, the first pixel and the second pixel are adjacent such that there are no intervening pixels between the first pixel and the second pixel along the first common row. In the same or other embodiments, the third pixel and the fourth pixel are adjacent such that there are no intervening pixels between the third pixel and the fourth pixel along the second common row. In the same or other embodiments, the first common row and the second common row are adjacent such that there are no intervening rows in the rows between the first common row and the second common row.

[0033] As discussed above, each given pixel included in the plurality of pixels 105 can include a single or multiple photosensitive elements (e.g., one or more photodiodes) configured to generate a response to incident light (e.g., accumulate photo-generated image charges), which can be transferred to a corresponding floating diffusion region associated with the given pixel. In some embodiments, the plurality of pixels 105 of the sensor die 101 are operated in response to a global shutter signal. In other words, in response to the global shutter signal, accumulated image charges can be transferred from respective photodiode regions included in the plurality of pixels 105 to corresponding floating diffusion regions. In some embodiments, the pixel circuitry 153 includes a plurality of storage nodes (e.g., one or more reset storage capacitors and one or more storage capacitors to read out the levels of the floating diffusion regions after reset and photo-carrier accumulation, respectively) each associated with one or more pixels included in the plurality of pixels 105. In some embodiments, the plurality of storage nodes are configured to store image signal levels and reset signal levels for each of the plurality of pixels 105, respectively. In some embodiments, the logic die 151 can operate on a row-by-row basis. In other words, image data can be generated based on the plurality of storage nodes of the logic die 151 read out on a row-by-row basis, as opposed to being read out simultaneously from the global shutter signal of the sensor die 101. It should be appreciated that, in some embodiments, the pixel circuitry 153 is configured to provide selective readout from the plurality of storage nodes, facilitating capturing image frames for multiple exposure periods. Advantageously, this approach allows for the benefits of global shuttering (e.g., mitigated rolling shutter artifacts) while still maintaining the low noise benefits facilitated by row-by-row readout from the plurality of storage nodes.

[0034] As Figure 1A illustrated in FIG. 1, the sensor die 101 and the logic die 151 include various analog and / or digital support circuitry for the imaging system 100. In some embodiments, the support circuitry includes, but is not limited to, row and column decoders and drivers (e.g., the drivers 111), analog signal processing chains, digital imaging processing blocks, memory, timing and control circuitry (e.g., the control circuitry 161), input / output (I / O) interfaces (e.g., the I / O interfaces 109 and 159), vertical scanners (e.g., the v-type scanner 157), sample-and-hold circuitry, amplifiers, analog-to-digital converter circuitry (e.g., the column circuitry 155), digital processors, and any other embodiments of logic circuitry suitable for the functionality of the imaging system 100.

[0035] Figure 1B illustrates a cross-sectional view 100-A of the sensor die 101 included in the imaging system 100 of Figure 1A FIG. 1, in accordance with the teachings of this disclosure. More specifically, the cross-sectional view 100-A is shown to include a plurality of pixels 105, a plurality of storage nodes 107, and a plurality of column circuitry 155, as described above. Figure 1AA portion of a cross-section of a row of pixels (e.g., a first row) included in a pixel array formed by the plurality of pixels 105 is illustrated in the middle. Referring back to Figure 1B The plurality of pixels 105 includes a plurality of photodiodes 104 formed in a semiconductor material 102 (e.g., a silicon wafer or substrate, a silicon-germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, any other alloy formed from a group III-V compound, other semiconductor materials or alloys, combinations thereof, or a bulk substrate, corresponding to or otherwise included in the sensor wafer 101), a plurality of color filters 106 (e.g., red, green, blue, infrared, clear, transparent, cyan, magenta, yellow, black, or any other color filter to filter visible or non-visible light that would otherwise be incident on an optically aligned photodiode included in the plurality of photodiodes 104), and a plurality of microlenses 108. In some embodiments, each pixel (e.g., the first pixel 105-1, the second pixel 105-2, or any other unlabeled individual pixel included in the plurality of pixels 105) includes an optically aligned stack of at least one of the plurality of photodiodes 104, at least one of the plurality of color filters 106, and at least one of the plurality of microlenses 108. As illustrated, the plurality of color filters 106 is disposed between the plurality of photodiodes 104 and the plurality of microlenses 108. It should be appreciated that view 100-A illustrates an individual row included in a pixel array formed by the plurality of pixels 105, each of which can have "N" elements. In other words, each of the number of rows can have N photodiodes included in the plurality of photodiodes 104, N color filters included in the plurality of color filters 106, and N microlenses included in the plurality of microlenses 108, where N corresponds to an integer greater than 2. Thus, photodiode 104-N, color filter 106-N, and microlens 108-N each correspond to the Nth element within the row illustrated in view 100-A. Thus, in the illustrated embodiment, there is a one-to-one correspondence between photodiodes included in the plurality of photodiodes 104, color filters included in the plurality of color filters 106, and microlenses included in the plurality of microlenses 108. However, in other embodiments, there can be a correspondence other than one-to-one. In one embodiment, an individual microlens can be optically aligned with (e.g., share) more than one color filter included in the plurality of color filters 106 and / or more than one photodiode included in the plurality of photodiodes 104.

[0036] In the illustrated embodiment, a first pixel 105-1 included in the plurality of pixels 105 includes a first photodiode 104-1 included in the plurality of photodiodes 104 disposed in the first portion 102-1 of the semiconductor material 102, a first color filter 106-1 (e.g., a blue color filter) included in the plurality of color filters 106, and a first microlens 108-1 included in the plurality of microlenses 108. As illustrated, the first photodiode 104-1, the first color filter 106-1, and the first microlens 108-1 are optically aligned with one another to form the first pixel 105-1. Adjacent to the first pixel 105-1 is a second pixel 105-2 (e.g., with no intervening pixels between the first pixel 105-1 and the second pixel 102-2), which includes a second photodiode 104-2 included in the plurality of photodiodes 104 disposed in the second portion 102-2 of the semiconductor material 102, a second color filter 106-2 (e.g., an infrared or "IR" filter) included in the plurality of color filters 106, and a second microlens 108-2 included in the plurality of microlenses 108. It should be appreciated that in some embodiments, the IR filter (e.g., the second color filter 106-2 included in the plurality of color filters 106 or any other IR filter) may correspond to a clear or transparent color filter that allows transmission of near-infrared, infrared, or far-infrared light (e.g., light having a wavelength between 800 nm and 3000 nm). Thus, it should be understood that in some embodiments, the IR filters included in the plurality of color filters 106 do not necessarily attenuate light within the visible range of the electromagnetic spectrum (e.g., approximately 300 nm to 800 nm). In other embodiments, the IR filters included in the plurality of color filters 106 attenuate incident light outside the infrared range of the electromagnetic spectrum (e.g., approximately 800 nm to 3000 nm) (e.g., via reflection, diffraction, absorption, or other means). It should be understood that color filters associated with the visible range of the electromagnetic spectrum (e.g., red, green, blue, or other) can attenuate incident light outside of the designated color (e.g., a blue color filter attenuates visible light outside the region of the visible range of the electromagnetic spectrum corresponding to blue, a green color filter attenuates visible light outside the region of the visible range of the electromagnetic spectrum corresponding to green, and so on).

[0037] As discussed above, Figure 1A The imaging system 100 illustrated in FIG. Figure 1BThe cross-sectional view 100-A illustrated in FIG. 1 A can not include all elements to avoid obscuring certain aspects of the disclosure. In some embodiments, the imaging system 100 can further include one or more doped semiconductor regions to form a plurality of photodiodes 104 (e.g., one or more photodiodes, pinned photodiodes, etc.), form isolation structures (e.g., shallow trench isolation structures disposed between adjacent photodiodes included in the plurality of photodiodes 104, deep trench isolation structures, etc.), metal grid structures (e.g., one or more metal structures disposed between adjacent color filters included in the plurality of color filters 106), an attenuation layer, an anti-reflective film, a filter, or other components in the semiconductor material 102.

[0038] Figure 1C FIG. 1 B illustrates a top view 100-B of a sensor wafer 101 included in an imaging system in accordance with the teachings of this disclosure. More specifically, the top view 100-B illustrates a pixel array formed by a plurality of pixels 105 illustrated in FIG. 1 A. Referring back to FIG. 1 A, the view 100-B illustrates the plurality of pixels 105 arranged in a number of rows (e.g., R1, R2, R3,... RY) and a number of columns (e.g., C1, C2, C3,... CY). The rows (e.g., R1, R2, R3, etc.) can be represented by the view 100-A illustrated in FIG. 1 A. For example, a cross-sectional view of the row “R2” illustrated in FIG. 1 A can correspond to the view 100-A illustrated in FIG. 1 A. Referring back to FIG. 1 A, the view 100-B illustrates the plurality of pixels 105 arranged in a number of columns (e.g., C1, C2, C3,... CY). The columns (e.g., C1, C2, C3, etc.) can be represented by the view 100-A illustrated in FIG. 1 A. For example, a cross-sectional view of the column “C2” illustrated in FIG. 1 A can correspond to the view 100-A illustrated in FIG. 1 A. Figure 1A Figure 1A Figure 1C Figure 1B Figure 1C Figure 1B Figure 1C Figure 1C Figure 1B Figure 1B ​​​​​​​​​In the illustrated embodiment, the first pixel (e.g., 105-B), the second pixel (e.g., 105-IR), the third pixel (e.g., 105-R), and the fourth pixel (e.g., 105-G) are adjacent to each other to form an image in the imaging system (e.g., Figure 1A 10. A first pixel cell (e.g., pixel cell 110) included in a plurality of pixel cells of the imaging system 100 illustrated in FIG. It should be appreciated that, in some embodiments, different color filters included in the plurality of color filters 106 (e.g., 106-B, 106-IR, 106-R, and / or 106-G) may have different spectral photoresponses to various wavelengths of light within the electromagnetic spectrum. In one embodiment, a second pixel (e.g., 105-IR) of a first pixel cell (e.g., pixel cell 110) is more sensitive to a first wavelength (e.g., one or more discrete wavelengths included in the infrared range of the electromagnetic spectrum, such as any wavelength between 800 nm and 3000 nm) than a first pixel (e.g., 105-B, 105-G, and / or 105-R). In other words, the second transmittance of the first wavelength through the corresponding color filter (e.g., IR color filter) included in the multiple color filters 106 of the second pixel is greater than the first transmittance of the first wavelength through the corresponding color filter (e.g., red, green and / or blue color filter) included in the multiple color filters 106 of the first pixel.

[0039] Figure 1D Illustrate a method for Figure 1A 1. More specifically, the example pixel circuit 150 of the individual pixel 105-N included in the plurality of pixels 105 of the imaging system illustrated in FIG. Figure 1DThe schematic diagram illustrated in FIG. illustrates pixel 105-N and associated pixel circuitry 153-N. For discussion purposes, the portion of circuitry included in pixel circuitry 153 that is associated with pixel 105-N and that is located in or on logic die 151 is referred to as pixel circuitry 153-N. However, it should be understood that in the illustrated embodiment, pixel 105-N also includes circuitry located on sensor die 101. Thus, as discussed in embodiments herein, the term "pixel" includes at least one photodiode included in a plurality of photodiodes and can further include circuitry, control lines, etc. associated with the at least one photodiode. In some embodiments, the at least one photodiode, circuitry, control lines are all located on or in a common substrate (e.g., sensor die 101). In the same or other embodiments, circuitry and control lines can be distributed across multiple substrates (e.g., sensor die 101 and logic die 151). Further, it should be understood that Figure 1D The circuit diagrams illustrated in FIG. are not necessarily meant to imply a particular physical location of elements within or on sensor die 101 and / or logic die 151.

[0040] As Figure 1D As illustrated in FIG., pixel 105-N includes photodiode 104-N (e.g., a pinned photodiode), transfer transistor TX including transfer gate 112, floating diffusion region 114, reset transistor RST1 including first reset gate 116, source follower transistor SF1, and select transistor SEL including select gate 118, each of which is disposed in, on, or otherwise included in sensor die 101. Pixel circuitry 153-N associated with pixel 105-N includes current source 122 including transistor CS and transistor CSW, second reset transistor RST2 including second reset gate 128, reset storage transistor SSW R , reset storage capacitor C R , storage transistor SSW S , storage capacitor C S , row select transistor RS including row select gate 134, and second source follower transistor SF2, each of which is disposed in, on, or otherwise included in logic die 151. As illustrated, reset storage transistor SSW R , reset storage gate 130, reset storage capacitor C R , storage transistor SSW S , storage gate 132, and storage capacitor C SA storage node 124 associated with the pixel 105-N is formed. Note that the sensor die 101 can be coupled to the logic die 151 on a per-pixel basis via a plurality of interconnects (hybrid pads, through-silicon vias, or other suitable circuit coupling technology) including the interconnect 120. In other words, each pixel (e.g., Figure 1A An individual pixel of the plurality of pixels 105 illustrated in FIG. 1A, such as the pixel 153-N illustrated in FIG. 1B, is individually coupled to associated pixel circuitry (e.g., Figure 1D A portion of the pixel circuitry 153 associated with an individual pixel of the plurality of pixels 105 illustrated in FIG. 1A, such as the pixel circuitry 153-N illustrated in FIG. 1B. The circuitry of the pixel 105-N included in the sensor die 101 is electrically coupled to the pixel circuitry 153-N via the interconnect 120. Figure 1D Figure 1A A portion of the pixel circuitry 153 associated with an individual pixel of the plurality of pixels 105 illustrated in FIG. 1A, such as the pixel circuitry 153-N illustrated in FIG. 1B. The circuitry of the pixel 105-N included in the sensor die 101 is electrically coupled to the pixel circuitry 153-N via the interconnect 120. Figure 1D

[0041] As illustrated, a transfer transistor TX is coupled between the photodiode 104-N and a floating diffusion region 114. The floating diffusion region 114 is coupled between the transfer transistor TX, a reset transistor RST1, and a source follower transistor SF1. The source follower transistor SF1 is coupled between the floating diffusion region 114 and a select transistor SEL. The floating diffusion region 114 is coupled to a gate of the source follower transistor SF1. The interconnect 120 is coupled between the floating diffusion region 114 and a storage node 124 (e.g., indirectly via the source follower transistor SF1 and the select transistor SEL). The storage node 124 is further coupled between the interconnect 120 and a second source follower transistor SF2. A reset storage transistor SSW R is coupled between the reset storage capacitor C R and the second reset transistor RST2. The storage capacitor SSW S is coupled between the storage capacitor C S and the second reset transistor RST2. The second source follower transistor SF2 is coupled between a row select transistor RS and the storage node 124. The row select transistor RS is coupled between a bit line and the storage node 124.

[0042] It should be appreciated that in the illustrated embodiment, each transistor (e.g., the transfer transistor TX, the reset transistor RST1, the select transistor SEL, the transistor CS, the transistor CSW, the reset storage transistor SSW R , the storage transistor SSW S ​​The gate terminals of transistors CS and row select transistor RS (e.g., transfer gate 112, first reset gate 116, select gate 118, second reset gate 128, the unlabeled gate of transistor CS, the unlabeled gate of transistor CSW, reset storage gate 130, storage gate 132, and row select gate 134) may be coupled to one or more control lines (e.g., see Figure 1E and Figure 1F ) for controlling the operation of the imaging system 100. Specifically, the control lines may be coupled to a controller, a control circuit system (e.g., see Figure 1A 1 ) or other circuitry not explicitly illustrated to control the operation of imaging system 100. In some embodiments, common elements along a common row can share control lines. In the same or other embodiments, specific elements can be configured with individual control lines to provide selective readout in accordance with embodiments of the present disclosure.

[0043] In some embodiments, the Figure 1A Each pixel in the plurality of pixels 105 illustrated in FIG. Figure 1D Thus, each pixel included in the plurality of pixels 105 is associated with a plurality of storage nodes (not illustrated but included in the Figure 1A ) are associated with individual storage nodes in the pixel circuitry 153 illustrated in FIG. Figure 1D 105-N). Thus, the logic die 151 includes a plurality of storage capacitors (e.g., a storage capacitor C for each pixel included in the plurality of pixels 105). S ), each storage capacitor is associated with a corresponding pixel in the plurality of pixels 105 of the sensor wafer 101. The plurality of storage capacitors includes a first storage capacitor associated with a first pixel and a second storage capacitor associated with a second pixel (e.g., the first storage capacitor and the second storage capacitor included in the plurality of storage capacitors are respectively associated with corresponding pixels included in the plurality of pixels 105 (e.g., Figure 1B Similarly, the logic die 151 includes a plurality of reset storage capacitors (eg, a reset storage capacitor C for each pixel included in the plurality of pixels 105). R ), each reset storage capacitor is associated with a corresponding pixel in the plurality of pixels 105 of the sensor wafer 101. The plurality of reset storage capacitors include a first pixel (eg, Figure 1B 1 and a first reset storage capacitor associated with a second pixel (eg, pixel 105-1 as illustrated in FIG. 1 ). Figure 1B A second reset storage capacitor is associated with pixel 105-2) illustrated in FIG.

[0044] During an operation of capturing a given image frame representing an external scene (e.g., a first image frame included in a plurality of image frames), in response to a transfer signal applied (e.g., asserted) to transfer gate 112 (e.g., via a transfer control line) to turn on transfer transistor TX, image charge accumulated by photodiode 104-N during an exposure period associated with the given image frame (e.g., a short exposure period, a long exposure period, or other) can be transferred to floating diffusion region 114. In some embodiments, the transfer signal can cause the image charge accumulated in each of the plurality of photodiodes 104 to be simultaneously transferred to a corresponding floating diffusion region associated with a plurality of pixels 105. Source follower transistor SF1 is coupled to photodiode 104-N to generate an image signal (e.g., a long exposure image signal, a short exposure image signal, or other, depending on the exposure period associated with the given image frame being read out) in response to the image charge accumulated by photodiode 104-N during the exposure period (e.g., a long exposure period, a short exposure period, or other exposure period). In the illustrated embodiment, the image signal is read out to storage node 124, or more specifically, via storage transistor SSW. S is read out to the corresponding storage capacitor C S In the same or other embodiments, reset transistor RST1 can be used to reset the charge in floating diffusion region 114 and, as appropriate, the charge in photodiode 104-N (e.g., to VDD or another suitable predetermined potential). During a reset period, a reset signal (e.g., a long exposure reset signal, a short exposure reset signal, or other, depending on the exposure period associated with a given image frame being read out) can be read out and stored on a corresponding reset storage capacitor C. R In some embodiments, for each pixel included in the plurality of pixels 105, a reset signal may be subtracted from the image signal (e.g., correlated double sampling) to generate image data corresponding to or otherwise representing an image frame. In the same or other embodiments, current source 122 in conjunction with reset transistor RST2 may be used to reset a capacitor (e.g., reset storage capacitor C R and / or storage capacitor C S ) is reset to a predetermined value. The image signal and reset signal can be read out to the column circuitry (e.g., via a row select signal applied to row select gate 134) on a row-by-row basis using row select transistors (e.g., via a row select signal applied to row select gate 134). Figure 1A 15) to generate image data. It should be appreciated that additional details related to the operation of imaging system 100 have been omitted, which will be discussed in more detail in subsequent sections.

[0045] Figure 1E Illustrate a method for Figure 1A 10. An example pixel control line arrangement 152 for a pixel cell (e.g., pixel cell 110) of the sensor wafer 101 illustrated in FIG. As previously discussed, the illustrated pixel cell 110 includes red (105-R), green (105-G), blue (105-B), and infrared (105-IR) pixels included in a plurality of pixels 105, each having a pixel control line arrangement 152 for a pixel cell (e.g., pixel cell 110) as shown in FIG. Figure 1D . As illustrated, blue pixel 105-B (e.g., first pixel) and infrared pixel 105-IR (e.g., second pixel) are disposed on row "n" (e.g., first row). Red pixel 105-R (e.g., third pixel) and green pixel 105-G (e.g., fourth pixel) are arranged on row "n+1" (e.g., second row), which is different from row "n". It should be understood that the first row and the second row are adjacent to each other (e.g., there are no intervening rows between the first row and the second row). Each pixel included in pixel unit 110 has its own corresponding circuitry instance on sensor wafer 101 (e.g., see Figure 1D ), which are controlled by corresponding control lines with appropriate tag names. Figure 1E As illustrated in the figure, the control line arrangement 152 includes a first reset control line RST1(n)154, a first transfer control line TX(n)156, a first selection control line SEL(n)158, a second reset control line RST1(n+1)160, a second transfer control line TX(n+1)162 and a second selection control line SEL(n+1)164. Figure 1E The general format of the control line names illustrated in indicates a coupled gate followed by the associated row. For example, the label "TX(n)" for control line TX(n) 156 indicates that control line TX(n) 156 may be coupled to the transfer gate of each pixel associated with row n (e.g., Figure 1D ), the label “RST1(n)” of the first reset control line RST1(n) 154 indicates that the first reset control line RST1(n) 154 may be coupled to the first reset gate of each pixel associated with row n (e.g., Figure 1D ). The connection nodes represented by black circles indicate connections to designated circuit elements associated with the corresponding pixels. For example, if at one or more pixels (e.g., Figure 1EA connection node is present on control line TX(n) 156 if the control line TX(n) 156 is coupled to the transfer gate of each of the one or more pixels (i.e., the transfer gate 112 of both pixels 105-B and 105-R). It should be appreciated that when a connection node is omitted for a corresponding control line as it passes through an associated pixel, then the corresponding control line is not coupled to the specified circuit element.

[0046] Thus, in the illustrated embodiment, a first reset control line RST1(n) 154 is electrically coupled to a first reset gate 116 of a reset transistor RST1 included in each of a first pixel 105-B and a second pixel 105-IR. A first transfer control line TX(n) 156 and a first select control line SEL(n) 158 are also located along row n (e.g., the first row), which are each coupled to a transfer transistor (e.g., Figure 1D (e.g., the transfer gate 112 of both pixels 105-B and 105-R) of the pixels 105-B and 105-IR included in row n (e.g., the first row). Figure 1D (e.g., the select gate 118 of both pixels 105-B and 105-R) of the pixels 105-B and 105-IR included in row n (e.g., the first row). Figure 1D (e.g., the select gate 118 of both pixels 105-B and 105-R) of the pixels 105-B and 105-IR included in row n (e.g., the first row). Figure 1D (e.g., the select gate 118 of both pixels 105-B and 105-R) of the pixels 105-B and 105-IR included in row n (e.g., the first row). Figure 1D (e.g., the transfer gate 112 of both pixels 105-B and 105-R) of the pixels 105-B and 105-IR included in row n (e.g., the first row).

[0047] Similarly, a row n+1 (e.g., the second row) including a third pixel 105-R, a fourth pixel 105-G, and optionally additional pixels (not illustrated) includes a second reset control line RST1 160(n+1), a second transfer control line TX(n+1) 162, and a second select control line SEL(n+1) 164, which are each coupled to respective gates (e.g., transfer gates, first reset gates, and select gates, such as the transfer gate 112, the first reset gate 116, and the select gate 118 illustrated in Figure 1E (e.g., the transfer gate 112, the first reset gate 116, and the select gate 118 illustrated in Figure 1D (e.g., the transfer gate 112, the first reset gate 116, and the select gate 118 illustrated in

[0048] In some embodiments, adjacent control lines included in each set of control lines associated with a given row (e.g., first reset control line RST1(n) 154, first transfer control line TX(n) 156, and first select control line SEL(n) 158, each associated with row n) may be separated from one another by a common separation distance (e.g., Figure 1E 166). In the same or other embodiments, the control lines of adjacent rows (e.g., row n and row n+1) may be symmetrical about axis 168 (e.g., a first sensor wafer control line group including first reset control line RST1(n) 154, first transfer control line TX(n) 156, and first select control line SEL(n) 158 for row n is symmetrical about axis 168 with a second sensor wafer control line group including second reset control line RST1(n+1) 160, second transfer control line TX(n+1) 162, and second select control line SEL(n+1) 164 for row n+1). It should be appreciated that in the illustrated embodiment, the connection nodes are aligned across a common column. However, in other embodiments, the connection nodes may not be aligned across a common column.

[0049] Figure 1F Illustrate a method for Figure 1A 1. Example pixel control line arrangement 172 of pixel circuitry (e.g., pixel circuitry 153-N) on logic die 151 associated with the pixel cell (e.g., pixel cell 110) illustrated in FIG. More specifically, Figure 1F The illustrated control lines supplement the Figure 1E , which is coupled to a control circuit system (e.g., Figure 1A , the control circuitry 161 illustrated in FIG), the column circuitry (eg, Figure 1A 155) and / or other circuitry to control the operation of a pixel cell (eg, pixel cell 110), or more specifically, to control Figure 1A 105 -B), and infrared (105 -IR) pixels. Each pixel included in pixel cell 110 has its own corresponding circuitry instance on sensor wafer 101 and logic wafer 151, as previously discussed. Figure 1D Therefore, refer back to Figure 1F, instances of pixel circuitry 153-N in pixel cell 110 are labeled 153-R, 153-G, 153-B, and 153-IR, respectively. Thus, for pixel cell 110, pixel circuitry 153-R of logic die 151 is associated with pixel 105-R of sensor die 101, pixel circuitry 153-G of logic die 151 is associated with pixel 105-G of sensor die 101, pixel circuitry 153-B of logic die 151 is associated with pixel 105-B, and pixel circuitry 153-IR is associated with pixel 105-IR.

[0050] like Figure 1F As illustrated in the figure, the control line arrangement 172 includes a first storage control line SSW_S(n) 174, a second storage control line SSW_IR_S(n) 178, a first reset storage control line SSW_R(n) 176, a second reset storage control line SSW_IR_R(n) 180, a second reset control line RST2(n) 182, a row selection control line RS(n) 184, a control line CSW(n) 186, and a control line CS(n) 188, each of which is associated with a row n (e.g., the first row). Similarly, for row n+1 (for example, the second row), there is a third storage control line SSW_S(n+1)175, a third reset storage line SSW_R(n+1)177, a control line SSW_IR_S(n+1)179, a control line SSW_IR_R(n+1)181, a second reset control line RST2(n+1)183, a row selection control line RS(n+1)185, a control line CSW(n+1)186 and a control line CS(n+1)189.

[0051] Figure 1F The general format of the control line names illustrated in the diagram is similar to Figure 1E , where the name indicates the coupled gate followed by the associated row. For example, the label "SSW_R(n)" for the first reset storage control line SSW_R(n) 176 indicates that the first reset storage control line SSW_R(n) 176 may be coupled to the reset storage gate of each pixel associated with row n (e.g., Figure 1D ), the label “SSW_S(n)” of the first storage control line SSW_S(n) 174 indicates that the first storage control line SSW_S(n) 174 may be coupled to the first storage gate of each pixel associated with row n (e.g., Figure 1D ) and so on. The connection nodes represented by black circles indicate connections to designated circuit elements associated with the corresponding pixels. For example, if at one or more pixels (e.g., Figure 1FThe presence of a connection node in the pixel circuitry of 153-B) illustrated in the middle on the first storage control line SSW S(n) 174, then the first storage control line SSW S(n) 174 is coupled to the storage gate included in the pixel circuitry of each of the one or more pixels. It will be appreciated that when a connection node is omitted from a corresponding control line as it passes through an associated pixel, then the corresponding control line is not coupled to the specified circuit element.

[0052] It will be appreciated that, Figure 1F The control line arrangement 172 illustrated in the middle is similar to the control line arrangement 152 illustrated in the middle, except that, Figure 1E One difference between the control line arrangement 152 illustrated in the middle and the control line arrangement 172 illustrated in the middle is that, Figure 1F Additional control lines are included to provide selective readout, facilitating operation to capture visible-infrared image frames with multiple exposure periods. Specifically, since infrared data from a short exposure period will be used in conjunction with color image data from a long exposure period to produce an image frame, visible pixels (e.g., 105-B) illustrated in the middle or other color pixels such as 105-G or 105-R in embodiments with different color filter arrangements, and non-visible pixels (e.g., 105-IR) illustrated in the middle) are included in the same row. Figure 1A Figure 1A The row containing both color pixels (e.g., 105-B) illustrated in the middle or other color pixels such as 105-G or 105-R in embodiments with different color filter arrangements, and non-visible pixels (e.g., 105-IR) illustrated in the middle) includes additional control lines to provide selective readout between color pixels and non-visible pixels (e.g., row n). To maintain control line symmetry and reduce or otherwise mitigate noise during readout, dummy control lines that are not coupled to any pixels are also included in rows that do not contain non-visible pixels (e.g., row n+1).

[0053] ​Thus, in the illustrated embodiment, the first reset storage control line SSW R(n) 176 is coupled to the reset storage gate included in the pixel circuitry of each visible pixel in row n (e.g., the pixel circuitry 153-B of pixel 105-B), while the second reset storage control line SSW IR R(n) 180 is coupled to the reset storage gate included in the pixel circuitry of each invisible pixel (e.g., the pixel circuitry 153-IR of pixel 105-IR). Similarly, the first storage control line SSW S(n) 174 is coupled to the storage gate included in the pixel circuitry of each visible pixel in row n (e.g., the pixel circuitry 153-B of pixel 105-B), while the second storage control line SSW IR S(n) 178 is coupled to the storage gate included in the pixel circuitry of each invisible pixel in row n (e.g., the pixel circuitry 153-IR of pixel 105-IR). Note that in the illustrated embodiment, row n+1 is not associated with any invisible pixels. Thus, the third storage control line SSW S(n+1) 175 and the third reset storage line SSW R(n+1) 177 are coupled to the storage gate and reset gate, respectively, included in the pixel circuitry of each visible pixel included in row n+1 (e.g., the pixel circuitry 153-R and 153-G). To maintain control line symmetry and mitigate noise during readout, there are control line SSW IR S(n+1) 179 and control line SSW IR R(n+1) 181 for row n+1, but not connected to the pixel circuitry of the pixels associated with row n+1, which is represented by the lack of a connection node along the control lines. In other words, control line SSW IR S(n+1) 179 and control line SSW IR R(n+1) 181 are dummy control lines. In particular, control line SSW IR S(n+1) 179 corresponds to a dummy storage control line and control line SSW IR R(n+1) 181 corresponds to a dummy reset storage control line.

[0054] The following details then describe the overall relationship between the control lines when viewed in the context of the pixel circuitry 153-B, 153-IR, 153-R, and 153-G, which are represented by different instances of the pixel circuitry 153-N as illustrated by Figure 1D Figure 1F The first storage control line SSW S(n) 174 is coupled to a first storage gate associated with a first pixel (e.g., the storage gate 132 included in the pixel circuitry 153-B associated with pixel 105-B). The first storage gate (e.g., the storage gate 132 included in the pixel circuitry 153-B) is included in a first storage capacitor (e.g., the storage capacitor C S ​) (eg, a first storage transistor SSW included in the pixel circuitry 153-B) S ). A second storage control line SSW_IR_S(n) 178 is coupled to a second storage gate associated with a second pixel (e.g., storage gate 132 included in pixel circuitry 153-IR associated with pixel 105-IR). The second storage gate (e.g., storage gate 132 included in pixel circuitry 153-IR) is included in a circuit coupled to a second storage capacitor (e.g., storage capacitor C included in pixel circuitry 153-IR). S ) (eg, a second storage transistor SSW included in the pixel circuitry 153-1R) S ). Figure 1F As illustrated in FIG. 1 , the first storage control line SSW_S(n) 174 is separated from the second storage control line SSW_IR_S(n) 178 to provide a first storage capacitor (eg, a storage capacitor C included in the pixel circuitry 153-B) with a charge. S ) or a second storage capacitor (eg, a storage capacitor C included in the pixel circuitry 153-1R) S ) provides selective readout. The logic die 151 further includes a third storage control line SSW_S(n+1) 175 coupled to a third storage gate associated with a third pixel (e.g., storage gate 132 included in pixel circuitry 153-R associated with pixel 105-R) and a fourth storage gate associated with a fourth pixel (e.g., storage gate 132 included in pixel circuitry 153-G associated with pixel 105-G). The third storage gate (e.g., storage gate 132 included in pixel circuitry 153-R) is included in a third storage capacitor (e.g., storage capacitor C included in pixel circuitry 153-R) coupled to the third storage gate associated with the third pixel (e.g., storage gate 132 included in pixel circuitry 153-R). S ) of a third storage transistor (eg, a storage transistor SSW included in the pixel circuit system 153-R) S ). A fourth storage gate (eg, storage gate 132 included in pixel circuitry 153-G) is included in a circuit coupled to a fourth storage capacitor (eg, storage capacitor C included in pixel circuitry 153-G). S ) of a fourth storage transistor (eg, storage transistor SSW included in pixel circuitry 153-G) S) near the third storage control line SSW S(n+1) 175. As illustrated, the dummy storage control line (e.g., control line SSW IR S(n+1) 179) is not connected to any gate, including the first, second, third, and fourth storage gates associated with the first, second, third, and fourth pixels. In Figure 1F In the illustrated embodiment, the dummy storage control line (e.g., control line SSW IR S(n+1) 179) is positioned to maintain control line symmetry of the logic die 151 such that a first separation distance 191 between the first storage control line SSW S(n) 174 and the second storage control line SSW IR S(n) 178 is equal to a second separation distance 193 between the third storage control line SSW S(n+1) 175 and the dummy storage control line (e.g., control line SSW IR S(n+1) 179).

[0055] It should be appreciated that a dummy control line (e.g., dummy storage control line SSW IR S(n+1) 179, dummy storage reset control line SSW IR R(n+1) 181, or other dummy control lines described in various embodiments of the present disclosure) can be biased to a predetermined value (e.g., a preset voltage level). In some embodiments, the predetermined value of the bias corresponds to a logic low (e.g., a ground or negative bias voltage, such as -1.4V) of one or more nearby control lines. In some embodiments, the predetermined value applied to the dummy control line corresponds to a logic low of a neighboring control line (i.e., not one of the dummy control lines). For example, the predetermined value of the bias applied to the dummy storage control line SSW IR S(n+1) 179 and / or the dummy storage reset control line SSW IR R(n+1) 181 can correspond to a logic low value of the control line SSW S(n+1) 175 and / or the third reset storage line SSW R(n+1) 177 to provide physical and electrical symmetry (e.g., when the active control line is at a logic low).

[0056] In the illustrated embodiment, the logic die 151 control lines of the pixel cell 110 further include a reset storage control line SSW R(n) 176 coupled to a first reset storage gate associated with the first pixel (e.g., a reset storage gate 130 included in the pixel circuitry 153-B associated with the pixel 105-B). The first reset storage gate (e.g., the reset storage gate 130 included in the pixel circuitry 153-B) is included in a first reset storage capacitor (e.g., the reset storage capacitor C R) (eg, a first reset storage transistor SSW included in the pixel circuit system 153-B) R ). A second reset storage control line SSW_IR_R(n) 180 is coupled to a second storage gate associated with a second pixel (e.g., reset storage gate 130 included in pixel circuitry 153-IR associated with pixel 105-IR). The second reset storage gate (e.g., reset storage gate 130 included in pixel circuitry 153-IR) is included in a second reset storage capacitor coupled to a second reset storage capacitor (e.g., reset storage capacitor C included in pixel circuitry 153-IR). R ) of a second storage transistor (eg, a reset storage transistor SSW included in the pixel circuitry 153-IR) R ). Figure 1F As illustrated in FIG. 1 , the first reset storage control line SSW_R(n) 176 is separated from the second reset storage control line SSW_IR_R(n) 180 to reset the first reset storage capacitor (eg, the reset storage capacitor C included in the pixel circuitry 153-B). R ) or a second reset storage capacitor (eg, a storage capacitor C included in the pixel circuitry 153-IR) R ) provides selective readout.

[0057] In the same or other embodiments, the control lines of logic die 151 associated with adjacent rows (e.g., row n and row n+1) can be symmetrical about axis 195 (e.g., the first logic die control line group including first storage control line SSW_S(n) 174, second storage control line SSW_IR_S(n) 178, first reset storage control line SSW_R(n) 176, and second reset storage control line SSW_IR_R(n+1) 180 of row n is symmetrical about axis 195 with the second logic die control line group including third storage control line SSW_S(n+1) 175, third reset storage line SSW_R(n+1) 177, control line SSW_IR_S(n+1) 179, and control line SSW_IR_R(n+1) 181 of row n+1). It should be understood that in the illustrated embodiment, the connection nodes are aligned across a common column. However, in other embodiments, the connection nodes may not be aligned across a common column.

[0058] Figure 1E The control line arrangement 152 and Figure 1F The control line arrangement 172 of FIG. 1 illustrates only an individual pixel cell 110, which may be one of many pixel cells included in a plurality of pixel cells (e.g., as shown in FIG. 1 ). Figure 1Aillustrated in FIG. 1). Thus, it should be appreciated that additional pixels and associated pixel circuitry can be included in row n and row n+1. In other words, in some embodiments of the disclosure, there can be more than two columns. Additionally, there can be additional rows above and / or below the pixel cells 110 (e.g., as illustrated in FIG. 2). Thus, the specific number of pixel cells, rows, and / or columns explicitly illustrated is not intended to be limiting and any number of pixel cells, rows, and / or columns can be included in various embodiments of the disclosure. Moreover, it should be appreciated that different color filter patterns or arrangements can be utilized (e.g., infrared pixels can be adjacent to any of red, green, or blue pixels or other visible pixels). However, in most embodiments, it should be appreciated that control line symmetry can be maintained to provide the advantages discussed herein. Figure 1A

[0059] Figure 2A illustrated in FIG. 1) according to the teachings of this disclosure. The method 200 can include blocks 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224, 226, and 228. It should be appreciated that several of the blocks of the method 200 including blocks 202-228 can occur in any order and even in parallel. Additionally, several blocks can be added to or removed from the method 200 according to the teachings of this disclosure. It should be appreciated that the method 200 represents one possible implementation for operating an imaging system (e.g., the imaging system 100 illustrated in FIG. 1) according to the teachings of this disclosure. Additionally, it should be appreciated that the method 200 is not limited to only operating the imaging system 100 illustrated in FIG. 1, but rather the method 200 can be applicable to operating other embodiments of imaging systems and / or image sensors. As Figures 1A to 1F Figures 1A to 1F Figure 2A

[0060] ​​​​During method 200, selective readout is utilized to capture image frames having multiple exposure periods. Specifically, a first image frame includes a long exposure period and a short exposure period. The duration of the short exposure period (i.e., the short exposure duration) is less than the duration of the long exposure period (i.e., the long exposure duration). In some embodiments, the short exposure period is configured to occur after the long exposure period. In some embodiments, the short exposure period is used to generate non-visible (e.g., near-infrared, infrared, or far-infrared) image data of an external or object scene, while the long exposure period is used to generate visible (e.g., red, green, blue, or other combinations representing the visible range of the electromagnetic spectrum) image data of the external scene.

[0061] Block 202 illustrates the start or initiation of method 200, wherein the capture of one or more image frames (e.g., one or more image frames imaging an external scene using visible and infrared image signals) having multiple exposure durations occurs. The initiation may occur in response to a user input (e.g., a user pressing or otherwise contacting a physical or virtual trigger), an event condition trigger (e.g., a vehicle shifting into reverse gear, a turn signal being activated), or otherwise.

[0062] Block 204 illustrates placing a plurality of photodiodes (e.g., Figures 1A to 1F The plurality of photodiodes 104 in the plurality of pixels 105 illustrated in FIG. 104 may be reset in response to a reset signal (e.g., for a plurality of photodiodes 104 in the plurality of pixels 105 illustrated in FIG. Figure 1A Each pixel in the plurality of pixels 105 of the imaging system 100 illustrated in FIG. Figure 1D The photodiodes are reset by assertion of a pulse (illustrated in FIG. 1 ) applied to the transfer gate 112 of the transfer transistor TX and the reset gate 116 of the reset transistor RST1. Appropriate signals cause charge to be placed across the plurality of photodiodes to provide a predetermined potential (e.g., Figure 1D VDD or other suitable predetermined potential as illustrated in FIG) and allows image charge to accumulate during long exposure periods. Figure 1E 1, RST1(n) 154, RST1(n+1) 160, TX(n) 156, and TX(n+1) 162 illustrated in FIG. 4A to apply a reset signal to turn on reset transistor RST1 and transfer transistor TX.

[0063] Block 206 illustrates the start of a long exposure period for an image frame. During the long exposure period, image charge is accumulated in the plurality of photodiodes in response to incident light from an external scene (e.g., from block 204). The accumulated image charge represents the external scene and has a magnitude based on the intensity of light incident on a given photodiode included in the plurality of photodiodes.

[0064] Block 208 illustrates the process of generating a pixel by performing a multi-pixel Figures 1A to 1F Each pixel included in the plurality of pixels 105 illustrated in FIG. 105 will have a corresponding floating diffusion region (eg, Figure 1D 14) is reset and a first floating diffusion reset of an image frame (eg, a first image frame) is performed, the plurality of pixels including a first pixel, a second pixel, a third pixel, and a fourth pixel (eg, Figures 1C to 1F The first floating diffusion reset may be performed by resetting the reset gate of each pixel included in the plurality of pixels (e.g., pixel 105-B, pixel 105-IR, pixel 105-R, and pixel 105-G). Figure 1D ) is asserted or otherwise pulsed, which in turn may activate (eg, turn on) a source follower transistor (eg, Figure 1D ) to allow for readout of a long exposure reset signal (eg, Figure 1D ). The reset level of the floating diffusion region 114 illustrated in FIG. 1 may be determined via an appropriate control line (e.g., Figure 1E 154 and RST1(n+1) 160) are pulsed to the reset gate of each pixel. Thus, in response to the first floating diffusion being reset and utilizing appropriate configuration (e.g., a select signal applied to select gate 118 to turn on select transistor SEL (e.g., a first select control line SEL(n) 158, a second select control line SEL(n+1) 164 to turn on the corresponding select transistor SEL)), the pixels from the corresponding floating diffusion region (e.g., Figure 1D 1) is read out to a reset storage capacitor associated with each of the plurality of pixels (e.g., a first reset storage capacitor associated with the first pixel, a second reset storage capacitor associated with the second pixel, a third reset storage capacitor associated with the third pixel, a fourth reset storage capacitor associated with the fourth pixel, etc.). In some embodiments, the reset storage capacitor is part of a storage node in pixel circuitry included on a logic die (e.g., included in a Figure 1D The reset storage capacitor C in the storage node 124 illustrated in FIG. R In some embodiments, the memory is reset by resetting the storage gate of each pixel included in the plurality of pixels (eg, Figure 1D The reset storage transistor SSW illustrated in FIG. Ron the reset storage gate 130) to facilitate readout of the long-exposure reset signal.

[0065] Block 210 illustrates transferring first image charges accumulated during a long-exposure period of an image frame (e.g., a first image frame) to respective floating diffusion regions of a plurality of pixels (e.g., floating diffusion regions 114 for each of a first pixel (e.g., 105-B), a second pixel (e.g., 105-IR), a third pixel (e.g., 105-R), a fourth pixel (e.g., 105-G), etc., as illustrated in FIG. 1). Figures 1C to 1F In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of a first pixel, a second pixel, a third pixel, a fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 as illustrated in FIG. 1) to transfer the first image charges accumulated during the long-exposure period (e.g., the first image charges accumulated during the long-exposure period of the first image frame can be transferred to respective floating diffusion regions of one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, etc.). Figure 1E In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of a first pixel, a second pixel, a third pixel, a fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 as illustrated in FIG. 1) to transfer the first image charges accumulated during the long-exposure period (e.g., the first image charges accumulated during the long-exposure period of the first image frame can be transferred to respective floating diffusion regions of one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, etc.). Figure 1D In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of a first pixel, a second pixel, a third pixel, a fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 as illustrated in FIG. 1) to transfer the first image charges accumulated during the long-exposure period (e.g., the first image charges accumulated during the long-exposure period of the first image frame can be transferred to respective floating diffusion regions of one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, etc.).

[0066] Block 212 shows reading out the long-exposure image signals from the respective floating diffusion regions to respective storage capacitors (e.g., a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel) included in storage nodes for each pixel included in the plurality of pixels (e.g., storage nodes 116 as illustrated in FIG. 1). Figure 1D S More specifically, upon transfer of the long-exposure image signals to the respective floating diffusion regions (e.g., floating diffusion regions 114 as illustrated in FIG. 1), corresponding source follower transistors (e.g., source follower transistors 118 as illustrated in FIG. 1) are enabled to facilitate readout of the long-exposure image signals. Figure 1D Figure 1D ​​The source follower transistor SF1 illustrated in FIG will then be turned on and with the appropriate configuration (eg, a select signal applied to select gate 118 to turn on select transistor SEL and applied to storage gate 132 to turn on storage transistor SSW S The storage control line signal, such as Figure 1D ), then the charge representing the magnitude of the charge stored in the corresponding floating diffusion region of the sensor die will be stored in the storage capacitor of the logic die. In some embodiments, separate control line signals (e.g., a first storage control line signal and a second storage control line signal) will be asserted or otherwise applied simultaneously to the appropriate storage control lines (e.g., a first storage control line SSW_S(n) 174 and a second storage control line SSW_IR_S(n) 178) to turn on the storage capacitors along a common row (e.g., Figures 1A to 1F 105 -B and the second pixel 105 -IR) are oriented with associated storage transistors of different pixels (eg, Figure 1D The storage transistor SSW illustrated in FIG. S In the same or other embodiments, individual storage line control signals will be asserted or otherwise applied to the appropriate control lines (e.g., Figure 1F 175), the appropriate control line is coupled to the storage cells along a common row (e.g., as shown in FIG. Figures 1A to 1F All pixels of the second row (including the third pixel 105-R and the fourth pixel 105-G) illustrated in FIG.

[0067] Block 214 illustrates starting a short exposure period for an image frame. In some embodiments, the short exposure period may begin in response to resetting the plurality of photodiodes. In other words, during block 214, the plurality of photodiodes may be reset (e.g., Figure 2A 204 ). The plurality of photodiodes may accumulate image charge representative of the external scene and having a magnitude based on the intensity of light incident on a given photodiode included in the plurality of photodiodes during a short exposure period.

[0068] Block 216 shows emitting a pulse of electromagnetic radiation of a first spectrum during a short exposure period of an image (e.g., a first image frame). The emission of the electromagnetic radiation of the first spectrum is synchronized with the short exposure period. It should be appreciated that, to mitigate crosstalk between the short exposure period of an image frame and the long exposure period of a subsequent image frame, the pulse duration of the pulse is less than the short exposure duration of the short exposure period of the image frame. In some embodiments, the pulse duration of the pulse is less than one-tenth the duration of the long exposure period, which can enable the capture of invisible images during the short exposure period while minimizing the impact on visible images captured during the long exposure period. The short exposure duration of the short exposure period can be configured based on the amount of time required to capture the electromagnetic radiation of the first spectrum reflected from an external scene. It should be appreciated that the electromagnetic radiation of the first spectrum includes a first wavelength, which can be within the infrared range of the electromagnetic spectrum (e.g., from the near infrared to the far infrared, such as 800 nm to 3000 nm). The electromagnetic radiation of the first spectrum can be generated by a light source, which can be a component external to the image sensor. During a short exposure period, the plurality of photodiodes accumulate image charges in response to pulses of electromagnetic radiation of the first spectrum reflected from one or more objects in an external scene and incident on the plurality of photodiodes. The image charges can be used to generate an illuminated image that does not interfere with the human eye (i.e., an invisible image based on pulses of electromagnetic radiation of the first spectrum outside the visible light range) and / or depth or distance information associated with the external scene (e.g., the distance or depth of one or more pixels included in the plurality of pixels from one or more objects included in the external scene). In some embodiments, time-of-flight information and / or phase difference information can be calculated based on the image charges accumulated during the short exposure period.

[0069] Block 218 illustrates the process of performing the multi-pixel Figures 1A to 1F Each pixel included in the plurality of pixels 105 illustrated in FIG. 105 will have a corresponding floating diffusion region (eg, Figure 1D 14) is reset and a second floating diffusion reset of an image frame (eg, a first image frame) is performed, the plurality of pixels including a first pixel, a second pixel, a third pixel, and a fourth pixel (eg, Figures 1C to 1F Pixel 105-B, pixel 105-IR, pixel 105-R, and pixel 105-G are illustrated in FIG.

[0070] In contrast to block 208 where the long exposure reset signal for each pixel is read out to an associated reset storage capacitor, in block 218 a selective readout is performed to store the long exposure reset signal associated with the visible pixels (e.g., Figure 1A 105 -B, 105 -R, and 105 -G of the pixel cell 110 illustrated in FIG, while the first portion of the long exposure reset signal is associated with the invisible pixels (eg, Figure 1AThe second portion associated with the pixel cell 110 illustrated in FIG. 1 15-IR) will be replaced with a corresponding short exposure reset signal. For example, in the case of the pixel cell 110 illustrated in FIG. Figures 1A to 1F In the case of the pixel cell 110 illustrated in FIG. 1 15-IR), in response to the second floating diffusion reset, a short exposure reset signal from a corresponding one of the floating diffusion regions (e.g., the floating diffusion region 114 of the pixel 105-IR) is read out to a second reset storage capacitor (e.g., the reset storage capacitor C R ) associated with the second pixel. This is accomplished, at least in part, by pulsing (i.e., asserting a signal to) the reset storage gate 130 of the reset storage transistor SSW R of the invisible pixel (e.g., the pixel 105-IR) to turn on the reset storage transistor SSW R of the invisible pixel while not turning on the reset storage transistor SSW R .

[0071] Block 220 shows transferring second image charge accumulated during a short exposure period of an image frame (e.g., a first image frame) to respective floating diffusion regions of a plurality of pixels (e.g., the floating diffusion region 114 for each of a first pixel (e.g., 105-B), a second pixel (e.g., 105-IR), a third pixel (e.g., 105-R), a fourth pixel (e.g., 105-G), etc., as illustrated in FIG. Figures 1C to 1F In some embodiments, a transfer control line signal (e.g., a first transfer control line signal) associated with the plurality of pixels (e.g., one or more of the first pixel, the second pixel, the third pixel, the fourth pixel, or others) is asserted (e.g., applied to TX(n) 156 and TX(n+1) 162 illustrated in FIG. Figure 1E In some embodiments, the transfer control line signal corresponds to a pulse applied to a transfer gate of each of the plurality of pixels (e.g., the transfer gate 112 of the transfer transistor TX as illustrated in FIG. Figure 1D In the same or other embodiments, the transfer control line signal is applied simultaneously to the transfer gate of each of the plurality of pixels. In some embodiments, the start of block 220 corresponds to the end of a short exposure period of an image frame being captured (e.g., the first image frame).

[0072] Block 222 illustrates selectively reading out the short exposure image signal from the corresponding floating diffusion region to the corresponding storage capacitor (eg, when the second pixel corresponds to a non-visible pixel (eg, Figure 1A 1-IR of the pixel unit 110 illustrated in , a second storage capacitor associated with the second pixel). More specifically, the short exposure image signal can be read out to the storage capacitor associated with each invisible pixel (e.g., an infrared pixel) to overwrite or otherwise replace the previously stored long exposure image signal (e.g., see box 212). In contrast, the long exposure image signal associated with the visible pixels included in the plurality of pixels is not replaced or otherwise read out to the associated storage capacitor included in the visible pixels. In some embodiments, the readout of the short exposure signal is achieved by asserting an appropriate storage control line signal (e.g., asserting the second storage control line signal instead of the first storage control line signal to initiate reading out the short exposure image signal to the second storage capacitor and replacing the previously stored signal associated with the long exposure period of the first image frame). For example, in Figure 1F In the case of , this can be achieved by sending a signal to the second storage control line SSW_IR_S(n) 178 (which is Figure 1E 105-IR illustrated in FIG) is implemented by applying a pulse to the first storage control line SSW_S(n) 174 (associated with Figure 1E 105-B illustrated in FIG) or the third storage control line SSW_S(n+1) 175 (associated with Figure 1E ) applying a pulse (associated with 105-R and 105-G illustrated in FIG).

[0073] Block 224 illustrates the removal of a plurality of storage capacitors (eg, for each of a plurality of pixels). Figure 1D The storage capacitor C illustrated in FIG S ) and a plurality of reset capacitors (eg, for each of the plurality of pixels such as Figure 1D The reset storage capacitor C illustrated in FIG R ) to generate image data corresponding to or otherwise representing an image frame (e.g., a first image frame). It should be understood that additional processing may be performed to generate the image frame (e.g., demosaicing, smoothing, etc.). In some embodiments, the image data is read out of the stored charge signal in the column circuit (e.g., Figure 1A The stored charge signal is read out by column circuitry 155, which may include an analog-to-digital converter, a sample and hold circuit, or otherwise determine the storage node (e.g., Figure 1Dthe state of each capacitor contained in the storage node 124) illustrated in the middle. Specifically, for a given pixel, the storage capacitor stores a signal level and the reset storage capacitor stores a reset level, which are read out (e.g., via Figure 1D the second source follower transistor SF2) illustrated in the middle to a bit line, which in turn reaches a column circuit that converts the signal level minus the reset level into a digital value (e.g., image data). For example, in one embodiment, from the first storage capacitor and the second storage capacitor (e.g., associated with the first pixel (e.g., Figures 1E to 1F the storage capacitor C S ) reads out the stored charge signal to generate at least a portion of image data for an image frame (e.g., a first image frame) based on a corresponding one of a long exposure image signal associated with a first pixel (e.g., Figures 1A to 1F the pixel 105-B) illustrated in the middle and a short exposure image signal associated with a second pixel (e.g., Figures 1A to 1F the pixel 105-IR) illustrated in the middle. In the same or another embodiment, the image data for the first image frame is based on a first difference between a corresponding one of the long exposure image signal associated with the first pixel and a corresponding one of the long exposure reset signal associated with the first pixel, and a second difference between the short exposure image signal and the short exposure reset signal. In some embodiments, the readout of the stored charge signal is done on a row-by-row basis to generate the image data, which can occur during the capture of a next image frame.

[0074] If additional image frames are to be captured, block 226 returns to block 204 and the method 200 continues to capture a next image frame. If no additional image frames are needed, block 226 proceeds to block 228 and the method 200 ends or otherwise terminates.

[0075] Figure 2B illustrates an example timing diagram 250 for capturing image frames (e.g., a first image frame 221 and a second image frame 223) representative of an external scene via selective readout during long and short exposure periods of an image frame (e.g., a long exposure period 225 and a short exposure period 227 of the first image frame 227) in accordance with the teachings of this disclosure. The timing diagram 250 provides an overview of the method 200 illustrated in the middle being performed by an image sensor or imaging system (e.g., Figure 2A the imaging system 100 and Figure 1A the imaging system 100 and Figures 1A to 1F225 ) . As discussed in previous embodiments, the plurality of pixels include visible (e.g., red, green, blue) and invisible (e.g., infrared) pixels. During the long exposure period 225, the photodiodes (e.g., Figure 1D Then, to end the long exposure period, the accumulated image charge is read out to the floating diffusion region (eg, corresponding to Figure 1D Then, all storage switches for visible and invisible pixels (e.g., Figure 1D The storage transistor SSW illustrated in FIG. S , for each pixel included in a plurality of pixels, by applying a pulse to, for example Figure 1F ) are turned on to read out the long exposure image signal to the storage capacitor associated with each of the plurality of pixels (e.g., Figure 1D The storage capacitor C illustrated in FIG S ). Shortly thereafter, a short exposure period 227 begins, during which the light source 241 emits a pulse of electromagnetic radiation (e.g., light having a wavelength between 800 nm and 3000 nm) toward the external scene captured by the image sensor and charge is accumulated in the photodiode of each of the plurality of pixels. Then, to end the short exposure period, the accumulated image charge is read out to the floating diffusion region (e.g., Figure 1D ), but only the storage switches associated with the invisible pixels are activated to read out the short exposure image signals (e.g., Figure 1D The storage transistor SSW illustrated in FIG. S , by applying pulses to the storage control lines of the invisible pixels, e.g. Figure 1F 2. The image sensor 220 is illustrated in FIG. 220 as SSW_IR_S(n) 178 rather than SSW_S(n) 174. When the short-exposure image signals are read out, each short-exposure image signal included in the short-exposure image signals replaces a corresponding one of the long-exposure image signals (e.g., generated in response to image light reflected from an external scene incident on the image sensor during the long exposure period 225). Thereafter, the next image frame (e.g., the second image frame 223) begins and rolling readout 231 of the stored charge signals is performed to generate image data for the first image frame 221. In other words, reading out the stored charge signals to generate image data is performed on a row-by-row basis.

[0076] Figure 3A and Figure 3BCircuitry for pixel cells on sensor die 301 and logic die 351 according to the teachings of this disclosure is illustrated, respectively. It should be appreciated that Figure 3A and Figure 3B The circuit diagrams illustrated in Figures 1A to 1F The imaging system 100 illustrated in Figure 3A Circuitry 300 for pixel cells on sensor die 301 is illustrated, including a blue pixel (e.g., photodiode PD B associated with a first pixel in a first row), an infrared pixel (e.g., photodiode PD IR associated with a second pixel in the first row), a red pixel (e.g., photodiode PD R associated with a third pixel in a second row), and a green pixel (e.g., photodiode PD G associated with a fourth pixel in the second row). It should be appreciated that circuitry 300 is similar in many respects to the circuitry of sensor die 101 illustrated in Figure 1D to avoid obscuring the disclosure, particular elements (e.g., gates of individual transistors, source follower transistors, etc.) are not labeled in Figure 3A The circuitry of sensor die 101 illustrated in Figure 1D The circuitry of sensor die 101 illustrated in Figure 3A One difference between the circuitry of sensor die 101 illustrated in Figure 3A As illustrated in Figure 3A Control lines (e.g., RST1 354 and SEL 358) are also illustrated as being coupled to control pixels of multiple rows (e.g., RST1 354 can be used to simultaneously reset floating diffusion regions FD 1 and FD 2 and photodiodes PD B, PD IR, PD R, and PD G in conjunction with appropriate signals or pulses on transfer control lines TX(n) 356 and TX(n+1) 362). In other embodiments, separate control lines can be provided for each row and function (e.g., first and second reset and select control lines for the first and second rows).

[0077] Now refer to Figure 3B , illustrates pixel circuitry 353 on or in a logic die 351 for a pixel cell, which is similar in many respects to Figure 1D Specifically, each photodiode is coupled to a corresponding storage node (e.g., storage node 324-B and a pixel circuit system 153-N on or in the logic chip 151 illustrated in FIG. Figure 3A The blue pixel of PD_B is associated with the storage node 324-IR and contains Figure 3A The infrared pixel of PD_IR is associated with the storage node 324-R and contains Figure 3A The red pixel of PD_R is associated with the storage node 324-G, and the storage node 324-G is associated with the red pixel of PD_R. Figure 3A It will be appreciated that pixel circuitry 353 is similar in many respects to the green pixel of PD_G. Figure 1D 1 and 2. The pixel circuitry 153-N of the logic die 151 illustrated in FIG4 has been expanded to show a full pixel cell. For example, there are separate control lines for the storage nodes of the invisible pixels that share a row with the visible pixels (e.g., the infrared and blue pixels in the second row) to provide selective readout to the appropriate storage nodes (e.g., SSW_IR_S(n) 378 and SSW_IR_R(n) 380 are coupled to storage node 324-IR, while SSW_S(n) 374 and SSW_R(n) 376 are coupled to storage node 324-B). In contrast, the control lines for the storage nodes associated with the row of only visible pixels (e.g., the red and green pixels in the second row) are shared (e.g., SSW_S(n+1) 375 and SSW_R(n+1) 377 are coupled to storage node 324-R and storage node 324-G). It should be understood that the control lines coupled to Figure 3B The control lines of the pixel circuitry 353 illustrated in FIG. 3 may be functionally connected to Figure 1F The control lines illustrated in FIG are similar or otherwise analogous. In other words, Figure 3B The SSW_S(n) 374 may correspond to or be similar to Figure 1F The first storage control line SSW_S(n) 174, Figure 3B The SSW_IR_S(n) 378 may correspond to or be similar to Figure 1F The second storage control line SSW_IR_S(n) 178, Figure 3B The SSW_R(n) 376 may correspond to or be similar to Figure 1F The first reset storage control line SSW_R(n) 176, Figure 3B The SSW_IR_R(n) 380 may correspond to or be similar to Figure 1F The second reset storage control line SSW_IR_R(n) 180, Figure 3B The RST2(n)382 may correspond to or be similar to Figure 1F The control line RST2(n)182, Figure 3B RS(n)384 may correspond to or be similar to Figure 1F The row selection control line RS(n)184, Figure 3B The CSW(n) 386 may correspond to or be similar to Figure 1F The control line CSW(n)186, Figure 3B The CS(n) 388 may correspond to or be similar to Figure 1F The control line CS(n)188, Figure 3B The SSW_S(n) 374 may correspond to or be similar to Figure 1F The third storage control line SSW_S(n+1)175, and Figure 3B The SSW_R(n+1)377 may correspond to or be similar to Figure 1F The third reset storage line SSW_R(n+1)177.

[0078] Figures 3C to 3D Illustrated is an example method 350 of operation for an imaging system according to the teachings of the present disclosure (ie, Figure 3C 350-1 and Figure 3D 350-2) as illustrated above, the imaging system can selectively read out to capture visible-infrared images. Method 350 can be implemented by an imaging system having pixel unit circuitry distributed across a sensor chip and a logic chip, such as Figure 3A and Figure 3B As illustrated in (e.g., Figure 3A The sensor wafer 301 and Figure 3B 351 is illustrated in FIG. 350 . Method 350 includes blocks 303, 305, 307, 309, 311, 313, 315, 317, 319, 321, 323, 325, 327, 329, 331, and 333. It should be appreciated that several blocks of method 350, including blocks 303 through 333, may occur in any order and even in parallel. Additionally, blocks may be added to or removed from method 350 in accordance with the teachings of the present disclosure. It should be appreciated that method 350 represents one possible implementation for operating an imaging system having a plurality of Figure 3A and Figure 3B The pixel cell circuitry distributed across the sensor die and logic die illustrated in FIG. Figure 3A The sensor wafer 301 and Figure 3B 351). In addition, it should be understood that the method 350 is not limited to Figures 3A to 3BRather than the imaging system illustrated in FIG, method 350 may be applicable to controlling the operation of other embodiments of imaging systems and / or image sensors. Figure 3C and Figure 3D As illustrated in , each loop of method 350 (e.g., a set of boxes 305 to 329) can represent capturing an individual image frame representing an external scene. It should be understood that multiple image frames (e.g., a first image frame, a second image frame, etc.) can be captured to generate a video of the external scene.

[0079] Figure 3C Block 303 of FIG. 3 illustrates the beginning or initiation of method 350, wherein the capture of one or more image frames having multiple exposure durations (e.g., one or more image frames imaging an external scene using visible and infrared image signals) occurs. In some embodiments, block 303 may be associated with Figure 2A Block 202 illustrated in FIG. 1 is similar to and may include the same or similar features.

[0080] Figure 3C Block 305 shows the multiple photodiodes (e.g., Figure 3A PD_B, PD_IR, PD_R, ​​and PD_G) are reset. Figure 3A The plurality of photodiodes are reset by assertion of a pulse on the RST1 354, TX(n) 356, and TX(n+1) 362 control lines illustrated in FIG. 3 to provide a predetermined potential (eg, Figure 3A VDD or other suitable predetermined potential as illustrated in FIG) and allows image charge to accumulate during long exposure periods. In some embodiments, block 305 may be coupled with Figure 2A Block 204 illustrated in is similar to and may include the same or similar features.

[0081] Figure 3C Block 307 of FIG. 1 illustrates the start of a long exposure period for an image frame. During the long exposure period, image charge (e.g., from block 307) is accumulated in the plurality of photodiodes in response to the plurality of photodiodes being reset. The accumulated image charge represents the external scene and has a magnitude based on the intensity of light incident on a given photodiode included in the plurality of photodiodes. In some embodiments, block 307 may be associated with Figure 2A Block 202 illustrated in FIG. 1 is similar to and may include the same or similar features.

[0082] Figure 3C Block 309 illustrates performing a floating diffusion reset for an image frame (eg, a first image frame) and selective readout of the reset storage capacitors to a first set of pixels. Figure 3AIn the case where each floating diffusion region is shared by two adjacent pixels in the same column (as illustrated in FIG. 1), a first group of pixels is supplemented by a second group of pixels, the first group of pixels and the second group of pixels collectively covering a plurality of pixels (e.g., each pixel cell formed by a plurality of pixels). For example, in the illustrated embodiment, the first group of pixels corresponds to the pixels associated with PD_R and PD_G (e.g., row n+1) and the second group of pixels corresponds to the pixels associated with PD_B and PD_IR (e.g., row n), the pixels collectively covering the plurality of pixels as illustrated in FIG. 1. However, it should be appreciated that different schemes of sharing floating diffusion regions (e.g., PD_IR with any of PD_R, PD_G, or PD_B in the same row) can also be utilized depending on the particular layout or arrangement of the plurality of pixels. Figure 3A

[0083] The shared floating diffusion regions (e.g., FD_1 and FD_2 illustrated in FIG. 1) can be reset by asserting or otherwise pulsing the appropriate control lines (e.g., RST1 354 and TX(n+1) 362 for the first group of pixels). After the floating diffusion regions are reset, the reset levels of the floating diffusion regions can be selectively read out to the corresponding reset storage capacitors (e.g., in the case of the first group of pixels, SEL 358 and SSW_R(n+1) 377 are asserted to read the reset levels of FD_1 and FD_2 illustrated in FIG. 1 to R_C and G_C illustrated in FIG. 1, respectively) by asserting or otherwise pulsing the appropriate control lines (e.g., in the case of the first group of pixels, TX(n+1) is asserted to read the reset levels of FD_1 and FD_2 illustrated in FIG. 1 to R_C and G_C illustrated in FIG. 1, respectively). Figure 3A Figure 3A Figure 3B Figure 3A Figure 3B R R

[0084] Figure 3C Block 311 of FIG. 1 illustrates performing a selective transfer of image charge accumulated during a long exposure period to storage capacitors of a first group of pixels (e.g., R_C and G_C of the first group of pixels illustrated in FIG. 1). In one embodiment, image charge accumulated in PD_R and PD_G of FIG. 1 during the long exposure period is transferred to floating diffusion regions FD_1 and FD_2, respectively (e.g., by asserting or otherwise pulsing TX(n+1) 362 illustrated in FIG. 1 and then by asserting the appropriate control lines (e.g., to SEL 358 and SSW_R(n+1) 377 illustrated in FIG. 1). Figure 3B S S Figure 3A Figure 3A Figure 3A Figure 3B ​​​​​​​​​​​​​​The SSW_S(n+1) 375 illustrated in the middle applies a pulse) to read out the long exposure image signal representing the image charge to the appropriate storage capacitor (e.g., Figure 3B The R_C S and G_C S illustrated in the middle are discharged.

[0085] Figure 3C The block 313 illustrates performing a floating diffusion reset of an image frame (e.g., a first image frame) and a selective readout of the reset storage capacitor to a second set of pixels (e.g., the pixels associated with PD_B and PD_IR illustrated in the middle). The shared floating diffusion region (e.g., FD_1 and FD_2 illustrated in the middle) can be reset by asserting or otherwise pulsing the appropriate control lines (e.g., RST1 354 and TX(n) 356 for the second set of pixels). Immediately after the floating diffusion region is reset, the reset level of the floating diffusion region can be selectively read out to the corresponding reset storage capacitor (e.g., in the case of the second set of pixels, TX(n) is asserted to read out the reset level of FD_1 and FD_2 to B_C and IR_C illustrated in the middle, respectively) by asserting or otherwise pulsing the appropriate control lines (e.g., SEL 358 for the second set of pixels, SSW_R(n) 376 and SSW_IR_R(n) 380 for the second set of pixels). Figure 3A Figure 3A Figure 3A Figure 3B Figure 3A Figure 3B R R

[0086] Figure 3C The block 315 illustrates performing a selective transfer of the image charge accumulated during the long exposure period to the storage capacitor of the second set of pixels (e.g., B_C and IR_C illustrated in the middle for the second set of pixels). In one embodiment, the image charge accumulated in PD_B and PD_IR of the second set of pixels during the long exposure period is transferred to the floating diffusion regions FD_1 and FD_2, respectively (e.g., by asserting or otherwise pulsing TX(n) 356 illustrated in the middle and then by asserting the appropriate control lines (e.g., to SEL 358 illustrated in the middle for the second set of pixels, and to SSW_R(n) 376 and SSW_IR_R(n) 380 illustrated in the middle for the second set of pixels). Figure 3B S S Figure 3A Figure 3A Figure 3A Figure 3B ​​​​​​​​​​​​​​) reads out the long exposure image signal representing the image charge to the appropriate storage capacitors (e.g., Figure 3B B_C illustrated in S and IR_C S )).

[0087] It should be understood that in some embodiments, Figure 3C Blocks 309 and 313 of the method 350 illustrated in FIG. 3 may collectively correspond to Figure 2A 208 of the method 200 illustrated in FIG. 200 , all of which may include the same or similar features. Additionally, in the same or other embodiments, Figure 3C Blocks 311 and 315 of the method 350 illustrated in FIG. 3 may collectively correspond to Figure 2A All of these blocks may include the same or similar features as shown in blocks 210 and 212 of the method 200 illustrated in FIG. Figure 3C , block 315 proceeds via "A" to Figure 3D Block 317 illustrated above.

[0088] Figure 3D Block 317 of FIG. 1 illustrates starting a short exposure period for an image frame. In some embodiments, the short exposure period may begin in response to resetting the plurality of photodiodes. In other words, during block 317, the plurality of photodiodes may be reset (e.g., Figure 3C The plurality of photodiodes may accumulate image charges representing the external scene and having a magnitude based on the intensity of light incident on a given photodiode included in the plurality of photodiodes during the short exposure period. In some embodiments, block 317 may be associated with Figure 2A Block 214 illustrated in is similar and may include the same or similar features.

[0089] Figure 3DBlock 319 illustrates emitting a pulse of electromagnetic radiation of a first spectrum (e.g., by a light source) during a short exposure period of an image (e.g., a first image frame). In some embodiments, the light source may be included in the image sensor, while in other embodiments, the light source may be disposed external to the image sensor. It will be appreciated that to mitigate crosstalk between the short exposure period of an image frame and the long exposure period of a subsequent image frame, the pulse duration of the pulse is less than the short exposure duration of the short exposure period of the image frame. In some embodiments, the pulse duration of the pulse is less than one-tenth the duration of the long exposure period, which may enable the capture of invisible images during the short exposure period while minimizing the impact on visible images captured during the long exposure period. It will be appreciated that the first spectrum of electromagnetic radiation includes a first wavelength that may be within the infrared range of the electromagnetic spectrum (e.g., from the near infrared to the far infrared, such as 800 nm to 3000 nm). During the short exposure period, the plurality of photodiodes accumulate image charges in response to pulses of electromagnetic radiation of the first spectrum reflected from one or more objects in the external scene to be incident on the plurality of photodiodes. The image charges can be used to generate an illuminated image that does not interfere with the human eye (e.g., an invisible image based on electromagnetic radiation outside the visible spectrum), or to generate depth or distance information associated with the external scene (e.g., a distance or depth of one or more pixels included in the plurality of pixels from the external scene). In some embodiments, time-of-flight information and / or phase difference information can be calculated based on the image charges accumulated during the short exposure period. In some embodiments, block 319 can be used with Figure 2A Block 216 illustrated in is similar and may include the same or similar features.

[0090] Figure 3D Block 321 of FIG. 3 illustrates performing a floating diffusion reset without reading out the reset storage capacitors of the first set of pixels. In other words, the floating diffusion regions (e.g., FD_1 and FD_2) may be reset, but the reset level of the floating diffusion regions will not be determined because the visible pixels (e.g., Figure 3A The pixels associated with PD_R and PD_G illustrated in FIG do not require a short exposure reset signal because Figures 3A to 3D The illustrated embodiment utilizes infrared pixels (e.g., with Figure 3A The short exposure image and reset signal are determined by the pixel associated with PD_IR illustrated in FIG. 1 . The resetting of the floating diffusion region can be performed by asserting the appropriate control line (e.g., applying to Figure 3A The RST1 354 shown above is not Figure 3B This is achieved by the pulse of SSW_R(n+1)377 illustrated in FIG.

[0091] Figure 3DBlock 323 of FIG. 1 shows performing the selective transfer of image charge accumulated during a short exposure period of an image frame (eg, a first image frame) to the floating diffusion region without transferring to the storage capacitors of the first set of pixels (eg, Figure 3B The R_C illustrated in S and G_CS S ). Similar to block 321, in the illustrated embodiment, a short exposure image signal is not required for the first set of pixels (or more specifically, the visible pixels). This can be accomplished by asserting the appropriate control line (e.g., applying to Figure 3A TX(n+1) 362 and RST1 354 are illustrated above instead of being applied to Figure 3B Selective transfer is performed using a pulse of SSW_S(n+1) 375 as illustrated above.

[0092] Figure 3D Block 325 illustrates the steps for one or more invisible pixels (e.g., Figure 3A ) and performing a reset to the storage capacitor (eg, Figure 3B IR_C illustrated in R ). The second set of pixels (per pixel cell) includes visible and invisible pixels, but only the pixels sensitive to emitted electromagnetic radiation (e.g., infrared pixels corresponding to invisible pixels) require short exposure image signals. Therefore, short exposure reset and image signals will be obtained for the invisible pixels while maintaining the previously obtained long exposure reset and image signals (e.g., in the Figure 3C 309, 311, 313, and 315 as illustrated in FIG. 309). This can be accomplished by asserting the appropriate control line (e.g., applying to Figure 3A RST1 354 and SEL 358 as illustrated in FIG. Figure 3B The SSW_IR_R(n) 380 illustrated in FIG is not applied to Figure 3B The reset of the floating diffusion region and the short exposure reset signal readout are achieved by pulses of SSW_R(n) 376 as illustrated in FIG.

[0093] Figure 3D Block 327 shows the results for one or more invisible pixels (e.g., Figure 3AIR associated with the PD_IR illustrated in FIG. 1 ) performs selective transfer of image charge accumulated during a short exposure period of an image frame (e.g., a first image frame) to a floating diffusion region and performs short exposure image signal readout to a storage capacitor for one or more invisible pixels. As previously discussed, short exposure image signals for the invisible pixels included in the second group of pixels are desired while maintaining long exposure image signals for the visible pixels. This can be accomplished by asserting appropriate control lines (e.g., applied to Figure 3A TX(n) 362 and SEL 358 as illustrated above and Figure 3B The SSW_IR_S(n) 378 illustrated in FIG is not applied to Figure 3B It will be appreciated that the selective readout and reset results in long exposure image signals associated with the invisible pixels (e.g., stored in Figure 3B IR_C illustrated in S The charge in the image is replaced by the corresponding short-exposure image signal.

[0094] It should be understood that in some embodiments, Figure 3C Blocks 321 and 325 of the method 350 illustrated in FIG. 3 may collectively correspond to Figure 2A 218 of the method 200 illustrated in FIG. 21 , all of which may include the same or similar features. Additionally, in the same or other embodiments, Figure 3C Blocks 323 and 327 of the method 350 illustrated in FIG. 3 may collectively correspond to Figure 2A , all of which may include the same or similar features.

[0095] Figure 3D Block 329 illustrates the steps of: Figure 3B The storage capacitor R_C illustrated in FIG S , B_C S 、G_C S and IR_C S ) and a plurality of reset capacitors for each of the plurality of pixels (e.g., Figure 3B The reset storage capacitor R_C illustrated in FIG R , B_C R 、G_C R and IR_C R ) reads out the stored charge signal to generate image data corresponding to or otherwise representing an image frame (e.g., a first image frame): asserts the appropriate control line (applies to the appropriate control line at the appropriate time) Figure 3Bthe SSW_R(n+1) 377, SSW_S(n+1) 375, SSW_R(n) 376, SSW_S(n) 374, SSW_IR_R(n) 380, or SSW_IR_S(n) 378, and RS(n) 384 to read out the stored charge signal to a bit line, which in turn reaches a column circuit that converts the signal level minus the reset level into a digital value (e.g., image data). It should be appreciated that in some embodiments, reading out the stored charge signal can be performed on a row-by-row basis (e.g., while multiple photodiodes are accumulating image charges for a subsequent image frame). In some embodiments, block 329 can be similar to and can include the same or similar features as block 224 illustrated in Figure 2A

[0096] If additional image frames are to be captured, block 331 returns to block 305 via "B" and method 350 continues to capture the next image frame. If no additional image frames are needed, block 331 proceeds to block 333 and method 350 ends or otherwise terminates.

[0097] Figure 4 An example pixel control line arrangement 400 for a logic die 451 in accordance with the teachings of this disclosure is illustrated. It should be appreciated that the control line arrangement 400 illustrating a plurality of pixel cells 410 (e.g., a first pixel cell 410-1 and a second pixel cell 410-2) can have circuitry similar to that described in various embodiments of this disclosure (e.g., the distributed circuitry arrangement illustrated in Figure 1D Figure 3A and / or Figure 3B may incorporate various methods of this disclosure (e.g., the method 200 illustrated in Figure 2A and / or Figure 3C and Figure 3D method 350 illustrated in). Thus, Figure 4 The control line arrangement 400 illustrated in shows control line traces for rows n, n+1, n+2, and n+3, including SSW_R, SSW_S, SSW_IR, and SSW_IR_S, with similar naming of control lines having similar functionality as described in embodiments of this disclosure. The control line arrangement 400 also includes an "other" overlay label that provides a representation of a set of control lines that can otherwise exist that are not explicitly illustrated (e.g., CS(n), CSW(n), RS(n), and RST2(n) for other (n), etc.).

[0098] As Figure 4 ​​In the illustrated embodiment, some rows contain only visible pixels (e.g., row n+1 and row n+3), while other rows contain visible and non-visible pixels (e.g., row n and row n+2). However, in the illustrated embodiment, it can not be desirable to obtain a short exposure image and a reset signal for each infrared pixel (e.g., pixels labeled IR1 and IR2). For example, a lower resolution non-visible image of the external scene (e.g., an image based on infrared light or other non-visible electromagnetic radiation) can be acceptable, which can free up every other infrared pixel (e.g., IR1 or IR2) for purposes other than generating a short exposure image signal. Thus, in some embodiments, IR1 or IR2 can be used to generate a calibration image signal for visible color pixels (e.g., red, green, and blue pixels) during a long exposure period. For example, infrared pixel IR1 (a first type of infrared pixel) can be configured to store image signals captured during a short exposure period and a reset signal to capture emitted non-visible light without interference from nearby visible color pixels (e.g., red, green, and blue pixels), and infrared pixel IR2 (a second type of infrared pixel) can be configured to store image and reset signals captured during a long exposure period simultaneously with other visible color pixels for pixel calibration purposes, reducing color cross-talk between infrared pixels and nearby visible color pixels. In some embodiments, IR1 and IR2 pixels can be structurally identical. However, in other embodiments, IR1 and IR2 pixels can differ from one another (e.g., via a color filter or other component) depending on their intended function. In one embodiment, a color filter associated with an IR2 pixel can block or otherwise attenuate visible light to generate a reference signal that can be subtracted from long exposure image signals associated with nearby visible pixels (e.g., to mitigate the effects of ambient infrared light affecting long exposure image signals). In other embodiments, a color filter of an IR2 pixel can block all light to generate a black reference signal to be subtracted from long exposure image signals.

[0099] It should be appreciated that in the illustrated embodiment, infrared pixels IR1 and IR2 are coupled differently to control lines (e.g., SSW_R(n), SSW_S(n), SSW_IR_S(n), etc.), which need not be the same on a row-by-row basis (e.g., the connections of control lines for row n need not be the same as the connections of control lines for row n+1). For example, for pixels in a given row (e.g., row n, which includes two blue (B) pixels, an IR1 pixel, and an IR2 pixel of a sensor wafer, with a first B pixel adjacent to IR2 and a second B pixel adjacent to IR1 and IR2), the control lines are coupled to the pixel circuitry of the pixels in a particular manner. Each of the pixels can include a corresponding storage capacitor, a reset storage capacitor, a storage gate, a storage transistor, a reset storage gate, a reset storage transistor, etc., as appropriate for the pixel type (e.g., B, IR1, IR2). For example, for a B pixel, the storage capacitor can be coupled to the storage gate, and the reset storage capacitor can be coupled to the reset storage gate. For an IR1 pixel, the storage capacitor can be coupled to the storage gate, and the reset storage capacitor can be coupled to the reset storage gate. For an IR2 pixel, the storage capacitor can be coupled to the storage gate, and the reset storage capacitor can be coupled to the reset storage gate. In some embodiments, the storage capacitor and the reset storage capacitor can be the same capacitor (e.g., a single capacitor that is switched between storage and reset functions). In other embodiments, the storage capacitor and the reset storage capacitor can be separate capacitors. Figure 1DAs illustrated, this means that for a given row illustrated in Figure 4 each pixel has corresponding pixel circuitry (e.g., at least four storage capacitors in row n, at least four storage gates in row n, etc.). In the context of Figure 1D returning reference to Figure 4 , the storage control line SSW_S(n) is coupled to the storage gates of the blue pixels in row n and the IR1 pixels in row n, but not to the storage gates of the IR2 pixels of row n. Separate control lines for reading out the IR2 pixels in row n (e.g., via SSW_IR_S(n)) allow for selective storage of image signals with respect to the blue pixels and IR1 pixels in row n. The same applies to reset operations (e.g., via SSW_R and SSW_IR_R). Additionally, it should be appreciated that in the illustrated embodiment, the connections of the IR1 and IR2 pixels are alternating. For example, in row n+2, IR1 is located in the same column as IR2 in row n. It should further be appreciated that in some embodiments, for the convenience of row readout, the IR1 and IR2 pixels can be alternately disposed on a row basis in the pixel array. For example, one or more first visible color pixels (e.g., red, green, blue, or other color) and first non-visible pixels (e.g., first infrared or IR1 pixels) that share control lines (e.g., via SSW_R(n) and SSW_S(n) for simultaneous readout and reset of the first visible color pixels and first non-visible color pixels) are arranged in a first common row, while one or more second visible color pixels (e.g., red, green, blue, or other color) and second non-visible pixels (e.g., second infrared or IR2 pixels) that can be read out and reset independently of one another (e.g., separate control lines (e.g., SSW_IR_R(n) and SSW_IR_S(n)) read out and reset the IR2 pixels independent of the second visible color pixels) are arranged in a second common row, where the first common row and the second common row are alternately arranged in the pixel array.

[0100] Thus, in the illustrated embodiment, there are generally two types of adjacent pair of pixel connections. A first pair of pixels along a common row that includes visible (e.g., red, green, blue, or other color) and non-visible pixels (e.g., infrared) that can be read out and reset independently of one another (i.e., separate control lines (e.g., SSW_IR_R(n) and SSW_IR_S(n)) read out and reset the IR2 pixels of row n independent of the B and IR1 pixels of row n), and a second pair of pixels along a common row that includes visible (e.g., red, green, blue, or other color) and non-visible pixels (e.g., infrared) that cannot be read out and reset independently of one another (i.e., shared control lines (e.g., SSW_R(n) and SSW_S(n)) simultaneously read out and reset the B pixels and IR1 pixels of row n). Then, as with Figure 2A、 Figure 3C and / or Figure 3D the operation discussed is implemented. For example, in an image frame having a short exposure period and a long exposure period, image charges during the short exposure period can be stored (e.g., via control lines associated with IR2), while also storing image charges during the long exposure period of the image frame (e.g., control lines associated with R, G, B, and IR1 pixels).

[0101] In one embodiment, the operations include transferring first image charges accumulated during a long exposure period of a first image frame to respective floating diffusion regions of the first, second, third, and fourth pixels, reading out long exposure image signals from the respective floating diffusion regions to respective storage capacitors (e.g., first, second, third, and fourth storage capacitors associated with the first, second, third, and fourth pixels, respectively), and reading out storage charge signals from the first, second, third, and fourth storage capacitors to generate image data for the first image frame such that the image data is based on corresponding ones of long exposure image signals associated with the first, third, and fourth pixels (e.g., red, green, blue, and / or IR1 pixels) and a short exposure image signal associated with the second pixel (e.g., an IR2 pixel). This can be accomplished by asserting the first, second, and third storage control line signals after the long exposure period of the first image frame to initiate reading out the long exposure image signals, and asserting the second storage control line signal, but not the first and third storage control lines, to initiate reading out the short exposure image signal to the second storage capacitor and replacing the previous stored signal associated with the long exposure period of the first image frame. When the first, third, and fourth pixels are distributed across more than one row, the first storage control line signal can be applied to SSW_S(n), the second storage control line signal can be applied to SSW_IR_S(n), and the third storage control line signal is applied to SSW_S(n+1) or some other SSW_S control line on a different row than row n.

[0102] Figure 5A FIG. illustrates example pixel circuitry 550 for individual pixels 505-N included in an imaging system, in accordance with the teachings of this disclosure. More specifically, Figure 5A The pixel circuitry 550 illustrated in FIG. is distributed across at least the sensor wafer 501 and the logic wafer 551, with the circuitry for the pixels 505-N located on the sensor wafer 501 and the pixel circuitry 553-N located on the logic wafer 551. The pixel circuitry 550 is similar in many respects to the pixel circuitry 150 illustrated in FIG.. Figure 1D The pixel circuitry 550 illustrated in FIG. is distributed across at least the sensor wafer 501 and the logic wafer 551, with the circuitry for the pixels 505-N located on the sensor wafer 501 and the pixel circuitry 553-N located on the logic wafer 551. The pixel circuitry 550 is similar in many respects to the pixel circuitry 150 illustrated in FIG.. Figure 5APixel circuit 550 includes similarly labeled elements (e.g., VDD, RST1, FD, TX, PD, SF1, SEL, RST2, CSW, CS, RS, SF2, CSW, CS, and bit line) that can operate in similar manners or otherwise include the same features as described with respect to Figure 1D In other words, pixel circuit 550 can be one possible implementation of imaging system 100 illustrated in Figure 1A Thus, pixel circuit 550 can be implemented in various embodiments of the present disclosure.

[0103] Figure 1D One difference between pixel circuit 150 of Figure 5A and pixel circuit 550 of Figure 1D is that pixel circuitry 553-N of pixel 505-N includes a set of at least four capacitors (e.g., C RL , C SL , C RS , C SS ). In other words, instead of each pixel having only one storage node as illustrated in pixel circuit 150 of Figure 1D , each pixel in pixel circuit 550 includes at least two storage nodes to capture an image frame using multiple exposure periods (e.g., long exposure node 524-L and short exposure node 524-S). Thus, a first pixel included in the plurality of pixels (e.g., a first instance of pixel circuit 550) includes a first set of four capacitors each associated with the first pixel, including a first storage capacitor (e.g., a first instance of C SL or C SS ), and a second pixel included in the plurality of pixels (e.g., a second instance of pixel circuit 550) includes a second set of four capacitors each associated with the second pixel, including a second storage capacitor (e.g., a second instance of C SL or C SS ). In some embodiments, the number of storage nodes per pixel matches the number of exposure periods per image frame (e.g., short exposure storage node 524-S for short exposure periods, and long exposure node 524-L for long exposure periods), which can be advantageous for certain pixel layouts. For example, in one embodiment, each pixel cell can be formed from visible pixels (e.g., a red pixel, a blue pixel, and two green pixels). In the same or other embodiments, the color filter of one or more of the visible pixels can permit sufficient transmission of infrared light such that a short exposure image signal associated with the emitted infrared light can still be captured.

[0104] Figure 5B FIG. 2 illustrates an example pixel control line arrangement 252 of sensor die 201 of the imaging system illustrated in Figure 5A FIG. 3 illustrates an example pixel control line arrangement 352 of sensor die 301 of the imaging system illustrated inFigure 5B The pixel control line arrangement 552 illustrated in FIG. 5 is similar to Figure 1E and may include the same or similar features. One difference is the pixel layout of the individual pixel cells. The pixel cell includes a red pixel (e.g., a pixel labeled R), a blue pixel (e.g., a pixel labeled B), and two green pixels (e.g., pixels labeled G1 and G2), which may be arranged based on a Bayer pattern, but does not include an infrared pixel. In other words, for a given pixel cell, the adjacent pixels are different visible color pixels (e.g., G1 and R are different visible color pixels, G2 and B are different visible color pixels, etc.). It should be understood that according to embodiments of the present disclosure, the control lines (e.g., RST1, TX, and SEL) may be used to apply pulses to the coupled circuit elements of the pixels (e.g., Figure 5B The SEL control line can be operated to control Figure 5A ). In the same or other embodiments, the control lines of adjacent rows (eg, row n and row n+1) can be symmetrical about axis 568.

[0105] Figure 5C Illustrate a diagram according to the teachings of the present disclosure Figure 5A An example pixel control line arrangement 572 of the logic die 551 is illustrated in FIG. Figure 5B The pixel control line arrangement 572 illustrated in FIG. 5 is similar to Figure 1F and may include the same or similar features. One difference is that instead of having dummy control lines (e.g., Figure 1F 1 ), there are individual control lines coupled to each capacitor included in each of the plurality of storage nodes (eg, SSW_IR_S(n+1) 179 and SSW_IR_R(n+1) 181 ). Figure 5C The SSW_R(n)_LONG, SSW(S(n)_LONG, SSW_R(n)_SHORT and SSW_S(n)_SHORT are coupled to Figure 5A The capacitor C illustrated in FIG RL 、C SL 、C RS and C SS), to generate the image and reset signals for each exposure period (e.g., long exposure period and short exposure period) without having to replace any previously stored signals (e.g., the short exposure image and reset signals can be obtained without replacing the long exposure image and reset signals). Since the capacitor of each pixel (e.g., a set of four capacitors collectively included in the long exposure storage node 524-L and the short exposure storage node 524-S) is controlled on a row-by-row basis (e.g., row n, row n+1, etc.), each storage control line (e.g., a first storage control line corresponding to SSW S(n)_LONG or SSW S(n)_SHORT) is coupled to multiple transistor gates (e.g., for each pixel in a given row, to the gates of the Figure 5A SSW SL or SSW SS transistor associated with the gates).

[0106] Figure 5C The control line arrangement 572 of the logic die 551 is also similar in many respects to the control line arrangement 172 of Figure 1F . For example, the control lines of the logic die 551 associated with adjacent rows (e.g., row n and row n+1) can be symmetric about the axis 595. In the same or other embodiments, the control lines are positioned to maintain control line symmetry of the logic die 551 such that a first separation distance 591 between the control line SSW S(n)_LONG and the control line SSW S(n)_SHORT is equal to a second separation distance 593 between the control line SSW S(n+1)_LONG and the control line SSW S(n+1)_SHORT.

[0107] It should be appreciated that the operation of controlling an imaging system having pixel cell circuitry, layout, and control line arrangements as illustrated in Figures 5A to 5C is similar to the operation of the method 200 illustrated in Figure 2A . One difference is that, instead of performing selective readout (e.g., blocks 218-222), the short exposure image and reset signals for each pixel are also stored or otherwise read out, such that the image signals for each pixel include both the short exposure image signals and the long exposure image signals and the reset signals include both the short exposure reset signals and the long exposure reset signals.

[0108] Figure 5DAn example timing diagram 580 is illustrated for capturing image frames representing an external scene (e.g., first image frame 581 and second image frame 583) via selective readout during long and short exposure periods of the image frames (e.g., long exposure period 5811 and short exposure period 5813 of first image frame 581) in accordance with the teachings of the present disclosure. The short exposure period has a duration less than the long exposure period. The timing diagram 580 provides a timing diagram for capturing image frames representing an external scene (e.g., first image frame 581 and second image frame 583) via selective readout during long and short exposure periods of the image frames (e.g., long exposure period 5811 and short exposure period 5813 of first image frame 581). The short exposure period has a duration less than the long exposure period. The timing diagram 580 provides a timing diagram for capturing image frames representing an external scene (e.g., first image frame 581 and second image frame 583) via selective readout in accordance with the teachings of the present disclosure. Figure 1A The imaging system 100 illustrated in FIG. Figures 5A to 5C ) and associated structures illustrated in FIG. As discussed in previous embodiments, the plurality of pixels include visible color pixels (e.g., Figure 5B and Figure 5C Prior to the long exposure period 5811, the photodiode of each visible color pixel (e.g., red, green, blue as indicated by the color filter arrangement shown in FIG) is pulsed by applying a pulse to the corresponding reset control line RST1 and transfer control line TX. Figure 5A ) and the floating diffusion region (e.g., Figure 5A During the long exposure period 5811, the photodiode (eg, Figure 5A Then, to end the long exposure period, the floating diffusion region is reset by applying a pulse to the corresponding reset control line RST1, wherein the floating diffusion region is reset by applying a pulse to the corresponding reset storage control line (e.g., Figure 5C The reset signal is read out to the reset storage capacitor C associated with the long exposure by applying a pulse (SSW_R(n)_LONG and SSW_R(n+1)_LONG) illustrated in FIG. RL (like Figure 5A ), to turn on the reset storage transistor SSW of each pixel included in the plurality of pixels RL , thereby reading out a reset signal to a reset storage capacitor associated with each of the plurality of pixels (e.g., Figure 5A The reset storage capacitor C illustrated in FIG RL Thereafter, the accumulated image charge is read out to the floating diffusion region (eg, Figure 5A Then, for each pixel included in the plurality of pixels, a corresponding floating diffusion region FD is provided by sending a signal to a storage control line (eg, Figure 5C SSW_S(n)_LONG and SSW_S(n+1)_LONG) illustrated in FIG. 2 apply a pulse, the storage transistor (e.g., Figure 5AThe storage transistor SSW associated with the long exposure illustrated in FIG. SL ) is turned on to read out the long exposure image signal to the image storage capacitor associated with each of the plurality of pixels (e.g., Figure 5A The storage capacitor C illustrated in FIG SL ). Shortly thereafter, a short exposure period 5813 begins, during which the light source 241 emits a pulse of electromagnetic radiation (e.g., light having a wavelength between 800 nm and 3000 nm, or light that otherwise corresponds to invisible light or electromagnetic radiation) toward the external scene captured by the image sensor, and charge is accumulated in the photodiode of each of the plurality of pixels. Then, to end the short exposure period, the floating diffusion region (e.g., Figure 5A The floating diffusion region FD illustrated in FIG is reset, wherein the floating diffusion region FD is reset by sending a reset signal to a corresponding reset storage control line (eg, as shown in FIG. Figure 5C The SSW_R(n)_SHORT and SSW_R(n+1)_SHORT) illustrated in FIG. 1 apply a pulse to read the reset signal to the Figure 5A The short exposure associated with the reset storage capacitor C illustrated in FIG. RS , thereby turning on the storage transistor SSW of each pixel included in the plurality of pixels RS To read out a reset signal to a reset storage capacitor associated with each of the plurality of pixels (eg, Figure 5A The reset storage capacitor C illustrated in FIG RS Thereafter, the accumulated image charge is read out to the floating diffusion region (eg, Figure 5A ), a storage transistor associated with short exposure included in each pixel is activated to read out a short exposure image signal (eg, a floating diffusion region FD illustrated in FIG. 1 ). Figure 5A The storage transistor SSW illustrated in FIG. SS , by, for example, Figure 5C ). Thereafter, the next image frame (e.g., second image frame 583) begins and rolling readout of the stored charge signals is performed to generate image data for the first image frame 581. In other words, reading out the stored charge signals to generate image data is done on a row-by-row basis.

[0109] Figure 6 is a functional block diagram of an imaging system 600 capable of selective readout for visible-infrared image capture according to the teachings of the present disclosure. The imaging system 600 is embodied Figure 2A The method 250 illustrated in Figure 3A and Figure 3B The method 350 illustrated in FIG. Figure 5Bone possible system of the method 550 illustrated in FIG. 6. Thus, it should be appreciated that, in accordance with the teachings of the present disclosure, an imaging system 600 can have corresponding or otherwise similar components to those illustrated in Figures 1A to 1F the imaging system 100 illustrated in FIG. 1, Figure 1D , Figure 3A , Figure 3B , Figure 5A the circuitry illustrated in FIG. 6, Figure 1E , Figure 1F , Figure 3A , Figure 3B , Figure 4 , Figure 5B , Figure 5C the control line arrangement illustrated in FIG. 6, or combinations thereof. As illustrated, the imaging system 600 includes a sensor wafer 601 coupled to a logic wafer 651, optics 615, a light source 617, and optics 619. The sensor wafer 601 includes a semiconductor material 631 (e.g., silicon or a wafer), a plurality of photodiodes 633, a plurality of color filters 635 (e.g., red, green, blue, infrared, or other color filters arranged over the plurality of photodiodes 633 to form one or more pixel cells), and a plurality of microlenses 637 arranged to focus portions of incident light 698 onto individual photodiodes included in the plurality of photodiodes 633. The light source 617 is optically coupled to the optics 619 (e.g., one or more optical components such as one or more lenses, filters, or other elements) and is operable to emit electromagnetic radiation of a first spectrum (e.g., infrared light including a first wavelength between 800 nm and 3000 nm) toward an external scene 603, which electromagnetic radiation of the first spectrum can then be reflected as incident light 698 (e.g., during a short exposure period).

[0110] The logic die 651 at least partially functions as a controller 610 that includes logic and / or circuitry to control operation of various components of the imaging system 600, e.g., during pre-, post-, and in-situ stages of image and / or video acquisition. The controller 610 can be implemented as hardware logic (e.g., application specific integrated circuitry, field programmable gate array, system on a chip, etc.), software / firmware logic executing on a general purpose microcontroller or microprocessor, or a combination of hardware and software / firmware logic. In one embodiment, the controller 610 includes a processor 612 coupled to a memory 614 that stores instructions executed by the controller 610 or otherwise by one or more components of the imaging system 600. The instructions, when executed, can cause the imaging system 600 to perform operations associated with various functional modules, logic blocks, or circuitry of the imaging system 600, including any of the control circuitry 616, readout circuitry 618, functional logic 620, components of the sensor die 601, optics 615 (e.g., an objective having one or more optical components that can be adjusted to provide variable focus), and any other elements of the imaging system 600 (illustrated or otherwise), or a combination thereof.

[0111] The memory 614 is a non-transitory machine-accessible (e.g., computer-readable) medium that can include, but is not limited to, volatile (e.g., RAM) or non-volatile (e.g., ROM) storage systems that are accessible / readable by the controller 610. In some embodiments, a machine that has access to the non-transitory machine-accessible medium corresponds to the imaging system 600, including the logic die 651 coupled to the sensor die 601. In the same or other embodiments, the non-transitory machine-accessible storage medium corresponds to on-chip memory (e.g., the memory 614 and / or the functional logic 620) of a machine (e.g., the imaging system 600 or components thereof) to capture visible-infrared images via selective readout.

[0112] Control circuitry 616 can control operational characteristics of imaging system 600 (e.g., exposure duration, when to capture digital images or video, etc.). Control circuitry 616 can further control operation of light source 617 in accordance with imaging operations of the pixel cells formed by the plurality of photodiodes 633. Readout circuitry 618 reads or otherwise samples analog signals from individual photodiodes (e.g., reads out electrical signals generated by each of the plurality of photodiodes 633 representing image charges generated in response to incident light to generate phase detection signals, reads out image signals to capture image frames or video, etc.) and can include amplification circuitry, analog-to-digital (ADC) circuitry, image buffers, or others. In the illustrated embodiment, readout circuitry 618 is included in controller 610, but in other embodiments, readout circuitry 618 can be separate from controller 610. Functional logic 680 is coupled to readout circuitry 618 to receive electrical signals, in response generate phase detection signals, generate images in response to receiving image signals or data, etc. In some embodiments, electrical signals or image signals can be stored as phase detection signals or image data, respectively, and can be manipulated by functional logic 420 to perform operations (e.g., compute expected image signals, grade image signals, demosaic image data, apply post-image effects such as cropping, rotation, red-eye removal, adjust brightness, adjust contrast, detect presence of occlusions, or others).

[0113] It should be appreciated that the imaging systems discussed herein (e.g., Figures 1A to 1F the imaging system 100 and Figure 6The imaging system 600 illustrated in the middle can be fabricated by semiconductor device processing and microfabrication techniques known to those skilled in the art. In one embodiment, fabrication of the imaging system 600 can include providing a semiconductor material (e.g., a silicon wafer having a front side and a back side), forming a mask or template (e.g., formed from solidified photoresist) on the front side of the semiconductor material via photolithography to provide a plurality of exposed regions of the front side of the semiconductor material, doping the exposed portions of the semiconductor material (e.g., via ion implantation, chemical vapor deposition, physical vapor deposition, etc.) to form a plurality of photodiodes 635 extending from the front side of the semiconductor material into the semiconductor material, removing the mask or template (e.g., by dissolving the solidified photoresist with a solvent), and planarizing the front side of the semiconductor material (e.g., via chemical mechanical planarization or polishing). In the same or another embodiment, photolithography can similarly be used to form the plurality of color filters 635 and the plurality of microlenses 637 (e.g., individual or shared microlenses, which can be polymer-based microlenses having a target shape and size formed from a master mold or template). It should be appreciated that the described techniques are merely illustrative and not exhaustive, and other techniques can be utilized to fabricate one or more components of various embodiments of the present disclosure.

[0114] The processes explained above can employ software and / or hardware. The described techniques can constitute machine-executable instructions embodied within tangible or non-transitory machine (e.g., computer) readable storage media used in operation of the machine. Such machine-executable instructions can be used to program computing devices (e.g., controller 610 of FIG. 6) to implement processes described herein. Figure 6 The processes explained above can be implemented using software and / or hardware. The software comprises machine executable instructions 620 stored on machine- readable storage medium 630 (e.g., non-transitory storage medium) at a computing device (e.g., controller 610 of FIG. 6). These instructions 620 represent an embodiment of a technical solution to a problem in the art and are used to program the machine (e.g., controller 610) to implement a process described herein. The instructions 620 can be provided on the machine-readable storage medium 630 by embedding them in the machine-readable storage medium 630 (e.g., recording them on the machine-readable storage medium 630), by writing them to the machine-readable storage medium 630 (e.g., downloading them onto the machine-readable storage medium 630), or by any other method of encoding the machine- executable instructions 620 on the machine-readable storage medium 630.

[0115] Tangible machine-readable storage media includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, machine-readable storage media includes recordable / non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0116] The above description of illustrated embodiments of the application, including what is described in the abstract, is not intended to be exhaustive or to limit the application to the precise forms disclosed. While specific embodiments of, and examples for, the application are described herein for illustrative purposes, various modifications are possible within the scope of the application, as those skilled in the relevant art will recognize.

[0117] These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the application to the specific examples disclosed in the specification and the claims are to be accorded the full scope consistent with the principles of patent law.

Claims

1. A method of operating an imaging system, the method comprising: transferring first image charges accumulated during a long exposure period of a first image frame to corresponding floating diffusion regions of a first pixel and a second pixel; reading out a long exposure image signal from the corresponding floating diffusion region to a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel; transferring second image charge accumulated during a short exposure period of the first image frame to the respective floating diffusion regions of the first pixel and the second pixel; reading out a short exposure image signal from a corresponding one of the floating diffusion regions to the second storage capacitor; and Stored charge signals are read out from the first and second storage capacitors to generate image data for the first image frame, wherein the image data is based on a corresponding one of the long exposure image signal associated with the first pixel and the short exposure image signal associated with the second pixel.

2. The method according to claim 1, further comprising: asserting both a first storage control line signal and a second storage control line signal to initiate reading out the long exposure image signal associated with the first pixel and the second pixel of the first image frame to the first storage capacitor and the second storage capacitor; and The second storage control line signal, rather than the first storage control line signal, is asserted to initiate reading out the short exposure image signal associated with the second pixel to the second storage capacitor and replace the storage signal associated with the long exposure period of the first image frame previously stored in the second storage capacitor.

3. The method according to claim 2, further comprising: asserting first transfer control line signals associated with both the first pixel and the second pixel for said transferring the first image charge accumulated during the long exposure period of the first image frame; and The first transfer control line signal associated with both the first pixel and the second pixel is asserted for the transfer of the second image charge accumulated during the short exposure period of the first image frame.

4. The method according to claim 1, further comprising: Pulses of electromagnetic radiation of a first spectrum are emitted during the short exposure period of the first image frame, wherein a pulse duration of the pulse is less than a short exposure duration of the short exposure period, and wherein the short exposure duration is less than a long exposure duration of the long exposure period. 5 . The method of claim 4 , wherein the first spectrum of electromagnetic radiation comprises a first wavelength, and wherein the second pixel is more sensitive to the first wavelength than the first pixel. The method of claim 4 , wherein the pulse duration is less than one tenth of the long exposure duration.

7. The method according to claim 1, further comprising: performing a first floating diffusion reset of the first image frame by resetting the corresponding floating diffusion regions of the first pixel and the second pixel before transferring the first image charge; responsive to the first floating diffusion reset, reading out a long exposure reset signal from the corresponding floating diffusion region to a first reset storage capacitor associated with the first pixel and a second reset storage capacitor associated with the second pixel; performing a second floating diffusion reset of the first image frame by resetting the corresponding floating diffusion regions of the first pixel and the second pixel before the transferring of the second image charge; and In response to the second floating diffusion reset, a short exposure reset signal is read out from the corresponding one of the floating diffusion regions to the second reset storage capacitor associated with the second pixel.

8. The method of claim 7, wherein the image data of the first image frame is based on: a first difference between the corresponding one of the long exposure image signals associated with the first pixel and the corresponding one of the long exposure reset signals associated with the first pixel; and a second difference between the short exposure image signal and the short exposure reset signal.

9. The method of claim 1 , wherein the imaging system comprises a plurality of pixels arranged in rows and columns, including the first pixels and the second pixels, and wherein reading out the stored charge signals to generate the image data is accomplished on a row-by-row basis. 10 . The method of claim 1 , wherein the reading out the short-exposure image signal replaces a corresponding one of the long-exposure image signals associated with the second storage capacitor.

11. The method of claim 1, wherein the first pixel is a visible color pixel and the second pixel is an infrared pixel adjacent to the visible color pixel.

12. The method of claim 1 , wherein the imaging system comprises a plurality of pixels arranged in rows and columns, including the first pixel and the second pixel, and wherein the first pixel and the second pixel are adjacent to each other and are positioned in a first row included in the rows.

13. The method of claim 1, wherein the plurality of pixels of the imaging system further include a third pixel that shares one of the respective floating diffusion regions of the first pixel or the second pixel.

14. An imaging system comprising: an image sensor comprising a plurality of pixels arranged in rows and columns, wherein the plurality of pixels comprises a first pixel and a second pixel each positioned within a first row included in the rows; a controller coupled to the image sensor, the controller including logic storing instructions that, when executed by the controller, cause the imaging system to perform operations comprising: transferring first image charge accumulated during a long exposure period of a first image frame to corresponding floating diffusion regions of the first pixel and the second pixel; reading out a long exposure image signal from the corresponding floating diffusion region to a first storage capacitor associated with the first pixel and a second storage capacitor associated with the second pixel; transferring second image charge accumulated during a short exposure period of the first image frame to the respective floating diffusion regions of the first pixel and the second pixel; reading out a short exposure image signal from a corresponding one of the floating diffusion regions to the second storage capacitor; and Stored charge signals are read out from the first and second storage capacitors to generate image data for the first image frame, wherein the image data is based on a corresponding one of the long exposure image signal associated with the first pixel and the short exposure image signal associated with the second pixel.

15. The imaging system of claim 14, wherein the logic includes additional instructions that, when executed by the controller, cause the imaging system to perform other operations including: asserting both a first storage control line signal and a second storage control line signal after the long exposure period of the first image frame to initiate the reading out of the long exposure image signal; and The second storage control line signal is asserted instead of the first storage control line signal to initiate readout of the short exposure image signal to the second storage capacitor and replace a previously stored signal associated with the long exposure period of the first image frame.

16. The imaging system of claim 15, wherein the logic includes additional instructions that, when executed by the controller, cause the imaging system to perform other operations including: asserting first transfer control line signals associated with both the first pixel and the second pixel for said transferring the first image charge accumulated during the long exposure period of the first image frame; and The first transfer control line signal associated with both the first pixel and the second pixel is asserted for the transfer of the second image charge accumulated during the short exposure period of the first image frame.

17. The imaging system of claim 14, further comprising: a light source configured to emit a first spectrum of electromagnetic radiation comprising at least a first wavelength, and wherein the logic includes additional instructions that, when executed by the controller, cause the imaging system to perform other operations including: A pulse of electromagnetic radiation of the first spectrum is emitted from the light source during the short exposure period of the first image frame, wherein a pulse duration of the pulse is less than a short exposure duration of the short exposure period, and wherein the short exposure duration is less than a long exposure duration of the long exposure period.

18. The imaging system of claim 17, wherein the second pixel is more sensitive to the first wavelength than the first pixel.

19. The imaging system of claim 17, wherein the pulse duration is less than one tenth of the long exposure duration.

20. The imaging system of claim 14, wherein the logic includes additional instructions that, when executed by the controller, cause the imaging system to perform other operations including: performing a first floating diffusion reset of the first image frame by resetting the corresponding floating diffusion regions of the first pixel and the second pixel before transferring the first image charge; After the first floating diffusion is reset, reading out a long exposure reset signal from the corresponding floating diffusion region to a first reset storage capacitor associated with the first pixel and a second reset storage capacitor associated with the second pixel; performing a second floating diffusion reset of the first image frame by resetting the corresponding floating diffusion regions of the first pixel and the second pixel before transferring the second image charge; and After the second floating diffusion is reset, a short exposure reset signal is read out from the corresponding one of the floating diffusion regions to the second reset storage capacitor associated with the second pixel.

21. The imaging system of claim 14, wherein said reading out said stored charge signal to generate said image data is performed on a row-by-row basis, wherein said second pixel is an infrared pixel, and wherein said first pixel is a visible color pixel adjacent to said second pixel.

22. The imaging system of claim 14, wherein the plurality of pixels further comprises a third pixel and a fourth pixel, wherein the first pixel and the third pixel are visible color pixels and the second pixel and the fourth pixel are invisible pixels, wherein the second pixel is adjacent to the first pixel and the fourth pixel is adjacent to the third pixel, wherein the logic includes additional instructions that, when executed by the controller, cause the imaging system to perform other operations including: transferring first image charges accumulated during the long exposure period of the first image frame to corresponding floating diffusion regions of the third pixel and the fourth pixel; reading out long-exposure image signals from the corresponding floating diffusion regions of the third and fourth pixels to a third storage capacitor associated with the third pixel and a fourth storage capacitor associated with the fourth pixel, respectively; and Stored charge signals are read out from the third and fourth storage capacitors to further generate the image data of the first image frame, wherein the image data is further based on the long exposure image signals associated with the third and fourth pixels.

23. The imaging system of claim 22, wherein the logic includes additional instructions that, when executed by the controller, cause the imaging system to perform other operations including: asserting a first storage control line signal, a second storage control line signal, and a third storage control line signal after the long exposure period of the first image frame to initiate reading out the long exposure image signal; and The second storage control line signal is asserted instead of the first and third storage control line signals to initiate reading out the short exposure image signal to the second storage capacitor and replacing a previously stored signal associated with the long exposure period of the first image frame.

Images