Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a plurality of gate lines, a plurality of data lines and a plurality of pixel units. The plurality of gate lines and the plurality of data lines are insulated and crossed to define a plurality of pixel regions. One pixel unit is arranged in each pixel region. The pixel unit comprises a TFT unit and a pixel electrode. The TFT unit comprises a plurality of sub-TFTs. Each sub-TFT has a sub-gate, a sub-source and a sub-drain. The plurality of sub-gates are electrically connected with each other, the plurality of sub-sources are electrically connected with each other, and the plurality of sub-drains are electrically connected with each other. At least one sub-gate is electrically connected with a gate line, and at least one sub-source is electrically connected with a data line. The pixel electrode is arranged on the TFT unit and is electrically connected with at least one sub-drain.

Description

Technical Field

[0001] This application relates to the field of display panel technology, specifically to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, the market demand for TFT-LCD (Thin Film Transistor Liquid Crystal Display) is increasing, and large-size, high-resolution, and high-refresh-rate products are beginning to be developed and produced on a large scale. As product specifications improve, the requirements for the electrical performance of TFT (Thin Film Transistor) devices are also increasing. Therefore, how to further improve the electrical performance of TFT devices is an urgent problem to be solved. Summary of the Invention

[0003] This application provides an array substrate and a display panel that can improve the electrical performance of TFT devices.

[0004] In a first aspect, embodiments of this application provide an array substrate, including multiple gate lines, multiple data lines, and multiple pixel units. The multiple gate lines and the multiple data lines are insulated from each other and intersect to define multiple pixel regions. Each pixel region contains one pixel unit, and the pixel unit includes: A TFT unit, comprising a plurality of sub-TFTs, each sub-TFT having a sub-gate, a sub-source, and a sub-drain; the plurality of sub-gates are electrically connected to each other, the plurality of sub-sources are electrically connected to each other, and the plurality of sub-drains are electrically connected to each other; wherein at least one sub-gate is electrically connected to the gate line, and at least one sub-source is electrically connected to the data line; and, A pixel electrode is disposed on the TFT unit and electrically connected to at least one of the sub-drain electrodes.

[0005] In one embodiment, the pixel electrode includes a main electrode and a plurality of sub-electrodes. The main electrode surrounds the periphery of the TFT unit. The main electrode is divided into a plurality of wiring regions. The plurality of wiring regions are arranged radially along the circumference of the main electrode and correspond one-to-one with the plurality of sub-TFTs. Each wiring region is arranged in a triangle. Each sub-electrode is located in one of the wiring regions and is electrically connected to the main electrode. One of the sub-electrodes is electrically connected to one of the sub-drain electrodes.

[0006] In one embodiment, the plurality of said sub-TFTs are arranged in a ring array; The sub-source electrode is U-shaped and has an arc-shaped electrode segment and an opening opposite to the arc-shaped electrode segment. Multiple sub-source electrodes are arranged in a ring array, and the multiple arc-shaped electrode segments are connected to each other. The multiple arc-shaped electrode segments enclose a hollow part. Each of the multiple sub-drain electrodes is respectively configured in a one-to-one correspondence with a multiple of the multiple sub-source electrodes. Each sub-drain electrode is arranged in a strip shape. One end of the sub-drain electrode extends from the opening of the corresponding sub-source electrode into the corresponding sub-source electrode. The other ends of the multiple sub-drain electrodes are electrically connected in sequence.

[0007] In one embodiment, the pixel electrode includes a main electrode and a plurality of sub-electrodes, the main electrode surrounding the periphery of the TFT unit; Each of the arc-shaped electrode segments has two common tangent lines that intersect with the two adjacent arc-shaped electrode segments, and the two common tangent lines and the main electrode together define a wiring area; Each of the sub-electrodes corresponds to one of the wiring areas.

[0008] In one embodiment, the sub-source poles are arranged in a strip shape, and a plurality of the sub-source poles are arranged radially along the circumference of the pixel region, and their multiple ends are connected to each other; The sub-drains are arranged in a strip shape, with one end of each sub-drain located between two adjacent sub-sources, and the other ends of the multiple sub-drains are electrically connected in sequence.

[0009] In one embodiment, the pixel unit further includes a gate auxiliary line, a source auxiliary line, and a drain auxiliary line. The gate auxiliary line is electrically connected to the gate line and the gate. The source auxiliary line is electrically connected to the data line and one of the sub-sources. The drain auxiliary line is electrically connected to a plurality of sub-drains in sequence and electrically connected to the pixel electrode through a via. The drain auxiliary line has a gap to avoid the source auxiliary line.

[0010] In one embodiment, the plurality of sub-TFTs includes a first sub-TFT closest to the gate line; The gate auxiliary line is electrically connected to the gate line and the sub-gate of the first sub-TFT.

[0011] In one embodiment, the drain auxiliary line includes a first auxiliary line and a second auxiliary line. The first auxiliary line surrounds the periphery of the TFT unit and is electrically connected to a plurality of sub-drains in sequence. One end of the second auxiliary line is electrically connected to the first auxiliary line, and the other end of the second auxiliary line is electrically connected to the pixel electrode through the via. The gap is located on the first auxiliary line.

[0012] In one embodiment, the plurality of sub-TFTs includes a second sub-TFT closest to the data line; The source auxiliary line is electrically connected to the data line and the sub-source of the second sub-TFT.

[0013] Secondly, this application provides a display panel, which includes the array substrate described above.

[0014] Beneficial effects: In the array substrate provided in this application, the TFT unit includes multiple sub-TFTs, each of which has a sub-gate, a sub-source, and a sub-drain. The multiple sub-gates are electrically connected to each other, the multiple sub-sources are electrically connected to each other, and the multiple sub-drains are electrically connected to each other. That is, the multiple sub-TFTs in the TFT unit are arranged in parallel. It is known that a channel is formed between each sub-source and the corresponding sub-drain. Arranging multiple sub-TFTs in parallel can improve the W / L value of the channel of the TFT unit, thereby improving the electrical performance of the TFT unit. Attached Figure Description

[0015] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0016] Figure 1 This is a schematic diagram of a first structure of the array substrate provided in an embodiment of this application; Figure 2 This is a schematic diagram of a second structure of the array substrate provided in an embodiment of this application; Figure 3 This is a schematic diagram of a third structure of the array substrate provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be understood that the terms "above," "below," "front," "back," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and should not be construed as limiting this application. Furthermore, unless otherwise expressly specified and limited, "above" or "below" the second feature of the first feature merely indicates that the first feature is at a higher or lower level than the second feature, and does not indicate a direct connection relationship.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only, and features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0020] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation", "connection" and "linking" should be interpreted broadly without specifically limiting the connection method. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0021] The following disclosure provides many different embodiments for implementing different structures of this application. To simplify the disclosure of this application, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0022] This application provides an array substrate and a display panel. The display panel can be a display panel for devices such as televisions, smartphones, tablets, computers, and wearable devices, and no specific limitations are made here.

[0023] In a first aspect, embodiments of this application provide an array substrate 100. Please refer to... Figures 1 to 3The array substrate 100 includes multiple gate lines 1, multiple data lines 2, and multiple pixel units 3. The multiple gate lines 1 and multiple data lines 2 are insulated and intersecting to define multiple pixel regions (not shown in the figure). Each pixel region is provided with one pixel unit 3. The pixel unit 3 includes a TFT unit 31 and a pixel electrode 32. The TFT unit 31 includes multiple sub-TFTs 311. Each sub-TFT 311 has a sub-gate 3111, a sub-source 3112, and a sub-drain 3113. The multiple sub-gates 3111 are electrically connected to each other. The multiple sub-sources 3112 are electrically connected to each other. The multiple sub-drains 3113 are electrically connected to each other. At least one sub-gate 3111 is electrically connected to the gate line 1, and at least one sub-source 3112 is electrically connected to the data line 2. The pixel electrode 32 is disposed on the TFT unit 31 and is electrically connected to at least one sub-drain 3113.

[0024] In the array substrate 100 provided in this application, the TFT unit 31 includes a plurality of sub-TFTs 311. Each sub-TFT 311 has a sub-gate 3111, a sub-source 3112, and a sub-drain 3113. The plurality of sub-gates 3111 are electrically connected to each other, the plurality of sub-sources 3112 are electrically connected to each other, and the plurality of sub-drains 3113 are electrically connected to each other. That is, the plurality of sub-TFTs 311 in the TFT unit 31 are arranged in parallel. It is known that a channel is formed between each sub-source 3112 and the corresponding sub-drain 3113. By arranging the plurality of sub-TFTs 311 in parallel, the W / L value of the channel of the TFT unit 31 can be improved, thereby improving the electrical performance of the TFT unit 31.

[0025] In one embodiment, the pixel electrode 32 includes a main electrode 321 and a plurality of sub-electrodes 322. The main electrode 321 surrounds the periphery of the TFT unit 31. The main electrode 321 is divided into a plurality of wiring regions 3a. The plurality of wiring regions 3a are arranged radially along the circumference of the main electrode 321 and correspond one-to-one with the plurality of sub-TFTs 311. Each wiring region 3a is arranged in a triangle. Each sub-electrode 322 is located in one of the wiring regions 3a and is electrically connected to the main electrode 321. One of the sub-electrodes 322 is electrically connected to one of the sub-drain electrodes 3113.

[0026] The main electrode 321 is disposed around the periphery of the TFT unit 31. Multiple wiring areas 3a are arranged radially within the main electrode 321. Each wiring area 3a corresponds to a sub-TFT 311, and each sub-electrode 322 is located within a wiring area 3a. The multiple sub-electrodes 322 are independent of each other, but are electrically connected through the main electrode 321. One of the sub-electrodes 322 is electrically connected to a sub-drain 3113, thus realizing the connection between the pixel electrode 32 and the sub-drain 3113. Furthermore, each wiring area 3a is triangularly arranged. Compared with the existing rectangular wiring area 3a, the triangular wiring area 3a has a larger viewing angle, so that the display panel has a better oblique viewing angle at different angles.

[0027] This application does not specifically limit the arrangement position of the TFT unit 31. In one embodiment, the TFT unit 31 is located at the center of the pixel unit 3. In this way, the pixel units 3 can be arranged reasonably and compactly, and the space occupied by a single pixel unit 3 can be reduced.

[0028] This application does not impose specific restrictions on the routing of the sub-electrode 322. In one embodiment, the sub-electrode 322 includes multiple metal lines arranged sequentially around the center of the pixel unit 3. Each metal line is trapezoidal in shape, with its two inclined sides parallel to the two boundaries of the wiring area 3a, and its top and bottom edges parallel to the edge of the corresponding side of the positive electrode. This results in a more rational and compact routing arrangement for the sub-electrode 322.

[0029] In one embodiment, since multiple sub-gates 3111 are disposed on the same layer, and each sub-gate 3111 overlaps with the corresponding sub-source 3112 and sub-drain 3113, in order to avoid the overlapping of multiple sub-gates 3111, multiple sub-gates 3111 can be disposed as a single unit. That is, multiple sub-TFTs 311 share the entire gate, which simplifies the manufacturing process of the sub-gates 3111.

[0030] In one embodiment, please refer to Figure 1The multiple sub-TFTs 311 are arranged in a ring array, which is reasonable and compact, reducing the space occupied by a single pixel unit. At the same time, the sub-source electrode 3112 is U-shaped and has an arc-shaped electrode segment and an opening opposite to the arc-shaped electrode segment. The multiple sub-source electrodes 3112 are arranged in a ring array, and the multiple arc-shaped electrode segments are interconnected, forming a hollow portion 33 at the multiple arc-shaped electrode segments. The multiple sub-drain electrodes 3113 are respectively arranged one-to-one with the multiple sub-source electrodes 3112. Each sub-drain electrode 3113 is strip-shaped, with one end of the sub-drain electrode 3113 extending from the opening of the corresponding sub-source electrode 3112 into the corresponding sub-source electrode 3112, and the other ends of the multiple sub-drain electrodes 3113 are electrically connected in sequence.

[0031] In this embodiment, the sub-source electrodes 3112 are U-shaped, and the multiple arc-shaped electrode segments of the multiple sub-source electrodes 3112 are arranged in a ring array to connect the multiple sub-source electrodes 3112 in parallel. Simultaneously, the multiple arc-shaped electrode segments enclose a hollow portion 33 at the center of the pixel unit 3. It is understood that capacitance is generated at the metal overlap area. The formation of the hollow portion 33 reduces the metal overlap area, thereby reducing the capacitance generated by the metal overlap and thus lowering RC loading. This solves the problem of large RC loading of the traces caused by the parallel connection of multiple sub-TFTs 311.

[0032] Further reading Figure 1 The pixel electrode 32 includes a main electrode 321 and a plurality of sub-electrodes 322. The main electrode 321 surrounds the periphery of the TFT unit 31. Each arc-shaped electrode segment has two intersecting common tangent lines 34 between it and two adjacent arc-shaped electrode segments. The two common tangent lines 34 and the main electrode 321 together define a wiring area 3a. Each sub-electrode 322 corresponds to one wiring area 3a. Thus, the wiring area 3a is divided simply and reasonably, and the sub-electrodes 322 are arranged reasonably.

[0033] In one embodiment, please refer to Figure 2 and Figure 3 The sub-source electrode 3112 is arranged in a strip shape, and multiple sub-source electrodes 3112 are arranged radially along the circumference of the pixel region, and their multiple ends are connected to each other; the sub-drain electrode 3113 is arranged in a strip shape, one end of each sub-drain electrode 3113 is located between two adjacent sub-source electrodes 3112, and the other ends of multiple sub-drain electrodes 3113 are electrically connected in sequence.

[0034] Further reading Figure 2 and Figure 3The extension lines of two adjacent sub-source electrodes 3112 define a wiring region 3a between the main electrode 321; thus, the wiring region 3a is divided in a simple and reasonable manner.

[0035] In one embodiment, the pixel unit 3 further includes a gate auxiliary line 35, a source auxiliary line 36, and a drain auxiliary line 37. The gate auxiliary line 35 is electrically connected to the gate line 1 and the sub-gate 3111. The source auxiliary line 36 is electrically connected to the data line 2 and one of the sub-sources 3112. The drain auxiliary line 37 is electrically connected to a plurality of sub-drains 3113 in sequence and is electrically connected to the pixel electrode 32 through a via 38. The drain auxiliary line 37 is provided with a notch 39 to avoid the source auxiliary line 36.

[0036] This application does not impose specific limitations on the placement of the gate auxiliary line 35. In one embodiment, the plurality of sub-TFTs 311 include a first sub-TFT closest to the gate line 1; the gate auxiliary line 35 electrically connects the gate line 1 and the sub-gate 3111 of the first sub-TFT. By connecting the gate line 1 and the nearest first sub-TFT using the gate auxiliary line 35, the length of the gate auxiliary line 35 can be shortened, simplifying the wiring of the pixel unit 3. Furthermore, to further shorten the length of the gate auxiliary line 35, the gate auxiliary line 35 is configured to be parallel to the data line 2.

[0037] In one embodiment, the drain auxiliary line 37 includes a first auxiliary line 371 and a second auxiliary line 372. The first auxiliary line 371 surrounds the periphery of the TFT unit 31 and is electrically connected to a plurality of sub-drains 3113 in sequence. One end of the second auxiliary line 372 is electrically connected to the first auxiliary line 371, and the other end of the second auxiliary line 372 is electrically connected to the pixel electrode 32 through the via 38. The notch 39 is disposed on the first auxiliary line 371. In this embodiment, by having the first auxiliary line 371 surround the periphery of the TFT unit 31 and connect the plurality of sub-drains 3113 in parallel, the wiring of the pixel unit 3 is simplified, making the wiring of the pixel unit 3 more compact and reasonable, and reducing the space occupied by the pixel unit 3. Simultaneously, the second auxiliary line 372 is provided to electrically connect the first auxiliary line 371 and the sub-electrode 322, realizing the connection between the plurality of sub-drains 3113 and the sub-electrode 322.

[0038] This application does not impose specific restrictions on the routing of the second auxiliary line 372. In one embodiment, the second auxiliary line 372 is located on the boundary between two adjacent wiring regions 3a, the extension axis of the second auxiliary line 372 is parallel to the boundary, one end of the second auxiliary line 372 is connected to the first auxiliary line 371, and the other end of the second auxiliary line 372 extends toward the edge of the main electrode 321 and is electrically connected to the sub-electrode 322 through the via 38. In this way, the problem of a decrease in the aperture ratio of the pixel unit 3 due to the source and drain metal traces entering the wiring region 3a can be avoided.

[0039] In one embodiment, the plurality of sub-TFTs 311 include a second sub-TFT closest to the data line 2; the source auxiliary line 36 electrically connects the data line 2 and the sub-source 3112 of the second sub-TFT. By using the source auxiliary line 36 to connect the data line 2 and the nearest second sub-TFT, the length of the source auxiliary line 36 can be shortened, simplifying the wiring of the pixel unit 3.

[0040] This application does not impose specific restrictions on the routing of the source auxiliary line 36. The plurality of wiring regions 3a include a second wiring region 3a corresponding to the second sub-TFT. The extension axis of the source auxiliary line 36 is arranged parallel to the boundary of the second wiring region 3a. This avoids the problem of a decrease in the aperture ratio of the pixel unit 3 due to source / drain metal traces entering the wiring region 3a.

[0041] Secondly, embodiments of this application also provide a display panel, which includes an array substrate 100. It should be noted that the array substrate 100 is configured as described above. That is, the array substrate 100 has all the embodiments of the array substrate 100 described above, and the display panel has all the technical features of all the embodiments of the array substrate 100 described above, and thus has all the beneficial effects brought about by all the technical features. These will not be elaborated here.

[0042] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0043] The above provides a detailed description of an array substrate and a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate comprising multiple gate lines, multiple data lines, and multiple pixel units, wherein the multiple gate lines and the multiple data lines are insulated from each other and intersect to define multiple pixel regions, and one pixel unit is disposed in each pixel region, characterized in that, The pixel unit includes: A TFT unit, comprising a plurality of sub-TFTs, each sub-TFT having a sub-gate, a sub-source, and a sub-drain; the plurality of sub-gates are electrically connected to each other, the plurality of sub-sources are electrically connected to each other, and the plurality of sub-drains are electrically connected to each other; wherein at least one sub-gate is electrically connected to the gate line, and at least one sub-source is electrically connected to the data line; and, A pixel electrode is disposed on the TFT unit and electrically connected to at least one of the sub-drain electrodes; The pixel electrode includes a main electrode and multiple sub-electrodes. The main electrode surrounds the periphery of the TFT unit. The main electrode is divided into multiple wiring regions. The multiple wiring regions are arranged radially along the circumference of the main electrode and correspond one-to-one with the multiple sub-TFTs. Each wiring region is arranged in a triangle. Each sub-electrode is located in one of the wiring regions and is electrically connected to the main electrode. One of the sub-electrodes is electrically connected to one of the sub-drain electrodes.

2. The array substrate as described in claim 1, characterized in that, The multiple sub-TFTs are arranged in a ring array; The sub-source electrode is U-shaped and has an arc-shaped electrode segment and an opening opposite to the arc-shaped electrode segment. Multiple sub-source electrodes are arranged in a ring array, and the multiple arc-shaped electrode segments are connected to each other. The multiple arc-shaped electrode segments enclose a hollow part. Each of the multiple sub-drain electrodes is respectively configured in a one-to-one correspondence with a multiple of the multiple sub-source electrodes. Each sub-drain electrode is arranged in a strip shape. One end of the sub-drain electrode extends from the opening of the corresponding sub-source electrode into the corresponding sub-source electrode. The other ends of the multiple sub-drain electrodes are electrically connected in sequence.

3. The array substrate as described in claim 2, characterized in that, The pixel electrode includes a main electrode and multiple sub-electrodes, with the main electrode surrounding the periphery of the TFT unit; Each of the arc-shaped electrode segments has two common tangent lines that intersect with the two adjacent arc-shaped electrode segments, and the two common tangent lines together with the main electrode define a wiring area; Each of the sub-electrodes corresponds to one of the wiring areas.

4. The array substrate as described in claim 1, characterized in that, The sub-source poles are arranged in a strip shape, and multiple sub-source poles are arranged radially along the circumference of the pixel region, with multiple ends connected to each other. The sub-drains are arranged in a strip shape, with one end of each sub-drain located between two adjacent sub-sources, and the other ends of the multiple sub-drains are electrically connected in sequence.

5. The array substrate as described in claim 2 or 4, characterized in that, The pixel unit further includes a gate auxiliary line, a source auxiliary line, and a drain auxiliary line. The gate auxiliary line is electrically connected to the gate line and the sub-gate. The source auxiliary line is electrically connected to the data line and one of the sub-sources. The drain auxiliary line is electrically connected to a plurality of sub-drains in sequence and is electrically connected to the pixel electrode through a via. The drain auxiliary line has a gap to avoid the source auxiliary line.

6. The array substrate as described in claim 5, characterized in that, The plurality of said sub-TFTs includes the first sub-TFT closest to said gate line; The gate auxiliary line is electrically connected to the gate line and the sub-gate of the first sub-TFT.

7. The array substrate as described in claim 5, characterized in that, The drain auxiliary line includes a first auxiliary line and a second auxiliary line. The first auxiliary line surrounds the periphery of the TFT unit and is electrically connected to a plurality of sub-drains in sequence. One end of the second auxiliary line is electrically connected to the first auxiliary line, and the other end of the second auxiliary line is electrically connected to the pixel electrode through the via. The gap is located on the first auxiliary line.

8. The array substrate as described in claim 5, characterized in that, The plurality of said sub-TFTs includes the second sub-TFT closest to the data line; The source auxiliary line is electrically connected to the data line and the sub-source of the second sub-TFT.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8.

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