Display driving method, display module and display device

Abstract

This application discloses a display driving method, a display module, and a display device, relating to the field of display technology, to improve the macroscopic brightness difference between the upper and lower sides of the final displayed image and enhance the uniformity of display brightness. The display module includes a display panel, a display driving circuit, and a backlight. One frame cycle of the display includes at least one display period, configured to display an image of one color. The display period includes a charging period and a light-emitting period, with multiple pixels divided into multiple pixel groups. The charging period includes multiple charging sub-periods. The display driving circuit is configured to write data signals to pixels in one of the pixel groups during each charging sub-period to drive the liquid crystal rotation of the pixels in that pixel group. Light emitted by the backlight during the light-emitting period passes through the display panel. This application is used for image display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display driving method, display module and display device. Background Technology

[0002] With the development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, liquid crystal displays (LCDs) have gained increasingly widespread use due to their advantages such as low power consumption, thinness, and soft, eye-friendly images. However, current LCD displays exhibit a significant difference in brightness at both ends of the column direction. Summary of the Invention

[0003] This disclosure provides a display driving method, a display module, and a display device to improve the macroscopic brightness difference between the upper and lower sides of the final displayed image and enhance the uniformity of display brightness.

[0004] To achieve the above objectives, the present disclosure adopts the following technical solution:

[0005] On one hand, a display module is provided. The display module includes a display panel and a backlight. The display panel includes a plurality of pixels arranged in an array, a plurality of scan signal lines extending along the row direction, and a plurality of data lines extending along the column direction. The plurality of scan signal lines and the data lines are electrically connected to the plurality of pixels respectively, for driving the liquid crystal of the pixels to rotate.

[0006] The display module further includes a display driving circuit, which includes a gate driving circuit and a source driving circuit; the gate driving circuit is connected to the plurality of scan signal lines, and the source driving circuit is connected to the plurality of data lines.

[0007] The display module displays a frame cycle including at least one display period, which is configured to display an image of one color; the display period includes a charging period and a light-emitting period, wherein the start time of the charging period is earlier than the start time of the light-emitting period within a display period; and the end time of the charging period is earlier than the end time of the light-emitting period within a display period.

[0008] The plurality of pixels are divided into a plurality of pixel groups. The charging period includes a plurality of charging sub-periods, and the display driving circuit is configured to write data signals to pixels in one of the pixel groups in each charging sub-period to drive the liquid crystal of the pixels in that pixel group to rotate. The light emitted by the backlight during the light emission period passes through the display panel.

[0009] In some embodiments, the charging period and the light-emitting period do not overlap. The start time of the light-emitting period is set to satisfy the condition that after the charging period ends, the liquid crystal of the last pixel charged during the display period is still within the flipping time period.

[0010] In some embodiments, the plurality of scan signal lines are divided into a plurality of scan signal line groups, the scan signal lines in the plurality of scan signal line groups are arranged sequentially in a column direction, and the scan signal lines in each scan signal line group are electrically connected to pixels in the same pixel group. The gate driving circuit is configured to drive the plurality of scan signal lines in a scan signal line group sequentially in a charging sub-period. The source driving circuit is configured to output data signals to the plurality of data lines in each charging sub-period.

[0011] In some embodiments, the display driving circuit includes a plurality of gate driving circuits, each gate driving circuit being connected to a plurality of scan signal lines of a scan signal line group. The plurality of gate driving circuits are configured to drive sequentially within a charging period, and in two adjacent gate driving circuits, the start time of the later gate driving circuit is after the end time of the previous gate driving circuit.

[0012] In some embodiments, the display driving circuit includes a plurality of gate driving circuits, each gate driving circuit being connected to multiple scan signal lines of a scan signal line group, and each gate driving circuit including a plurality of cascaded shift registers. The plurality of gate driving circuits are configured to drive sequentially within a charging period, and in two adjacent gate driving circuits, the output signal of any shift register in one gate driving circuit, except for the first and / or the last shift register, is located between the output signals of the two cascaded shift registers in the other gate driving circuit.

[0013] In some embodiments, the plurality of scan signal lines are connected to the same gate driving circuit, and the display module further includes a gate control circuit, which is connected to the gate driving circuit and the plurality of scan signal lines; the gate control circuit is configured to control the switching on and off of the scan signal lines of each scan signal line group with the gate driving circuit.

[0014] In some embodiments, the plurality of scan signal lines includes an odd scan signal line group and an even scan signal line group. The odd scan signal line group includes a plurality of third scan signals, and the even scan signal line group includes a plurality of fourth scan signal lines. The plurality of third scan signal lines and the plurality of fourth scan signal lines are arranged alternately in the column direction. Two adjacent rows of pixels include a first pixel row and a second pixel row. Pixels in odd-numbered columns of the first pixel row and pixels in even-numbered columns of the second pixel row are electrically connected to one of the third scan signals and the fourth scan signal lines. Pixels in even-numbered columns of the second pixel row and pixels in odd-numbered columns of the second pixel row are electrically connected to the other of the third scan signal and the fourth scan signal line. Each column of pixels is electrically connected to the same data line.

[0015] In some embodiments, any two adjacent data lines are configured such that the polarities of the output data signals are opposite.

[0016] In some embodiments, the plurality of data lines are divided into multiple data line groups, the data lines in the multiple data line groups are arranged sequentially and cyclically in the row direction, and the data lines in each data line group are electrically connected to pixels in the same pixel group. The gate driving circuit is configured to drive the plurality of scan signal lines multiple times during a charging period, and to drive the plurality of scan signal lines once sequentially in each charging sub-period according to the scan order during each charging sub-period. The source driving circuit is configured to output data signals to the plurality of data lines in a data line group during a charging sub-period.

[0017] In some embodiments, the display driving circuit includes a plurality of source driving circuits, each source driving circuit being connected to multiple data lines of a data line group. The plurality of source driving circuits are configured to drive sequentially during a charging period, and the start time of each source driving circuit's drive is the same as the start time of one drive of the gate driving circuit.

[0018] In some embodiments, the plurality of data lines are connected to the same source drive circuit, and the display module further includes a source control circuit, which is connected to the source drive circuit and the plurality of data lines; the source control circuit is configured to control the connection and disconnection of the data lines of each data line group with the source drive circuit.

[0019] In some embodiments, the plurality of data lines includes an odd data line group and an even data line group. The odd data line group includes a plurality of third data lines, and the even data line group includes a plurality of fourth data lines. The plurality of third data lines and the plurality of fourth data lines are arranged alternately in the row direction. Two adjacent columns of pixels include a first pixel column and a second pixel column. Pixels in odd-numbered rows of the first pixel column and pixels in even-numbered rows of the second pixel column are electrically connected to one of the third data lines and the fourth data lines. Pixels in even-numbered rows of the second pixel column and pixels in odd-numbered rows of the second pixel column are electrically connected to the other of the third data line and the fourth data line. Each row of pixels is electrically connected to the same scan signal line.

[0020] In some embodiments, in the same data line group, any two adjacent data lines are configured such that the polarities of the output data signals are opposite.

[0021] In some embodiments, each row of pixels is electrically connected to the same scan signal line, and each column of pixels is electrically connected to the same data line.

[0022] In some embodiments, when the multiple scan signal lines are divided into multiple scan signal line groups, any two adjacent data lines are configured such that the polarities of the output data signals are opposite. In the case where the multiple data lines are divided into multiple data line groups, within the same data line group, any two adjacent data lines are configured such that the polarities of the output data signals are opposite.

[0023] In some embodiments, the driving order of the plurality of pixel groups is the same; or, at least two of the plurality of pixel groups have different driving orders.

[0024] The display module provided in this embodiment can, in multiple charging sub-periods, partially merge the liquid crystal response time of the pixels of the pixel group corresponding to the previous charging sub-period with the data writing time of the pixels of the pixel group corresponding to the next charging sub-period.

[0025] In this scenario, during the light-emitting period, the long axis of the liquid crystal in the pixel group corresponding to the previous charging sub-period can quickly deflect to the electric field direction. This means the brightness of the image formed by the pixels in the pixel group corresponding to the previous charging sub-period is greater than the brightness of the image formed by the pixels in the pixel group corresponding to the next charging sub-period. By superimposing images formed in different charging sub-periods, the brightness of adjacent pixels can be blended to balance the overall brightness of the image, reducing the macroscopic brightness difference at both ends of the column direction in the final displayed image of a display period, and improving the uniformity of display brightness.

[0026] On the other hand, a display device is provided. The display device includes the display module described in any of the above embodiments, and the display device is an active display device or a projection display device.

[0027] In another aspect, a display driving method for a display module is provided. The display module includes a display panel and a backlight. The display panel includes a plurality of pixels arranged in an array, and the plurality of pixels are divided into a plurality of pixel groups. One frame cycle displayed by the display module includes at least one display period, and the display period displays an image of one color. The display period includes a charging period and a light-emitting period. Within a display period, the start time of the charging period is earlier than the start time of the light-emitting period; within a display period, the end time of the charging period is earlier than the end time of the light-emitting period. The charging period includes a plurality of charging sub-periods.

[0028] During one of the display periods, the display driving method includes: writing data signals to the pixel electrodes of each pixel in one of the plurality of pixel groups during each charging sub-period. During the light emission period, the backlight emits a single color of light.

[0029] In some embodiments, the start times of the plurality of charging sub-segments are arranged sequentially, and in two adjacent charging sub-segments, the start time of the latter charging sub-segment is after the end time of the former charging sub-segment.

[0030] In some embodiments, each charging sub-period includes multiple line scan periods, during which data is written to a row of pixels in a pixel group. The start times of the multiple charging sub-periods are arranged sequentially, and in any two adjacent charging sub-periods, except for the first and / or last line scan period, any line scan period in one charging sub-period is located between two adjacent line scan periods in the other charging sub-period.

[0031] In some embodiments, writing data signals to each pixel in one of the plurality of pixel groups includes: writing data signals to multiple rows of pixels spaced apart, or writing data signals to multiple columns of pixels spaced apart.

[0032] In some embodiments, writing data signals to each pixel in one of the plurality of pixel groups includes writing data signals to a plurality of pixels that are spaced apart in both the row and column directions.

[0033] In some embodiments, among the plurality of pixels, the periphery of a non-edge pixel includes at least one pixel with a different polarity.

[0034] In some embodiments, a frame cycle displayed by the display module includes three display periods, which respectively display a red image, a blue image, and a green image.

[0035] In some embodiments, during a display period, at least two sub-periods of charging have different driving orders for two pixel groups.

[0036] The beneficial effects of the display device and display driving method provided in this disclosure are the same as those of the display module provided in the above technical solutions, and will not be repeated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0038] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0039] Figure 2 A cross-sectional view of a display device according to some embodiments;

[0040] Figure 3A This is a cross-sectional view of a display panel according to some embodiments;

[0041] Figure 3B This is a cross-sectional view of another display panel according to some embodiments;

[0042] Figure 4A This is a circuit diagram of a display panel according to some embodiments;

[0043] Figure 4B This is a circuit diagram of another display panel according to some other embodiments;

[0044] Figure 5A A timing diagram of a display panel according to some embodiments;

[0045] Figure 5B A timing diagram of another display panel according to some embodiments;

[0046] Figure 5C This is a timing diagram of yet another display panel according to some embodiments;

[0047] Figure 6This is a structural diagram of a display panel according to some embodiments;

[0048] Figure 7 This is a structural diagram of another display panel according to some embodiments;

[0049] Figure 8 This is a structural diagram of yet another display panel according to some embodiments;

[0050] Figure 9 This is a structural diagram of another display panel according to some embodiments;

[0051] Figure 10 This is a structural diagram of yet another display panel according to some embodiments;

[0052] Figure 11 This is a structural diagram of yet another display panel according to some embodiments;

[0053] Figures 12-14 This is a flowchart of a display driving method for a display panel according to some embodiments. Detailed Implementation

[0054] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0055] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0056] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0057] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0058] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0059] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0060] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0061] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0062] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0063] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] The pixel circuits provided in the embodiments of this disclosure can use thin film transistors (TFTs), metal oxidant semiconductors (MOSs), or other switching devices with the same characteristics. In the embodiments of this disclosure, thin film transistors are used as an example for illustration.

[0066] In this document, the control electrode of each thin-film transistor used in the pixel driving circuit (pixel circuit) is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first and second electrodes of the thin-film transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, when the thin-film transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the thin-film transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0067] See Figure 1 Some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0068] Specifically, the display device 1000 can be a field sequence display device.

[0069] The display device 1000 can be an active display device or a projection display device. An active display device is understood as one where the light presenting the displayed content enters the user's eyes directly when the user is viewing it. A projection display device is understood as one where the light presenting the displayed content is reflected or scattered by a surface (such as a projection screen or wall) before entering the user's eyes when the user is viewing it.

[0070] For example, the display device 1000 can be any product or component with display function, such as a projector, television, laptop, tablet, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, etc.

[0071] Depending on whether the user can see the back of the display device 1000, the display device 1000 can be a transparent display device or an opaque display device.

[0072] In some embodiments, see Figure 1 The display device 1000 is a liquid crystal display (LCD).

[0073] Based on this, such as Figure 1 and Figure 2 As shown, the display device 1000 includes a display module 100 and a backlight module 200.

[0074] For example, such as Figure 1 and Figure 2 As shown, the display device 1000 includes a display module 100, a backlight module 200, and a housing 300.

[0075] like Figure 2 As shown, the housing 300 may include, for example, a frame 310 and a cover plate 320. The longitudinal section of the frame 310 is U-shaped. The display module 100 and the backlight module 200 are disposed inside the frame 310, and the cover plate 320 is disposed at the opening of the frame 310.

[0076] like Figure 2 As shown, the backlight module 200 is configured to provide the display module 100 with the light required to display the image. The backlight module 200 includes a backlight source, which may be, for example, a light-emitting diode (LED).

[0077] It should be noted that the backlight may include multiple backlights with different emission colors. For example, the backlight may include a red backlight with a red emission color, a green backlight with a green emission color, and a blue backlight with a blue emission color.

[0078] like Figure 2 As shown, the display module 100 may include, for example, a display panel 110 and a circuit board 120, as well as other electronic components.

[0079] Among them, such as Figure 2As shown, the display panel 110 includes an array substrate 10, a cell substrate 20, and a liquid crystal layer 30 disposed between the array substrate 10 and the cell substrate 20.

[0080] like Figure 3B As shown, the substrate 20 may include, for example, a first substrate 21.

[0081] In some embodiments, such as Figure 1 , Figure 2 and Figure 3A As shown, the array substrate 10 may include a second substrate 11 and a plurality of pixels P disposed on the second substrate 11.

[0082] Pixel P includes a pixel electrode 12 and a pixel circuit 13 that are electrically connected to each other. Pixel circuit 13 includes a thin-film transistor 130, which includes an active layer 131, a source 132, a drain 133, and a gate 134. The source 132 and drain 133 are respectively in contact with the active layer 131. In this case, pixel electrode 12 can be electrically connected to either the source 132 or the drain 133 of thin-film transistor 130. Figure 3A The diagram illustrates the electrical connection between pixel electrode 12 and drain 133 of thin-film transistor 130.

[0083] In addition, see Figure 1 Multiple pixels P can be arranged in multiple rows and columns, for example. Each row can include multiple pixels P arranged along the row direction X, and each column can include multiple pixels P arranged along the column direction Y.

[0084] It should be noted that in this article, the definitions of row and column are relative concepts, representing two different directions of extension of the array arrangement.

[0085] For ease of description, multiple pixels P arranged in a row along the row direction X are called pixels in the same row, and multiple pixels P arranged in a column direction Y are called pixels in the same column.

[0086] Based on this, refer to Figure 3A and Figure 3B The display panel 110 also includes a common electrode 14, and an electric field is generated between the pixel electrode 12 and the common electrode 14 to deflect the liquid crystal molecules in the liquid crystal layer 30.

[0087] In some embodiments, such as Figure 3B As shown, the common electrode 14 can be disposed on the second substrate 11, that is, the array substrate 10 includes the common electrode 14. Exemplarily, as... Figure 3BAs shown, the pixel electrode 12 and the common electrode 14 can be disposed on the same layer. Each pixel electrode 12 and the common electrode 14 includes a plurality of spaced strip electrodes, and the strip electrodes of the pixel electrode 12 and the strip electrodes of the common electrode 14 are arranged alternately.

[0088] In other embodiments, such as Figure 3A As shown, the common electrode 14 can be disposed on the first substrate 21, that is, the common electrode 14 is included on the cell substrate 20.

[0089] In some embodiments, such as Figure 3A and Figure 4A As shown, the array substrate 10 may further include multiple gate lines GL and multiple data lines DL disposed on the second substrate 11.

[0090] Multiple gate lines GL extend along the row direction X and are connected to the pixel circuit 13. Multiple data lines DL extend along the column direction Y and are connected to the pixel circuit 13, used to drive the liquid crystal rotation of pixel P.

[0091] In some embodiments, such as Figure 2 and Figure 4A As shown, the display module 100 may further include a display driving circuit 140.

[0092] The display driving circuit 140 includes a gate driving circuit 141 and a source driving circuit 142. The gate driving circuit 141 is connected to the scan signal line GL, and the source driving circuit 142 is connected to the data line DL.

[0093] For example, see Figure 3A and Figure 4A The gate drive circuit 141 can be disposed on the second substrate 11 and located on the side in the extension direction of the scan signal line GL. The source drive circuit 142 can be disposed on the second substrate 11 and located on the side in the extension direction of the data line DL.

[0094] It should be noted that the gate drive circuit 141 and the source drive circuit 142 are disposed on the circuit board 120 and are connected to the scan signal line GL and the data line DL through the flexible circuit board. The embodiments disclosed herein will not be described in detail here.

[0095] In some embodiments, see Figure 4A and Figure 4B The gate drive circuit 141 includes multiple cascaded shift registers RS, each shift register RS ​​being coupled to at least one scan signal line GL. Figure 4A and Figure 4B The diagram illustrates the coupling of each stage shift register RS ​​with a scan signal line GL.

[0096] It should be noted that, Figure 4A The example illustrates the cascading of shift registers in odd-numbered rows of one gate drive circuit and the cascading of shift registers in even-numbered rows of another gate drive circuit. Figure 4B The following is an example of the successive cascading of shift registers in a gate drive circuit.

[0097] In some embodiments, see Figure 4A and Figure 4B In each pair of adjacent shift registers RS, the signal input terminal of the next shift register RS ​​is coupled to the output terminal of the previous shift register RS, and the signal input terminal of the first shift register is coupled to the corresponding initialization signal line.

[0098] The structure of the pixel circuit 13 described above includes various types, and can be selected and configured according to actual needs.

[0099] For example, such as Figure 4A and Figure 4B As shown, the pixel circuit 13 may include a switching transistor T, a scan signal terminal G, and a data signal terminal D. The scan signal terminal G is connected to the scan signal line GL, and the data signal terminal D is connected to the data line DL.

[0100] Among them, the control electrode of the switching transistor T is electrically connected to the scanning signal terminal G, the first electrode of the switching transistor T is electrically connected to the data signal terminal D, and the second electrode of the switching transistor T is electrically connected to the pixel electrode 12.

[0101] It should be noted that the switching transistor T is configured to transmit the data signal received at the data signal terminal D to the pixel electrode 12 in response to the scan signal received at the scan signal terminal G.

[0102] Based on this, a frame period may include at least one display period configured to display an image of a single color. For example, a frame period may include three sequentially occurring display periods, configured to display a red image, a green image, and a blue image, respectively.

[0103] Among them, see Figure 5A , Figure 5B and Figure 5C The display period may include, for example, a charging period P1 and a light-emitting period P2 that occur sequentially.

[0104] Within a display period, the start time of the charging period P1 is earlier than the start time of the light-emitting period P2; within a display period, the end time of the charging period P1 is earlier than the end time of the light-emitting period P2.

[0105] For example, the charging period P1 and the light-emitting period P2 do not overlap. For instance, the start time of the light-emitting period P2 is after the end of the charging period P1.

[0106] During the charging period P1, the scanning signal provided by the scanning signal terminal G is at a high level, the switching transistor T is turned on under the control of the scanning signal, and the pixel electrode 12 receives the data signal from the data signal terminal D.

[0107] During the light-emitting period P2, the light emitted by the backlight passes through the display panel 110 to display the image.

[0108] It should be noted that the backlight emits a single color of light during its emission period P2. A single color of light can be understood as the color of the light emitted by the backlight P2 (which can be a single color directly emitted by the backlight or a mixture of multiple colors emitted by the backlight) remaining unchanged during a single emission period. For example, the single color could be one of red, green, or blue.

[0109] Specifically, display module 100 is a field-sequence module. For example, one frame cycle includes three display periods: a red light display period, a green light display period, and a blue light display period. For example, within one frame cycle, the red light display period, green light display period, and blue light display period are arranged sequentially. During the red light display period's emission period P2, the backlight emits red light; during the green light display period's emission period P2, the backlight emits green light; and during the blue light display period's emission period P2, the backlight emits blue light. One frame cycle is relatively short, allowing the human eye to perceive a color image by mixing the three colors of light.

[0110] It should be noted that, Figure 5A , Figure 5B and Figure 5C The illustrations all use LEDs as the backlight source.

[0111] In related technologies, the brightness of images displayed by liquid crystal display devices varies significantly.

[0112] To improve the above technical issues, please refer to Figure 5A , Figure 5B and Figure 5C In some embodiments of the present disclosure, the display module 100 includes a charging period P1 comprising a plurality of charging sub-periods P10.

[0113] Among them, such as Figure 6 and Figure 7 As shown, multiple pixels P are divided into multiple pixel groups 400, and the pixels P of the multiple pixel groups 400 are arranged sequentially in the row direction X and / or column direction Y. Furthermore, the display driving circuit 140 is configured to, in each charging sub-period P10 (see...), Figure 5A ), to the pixel electrode 12 of pixel P in a pixel group 400 (see Figure 4AWrite data signals to drive the liquid crystal of pixel P in a pixel group 400 to rotate.

[0114] As can be seen from the above, in multiple charging sub-periods P10, the liquid crystal response time of pixel P of pixel group 400 corresponding to the previous charging sub-period P10 can be partially merged with the data writing time of pixel P of pixel group 400 corresponding to the next charging sub-period P10.

[0115] In this scenario, during the light-emitting period P2, the long axis of the liquid crystal of pixel P in pixel group 400 corresponding to the previous charging sub-period P10 can quickly deflect to the electric field direction. This means the brightness of the image formed by pixel P in pixel group 400 corresponding to the previous charging sub-period P10 is greater than the brightness of the image formed by pixel P in pixel group 400 corresponding to the subsequent charging sub-period P10. Thus, by superimposing images formed in different charging sub-periods P10, the brightness of adjacent pixels P can be blended to balance the overall brightness of the image, reducing the macroscopic brightness difference between the two ends of the final displayed image in the column direction Y during a display period, and improving the uniformity of the displayed brightness.

[0116] Among them, see Figure 6 and Figure 7 Multiple pixel groups 400 have the same driving order; or, see [link to relevant documentation]. Figure 10 and Figure 11 At least two of the multiple pixel groups 400 have different driving orders.

[0117] It should be noted that the driving sequence refers to the order in which the pixel electrodes 12 in each pixel P of the pixel group 400 are charged. That is, the scanning sequence of the gate driving circuit 141 electrically connected to each pixel P in the pixel group 400.

[0118] When at least two pixel groups 400 have different driving orders, the image formed by the pixel P of one pixel group 400 is brighter at the first end than the second end in the column direction Y; the image formed by the pixel P of the other pixel group 400 is brighter at the second end than the first end in the column direction Y.

[0119] In this way, the superposition of images formed by different charging time periods P10 can be used to fuse the brightness of adjacent pixels P, thereby balancing the overall brightness of the image and reducing the macroscopic brightness difference between the two ends of the final displayed image in the column direction Y, thus improving the uniformity of display brightness. It should be noted that the first end and the second end are the two opposite ends of the image in the column direction Y.

[0120] Furthermore, the start time setting of the aforementioned light-emitting period P2 satisfies the following condition: after the charging period P1 ends, and within the display period, the liquid crystal of the last charged pixel P is still in the flipping period, so as to avoid the display time of the image displayed in each display period being severely insufficient, thereby improving the display brightness.

[0121] In some embodiments, see Figure 6 The aforementioned multiple scan signal lines GL are divided into multiple scan signal line groups GL10. The scan signal lines GL in the multiple scan signal line groups GL10 are arranged sequentially in the column direction Y. The scan signal line GL in each scan signal line group GL10 is electrically connected to the pixel P in the same pixel group 400, that is, electrically connected to the pixel circuit 13 of the pixel P in the same pixel group 400.

[0122] Here, sequential cyclic arrangement means that in any scan signal line group GL10, between any two adjacent scan signal lines DL, there is one scan signal line DL from each of the other scan signal line groups GL10, and the arrangement order of the scan signal lines DL in different scan signal line groups GL10 is fixed.

[0123] For example, such as Figure 6 and Figure 7 As shown, multiple pixels P are divided into two pixel groups 400. The two pixel groups 400 include a first pixel group 410 and a second pixel group 420, and the pixels P of the first pixel group 410 and the second pixel group 420 are arranged sequentially in the row direction X and / or column direction Y.

[0124] At this time, the multiple scan signal lines GL are divided into the first scan signal line group GL11 and the second scan signal line group GL12.

[0125] The first scan signal line group GL11 includes multiple first scan signal lines GL1, and the second scan signal line group GL12 includes multiple second scan signal lines GL2. The first scan signal lines GL1 and the second scan signal lines GL2 are arranged sequentially in the column direction Y, and the first scan signal lines GL1 are connected to the pixel circuit 13 of pixel P in the first pixel group 410 (see...). Figure 4A The second scan signal line GL2 is connected to the pixel circuit 13 of pixel P in the second pixel group 420 (see...). Figure 4A )connect.

[0126] In this configuration, the gate drive circuit 141 is configured to sequentially drive multiple scan signal lines GL in a scan signal line group GL10 in a scan sequence during a charging sub-period P10. The source drive circuit 142 is configured to output data signals to multiple data lines DL during each charging sub-period P10.

[0127] In some examples, see Figure 4A The display driving circuit 140 includes multiple gate driving circuits 141, each gate driving circuit 141 being connected to multiple scan signal lines GL of a scan signal line group GL10. This arrangement results in minimal changes to the circuit structure and facilitates fabrication.

[0128] It should be noted that, Figure 4A The diagram uses two gate drive circuits 141 as an example.

[0129] Based on this, multiple gate drive circuits 141 are configured to drive sequentially within a charging period P1, and in two adjacent gate drive circuits 141, the start time of the latter gate drive circuit 141 is after the end time of the former gate drive circuit 141.

[0130] It should be noted that sequential driving of the gate driving circuit 141 means that the starting time of the gate driving circuit 141 is different.

[0131] For example, in two adjacent gate drive circuits 141, the input signal of the first shift register RS1 of the latter gate drive circuit 141 is the same as the output signal of the last shift register RS(N) of the former gate drive circuit 141.

[0132] Here, in the case where the multiple gate drive circuits 141 include two gate drive circuits 141, the multiple charging sub-periods P10 include a first charging sub-period P11 and a second charging sub-period P12. The timing of the first charging sub-period P11 and the second charging sub-period P12 can be referenced. Figure 5A .in, Figure 5A The illustration only takes the example of each charging sub-period P10, which includes four line scanning periods.

[0133] It should be noted that the scanning order of different gate drive circuits 141 can be opposite or the same, and this disclosure does not specifically limit this.

[0134] For example, such as Figure 4A and Figure 5A As shown, the display module 100 includes two gate drive circuits 141 and 720 scan signal lines GL. The driving sequence of the two gate drive circuits 141 can be as follows:

[0135] The first scan signal line DL, the third scan signal line DL, the fifth scan signal line DL... the 719th scan signal line DL, the second scan signal line DL, the fourth scan signal line DL... the 718th scan signal line DL, and the 720th scan signal line. At this time, the driving sequence of the two gate drive circuits 141 is the same.

[0136] Alternatively, the sequence could be: 1st scan signal line DL, 3rd scan signal line DL, 5th scan signal line DL... 719th scan signal line DL, 720th scan signal line DL, 718th scan signal line DL... 4th scan signal line DL, 2nd scan signal line. In this case, the driving sequence of the two gate drive circuits 141 is different.

[0137] In this scenario, the liquid crystal response time of pixel P in pixel group 400 (first pixel group 410) corresponding to the previous charging sub-period P10 (first charging sub-period P11) can be merged with the data write time of pixel P in pixel group 400 (second pixel group 420) corresponding to the next charging sub-period P10 (second charging sub-period P12). Simultaneously, the time difference between the start of the row scan period corresponding to the first scan signal line GL and the last scan signal line GL in the image formed by pixels P of each pixel group 400 is reduced. That is, the maximum time difference between the start of liquid crystal response of pixels P in the image formed by pixels P of each pixel group 400 is reduced, thus reducing the macroscopic brightness difference at both ends of the image formed by pixels P of each pixel group 400 in the column direction Y. In this way, by superimposing images formed by different charging sub-periods P10, the brightness of adjacent pixels P can be merged to balance the overall brightness of the screen, reducing the macroscopic brightness difference at both ends of the image displayed in the column direction Y of a display period, and improving the uniformity of display brightness.

[0138] In other examples, see Figure 10 and Figure 11 The display driving circuit 140 includes multiple gate driving circuits 141, each gate driving circuit 141 being connected to multiple scan signal lines GL of a scan signal line group GL10. This configuration minimizes changes to the circuit structure, reduces adjustment difficulty, and facilitates fabrication.

[0139] The plurality of gate drive circuits 141 are configured to drive sequentially within a charging period P1, and in two adjacent gate drive circuits 141, the output signal of any shift register RS ​​in one gate drive circuit 141, except for the first shift register RS1 and / or the last shift register RS(N), is located between the output signals of the two cascaded shift register RS ​​in the other gate drive circuit 141.

[0140] Here, among the multiple gate drive circuits 141, at least two of the multiple shift registers RS in the gate drive circuits 141 may have opposite cascade directions, i.e., opposite scan sequences. That is, at least two charging sub-periods P10 have opposite scan sequences of the gate drive circuits 141, and the row scan periods in the two charging sub-periods P10 with opposite scan sequences are interleaved.

[0141] Here, in the case where the multiple gate drive circuits 141 include two gate drive circuits 141, the multiple charging sub-periods P10 include a first charging sub-period P11 and a second charging sub-period P12. The timing of the first charging sub-period P11 and the second charging sub-period P12 can be referenced, for example. Figure 5B .in, Figure 5B The illustration only takes the example of each charging sub-period P10, which includes four line scanning periods.

[0142] For example, such as Figure 5B and Figure 10 As shown, the display module 100 includes two gate drive circuits 141 and 720 scan signal lines GL. The driving sequence of the two gate drive circuits 141 can be as follows:

[0143] Scan signal line 1 (DL), scan signal line 720 (DL), scan signal line 3 (DL), scan signal line 718 (DL)... scan signal line 361 (DL), scan signal line 360 ​​(DL)... scan signal line 719 (DL), scan signal line 2.

[0144] At this time, when there are at least two gate drive circuits 141 with opposite scanning orders, the two images composed of pixels P of the two pixel groups 400 corresponding to the two gate drive circuits 141 with opposite scanning orders, one image gradually decreases in brightness from top to bottom, and the other gradually decreases in brightness from bottom to top.

[0145] In this way, the images formed by the charging sub-periods P10 of the two gate driving circuits 141 with opposite scanning order can be superimposed to make the brightness of adjacent pixels P merged to balance the overall brightness of the screen, thereby reducing the macroscopic brightness difference between the two ends of the image in the column direction Y of the final displayed image in a display period and improving the uniformity of display brightness.

[0146] In some other examples, see Figure 6 and Figure 7 The display driving circuit 140 may include a gate driving circuit 141, that is, multiple scan signal lines GL are connected to the same gate driving circuit 141.

[0147] At this time, the display module 100 also includes a gate control circuit 150, which is connected to the gate drive circuit 141 and multiple scan signal lines GL. The gate control circuit 150 is configured to control the switching on and off of the scan signal lines GL of each scan signal line group GL10 with the gate drive circuit 141.

[0148] For example, the gate control circuit 150 includes a plurality of gate control sub-circuits 151, each gate control sub-circuit 151 being disposed between the scan signal line GL of a scan signal line group GL10 and the gate drive circuit 141, and being configured to control the on and off of the scan signal line GL of a scan signal line group GL10 and the gate drive circuit 141.

[0149] For example, such as Figure 6 and Figure 7 As shown, the multiple scan signal lines GL are divided into the first scan signal line group GL11 and the second scan signal line group GL12.

[0150] At this time, the plurality of gate control sub-circuits 151 include a plurality of first gate control sub-circuits 1511 and a plurality of second gate control sub-circuits 1512.

[0151] like Figure 6 and Figure 7 As shown, the first gate control sub-circuit 1511 includes a first transistor T1. The first terminal of the first transistor T1 is coupled to the gate drive circuit 141, the second terminal is coupled to the first scan signal line GL1, and the control terminal is coupled to the first control signal line 152.

[0152] like Figure 6 and Figure 7 As shown, the second gate control sub-circuit 1512 includes a second transistor T2. The first terminal of the second transistor T2 is coupled to the gate drive circuit 141, the second terminal is coupled to the second scan signal line GL2, and the control terminal is coupled to the second control signal line 153.

[0153] It should be noted that at the same time, among the voltage signals transmitted by the first control signal line 152 and the second control signal line 153, one is at a high level and the other is at a low level, so that the first scan signal line GL1 is connected to the gate drive circuit 141 and the second scan signal line GL2 is disconnected from the gate drive circuit 141; or, so that the second scan signal line GL2 is connected to the gate drive circuit 141 and the first scan signal line GL1 is disconnected from the gate drive circuit 141.

[0154] In this configuration, the display driving circuit 140 can control the on / off state of the scan signal lines GL in different scan signal line groups GL10, using only one gate driving circuit 141, thereby reducing the size of the display device 1000 (see [link]). Figure 1 () border.

[0155] It is understandable that the way multiple pixel groups of 400 pixels P are arranged in a sequential cycle is not unique.

[0156] In some examples, see Figure 7 , Figure 9 and Figure 11 Multiple pixel groups of 400 pixels P are arranged sequentially in both the row direction X and the column direction Y.

[0157] For example, such as Figure 7 and Figure 11 As shown, the multiple scan signal lines GL include odd scan signal line groups and even scan signal line groups. The odd scan signal line groups include multiple third scan signals, and the even scan signal line groups include multiple fourth scan signal lines. The multiple third scan signal lines and multiple fourth scan signal lines are arranged alternately in the column direction Y.

[0158] It should be noted that one of the third and fourth scan signal lines is an odd-numbered scan signal line GL, and the other is an even-numbered scan signal line GL.

[0159] Based on this, two adjacent rows of pixels P include a first pixel row and a second pixel row. Pixels P in odd-numbered columns of the first pixel row and pixels P in even-numbered columns of the second pixel row are electrically connected to one of the third scan signal line and the fourth scan signal line. Pixels P in even-numbered columns of the second pixel row and pixels P in odd-numbered columns of the second pixel row are electrically connected to the other of the third scan signal line and the fourth scan signal line. The pixel circuit 13 of each column of pixels P is electrically connected to the same data line DL.

[0160] In this case, the circumferentially adjacent pixels P of pixel P in each pixel group 400 are all pixels P of other pixel groups 400. That is, the pixels P of multiple pixel groups 400 are arranged sequentially in the row direction X and column direction Y. In this way, the brightness of each pixel P can be blended with the brightness of all the circumferentially adjacent pixels P to balance the overall brightness of the screen, making the distribution of display brightness more uniform.

[0161] In other examples, see Figure 6 and Figure 10 Multiple pixel groups of 400 pixels P are arranged sequentially in the column direction Y.

[0162] For example, such as Figure 6 and Figure 10 As shown, the pixel circuit 13 of each row of pixels P is connected to the same scan signal line GL, and the pixel circuit 13 of each column of pixels P is connected to the same data line DL.

[0163] In this case, the pixel P in each pixel group 400 is adjacent to the pixel P in the column direction Y, which is the pixel P of other pixel groups 400. That is, the pixels P of multiple pixel groups 400 are arranged sequentially in the column direction Y. In this way, the brightness of each pixel P can be blended with the brightness of the pixel P adjacent to it in the column direction Y, balancing the overall brightness of the screen, making the distribution of display brightness more uniform, and the structure is simple and easy to manufacture.

[0164] Furthermore, during each charging sub-period P10, any two adjacent data lines DL are configured to output data signals with opposite polarities. In this way, during the display of the same frame image, the data signals of adjacent pixels P have opposite polarities, thus allowing for the use of spatial fusion of adjacent pixel waveforms to suppress flicker and improve display quality.

[0165] In other embodiments, see Figure 8 and Figure 9 Multiple data lines DL are divided into multiple data line groups DL10. The data lines DL in the multiple data line groups DL10 are arranged sequentially in the row direction X, and the data lines DL in each data line group DL10 are connected to the pixel circuit 13 of the pixel P in the same pixel group 400.

[0166] Here, sequential cyclic arrangement means that in any data line group DL10, between any two adjacent data lines DL, there is one data line DL from all other data line groups DL10, and the arrangement order of data lines DL in different data line groups DL10 is fixed.

[0167] For example, such as Figure 8 and Figure 9 As shown, multiple pixels P are divided into two pixel groups 400, and the pixels P of the two pixel groups 400 are arranged sequentially in the row direction X and / or column direction Y.

[0168] At this time, the multiple data lines DL are divided into the first data line group DL11 and the second data line group DL12.

[0169] The first data line group DL11 includes multiple first data lines DL1, and the second data line group DL12 includes multiple second data lines DL2. The first data lines DL1 and the second data lines DL2 are arranged sequentially in the row direction X, and the first data lines DL1 are connected to the pixel circuit 13 of pixel P in one pixel group 400, and the second data lines DL2 are connected to the pixel circuit 13 of pixel P in another pixel group 400.

[0170] In this configuration, the gate drive circuit 141 is configured to drive multiple times during a charging period P1, and to drive multiple scan signal lines GL sequentially once in each charging sub-period P10 according to the scan sequence. That is, during a display period, the gate drive circuit 141 is executed multiple times according to a preset timing sequence. The source drive circuit 142 is configured to output data signals to multiple data lines DL in a data line group DL10 during a charging sub-period P10.

[0171] In some examples, see Figure 4B The display driving circuit 140 includes multiple source driving circuits 142, each of which is connected to multiple data lines DL of a data line group DL10. This configuration minimizes changes to the circuit structure and facilitates fabrication.

[0172] Based on this, multiple source drive circuits 142 are configured to drive sequentially within a charging period P1, and the start time of each source drive circuit 142 is the same as the start time of the gate drive circuit 141 driving once.

[0173] It should be noted that the sequential driving of multiple source drive circuits 142 means that the starting times of the multiple source drive circuits 142 are different.

[0174] For example, the gate drive circuit 141 is executed repeatedly according to a preset timing sequence, and the input signal of the first shift register RS1 of the gate drive circuit 141 in the next cycle is the same as the output signal of the last shift register RS(N) of the previous cycle; and in each charging sub-period P10, a source drive circuit 142 outputs data signals to multiple data lines DL in a data line group DL10.

[0175] Here, in the case where the multiple source drive circuits 142 include two source drive circuits 142, the multiple charging sub-periods P10 include a first charging sub-period P11 and a second charging sub-period P12. The timing of the first charging sub-period P11 and the second charging sub-period P12 can be referenced. Figure 5C .in, Figure 5C The illustration only takes the example of each charging sub-period P10, which includes four line scanning periods.

[0176] It should be noted that the scanning order of the gate drive circuit 141 during different charging sub-periods P10 can be reversed or the same, and this embodiment does not specifically limit this.

[0177] In this case, the circuit structure of the gate driving circuit 141 does not require adjustment, making it easy to fabricate. The liquid crystal response time of pixel P in pixel group 400 corresponding to the previous charging sub-period P10 (first charging sub-period P11) can be merged with the data writing time of pixel P in pixel group 400 corresponding to the next charging sub-period P10 (second charging sub-period P12). In this way, the image superposition formed by different charging sub-periods P10 can be used to balance the brightness of adjacent pixels P, thereby reducing the macroscopic brightness difference at both ends of the image displayed in the column direction Y in a display period and improving the uniformity of display brightness.

[0178] In other examples, such as Figure 8 and Figure 9 As shown, the display driving circuit 140 may include a source driving circuit 142, that is, multiple data lines DL are connected to the same source driving circuit 142.

[0179] At this time, refer to Figure 8 and Figure 9 The display module 100 also includes a source control circuit 160, which is connected to the source drive circuit 142 and multiple data lines DL. The source control circuit 160 is configured to control the connection and disconnection of the data lines DL of each data line group DL10 with the source drive circuit 142.

[0180] For example, the source control circuit 160 includes a plurality of source control sub-circuits 161, each source control sub-circuit 161 being disposed between the data line DL of a data line group DL10 and the source drive circuit 142, and being configured to control the connection and disconnection of the data line DL of the data line group DL10 and the source drive circuit 142.

[0181] For example, such as Figure 8 and Figure 9 As shown, the multiple data lines DL are divided into the first data line group DL11 and the second data line group DL12.

[0182] At this time, the multiple source control sub-circuits 161 include multiple first source control sub-circuits 1611 and multiple second source control sub-circuits 1612.

[0183] like Figure 8 and Figure 9 As shown, the first source control sub-circuit 1611 includes a third transistor T3. The first terminal of the third transistor T3 is coupled to the source drive circuit 142, the second terminal is coupled to the first data line DL1, and the control terminal is coupled to the third control signal line 162.

[0184] like Figure 8 and Figure 9As shown, the second source control sub-circuit 1612 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is coupled to the source control sub-circuit 161, the second terminal is coupled to the second data line DL2, and the control terminal is coupled to the fourth control signal line 163.

[0185] It should be noted that at the same time, among the voltage signals transmitted by the third control signal line 162 and the fourth control signal line 163, one is at a high level and the other is at a low level, so that the first data line DL1 is connected to the source drive circuit 142 and the second scan signal line GL2 is disconnected from the source drive circuit 142; or, so that the second data line DL2 is connected to the source drive circuit 142 and the first data line DL1 is disconnected from the source drive circuit 142.

[0186] In this configuration, the display driver circuit 140 can control the on / off state of data lines DL in different data line groups DL10 by including only one source driver circuit 142, thereby reducing the number of source driver circuits 142 and reducing the size of the display device 1000 (see [reference]). Figure 1 () border.

[0187] It is understandable that the way multiple pixel groups of 400 pixels P are arranged in a sequential cycle is not unique.

[0188] In some examples, see Figure 9 Multiple pixel groups of 400 pixels P are arranged sequentially in both the row direction X and the column direction Y.

[0189] For example, such as Figure 9 As shown, the multiple data lines DL include odd data line groups and even data line groups. The odd data line groups include multiple third data lines, and the even data line groups include multiple fourth data lines. The multiple third data lines and multiple fourth data lines are arranged alternately in the row direction X.

[0190] It should be noted that one of the third and fourth data lines is the odd-numbered data line DL, and the other is the even-numbered data line DL.

[0191] Based on this, two adjacent columns of pixels P include a first pixel column and a second pixel column. Pixels P in odd-numbered rows of the first pixel column and pixels P in even-numbered rows of the second pixel column are electrically connected to one of the third data line and the fourth data line. Pixels P in even-numbered rows of the second pixel column and pixels P in odd-numbered rows of the second pixel column are electrically connected to the other of the third data line and the fourth data line. Furthermore, the pixel circuit 13 of each row of pixels P is electrically connected to the same scan signal line GL.

[0192] In this case, the circumferentially adjacent pixels P of pixel P in each pixel group 400 are all pixels P of other pixel groups 400. That is, the pixels P of multiple pixel groups 400 are arranged sequentially in the row direction X and column direction Y. In this way, the brightness of each pixel P can be blended with the brightness of all the circumferentially adjacent pixels P to balance the overall brightness of the screen, making the distribution of display brightness more uniform.

[0193] In other examples, see Figure 8 Multiple pixel groups of 400 pixels P are arranged sequentially in the row direction X.

[0194] For example, such as Figure 8 As shown, the pixel circuit 13 of each row of pixels P is connected to the same scan signal line GL, and the pixel circuit 13 of each column of pixels P is connected to the same data line DL. The structure is simple and easy to manufacture.

[0195] In this case, the pixel P in each pixel group 400 is adjacent to the pixel P in the row direction X, which is the pixel P of other pixel groups 400. That is, the pixels P of multiple pixel groups 400 are arranged sequentially in the row direction X. In this way, the brightness of each pixel P can be blended with the brightness of the pixel P adjacent to it in the row direction X, balancing the overall brightness of the screen, making the distribution of display brightness more uniform, and the structure is simple and easy to manufacture.

[0196] Furthermore, within the same data line group DL10, any two adjacent data lines DL are configured to output data signals with opposite polarities. This ensures that during the display of the same frame of image, the data signals of adjacent pixels P have opposite polarities, thus allowing for the use of spatial fusion of adjacent pixel waveforms to suppress flicker and improve display quality.

[0197] Some embodiments of this disclosure also provide a display driving method that can be applied to the display module described in any of the above embodiments.

[0198] During a display period, see Figure 12 The display driving method includes S100 to S200.

[0199] During each charging sub-period P10, the display driving method includes S100.

[0200] S100: Write data signals to each pixel in one of the multiple pixel groups.

[0201] In some examples, the above S100 includes: See Figure 6 and Figure 8 Data signals are written to multiple rows of pixels P with intervals set, or to multiple columns of pixels P with intervals set.

[0202] In this case, the pixels P in each pixel group 400 that are adjacent to each other in the row direction X or column direction Y can all be pixels P from other pixel groups 400. That is, the pixels P of multiple pixel groups 400 are arranged sequentially in the row direction X or column direction Y. In this way, the brightness of each pixel P can be blended with the brightness of the adjacent pixels P in the column direction Y, balancing the overall brightness of the screen, making the distribution of display brightness more uniform, and the structure is simple and easy to manufacture.

[0203] In other examples, the above S100 includes: (See below) Figure 7 and Figure 9 Data signals are written to multiple pixels P that are spaced apart in both the row direction X and the column direction Y.

[0204] In this case, the circumferentially adjacent pixels P of pixel P in each pixel group 400 can all be pixels P of other pixel groups 400. That is, the pixels P of multiple pixel groups 400 are arranged sequentially in both the row direction X and the column direction Y. In this way, the brightness of each pixel P can be blended with the brightness of all the circumferentially adjacent pixels P to balance the overall brightness of the screen, making the distribution of display brightness more uniform.

[0205] During the light-emitting period P2, the display driving method includes S200.

[0206] S200: The backlight emits a single color of light.

[0207] The backlight emits a single color of light to generate multiple sub-images, each of which includes multiple pixels P in a pixel group 400.

[0208] In multiple charging sub-periods P10, the liquid crystal response time of pixel P of pixel group 400 corresponding to the previous charging sub-period P10 can be partially merged with the data write time of pixel P of pixel group 400 corresponding to the next charging sub-period P10.

[0209] In this scenario, during the light-emitting period P2, the long axis of the liquid crystal of pixel P in pixel group 400 corresponding to the previous charging sub-period P10 can quickly deflect to the electric field direction. This means the brightness of the image formed by pixel P in pixel group 400 corresponding to the previous charging sub-period P10 is greater than the brightness of the image formed by pixel P in pixel group 400 corresponding to the subsequent charging sub-period P10. Thus, by superimposing images formed in different charging sub-periods P10, the brightness of adjacent pixels P can be blended to balance the overall brightness of the image, reducing the macroscopic brightness difference between the two ends of the final displayed image in the column direction Y during a display period, and improving the uniformity of the displayed brightness.

[0210] Among them, see Figure 5A and Figure 5CThe start times of multiple charging sub-segments P10 are arranged sequentially, and in two adjacent charging sub-segments P10, the start time of the latter charging sub-segment P10 is after the end time of the former charging sub-segment P10.

[0211] In addition, see Figure 5B Each charging sub-period P10 includes multiple line scan periods. During a line scan period, data signals are written to a row of pixels P in a pixel group 400. Furthermore, the start times of the multiple charging sub-periods P10 are arranged sequentially, and in two adjacent charging sub-periods P10, except for the first and / or last line scan period, any line scan period in one charging sub-period P10 is located between two adjacent line scan periods in the other charging sub-period P10.

[0212] In some embodiments, such as Figure 6 and Figure 7 As shown, multiple scan signal lines GL are divided into multiple scan signal line groups GL10. The scan signal lines GL in the multiple scan signal line groups GL10 are arranged sequentially in the column direction Y, and the scan signal lines GL in each scan signal line group GL10 are connected to the pixel circuit 13 of the pixel P in the same pixel group 400.

[0213] At this time, refer to Figure 13 The above S100 includes S110 to S120.

[0214] S110: Gate drive circuit 141 drives multiple scan signal lines GL in a scan signal line group GL10 in sequence according to the scan order.

[0215] See here. Figure 5A , Figure 5B , Figure 6 and Figure 10 Each charging sub-period P10 includes multiple line scanning periods, and the multiple line scanning periods in each charging sub-period P10 correspond one-to-one with the multiple scanning signal lines GL of a scanning signal line group GL10.

[0216] In some examples, such as Figure 5A and Figure 6 As shown, the start times of multiple charging sub-segments P10 are arranged sequentially, and in two adjacent charging sub-segments P10, the start time of the latter charging sub-segment P10 is after the end time of the former charging sub-segment P10. Furthermore, in two adjacent charging sub-segments P10, the time difference between the end time of the last line scan period of the former charging sub-segment P10 and the start time of the first line scan period of the latter charging sub-segment P10 can be the same as the time difference between the start times of two adjacent line scan periods within the charging sub-segment P10.

[0217] In other examples, such as Figure 5B and Figure 10 As shown, the start times of the multiple charging sub-periods P10 are arranged sequentially. Furthermore, in any two adjacent charging sub-periods P10, except for the first and / or last row scan period, any row scan period in one charging sub-period P10 is located between two adjacent row scan periods in the other charging sub-period P10. Additionally, the scanning order of the gate drive circuits 141 in at least two charging sub-periods P10 can be reversed.

[0218] S120: The source drive circuit 142 outputs data signals to all data lines DL.

[0219] In other embodiments, such as Figure 8 and Figure 9 As shown, when multiple data lines DL are divided into multiple data line groups DL10, and the data lines DL in the multiple data line groups DL10 are arranged sequentially in the row direction X, and the data lines DL in each data line group DL10 are connected to the pixel circuit 13 of the pixel P in the same pixel group 400, refer to Figure 14 The above S100 includes S130 to S140.

[0220] S130: The gate drive circuit drives all scan signal lines sequentially according to the scan order.

[0221] Among them, see Figure 5C During a charging period P1, the gate drive circuit 141 repeats the operation multiple times according to a preset timing sequence, each time corresponding to a charging sub-period P10.

[0222] S140: The source drive circuit outputs data signals to multiple data lines in a data line group.

[0223] Among them, see Figure 5C , Figure 8 and Figure 9 During each charging sub-period P10, the source drive circuit 142 outputs data signals to multiple data lines DL in a data line group DL10.

[0224] In some embodiments, see Figure 6 Among the aforementioned multiple pixels P, the periphery of a non-edge pixel P includes at least one pixel P with a different polarity.

[0225] For example, such as Figure 6 As shown, a pixel P located outside the edge has a different polarity than the four surrounding pixels P. For example, as... Figure 7As shown, the pixel P located on a non-edge has a different polarity than the two pixels P on either side of it in the column direction Y. For example, as... Figure 9 As shown, the pixel P located on the non-edge has a different polarity than the three pixels P surrounding it.

[0226] In some embodiments, see Figure 2 The display module 100 displays a frame cycle consisting of three display periods, which respectively display a red image, a blue image, and a green image, thereby achieving full-color display.

[0227] In addition, see Figure 5B and Figure 10 Within a display period, at least two sub-periods P10 correspond to two pixel groups 400 with different driving sequences. That is, the scanning order of the two gate driving circuits 141 electrically connected to each pixel P in the two pixel groups 400 with different driving sequences is different.

[0228] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display module, comprising a display panel and a backlight, wherein the display panel includes a plurality of pixels arranged in an array, a plurality of scan signal lines extending along a row direction, and a plurality of data lines extending along a column direction, wherein the plurality of scan signal lines and the data lines are electrically connected to the plurality of pixels respectively, for driving the liquid crystal of the pixels to rotate, characterized in that, The display module further includes a display driving circuit, which includes a gate driving circuit and a source driving circuit; the gate driving circuit is connected to the plurality of scan signal lines, and the source driving circuit is connected to the plurality of data lines. One frame cycle displayed by the display module includes at least one display period, which is configured to display an image of one color. The display period includes a charging period and a light-emitting period. Within a display period, the start time of the charging period is earlier than the start time of the light-emitting period. Within a display period, the end time of the charging period is earlier than the end time of the light-emitting period; The plurality of pixels are divided into a plurality of pixel groups; the charging period includes a plurality of charging sub-periods; the display driving circuit is configured to write data signals to a pixel in one of the plurality of pixel groups in each charging sub-period to drive the liquid crystal rotation of the pixel in the one pixel group. The light emitted by the backlight during the light-emitting period passes through the display panel; The multiple data lines are divided into multiple data line groups, and the data lines in the multiple data line groups are arranged sequentially and cyclically in the row direction, and the data lines in each data line group are electrically connected to the pixels in the same pixel group. The gate drive circuit is configured to drive the gate multiple times during a charging period, and to drive the multiple scan signal lines once in the scanning order during each charging sub-period. The source drive circuit is configured to output data signals to multiple data lines in a data line group during a charging sub-period. The driving order of the multiple pixel groups is the same.

2. The display module according to claim 1, characterized in that, The charging period and the light-emitting period do not overlap; The start time of the light-emitting period is set to satisfy the following condition: after the charging period ends, and the liquid crystal of the last charged pixel in the display period is still within the time period of flipping.

3. The display module according to claim 1, characterized in that, The multiple scan signal lines are divided into multiple scan signal line groups. The scan signal lines in the multiple scan signal line groups are arranged sequentially in the column direction, and the scan signal lines in each scan signal line group are electrically connected to the pixels in the same pixel group. The gate drive circuit is configured to drive multiple scan signal lines in a scan signal line group sequentially in a scan order during a charging sub-period. The source drive circuit is configured to output data signals to the plurality of data lines during each charging sub-period.

4. The display module according to claim 3, characterized in that, The display driving circuit includes multiple gate driving circuits, and each gate driving circuit is connected to multiple scan signal lines of a scan signal line group; The plurality of gate driving circuits are configured to drive sequentially within a charging period, and in two adjacent gate driving circuits, the start time of the latter gate driving circuit is after the end time of the former gate driving circuit.

5. The display module according to claim 3, characterized in that, The display driving circuit includes multiple gate driving circuits, each gate driving circuit being connected to multiple scan signal lines of a scan signal line group, and each gate driving circuit including multiple cascaded shift registers. The plurality of gate drive circuits are configured to drive sequentially during a charging period, and in two adjacent gate drive circuits, the output signal of any shift register in one gate drive circuit, except for the first shift register and / or the last shift register, is located between the output signals of the two cascaded shift registers in the other gate drive circuit.

6. The display module according to claim 3, characterized in that, The multiple scan signal lines are connected to the same gate driving circuit, and the display module further includes: A gate control circuit is connected to the gate drive circuit and the plurality of scan signal lines; the gate control circuit is configured to control the switching on and off of the scan signal lines of each scan signal line group with the gate drive circuit.

7. The display module according to any one of claims 3 to 6, characterized in that, The plurality of scanning signal lines include an odd scanning signal line group and an even scanning signal line group. The odd scanning signal line group includes a plurality of third scanning signal lines, and the even scanning signal line group includes a plurality of fourth scanning signal lines. The plurality of third scanning signal lines and the plurality of fourth scanning signal lines are arranged alternately in the column direction. Two adjacent rows of pixels include the first pixel row and the second pixel row; The pixels in the odd-numbered columns of the first pixel row and the pixels in the even-numbered columns of the second pixel row are electrically connected to one of the third scan signal line and the fourth scan signal line; The pixels in the even-numbered columns of the second pixel row and the pixels in the odd-numbered columns of the second pixel row are electrically connected to the other of the third scan signal line and the fourth scan signal line; Each column of pixels is electrically connected to the same data line.

8. The display module according to claim 1, characterized in that, The display driving circuit includes multiple source driving circuits, and each source driving circuit is connected to multiple data lines of a data line group; The plurality of source drive circuits are configured to drive sequentially within a charging period, and the starting time of each source drive circuit is the same as the starting time of the gate drive circuit driving once.

9. The display module according to claim 8, characterized in that, The multiple data lines are connected to the same source drive circuit, and the display module further includes: A source control circuit is connected to the source drive circuit and the plurality of data lines; the source control circuit is configured to control the connection and disconnection of the data lines of each data line group with the source drive circuit.

10. The display module according to claim 8 or 9, characterized in that, The multiple data lines include an odd data line group and an even data line group. The odd data line group includes multiple third data lines, and the even data line group includes multiple fourth data lines. The multiple third data lines and the multiple fourth data lines are arranged alternately in the row direction. Two adjacent columns of pixels include the first pixel column and the second pixel column; The pixels in the odd-numbered rows of the first pixel column and the pixels in the even-numbered rows of the second pixel column are electrically connected to one of the third data line and the fourth data line; The pixels in the even-numbered rows of the second pixel column and the pixels in the odd-numbered rows of the second pixel column are electrically connected to the other of the third data line and the fourth data line; Each row of pixels is electrically connected to the same scan signal line.

11. The display module according to any one of claims 3 to 6, 8 or 9, characterized in that, Each row of pixels is electrically connected to the same scan signal line, and each column of pixels is electrically connected to the same data line.

12. The display module according to any one of claims 3 to 6, 8 or 9, characterized in that, In the same data line group, any two adjacent data lines are configured such that the polarity of the output data signals is opposite.

13. A display device, characterized in that, The display module includes any one of claims 1 to 12, wherein the display device is an active display device or a projection display device.

14. A display driving method for a display module, characterized in that, The display module is applied to any one of claims 1 to 12, the display module comprising a display panel and a backlight, the display panel comprising a plurality of pixels arranged in an array, the plurality of pixels being divided into a plurality of pixel groups; The display module displays a frame cycle including at least one display period, the display period displaying an image of one color; The display period includes a charging period and a light-emitting period. Within a display period, the start time of the charging period is earlier than the start time of the light-emitting period. Within a display period, the end time of the charging period is earlier than the end time of the light-emitting period; The charging period includes multiple sub-charging periods; During one of the display periods, the display driving method includes: During each charging sub-period, data signals are written to each pixel in one of the multiple pixel groups; During the light-emitting period, the backlight emits a single color of light.

15. The display driving method according to claim 14, characterized in that, The start times of the multiple charging sub-segments are arranged sequentially, and in two adjacent charging sub-segments, the start time of the latter charging sub-segment is after the end time of the former charging sub-segment.

16. The display driving method according to claim 14, characterized in that, Each of the charging sub-periods includes multiple row scan periods, during which write data signals are sent to a row of pixels in a pixel group; The start times of the plurality of charging sub-segments are arranged sequentially, and in two adjacent charging sub-segments, except for the first and / or the last row scan period, any row scan period in one charging sub-segment is located between two adjacent row scan periods in the other charging sub-segment.

17. The display driving method according to claim 14, characterized in that, The step of writing data signals to each pixel in one of the plurality of pixel groups includes: Write data signals to multiple rows of pixels with a set interval, or write data signals to multiple columns of pixels with a set interval.

18. The display driving method according to claim 14, characterized in that, The step of writing data signals to each pixel in one of the plurality of pixel groups includes: Data signals are written to multiple pixels that are spaced apart in both the row and column directions.

19. The display driving method according to any one of claims 14 to 18, characterized in that, Among the plurality of pixels, the periphery of a non-edge pixel includes at least one pixel with a different polarity.

20. The display driving method according to any one of claims 14 to 18, characterized in that, The display module displays a frame cycle consisting of three display periods, which respectively display a red image, a blue image, and a green image.

Images