Chip, preparation method thereof and electronic device

Abstract

Embodiments of the present application provide a chip, a preparation method thereof and an electronic device, and relate to the technical field of semiconductors, and are used for improving the yield of a conductive component in a chip. The chip comprises a first dielectric layer, the first dielectric layer comprising a first region and a second region; a resistance layer and a resistance protection layer are sequentially stacked in the first region on the first dielectric layer; the resistance protection layer comprises an etching stop layer and an etching barrier layer, the etching stop layer being arranged between the etching barrier layer and the resistance layer; the etching barrier layer has a first via hole, and the etching stop layer has a second via hole. A second dielectric layer is arranged on the first dielectric layer and covers the resistance protection layer. A first conductive column penetrates through the second dielectric layer and is electrically connected to the resistance layer through the first via hole and the second via hole; wherein the etching barrier layer is used as an etching protection layer in a first etching process for forming the resistance layer, and the etching stop layer is used as an etching protection layer in a second etching process for forming the first via hole.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, and an electronic device. Background Technology

[0002] With the development of electronic technology, users have increasingly higher performance requirements for electronic devices, resulting in larger and more numerous chips in these devices. However, as electronic devices continue to develop towards integration and ultra-thinness, the chips within them must also become smaller.

[0003] In some current products, chips not only include active devices such as transistors, but also passive devices such as resistor layers. In such chips that integrate active and passive devices, the yield rate of the resistor layer has always been a technical hurdle that is difficult for those skilled in the art to overcome. Summary of the Invention

[0004] This application provides a chip and its fabrication method, as well as an electronic device, for improving the yield of the resistive layer in the chip.

[0005] To achieve the above objectives, this embodiment adopts the following technical solution:

[0006] In a first aspect, this application provides a chip, which may be a bare chip or a packaged chip.

[0007] The chip includes a first dielectric layer, which includes a first region and a second region; a resistive layer and a resistive protection layer are sequentially stacked on the first dielectric layer within the first region. The resistive protection layer includes an etch stop layer and an etch barrier layer, with the etch stop layer disposed between the etch barrier layer and the resistive layer. A second dielectric layer is disposed on the first dielectric layer and covers the resistive protection layer; the first and second dielectric layers are made of different materials. A first conductive pillar penetrates the second dielectric layer and the resistive protection layer and is electrically connected to the resistive layer. The first conductive pillar includes a first conductive pillar body and a first filler layer, which covers the side and bottom surfaces of the first conductive pillar body; the thickness of the portion of the first filler layer in contact with the second dielectric layer is greater than the thickness of the portion of the first filler layer located on the bottom surface of the first conductive pillar body.

[0008] The chip provided in this application embodiment has a resistor protection layer above the resistor layer, comprising an etch stop layer and an etch barrier layer. The etch barrier layer acts as a barrier layer during the etching of the resistive film to form the resistor layer, protecting the pattern shape of the resistor layer. The etch stop layer acts as a stop layer during the etching barrier layer to form the first via where the first conductive pillar is placed. In this way, due to the presence of the etch stop layer, regardless of the etching process used to form an opening on the etch barrier layer, it has almost no impact on the resistor layer below the etch stop layer, ensuring the yield of the resistor layer. When the first conductive pillar needs to be fabricated subsequently, a separate etching step is used to form the second via on the etch stop layer. By adjusting the etching conditions, damage to the resistor layer can be minimized, improving the yield of the resistor layer. Moreover, by not exposing the resistor layer before fabricating the first conductive pillar, the exposure time of the resistor layer can be reduced, lowering the probability of oxidation and further improving the yield of the resistor layer. Furthermore, making the thickness of the portion of the first filler layer in contact with the second dielectric layer relatively large can improve the filling effect on the gap between the first conductive pillar body and the second dielectric layer, and improve the adhesion between the first conductive pillar body and the second dielectric layer. Making the thickness of the portion of the first filler layer located on the bottom surface of the first conductive pillar body relatively small can reduce the impact of the first filler layer on the conductivity of the first conductive pillar.

[0009] In one possible implementation, the resistive layer includes a first portion in contact with the first conductive pillar and a second portion in contact with the resistive protective layer. The ratio of the thickness of the first portion to the thickness of the second portion ranges from 0.2 to 1. In the chip provided by this application embodiment, the resistive layer is protected by the resistive protective layer during fabrication, preventing exposure of the resistive layer before the first conductive pillar is fabricated. This results in a short exposure time and minimal damage to the first portion. Furthermore, when exposure of the resistive layer is necessary, a separate etching process is used to create an opening in the resistive protective layer, minimizing over-etching damage to the first portion. Therefore, the chip provided by this application embodiment reduces damage to the first portion of the resistive layer located below the first conductive pillar during chip fabrication, achieving a thickness ratio of 0.2 to 1 for the first portion of the resistive layer. Compared to related technologies where the first portion of the resistive layer is almost entirely damaged, the actual resistance value of the resistive layer in the chip of this application is closer to the set resistance value, effectively mitigating resistance deviations caused by resistive layer damage and improving chip performance.

[0010] In one possible implementation, the resistor protection layer further includes an oxide barrier layer disposed between the etch stop layer and the resistor layer. The oxide barrier layer has a third via that communicates with the second via. By providing the oxide barrier layer, oxidation of the resistor layer by the resistor protection layer can be prevented.

[0011] In one possible implementation, the oxide barrier layer is made of silicon nitride, the etch stop layer is made of silicon oxide, and the etch barrier layer is made of silicon nitride. This is a low-cost implementation.

[0012] In one possible implementation, the resistive layer is made of titanium nitride, tantalum nitride, or titanium oxide. This is a low-cost implementation.

[0013] In one possible implementation, the chip further includes a second conductive pillar and a transistor; the transistor is disposed on the side of the first dielectric layer away from the second dielectric layer, and the projection of the transistor on the first dielectric layer does not overlap with the projection of the resistive layer on the first dielectric layer; the second conductive pillar penetrates the second dielectric layer and the first dielectric layer and is electrically connected to the transistor. The fabrication provided by the embodiments of this application can achieve, while ensuring the yield of the resistive layer product, the fabrication of the first conductive pillar in the region where the resistive layer is located and the second conductive pillar in the region where the transistor is located.

[0014] In one possible implementation, the second conductive pillar includes a second conductive pillar body and a second filling layer; the second filling layer covers the side surface of the second conductive pillar body, and the second conductive pillar body is in contact with the transistor. This is one possible structure.

[0015] In one possible implementation, the second conductive pillar further includes a third conductive pillar body and a third filling layer; the third conductive pillar body is disposed on the side of the second conductive pillar body away from the transistor, and the third filling layer covers the side and bottom surfaces of the third conductive pillar body. This is one possible structure.

[0016] In one possible implementation, the thickness of the portion of the third filler layer located on the side of the third conductive post body is greater than the thickness of the portion of the third filler layer located on the bottom surface of the third conductive post body. This is one possible structure.

[0017] In one possible implementation, the body of the second conductive pillar extends into the transistor, and the portion of the second conductive pillar extending into the transistor contacts the surface of the first dielectric layer away from the second dielectric layer. In this way, even if acidic polishing or etching solutions flow in from the gap between the second conductive pillar and the second dielectric film during subsequent fabrication, they will first contact the portion of the second conductive pillar located within the groove, thus reducing the damage to the transistor caused by the acidic polishing or etching solutions.

[0018] In one possible implementation, the chip further includes a first conductive pattern and a second conductive pattern; the first and second conductive patterns are disposed on the side of the second dielectric layer away from the first dielectric layer; a first conductive post is electrically connected to the first conductive pattern, and a second conductive post is electrically connected to the second conductive pattern. Signals from the resistive layer are transferred to the first conductive pattern via the first conductive post, and signals from the transistor are transferred to the second conductive pattern via the second conductive post.

[0019] A second aspect of the embodiments of this application provides an electronic device, including a chip and a circuit board according to any one of the first aspects, wherein the chip is disposed on the circuit board.

[0020] A third aspect of this application provides a method for fabricating a chip, comprising: forming a first dielectric film; sequentially forming a resistive film and a resistive protective film stacked on the first dielectric film, the resistive film covering the first dielectric film, and the resistive protective film located in a first region of the first dielectric film; the resistive protective film including an etch stop film and an etch barrier film, the etch stop film located between the etch barrier film and the resistive film; performing a first etching on the resistive film to form a resistive layer; the etch barrier film serving as an etch protection layer during the first etching process of forming the resistive layer, the resistive layer located in the first region; forming a second dielectric film; the second dielectric film being formed on the first dielectric film and covering the resistive protective film; and performing a second etching... A fourth via penetrating the second dielectric film and a first via penetrating the etch stop film are formed; an etch stop film is used as an etch protection layer in the second etch process of forming the first via; a second via is formed on the etch stop film, forming a first opening penetrating the second dielectric film and the resistive protection film, and a resistive protection layer; a first conductive pillar is formed in the first opening, and a second dielectric layer is formed; the first conductive pillar is electrically connected to the resistive layer, and the first conductive pillar includes a first conductive pillar body and a first filling layer, the first filling layer covering the side and bottom surfaces of the first conductive pillar body; the thickness of the portion of the first filling layer in contact with the second dielectric layer is greater than the thickness of the portion of the first filling layer located on the bottom surface of the first conductive pillar body.

[0021] The chip fabrication method provided in this application includes a resistive protective layer above the resistive layer comprising an etch stop layer and an etch barrier layer. The etch barrier layer acts as a barrier layer during the etching of the resistive film to form the resistive layer, protecting the pattern shape of the resistive layer. The etch stop layer acts as a stop layer during the etching barrier layer to form the opening for placing the first conductive pillar. Thus, due to the presence of the etch stop layer, regardless of the etching process used to form the first via on the etch barrier film during the second etching process, it has almost no impact on the resistive layer below the etch stop layer. This improves both the yield of the resistive layer and the process compatibility during chip fabrication. When the first conductive pillar needs to be fabricated subsequently, a separate etching step is used to form the second via on the etch stop layer. By adjusting the etching conditions, damage to the resistive layer can be minimized, further improving the yield of the resistive layer. Moreover, by not exposing the resistive layer before fabricating the first conductive pillar, the exposure time of the resistive layer can be reduced, lowering the probability of oxidation and further improving the yield of the resistive layer. Furthermore, making the thickness of the portion of the first filler layer in contact with the second dielectric layer relatively large can improve the filling effect on the gap between the first conductive pillar body and the second dielectric layer, and improve the adhesion between the first conductive pillar body and the second dielectric layer. Making the thickness of the portion of the first filler layer located on the bottom surface of the first conductive pillar body relatively small can reduce the impact of the first filler layer on the conductivity of the first conductive pillar.

[0022] In one possible implementation, before forming the first dielectric film, the fabrication method further includes: forming a transistor; the projection of the transistor on the first dielectric film does not overlap with the projection of the resistive layer on the first dielectric film; while forming a first opening penetrating the second dielectric film, the fabrication method further includes: forming a second opening penetrating the second dielectric film and the first dielectric film to form the first dielectric layer; the second opening exposes the transistor. The fabrication method provided in this application allows for compatibility between the fabrication processes of the first conductive pillar in the region where the resistive layer is located and the second conductive pillar in the region where the transistor is located. For example, the first and second openings can be formed simultaneously. In other words, the chip fabrication method provided in this application can achieve compatibility between the fabrication processes of the first and second conductive pillars while ensuring the yield of the resistive layer product.

[0023] In one possible implementation, before removing the portion of the resistive protective film located below the first opening, the fabrication method further includes: forming a first filling film and a second filling film; the first filling film covers the sidewall of the first opening, and the second filling film covers the sidewall of the second opening. The presence of the second filling film can improve the adhesion between the subsequently formed second conductive pillar body and the second opening.

[0024] In one possible implementation, before removing the portion of the resistive protective film located below the first opening, the fabrication method further includes: forming a second conductive pillar body within the second opening, the second conductive pillar body contacting the transistor, and the portion of the second filling film located on the side of the second conductive pillar body serving as a second filling layer. This is one possible implementation.

[0025] In one possible implementation, a first conductive pillar is formed within a first opening, and a second dielectric layer is formed, comprising: forming a third filling film covering the second dielectric film; forming a conductive film on the third filling film; and grinding the third filling film, the conductive film, and the second dielectric film to form a first filling layer, a first conductive pillar body, and a second dielectric layer; the first conductive pillar body is located within the first opening, and the portion of the third filling film within the first opening and the remaining portion of the first filling film constitute the first filling layer; the first filling layer covers the bottom and side surfaces of the first conductive pillar body; the first conductive pillar includes the first filling layer and the first conductive pillar body. Using the above preparation method to form the first conductive pillar, the chemical mechanical grinding of the second conductive pillar can be completed simultaneously during the preparation of the first conductive pillar, thus simultaneously completing the preparation of the second conductive pillar. Therefore, it can reduce process steps, lower costs, and improve efficiency.

[0026] In one possible implementation, a third conductive pillar body and a third filling layer are formed simultaneously with the first filling layer, the first conductive pillar body, and the second dielectric layer. The third conductive pillar body is disposed on the side of the second conductive pillar body away from the transistor. The portion of the third filling film located at the second opening and the portion of the second filling film located on the side of the third conductive pillar body constitute the third filling layer, which covers the bottom and side surfaces of the third conductive pillar body. This is one possible structure.

[0027] In one possible implementation, the resistive protective film further includes an oxide barrier film; the oxide barrier film is disposed between the etch stop film and the resistive layer; the fabrication method further includes forming a third via penetrating the oxide barrier film, the third via being connected to the second via. By providing the oxide barrier film, oxidation of the resistive layer by the resistive protective film can be prevented. Attached Figure Description

[0028] Figure 1 A schematic diagram of the frame of an electronic device provided in an embodiment of this application;

[0029] Figures 2A-2D This is a schematic diagram illustrating the chip fabrication process according to an embodiment of this application;

[0030] Figures 3-5 This is a schematic diagram illustrating the fabrication process of another chip according to an embodiment of this application;

[0031] Figure 6 A flowchart illustrating a chip fabrication method provided in this application embodiment;

[0032] Figures 7-16 This is a schematic diagram illustrating the chip fabrication process provided in an embodiment of this application.

[0033] Figure label:

[0034] 1-Electronic device; 2-Display module; 3-Mid-frame; 4-Housing; 5-Cover plate; 200-Substrate; 10-Transistor; 20-Adapter pattern; 30′-First dielectric film; 30-First dielectric layer; 40′-Resistor layer film; 40-Resistor layer; 41-First part; 42-Second part; 50-Resistor protection layer; 51-Oxide barrier layer; 52-Etch stop layer; 53-Etch stop layer; 50′-Resistor protection film; 51′-Oxide barrier film; 52′-Etch stop film; 53′-Etch stop film; 50″-Resistor protection base film; 51″-Oxide barrier base film; 52″-Etch stop base film; 53″-Etch stop base film; 531-First via; 521-Second via; 511-Third via; 60 71′-Second dielectric film; 60-Second dielectric layer; 62-Fourth via; 71′-Third opening; 71-First conductive pillar; 711′-Third filling film; 711-First filling layer; 7111-First filling portion; 7112-Second filling portion; 712′-Conductive film; 712-First conductive pillar body; 72′-Second opening; 72-Second conductive pillar; 721-Second conductive pillar body; 722-Second filling layer; 723-Third conductive pillar body; 724-Third filling layer; 73′-First opening; 80′-First filling base film; 81-First filling film; 82-Second filling film; 821-Third filling portion; 822-Fourth filling portion; 91-First conductive pattern; 92-Second conductive pattern. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0036] In the following embodiments of this application, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0037] In the embodiments of this application, "upper", "lower", "left" and "right" are not limited to the orientation of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0038] In this application, unless the context otherwise requires, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to," throughout the specification and claims. In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0039] In describing some embodiments, the term "electrical connection" and its derivative expressions may be used. For example, the term "electrical connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "electrical connection" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0040] In the embodiments of this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0041] Exemplary embodiments are described in this application with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0042] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). In-vehicle electronics products include in-vehicle navigation systems and in-vehicle high-density digital video discs (DVDs). Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics products include servers, storage devices, base stations, and other communication equipment.

[0043] This application does not impose any special limitations on the specific form of the above-described electronic device. For ease of explanation, the following embodiments all use a mobile phone as an example.

[0044] In this case, such as Figure 1 As shown, the electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0045] The display module 2 has a light-emitting side from which the display image can be seen and a back side opposite to the light-emitting side. The back side of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0046] The aforementioned display module 2 includes a display panel (DP).

[0047] In one possible embodiment of this application, the display module 2 is a liquid crystal display module. In this case, the aforementioned display screen is a liquid crystal display (LCD). Based on this, the display module 2 also includes a backlight unit (BLU) located on the back of the LCD (away from the side of the LCD used to display images).

[0048] The backlight module provides a light source to the LCD screen, enabling each subpixel in the LCD screen to emit light in order to display an image.

[0049] Alternatively, in another possible embodiment of this application, display module 2 is an organic light-emitting diode (OLED) display module. In this case, the aforementioned display screen is an organic light-emitting diode (OLED) display screen. Since each subpixel in an OLED display screen has an electroluminescent layer, the OLED display screen can achieve self-illumination after receiving an operating voltage. In this case, the aforementioned backlight module is not required in display module 2 with an OLED display screen.

[0050] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0051] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0052] The aforementioned electronic device 1 also includes a processor (CPU) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power management integrated circuit (PMIC), a memory chip (e.g., high bandwidth memory (HBM)), an audio processor chip, a touch screen control chip, a NAND flash memory, an image sensor chip, a charging protection chip, etc., disposed on a PCB. The PCB is used to carry the aforementioned chips and to complete signal interaction with the aforementioned chips.

[0053] The reliability and other properties of the chip (or logic integrated device, or integrated circuit device) have a direct impact on the lifespan and performance of electronic devices.

[0054] Chip fabrication typically includes front end of line (FEOL), mid end of line (MEOL), and back end of line (BEOL).

[0055] like Figure 2A As shown, the front-end process is used to form a transistor. For example, the transistor includes a source (S), a drain (D), and a gate (G).

[0056] like Figure 2B As shown, the intermediate process is used to form a transition layer that brings the conductive patterns from multiple transistors to the same plane. The conductive pillars in the transition layer are electrically connected to the source (S), drain (D), and gate (G) of the transistors. The formation of the transition layer typically involves first forming a dielectric layer with vias located above the conductive patterns, and then using via-filling techniques to form the conductive pillars.

[0057] Among them, such as Figure 2C As shown, in some process nodes, the transition layer formed in the mid-stage process comprises two parts. The first part consists of a transition metal disposed on the transistor surface and a first mid-stage dielectric layer surrounding the transition metal. The transition metal is electrically connected to the source (S), drain (D), and gate (G) of the transistor. The second part consists of conductive pillars disposed on the surface of the transition metal and a second mid-stage dielectric layer surrounding the conductive pillars. The conductive pillars are electrically connected to the transition metal. The transition metal is, for example, strip-shaped, and the conductive pillars are, for example, pillar-shaped. In this application, the dielectric layer surrounding the transition metal formed in the mid-stage process is referred to as the first mid-stage dielectric layer, and the dielectric layer surrounding the conductive pillars is referred to as the second mid-stage dielectric layer.

[0058] Figure 2C This structure can optimize the arrangement of redistribution layers in the later stages of manufacturing.

[0059] For ease of explanation, the structure formed by the intermediate process will be used as an example below. Figure 2C The structure shown is illustrated as an example.

[0060] like Figure 2D As shown, the back-end process is used to form a redistribution layer located on the transition layer. Signals in the transistors are transmitted through the transition layer to the redistribution layer, thereby being led out to signal terminals on the surface of the redistribution layer. After the chip is formed, the signal terminals are exposed on the surface of the chip. For example, the signal terminals serve as pads on the chip.

[0061] Some current chips include not only active devices such as transistors, but also passive devices such as resistors. In some technologies, passive devices such as resistors are formed simultaneously during mid-process manufacturing.

[0062] In some technologies, a method for fabricating a chip integrating transistors and resistors is illustrated, comprising:

[0063] S10, such as Figure 3 As shown, on a transistor fabricated by a front-end process, a first mid-end dielectric layer and a transition metal are formed by a mid-end process. Then, a first dielectric film is formed on the first mid-end dielectric layer. Next, a stacked resistive layer and an etch barrier film are sequentially formed on a first region of the first dielectric film. Then, a second dielectric film is formed on the first dielectric film, and the second dielectric film covers the etch barrier film located on the first region.

[0064] The resistive layer and the transition metal fabricated in the first intermediate dielectric layer are misaligned, or in other words, the projection of the resistive layer onto the first dielectric film and the projection of the transition metal onto the first dielectric film do not overlap. That is, the position of the resistive layer corresponds to the first region of the first dielectric film, and the position of the transition metal corresponds to the second region of the first dielectric film; the first and second regions do not overlap.

[0065] S20, such as Figure 4 As shown, a first via is formed that penetrates the second dielectric film and the etching barrier film, and a second via is formed that penetrates the first dielectric film and the second dielectric film. The portion retained in the first dielectric film serves as the first dielectric layer, the portion retained in the second dielectric film serves as the second dielectric layer, and the portion retained in the etching barrier film serves as the etching barrier layer.

[0066] Here, the resistor layer is exposed by setting a first via, and the adapter metal is exposed by setting a second via.

[0067] S30. A first conductive post is formed in the first via, and a second conductive post is formed in the second via.

[0068] Typically, the thickness of the first dielectric film above the transition metal (the dimension in the reverse direction of the chip thickness) is greater than the thickness of the resistive protective film. Furthermore, the thickness of the portion of the second dielectric film above the transition metal is greater than the thickness of the portion above the resistive layer. In other words, the sum of the thickness of the portion of the second dielectric film above the resistive layer and the thickness of the resistive protective film is less than the sum of the thickness of the second dielectric film and the thickness of the first dielectric film. When simultaneously forming the first and second vias, since the etching time, etching solution concentration, and process environment are all the same, the first via will be completed before the second via. However, the process has not yet stopped, which causes the etching solution to continue damaging the resistive layer, affecting the yield of the resistive layer. Moreover, as... Figure 5 As shown, if the resistance layer below the first conductive post is severely damaged, and there is a gap between the first conductive post and the sidewall of the first via, it will also affect the electrical connection between the first conductive post and the part of the resistance layer located below the resistance protection layer.

[0069] Based on this, embodiments of this application provide a chip and a method for fabricating the same, which improves the yield of conductive components in the chip while being compatible with the component fabrication process.

[0070] The chip provided in this application embodiment can be applied to the aforementioned electronic device. The chip provided in this application embodiment can be an unpackaged bare chip, which may include one integrated circuit block (which may be referred to as a two-dimensional (2D) bare chip) or multiple integrated circuit blocks (which may be referred to as a three-dimensional (3D) bare chip). The chip provided in this application embodiment can also be a packaged chip, which may include one bare chip or multiple bare chips.

[0071] The following examples illustrate the chip and fabrication method provided in the embodiments of this application.

[0072] Example 1

[0073] This application provides a method for fabricating a chip, such as... Figure 6 As shown, it includes:

[0074] S000, such as Figure 7 As shown, an adapter metal 20 is provided.

[0075] In some embodiments, step S000 includes:

[0076] S010, A transistor 10 is formed on a substrate 200.

[0077] When the chip is used as a radio frequency device in electronic devices such as base stations, the substrate 200 is made of an insulating material. When the chip is used as a power device in electronic devices such as mobile phones, the substrate 200 is made of a conductive material.

[0078] Transistor 10 is a basic element in electronic circuits, having at least one lead contact for electrical connection to wiring interconnects to complete signal transmission. Transistor 10 can be a transistor, diode, etc. For example, transistor 10 is a transistor, and the lead contact of transistor 10 includes a source (S), a drain (D), and a gate (G).

[0079] A chip may include one transistor 10 or multiple transistors 10. The chip fabrication method provided in this application embodiment is only an example of a single transistor 10 in the chip, illustrating the structure of each part of the chip. When the chip includes multiple transistors 10, the multiple transistors 10 can be transistors of the same type or different types. This application embodiment does not limit the number, type, or arrangement of transistors 10 in the chip; they can be reasonably set as needed.

[0080] For example, such as Figure 7 As shown, transistor 10 includes a complementary metal-oxide-semiconductor (CMOS) device, where the source (S), drain (D), and gate (G) of the CMOS are all lead contacts of transistor 10. Among them, Figure 7 The diagram also illustrates the gate insulating layer located below the gate G and the sidewall located on the side of the gate G. Figure 7 The structure of transistor 10 shown in the diagram is for illustrative purposes only and is not intended to be limiting.

[0081] Alternatively, for example, transistor 10 is a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), etc.

[0082] S020. An inter-level dielectric (ILD) layer and a transition metal (transition metal 20) penetrating the inter-level dielectric layer are formed on the surface of transistor 10.

[0083] The shape of the top view of the adapter metal is not limited; for example, it can be any shape such as a strip or column. The adapter metal can be the adapter metal 20 in the embodiments of this application. Of course, other conductive patterns on the adapter metal can also be used as the adapter metal 20 in the embodiments of this application; this is just an illustration. The chip may include one or more adapter metals 20.

[0084] The material of the transition metal 20 may be, for example, molybdenum (Mo). The material of the interlayer dielectric layer (ILD) may be, for example, silicon nitride.

[0085] S100, such as Figure 8A As shown, a first dielectric film 30′ is formed on the adapter metal 20.

[0086] For example, the first dielectric film 30′ covers the interlayer dielectric layer (ILD) and the transition metal 20. Of course, the embodiments of this application are not limited to... Figure 7 A first dielectric film 30′ is formed on the basis of the structure shown, which is only an illustration.

[0087] S200, such as Figure 8B As shown, a resistive film 40' and a resistive protective film 50' are formed on the first dielectric film 30'.

[0088] The resistive film 40' is located on the side of the first dielectric film 30' away from the interlayer dielectric layer (ILD), and the resistive protective film 50' is located on the surface of the resistive layer 40 away from the first dielectric film 30'. The resistive film 40' covers the first dielectric film 30', and the resistive protective film 50' is located within a first region of the first dielectric film 30'.

[0089] The resistive protective film 50′ includes a multilayer dielectric cover film, wherein the multilayer dielectric cover film includes at least two dielectric cover films of different materials.

[0090] In some embodiments, such as Figure 8B As shown, step S200 includes:

[0091] S210, a resistive layer film 40' and a resistive protective base film 50″ are sequentially formed on the first dielectric film 30'.

[0092] For example, such as Figure 8B As shown, the resistive protection base film 50″ includes an oxide barrier base film 51″, an etch stop base film 52″, and an etch stop base film 53″.

[0093] In this embodiment, the materials of the etching stop substrate 52″ and the etching barrier substrate 53″ include different dielectric materials. The material of the oxide barrier substrate 51″ is an oxygen-free dielectric material.

[0094] Of course, since the oxide barrier base film 51″ is used to protect the resistive layer film 40′ from oxidation, the oxide barrier base film 51″ may not be included in the resistive protection base film 50″. Figure 8B The image is for illustrative purposes only and is not intended to be limiting.

[0095] S220. Pattern the resistive protection base film 50″ to form the resistive protection film 50′.

[0096] For example, a combination of photolithography and dry etching can be used to remove the oxide barrier film 51″, etching stop film 52″, and etching barrier film 53″ in the region where the transfer metal 20 is located (non-high-resistivity device region), while retaining the oxide barrier film 51″, etching stop film 52″, and etching barrier film 53″ in the region where the resistor layer 40 to be formed is located (high-resistivity device region). The oxide barrier film 51″, etching stop film 52″, and etching barrier film 53″ in the high-resistivity device region serve as the oxide barrier film 51′, etching stop film 52′, and etching barrier film 53′ in the resistor protection film 50′.

[0097] Regarding the division of high-resistivity device regions and non-high-resistivity device regions, for example, the region where the resistor layer 40 to be formed is located can be the high-resistivity device region, and the remaining regions can be the non-high-resistivity device regions.

[0098] S230. Pattern the resistive layer film 40′ to form the resistive layer 40.

[0099] S250, such as Figure 8C As shown, the resistive film 40′ is first etched to form the resistive layer 40.

[0100] The projection of the transition metal 20 onto the first dielectric film 30′ (or substrate 200) does not overlap with the projection of the resistive layer 40 onto the first dielectric film 30′. Alternatively, it can be understood that the transition metal 20 and the resistive layer 40 are staggered along the thickness direction of the chip.

[0101] For example, the first region where the resistive layer 40 is located is called the high-resistance region, and the second region where the transition metal 20 is located is called the low-resistance region. For example, in this embodiment, all regions of the first dielectric film 30′ other than the first region are assigned to the second region.

[0102] For example, a wet etching process can be used to pattern the resistive film 40'. An etching barrier film 53' serves as an etching protection layer during the first etching process of forming the resistive layer 40, protecting the portion of the resistive film 40' located beneath it from being etched during the first etching. The formed resistive layer 40 is located within a first region of the first dielectric film 30'.

[0103] The resistive protective film 50′ is disposed on the surface of the resistive layer 40. For example, the projection of the resistive protective film 50′ on the first dielectric film 30′ may coincide with the projection of the resistive layer 40 on the first dielectric film 30′.

[0104] The etching barrier film 53' in the resistive protective film 50' is used as an etching barrier layer for the high-resistivity device region. When removing the resistive film 40' in the non-high-resistivity device region, it serves as an etching barrier layer for the dry etching process to prevent the high-resistivity device region from being opened, thus preventing the resistive film 40' in the high-resistivity device region from being removed.

[0105] For example, the materials of the etch stop film 53′ include silicon nitride (SiN), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), silicon carbide (SiC), etc. Therefore, the materials of the subsequently formed etch stop layer 53 include SiN, SiCN, SiCON, SiC, etc.

[0106] The etching stop film 52' in the resistor protection film 50' serves as the first dielectric film 30' for etching the non-high resistance device region, forming an etching stop layer for the non-high resistance device connection hole, and is used to protect the resistor layer 40.

[0107] For example, the materials of the etch stop film 52′ include silicon oxide (SiO), SiCN, SiCON, SiC, etc. Therefore, the materials of the subsequently formed etch stop layer 52 include SiO, SiCN, SiCON, SiC, etc. The material of the etch stop film 52′ is different from the materials of the etch barrier film 53′ and the oxide barrier film 51′.

[0108] The oxide barrier film 51' in the resistive protective film 50' is used to prevent the etching stop film 52' from oxidizing the underlying resistive layer 40.

[0109] For example, the material of the oxide barrier film 51′ includes SiN, SiCN, SiCON, SiC, etc. Therefore, the material of the subsequently formed oxide barrier layer 51 includes SiN, SiCN, SiCON, SiC, etc.

[0110] In some embodiments, the first dielectric film 30′, the oxide barrier film 51′, and the etching barrier film 53′ are made of the same material. This simplifies the process and avoids frequent material changes.

[0111] The resistive layer 40 is made of a conductive material, including oxides of metals and non-metals or metal nitrides. For example, the material of the resistive layer 40 includes titanium oxide, titanium nitride, tantalum nitride, etc.

[0112] S300, such as Figure 9 As shown, a second dielectric film 60′ is formed.

[0113] The second dielectric film 60' covers the resistor protection film 50' and the first dielectric film 30'. The material of the second dielectric film 60' is different from that of the first dielectric film 30', so the materials of the final first dielectric layer and the second dielectric layer are also different.

[0114] For example, the material of the first dielectric film 30′ includes silicon nitride, and the material of the second dielectric film 60′ includes silicon oxide (e.g., silicon oxide), silicon doped oxide, silicon fluoride oxide, silicon carbon doped oxide, etc.

[0115] For example, the second dielectric film 60′ can be formed using chemical vapor deposition, physical vapor deposition or other deposition methods.

[0116] S400, such as Figure 10 As shown, through the second etching, a fourth via 62 penetrating the second dielectric film 60' and a first via 531 penetrating the etching barrier film 53' are formed. At the same time, a second opening 72' penetrating the second dielectric film 60' and the first dielectric film 30' is formed, exposing the transition metal 20.

[0117] For example, the fourth via 62 is connected to the first via 531, forming a third opening 71'. The third opening 71' and the second opening 72' can be formed by photolithography and etching. The etching stop film 52' is used as an etching protection layer in the second etching process of forming the first via 531, to protect the resistive layer 40 below the etching stop film 52' from being etched in the second etching process.

[0118] For example, such as Figure 10 As shown, in step S400, a third opening 71' and a second opening 72' are formed simultaneously. The third opening 71' penetrates the second dielectric film 60' and the etching barrier film 53', and the second opening 72' penetrates the second dielectric film 60' and the first dielectric film 30'. When the third opening 71' and the second opening 72' are formed, the first dielectric layer 30 and the etching barrier layer 53 are formed simultaneously.

[0119] During the second etching, a fourth via 62 is formed on the second dielectric film 60', and a first via 531 is formed on the etching barrier film 53'. The first via 531 and the fourth via 62 are connected to form a third opening 71'.

[0120] This application does not limit the shape and size of the third opening 71' and the second opening 72'. The second opening 72' may expose part or all of the top surface of the transition metal 20 away from the substrate 200. Alternatively, the projection of the second opening 72' onto the substrate 200 may lie within the projection of the transition metal 20 onto the substrate 200, or the projection of the second opening 72' onto the substrate 200 may coincide with the projection of the transition metal 20 onto the substrate 200. Of course, the projection of the second opening 72' onto the substrate 200 may also cover the projection of the transition metal 20 onto the substrate 200, as long as it is ensured that the second conductive post subsequently formed within the second opening 72' does not cause a short circuit to adjacent transition metals 20. Alternatively, it can be understood that the second opening 72' is located directly above the transition metal 20, and the area of ​​the second opening 72' may be smaller than the area of ​​the transition metal 20, equal to the area of ​​the transition metal 20, or larger than the area of ​​the transition metal 20. This application embodiment illustrates the example where the area of ​​the second opening 72' is smaller than the area of ​​the transition metal 20.

[0121] This application does not limit the number of third openings 71' and second openings 72'. The number of third openings 71' corresponds to the number of resistive layers 40, and the number of second openings 72' corresponds to the number of transition metals 20. It should be emphasized that one transition metal 20 can be associated with one second opening 72', meaning that only one second opening 72' can be provided above one transition metal 20. One transition metal 20 can also be associated with multiple second openings 72', meaning that multiple second openings 72' can be provided above one transition metal 20. Alternatively, multiple transition metals 20 can be associated with the same second opening 72', meaning that the same second opening 72' can be provided above multiple transition metals 20 (e.g., these multiple transition metals 20 transmit the same signal).

[0122] For ease of explanation, such as Figure 10 As shown in the embodiment of this application, the formation of a third opening 71' and a plurality of second openings 72' in step S400, with each third opening 71' corresponding to an electrode layer 40 and each second opening 72' exposing a transition metal 20 is illustrated as an example.

[0123] It is important to emphasize here that after forming the third opening 71' and the second opening 72', the etching byproducts can be removed first, and then the subsequent step S500 can be performed. The method for removing the etching byproducts can be, for example, first dry cleaning to remove most of the etching byproducts, and then wet cleaning to remove the etching byproducts more thoroughly.

[0124] S500, such as Figure 11 As shown, a first filling film 81 and a second filling film 82 are formed.

[0125] The first filling film 81 covers the sidewall of the third opening 71', and the second filling film 82 covers the sidewall of the second opening 72'. It should be noted that the embodiments of this application do not limit the thickness of the first filling film 81 and the second filling film 82 to be equal, nor do they limit the thickness of the first filling film 81 to be equal at all locations, nor do they limit the thickness of the second filling film 82 to be equal at all locations.

[0126] In this embodiment of the application, the sidewall of each third opening 71' is covered with a first filling film 81, and the sidewall of each second opening 72' is covered with a second filling film 82, as an example.

[0127] The first filling film 81 and the second filling film 82 are made of conductive materials, such as metal compounds. For example, the materials of the first filling film 81 and the second filling film 82 include titanium nitride.

[0128] In some embodiments, such as Figure 11 As shown, step S500 includes:

[0129] S510, a first filling base film 80′ is formed, the first filling base film 80′ covers the second dielectric film 60′, the third opening 71′ and the second opening 72′.

[0130] For example, the first filling base film 80′ can be formed by chemical vapor deposition, physical vapor deposition or other deposition methods.

[0131] S520: Remove the portion of the first filling base film 80′ located at the surface 60′ of the second dielectric film and the bottom of the third opening 71′ and the second opening 72′, and retain the portion of the first filling base film 80′ that covers the sidewall of the third opening 71′ and the sidewall of the second opening 72′.

[0132] For example, a dry etching process can be used to perform unobstructed etching on the structure obtained in step S510 to etch the first filling base film 80′, retaining the portion of the first filling base film 80′ that covers the sidewalls of the third opening 71′ and the second opening 72′, to form the first filling film 81 and the second filling film 82.

[0133] S600, such as Figure 12 As shown, the adapter metal 20 is etched.

[0134] For example, such as Figure 12 As shown, when etching the adapter metal 20, the degree of etching can be such that the adapter metal 20 is etched back, forming a groove on the surface of the adapter metal 20, and the groove is connected to the second opening 72'. For example, the opening area of ​​the groove is larger than the opening area of ​​the second opening 72'.

[0135] The shape of the groove is not limited. Figure 12 The illustration uses an arc-shaped groove as an example. The groove can also be a rectangular groove, a V-shaped groove, or a trapezoidal groove, etc.

[0136] Of course, step S600 can be skipped, and step S500 can be executed before proceeding to step S700.

[0137] S700, such as Figure 13 As shown, a second conductive post body 721 is formed within the second opening 72'.

[0138] In some technologies, an electroplating process is used to form a copper (Cu) pillar as the body 721 of the second conductive pillar.

[0139] In other technologies, chemical vapor deposition (CVD) is used to form tungsten (W) pillars as the second conductive pillar body 721.

[0140] In other technologies, a thinner titanium nitride (TiN) layer is used as the barrier layer, and a cobalt (Co) pillar is used as the body of the second conductive pillar 721. This increases the process window of the second conductive pillar body 721 and reduces the resistance of the conductive pillar.

[0141] In some other technologies, a selective deposition process is used to form the second conductive pillar body 721 within the second opening 72'.

[0142] The second conductive pillar body 721 is in contact with the transition metal 20. The second filling film 82 is located on the side of the second conductive pillar body 721. The third filling portion 821 serves as the second filling layer 722. The second conductive pillar body 721 formed by the selective growth process is in contact with the sidewall of the second filling layer 722. The second conductive pillar body 721 is a solid structure and has no pores inside.

[0143] Selective growth process refers to epitaxial growth performed within a defined area on the substrate. In this application, it means starting epitaxial growth on the surface of the transition metal 20, rather than starting epitaxial growth on the surfaces of the second dielectric film 60′ and the etch stop film 52′.

[0144] Therefore, the second conductive pillar body 721 finally formed by the selective growth process in this application has a bottom surface that directly contacts the transition metal 20, a side surface that directly contacts the side wall of the second opening 72', and a solid structure with no pores inside.

[0145] The second conductive pillar body 721 is epitaxially grown directly on the surface of the metal structure 20 using a selective epitaxial growth process. Therefore, by using a selective growth process to form the second conductive pillar body 721, no barrier layer or nucleation layer is needed, which reduces the contact resistance between the second conductive pillar body 721 and the transition metal 20, making it suitable for chip structures with high aspect ratios. Furthermore, since the tungsten metal grows from bottom to top, no pores are formed inside the formed second conductive pillar body 721, further reducing its resistance.

[0146] The height of the second conductive pillar body 721 can be adjusted according to the depth of the second opening 72' and the grinding thickness of the subsequent chemical mechanical polishing process. When multiple second conductive pillar bodies 721 are formed simultaneously, the heights of the multiple second conductive pillar bodies 721 can be the same or different.

[0147] like Figure 13As shown, when the surface of the adapter metal 20 has a groove, the second conductive post body 721 extends into the adapter metal 20. The part of the second conductive post body 721 extending into the adapter metal 20 contacts the surface of the first dielectric layer 30 away from the second dielectric film 60′. The cross-sectional area of ​​the surface of the second conductive post body 721 that contacts the first dielectric layer 30 is greater than the cross-sectional area of ​​the part of the second conductive post body 721 located in the second opening 72′.

[0148] By etching a groove back onto the surface of the adapter metal 20, with the opening of the groove being larger than the opening of the second opening 72', the cross-sectional area of ​​the end of the subsequently formed second conductive post near the adapter metal 20 can be made larger than the cross-sectional area at other locations, thus creating a rivet effect. In this way, even if acidic polishing or etching solutions flow into the gap between the second conductive post and the second dielectric film 60' during subsequent fabrication, they will first contact the portion of the second conductive post located within the groove, reducing damage to the adapter metal 20 from the acidic polishing or etching solutions.

[0149] In some embodiments, such as Figure 13 As shown, the surface of the second conductive pillar body 721 is lower than the surface of the second dielectric film 60′. That is, the depth of the second conductive pillar body 721 is less than the depth of the second opening 72′.

[0150] In this way, the height of the second conductive post body 721 that is ground off can be reduced during the subsequent chemical mechanical polishing process, thereby reducing material waste and lowering costs.

[0151] The material of the second conductive pillar body 721 is not limited. The material of the second conductive pillar body 721 may include copper (Cu), aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), ruthenium (Ru), cobalt (Co), nickel (Ni), palladium (Pd), platinum (Pt), tungsten (W), silver (Ag), gold (Au), niobium (CN), etc.

[0152] In some embodiments, before performing step S700, the second opening 72' is first surface treated to remove chemical residues and dangling bonds from the sidewalls of the second opening 72' and the surface of the transition metal 20, thereby improving selectivity.

[0153] Chemical residues may be, for example, chemical substances left over from the process of forming the second opening 72′, and dangling bonds may be, for example, chemical bonds that have no electrons to pair with.

[0154] The surface of the second opening 72' can be treated by means of heat treatment, plasma treatment, treatment by introducing a reducing gas (e.g., hydrogen), treatment by introducing an oxidizing gas (e.g., oxygen and nitrous oxide), or treatment by introducing an inert gas.

[0155] S800, such as Figure 14 As shown, the portion of the resistor protection film 50′ located below the third opening 71′ is removed to form the first opening 73′, and the resistor protection layer 50 is formed.

[0156] Since the etch stop film 53' in the resistive protective film 50' has been opened by the third opening 71', the portion of the etch stop film 52' and the oxide barrier film 51' located below the third opening 71' is actually removed in step S800. A second via is formed on the etch stop film 52', and a third via is formed on the oxide barrier film 51' to form the first opening 73'. The first opening 73' penetrates the second dielectric film 60' and the resistive protective film 50', exposing the resistive layer 40. After the portion of the etch stop film 52' and the oxide barrier film 51' located below the third opening 71' is removed, an etch stop layer 52 and an oxide barrier layer 51 are formed, thereby forming the resistive protective layer 50. The resistor protection layer 50 includes an oxide barrier layer 51, an etch stop layer 52, and an etch stop layer 53, which are stacked sequentially along a direction away from the resistor layer 40. The oxide barrier layer 51 has a third via 511, the etch stop layer 52 has a second via 521, and the etch stop layer 53 has a first via 531.

[0157] The first and second etching processes etch different film layers; therefore, the etching parameters for the first and second etching processes are different. By adjusting the etching parameters of the second etching process, damage to the resistive layer 40 can be reduced.

[0158] like Figure 14 As shown, the resistive layer 40 is divided into two parts: the first part 41 is located below the first opening 73', and the second part 42 is located below the resistive protective layer 50. After the first conductive pillar is formed in the first opening 73', the first conductive pillar contacts the first part 41. In this application, the film layer above the first part 41 is removed only when the first conductive pillar is about to be formed, and a separate removal process is used to remove only this part of the film layer, thus minimizing over-etching damage.

[0159] S900, such as Figure 15A As shown, a first conductive pillar 71 is formed in the first opening 73', and a second dielectric layer 60 is formed therein.

[0160] The first conductive post 71 is electrically connected to the resistive layer 40.

[0161] In some embodiments, such as Figure 15A As shown, step S900 includes:

[0162] S910, forming a third filling membrane 711' covering the second dielectric membrane 60'.

[0163] S920, A conductive film 712' is formed on the third filling film 711'.

[0164] For example, if the third filling film 711′ is a nucleation layer, then a conductive film 712′ can be formed using a metal oxide chemical vapor deposition (MOCVD) process.

[0165] Alternatively, for example, if the third filler film 711′ is a barrier layer, then an electroplating process can be used to form a conductive film 712′.

[0166] S930, the third filling film 711′, the conductive film 712′ and the second dielectric film 60′ are ground to form the first filling layer 711, the first conductive pillar body 712 and the second dielectric layer 60.

[0167] For example, a chemical mechanical polishing process is used to polish the third filling film 711′, the conductive film 712′, and the second dielectric film 60′.

[0168] like Figure 15A As shown, the formed first conductive post 71 is located within the first opening 73'. The first conductive post 71 includes a first conductive post body 712 and a first filling layer 711, which covers the bottom and side surfaces of the first conductive post body 712. The third filling film 711' located within the first filling portion 7111 of the first opening 73' and the remaining first filling film 81 after grinding constitute the first filling layer 711 of the first conductive post 71. The conductive film 712' located within the first opening 73' after grinding constitutes the first conductive post body 712 of the first conductive post 71.

[0169] In this way, the portion of the first filling layer 711 that contacts the second dielectric layer 60 and the etching barrier layer 53 includes the first filling portion 7111 and the remaining first filling film 81 after polishing. The portion of the first filling layer 711 located on the bottom surface of the first conductive pillar body 712 also includes the first filling portion 7111. Therefore, the thickness of the portion of the first filling layer 711 that contacts the second dielectric layer 60 is greater than the thickness of the portion of the first filling layer 711 located on the bottom surface of the first conductive pillar body 712.

[0170] The material of the third filling membrane 711′ can be the same as the material of the first filling membrane 81, or they can be different.

[0171] In addition, the formed second conductive post 72 is located within the second opening 72', and the second conductive post 72 includes a second conductive post body 721 and a second filling layer 722.

[0172] Depending on the degree of grinding, in some embodiments, such as Figure 15B As shown, while forming the first filling layer 711, the first conductive pillar body 712 and the second dielectric layer 60, a third conductive pillar body 723 and a third filling layer 724 are also formed.

[0173] The second conductive post 72 is located within the second opening 72'. The second conductive post 72 includes a second conductive post body 721, a second filling layer 722, a third conductive post body 723, and a third filling layer 724.

[0174] The third conductive post body 723 is disposed on the side of the second conductive post body 721 away from the transition metal 20. The second filling layer 722 covers the side of the second conductive post body 721 located within the second opening 72'. The third filling layer 724 covers the bottom and side surfaces of the third conductive post body 723. Specifically, the second filling portion 7112 of the third filling film 711' located within the second opening 72' and the fourth filling portion 822 of the second filling film 82 located on the side surface of the third conductive post body 723 constitute the third filling layer 724. After grinding, the conductive film 712' located within the second opening 72' serves as the third conductive post body 723 of the second conductive post 72.

[0175] In this way, the portion of the third filling layer 724 located on the side of the third conductive pillar body 723 includes the second filling portion 7112 and the fourth filling portion 822, and the portion of the third filling layer 724 located on the bottom surface of the third conductive pillar body 723 includes the second filling portion 7112. Therefore, the thickness of the portion of the third filling layer 724 located on the side of the third conductive pillar body 723 is greater than the thickness of the portion of the third filling layer 724 located on the bottom surface of the third conductive pillar body 723.

[0176] The material of the third filling membrane 711′ can be the same as the material of the second filling membrane 82, or they can be different.

[0177] After the second dielectric film 60′ is ground, the remaining part is used as the second dielectric layer 60. The surface of the second dielectric layer 60 away from the first dielectric layer 30 is flat. The first filling film 711′ and conductive film 712′ located on the surface of the second dielectric film 60′ are completely removed.

[0178] The first conductive pillar 71 is formed using the above-described preparation method. During the preparation of the first conductive pillar 71, the chemical mechanical polishing of the second conductive pillar 72 can be completed simultaneously, thus reducing process steps, lowering costs, and improving efficiency.

[0179] In some other embodiments, step S900 includes forming a first conductive pillar 71 using a selective growth process.

[0180] S1000, such as Figure 16As shown, a first conductive pattern 91 and a second conductive pattern 92 are formed on the side of the second dielectric layer 60 away from the transition metal 20. The first conductive pattern 91 is electrically connected to the first conductive post 71, and the second conductive pattern 92 is electrically connected to the second conductive post 72.

[0181] The embodiments of this application do not limit the shape, function, or material of the first conductive pattern 91; it can be reasonably set according to the application scenario.

[0182] In some embodiments, such as Figure 16 As shown, the first conductive pattern 91 and the second conductive pattern 92 are conductive patterns included in the redistribution layer. That is, the first conductive pattern 91 and the second conductive pattern 92 are conductive patterns in the redistribution layer prepared by subsequent processes.

[0183] For example, the first conductive pattern 91 and the second conductive pattern 92 are conductive patterns in the wiring layer closest to the second dielectric layer 60 in the redistribution layer. The first conductive pattern 91 and the second conductive pattern 92 can be columnar, linear, or other shapes, which are not limited in this embodiment.

[0184] A first conductive pattern 91 can be electrically connected to one or more first conductive posts 71. The first conductive pattern 91 and the first conductive post 71 can be electrically connected by direct contact or indirect connection. The two ends of the first conductive post 71 are electrically connected to the resistive layer 40 and the first conductive pattern 91, respectively. A second conductive pattern 92 can be electrically connected to one or more second conductive posts 72. The second conductive pattern 92 and the second conductive post 72 can be electrically connected by direct contact or indirect connection. The two ends of the second conductive post 72 are electrically connected to the adapter metal 20 and the second conductive pattern 92, respectively.

[0185] The chip provided in this application embodiment has a resistor protection layer 50 above the resistor layer 40, including an etch stop layer 52 and an etch barrier layer 53. The etch barrier layer 53 acts as a barrier layer when etching the resistor layer film 40′ to form the resistor layer 40, protecting the pattern shape of the resistor layer 40. The etch stop layer 52 acts as a stop layer when etching the etch barrier layer 53 to form the opening for placing the first conductive pillar 71. Thus, due to the presence of the etch stop layer 52, regardless of the etching process used to form the first via 531 on the etch barrier layer 53 during the second etching process, it has almost no impact on the resistor layer 40 below the etch stop layer 52. This improves both the yield of the resistor layer 40 and the process compatibility during chip fabrication. When the first conductive pillar 71 needs to be fabricated subsequently, a separate etching step is used to form the second via 521 on the etch stop layer 52. By adjusting the etching conditions, damage to the resistor layer 40 can be minimized, improving the yield of the resistor layer 40. Furthermore, by not exposing the resistive layer 40 before fabricating the first conductive pillar 71, the exposure time of the resistive layer 40 can be reduced, decreasing the probability of oxidation and further improving its yield. Compared to the near-complete damage of the first portion 41 of the resistive layer 40 in related technologies, the actual resistance value of the resistive layer 40 in the chip fabricated in this application is closer to the set resistance value, effectively mitigating resistance deviation caused by damage to the resistive layer 40 and enhancing chip performance. Moreover, the thickness of the portion of the first filling layer 711 in contact with the second dielectric layer 60 is made relatively large, improving the filling effect on the gap between the first conductive pillar body 712 and the second dielectric layer 60, and enhancing the adhesion between the first conductive pillar body 712 and the second dielectric layer 60. The thickness of the portion of the first filling layer 711 located on the bottom surface of the first conductive pillar body 712 is made relatively small, reducing the impact of the first filling layer 711 on the conductivity of the first conductive pillar 71.

[0186] Furthermore, when the chip includes a first conductive pillar 71 and a second conductive pillar 72, the fabrication method provided in this application allows for compatibility between the fabrication processes of the first conductive pillar 71 in the high-resistivity device region and the second conductive pillar 72 in the low-resistivity device region. For example, the third opening 71' and the second opening 72' can be formed simultaneously, and the second conductive pillar 72 can be polished while the first conductive pillar 71 is being formed. In other words, the chip fabrication method provided in this application can achieve compatibility between the fabrication processes of the first conductive pillar 71 and the second conductive pillar 72 while ensuring the yield of the resistive layer 40 product.

[0187] In addition, the side of the second conductive post 72 has a second filling layer 722, which can increase the adhesion between the second conductive post body 721 and the sidewall of the second opening 72', thereby improving the problem of poor adhesion between the second conductive post 72 and the sidewall of the second opening 72'.

[0188] Based on this, the chip provided in the embodiments of this application, such as Figure 16 As shown, the chip includes a transistor 10, a first dielectric layer 30, a resistor layer 40 and a resistor protection layer 50, a second dielectric layer 60, and a first conductive pillar 71, which are sequentially stacked on the first dielectric layer 30 in a first region.

[0189] In some embodiments, an interlayer dielectric layer (ILD) is covered on the transistor 10, exposing the source (S), drain (D), and gate (G) of the transistor. A first dielectric layer 30 is disposed on the transistor 10, for example, on the interlayer dielectric layer (ILD).

[0190] In some embodiments, the chip further includes a transition metal 20, which is electrically connected to the source S, drain D, and gate G of the transistor 10, for leading the source S, drain D, and gate G of the transistor 10 to the same plane. For example, the transition metal 20 is located within the interlayer dielectric layer (ILD).

[0191] The resistive layer 40 is disposed in a first region of the first dielectric layer 30. The first region may correspond to the high-resistivity device region of the chip, for example. The resistive protective layer 50 covers the surface of the resistive layer 40.

[0192] The resistive protection layer 50 includes multiple dielectric overlays, for example, such as Figure 16 As shown, the resistor protection layer 50 includes three dielectric cover layers, which include an oxide barrier layer 51, an etch stop layer 52, and an etch stop layer 53 stacked sequentially in a direction away from the resistor layer 40.

[0193] An etch stop layer 52 is disposed between an etch barrier layer 53 and a resistive layer 40, and an oxide barrier layer 51 is disposed between an etch stop layer 52 and a resistive layer 40.

[0194] The oxide barrier layer 51 has a third via 511, the etch stop layer 52 has a second via 521, and the etch barrier layer 53 has a first via 531. The third via 511, the second via 521, and the first via 531 are connected.

[0195] The etching barrier layer 53 is used as an etching protection layer in the first etching process of forming the resistive layer 40, the etching stop layer 52 is used as an etching protection layer in the second etching process of forming the first via 531, and the oxide barrier layer 51 is used as a protective layer to prevent the etching stop layer 52 from oxidizing the resistive layer 40.

[0196] The etching barrier layer 53 and the etching stop layer 52 are made of different dielectric materials. The oxide barrier layer 51 is made of oxygen-free dielectric material, and the etching stop layer 52 is made of a different material than the oxide barrier layer 51 and the etching barrier layer 53.

[0197] For example, in the chip provided in this application embodiment, the etch stop layer 52 is made of the same material as the second dielectric layer 60, and the oxide barrier layer 51, etch stop layer 53, and first dielectric layer 30 are made of the same material. This reduces the number of material types, simplifies the fabrication process, and lowers costs.

[0198] The second dielectric layer 60 is disposed on the first dielectric layer 30 and covers the resistor protection layer 50. The second dielectric layer 60 has a fourth via, which communicates with the first via 531 on the etch barrier layer 53.

[0199] In some embodiments, the first dielectric layer 30 and the second dielectric layer 60 are made of different materials. For example, the first dielectric layer 30 is made of silicon nitride, and the second dielectric layer 60 is made of silicon oxide.

[0200] In the high-resistivity device region, a resistive layer 40 and a resistive protection layer 50 are sandwiched between the first dielectric layer 30 and the second dielectric layer 60. In the non-high-resistivity device region, the first dielectric layer 30 and the second dielectric layer 60 are in direct contact.

[0201] The first conductive post 71 penetrates the second dielectric layer 60 and the resistive protection layer 50, and is electrically connected to the resistive layer 40. For example, the first conductive post 71 passes through the fourth via 62, the first via 531, the second via 521, and the third via 511, and is electrically connected to the resistive layer 40. The fourth via 62, the first via 531, the second via 521, and the third via 511 form the first opening 73'.

[0202] The first conductive post 71 can be one or more. Figure 16 The chip includes a first conductive post 71 as an example for illustration.

[0203] In addition, the shape of the first conductive post 71 is not limited in the embodiments of this application. The shape of the first conductive post 71 can be cylindrical, rectangular, or cuboid.

[0204] In this case, the resistive layer 40 can be divided into a first part 41 that contacts the first conductive post 71 and a second part that contacts the resistive protective layer 50.

[0205] In this embodiment of the application, the resistive protective layer 50 above the first portion 41 is not penetrated until the first conductive pillar 71 is about to be formed during chip fabrication. Therefore, the exposure time of the first portion 41 is short, and the damage is minimal. Moreover, a separate etching process is used to create openings in the resistive protective layer 50, so there is almost no over-etching damage to the first portion 41.

[0206] Therefore, in the chip provided in this application embodiment, the ratio of the thickness of the first part 41 to the thickness of the second part 42 in the resistor layer 40 can range from 0.2 to 1.

[0207] For example, the ratio of the thickness of the first part 41 to the thickness of the second part 42 is 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or 0.9.

[0208] In some embodiments, the thickness of the first portion 41 in the resistive layer 40 is equal to the thickness of the second portion 42.

[0209] In some embodiments, the first conductive post 71 includes a first conductive post body 712 and a first filling layer 711, the first filling layer 711 covering the side and bottom surfaces of the first conductive post body 712.

[0210] Based on the above chip fabrication method, it can be seen that by using a structure where the first conductive pillar 71 includes a first conductive pillar body 712 and a first filling layer 711, the second conductive pillar 72 can be chemically mechanically polished simultaneously during the fabrication of the first conductive pillar 71. This can reduce process steps, lower costs, and improve efficiency.

[0211] In some embodiments, such as Figure 15B As shown, the portion of the first filling layer 711 that contacts the second dielectric layer 60 and the etching barrier layer 53 includes the first filling portion 7111 located within the first opening 73' of the third filling film 711' and the remaining first filling film 81 after polishing. The portion of the first filling layer 711 located on the bottom surface of the first conductive pillar body 712 includes the first filling portion 7111. Therefore, the thickness of the portion of the first filling layer 711 that contacts the second dielectric layer 60 is greater than the thickness of the portion of the first filling layer 711 located on the bottom surface of the first conductive pillar body 712.

[0212] In some embodiments, such as Figure 16 As shown, the chip also includes a transition metal 20 and a second conductive post 72.

[0213] The transition metal 20 can be, for example, the transition metal on the surface of the transistor. The transition metal 20 and the resistive layer 40 are staggered. The projection of the transition metal 20 on the first dielectric layer 30 does not overlap with the projection of the resistive layer 40 on the first dielectric layer 30.

[0214] The second conductive post 72 penetrates the second dielectric layer 60 and the first dielectric layer 30, and is electrically connected to the transition metal 20.

[0215] The second conductive post 72 can be one or more. Figure 16 The example shown is a chip with multiple second conductive pillars 72.

[0216] In addition, the shape of the second conductive post 72 is not limited in the embodiments of this application. The shape of the second conductive post 72 can be cylindrical, rectangular, or cuboid.

[0217] In some embodiments, the second conductive post 72 includes a second conductive post body 721 and a second filling layer 722.

[0218] In other embodiments, the second conductive post 72 includes a second conductive post body 721, a second filling layer 722, a third conductive post body 723, and a third filling layer 724.

[0219] The third conductive pillar body 723 is disposed above the second conductive pillar body 721. The third conductive pillar body 723 may be formed synchronously with the first conductive pillar body 712, and the third filling layer 724 may be formed synchronously with the first filling layer 711.

[0220] In some embodiments, such as Figure 15B As shown, the portion of the third filling layer 724 located on the side of the third conductive pillar body 723 includes a second filling portion 7112 of the third filling film 711' located within the second opening 72' and a fourth filling portion 822 of the second filling film 82 located on the side of the third conductive pillar body 723. The portion of the third filling layer 724 located on the bottom surface of the third conductive pillar body 723 includes the second filling portion 7112. Therefore, the thickness of the portion of the third filling layer 724 located on the side of the third conductive pillar body 723 is greater than the thickness of the portion of the third filling layer 724 located on the bottom surface of the third conductive pillar body 723.

[0221] In some embodiments, please refer to Figure 16 The chip also includes a first conductive pattern 91 and a second conductive pattern 92, which are disposed on the side of the second dielectric layer 60 away from the first dielectric layer 30. The first conductive post 71 is electrically connected to the first conductive pattern 91, and the second conductive post 72 is electrically connected to the second conductive pattern 92.

[0222] The chip provided in this application embodiment has a resistor protection layer 50 above the resistor layer 40, including an etch stop layer 52 and an etch barrier layer 53. The etch barrier layer 53 acts as a barrier layer when etching the resistor layer film 40′ to form the resistor layer 40, protecting the pattern shape of the resistor layer 40. The etch stop layer 52 acts as a stop layer when etching the etch barrier layer 53 to form the opening for placing the first conductive pillar 71. Thus, due to the presence of the etch stop layer 52, regardless of the etching process used to form the first via 531 on the etch barrier layer 53 during the second etching process, it has almost no impact on the resistor layer 40 below the etch stop layer 52. This improves both the yield of the resistor layer 40 and the process compatibility during chip fabrication. When the first conductive pillar 71 needs to be fabricated subsequently, a separate etching step is used to form the second via 521 on the etch stop layer 52. By adjusting the etching conditions, damage to the resistor layer 40 can be minimized, improving the yield of the resistor layer 40. Furthermore, by not exposing the resistive layer 40 before fabricating the first conductive pillar 71, the exposure time of the resistive layer 40 can be reduced, lowering the probability of oxidation and further improving the yield of the resistive layer 40. Moreover, by making the portion of the first filler layer 711 in contact with the second dielectric layer 60 relatively thick, the filling effect on the gap between the first conductive pillar body 712 and the second dielectric layer 60 can be improved, thus enhancing the adhesion between the first conductive pillar body 712 and the second dielectric layer 60. Conversely, by making the portion of the first filler layer 711 located on the bottom surface of the first conductive pillar body 712 relatively thin, the influence of the first filler layer 711 on the conductivity of the first conductive pillar 71 can be reduced.

[0223] In some embodiments, this application also provides a chip, which includes the aforementioned adapter metal 20, second conductive pillar 72 and second conductive pattern 92, but does not include the resistive layer 40, first conductive pillar 71 and first conductive pattern 91.

[0224] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized by The chip comprises: a first dielectric layer; a resistance layer and a resistance protection layer, which are sequentially arranged in a first region on the first dielectric layer; the resistance protection layer comprises an etching stop layer and an etching barrier layer, the etching stop layer is arranged between the etching barrier layer and the resistance layer; the etching barrier layer has a first via hole, and the etching stop layer has a second via hole; a second dielectric layer arranged on the first dielectric layer and covering the resistance protection layer; a first conductive column penetrating through the second dielectric layer and electrically connected with the resistance layer through the first via hole and the second via hole; the first conductive column comprises a first conductive column body and a first filling layer, the first filling layer covers the side surface and the bottom surface of the first conductive column body; the thickness of the part of the first filling layer in contact with the second dielectric layer is greater than the thickness of the part of the first filling layer located at the bottom surface of the first conductive column body; The etching barrier layer is used as an etching protection layer in a first etching process for forming the resistance layer, and the etching stop layer is used as an etching protection layer in a second etching process for forming the first via hole.

2. The chip according to claim 1, characterized in that, The resistance layer comprises a first part in contact with the first conductive column and a second part in contact with the resistance protection layer, and the ratio of the thickness of the first part to the thickness of the second part ranges from 0.2 to 1.

3. The chip according to claim 1 or 2, characterized in that, The resistance protection layer further comprises an oxidation barrier layer; the oxidation barrier layer is arranged between the etching stop layer and the resistance layer, and the oxidation barrier layer has a third via hole in communication with the second via hole.

4. The chip of claim 3, wherein The material of the oxidation barrier layer comprises silicon nitride, the material of the etching stop layer comprises silicon oxide, and the material of the etching barrier layer comprises silicon nitride.

5. The chip according to any one of claims 1 to 4, characterized in that The material of the resistance layer comprises titanium nitride, tantalum nitride or titanium oxide.

6. The chip according to any one of claims 1 to 5, characterized in that The chip further comprises a second conductive column and a transistor; The transistor is arranged on the side of the first dielectric layer away from the second dielectric layer, and the projection of the transistor on the first dielectric layer does not overlap with the projection of the resistance layer on the first dielectric layer; The second conductive column penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the transistor.

7. The chip of claim 6, wherein The second conductive column comprises a second conductive column body and a second filling layer; The second filling layer covers the side surface of the second conductive column body, and the second conductive column body is in contact with the transistor.

8. The chip of claim 7, wherein, The second conductive column further comprises a third conductive column body and a third filling layer; The third conductive column body is arranged on the side of the second conductive column body away from the transistor, and the third filling layer covers the side surface and the bottom surface of the third conductive column body.

9. The chip of claim 8, wherein, The thickness of the part of the third filling layer located at the side surface of the third conductive column body is greater than the thickness of the part of the third filling layer located at the bottom surface of the third conductive column body.

10. The chip according to any of claims 7 to 9, characterized in that The second conductive column body extends into the transistor, and the part of the second conductive column body extending into the transistor is in contact with the surface of the first dielectric layer away from the second dielectric layer.

11. The chip according to any of claims 6 to 10, characterized in that The chip further comprises a first conductive pattern and a second conductive pattern; The first conductive pattern and the second conductive pattern are arranged on a side of the second dielectric layer away from the first dielectric layer; the first conductive column is electrically connected with the first conductive pattern, and the second conductive column is electrically connected with the second conductive pattern.

12. An electronic device, comprising: The chip and the circuit board are arranged on the circuit board.

13. A method of producing a chip, characterized by The chip and the circuit board are arranged on the circuit board. A first dielectric film is formed. A resistance film and a resistance protection film are sequentially formed on the first dielectric film, the resistance film covers the first dielectric film, and the resistance protection film is located in a first region of the first dielectric film; the resistance protection film comprises an etching stop film and an etching barrier film, and the etching stop film is located between the etching barrier film and the resistance film. The resistance film is subjected to first etching to form a resistance layer. The etching barrier film is used as an etching protection layer in the first etching process for forming the resistance layer, and the resistance layer is located in the first region. A second dielectric film is formed. The second dielectric film is formed on the first dielectric film and covers the resistance protection film. Through second etching, a fourth via hole penetrating through the second dielectric film and a first via hole penetrating through the etching barrier film are formed. The etching stop film is used as an etching protection layer in the second etching process for forming the first via hole. A second via hole is formed on the etching stop film to form a first opening penetrating through the second dielectric film and the resistance protection film and a resistance protection layer. A first conductive column is formed in the first opening, and a second dielectric layer is formed; the first conductive column is electrically connected with the resistance layer; the first conductive column comprises a first conductive column body and a first filling layer, the first filling layer covers the side surface and the bottom surface of the first conductive column body; the thickness of the part of the first filling layer in contact with the second dielectric layer is greater than the thickness of the part of the first filling layer located at the bottom surface of the first conductive column body.

14. The method of claim 13, wherein the chip is prepared by a method comprising: Before the first dielectric film is formed, the preparation method further comprises: forming a transistor; the projection of the transistor on the first dielectric film does not overlap with the projection of the resistance layer on the first dielectric film. When the first opening penetrating through the second dielectric film is formed, the preparation method further comprises: forming a second opening penetrating through the second dielectric film and the first dielectric film to form a first dielectric layer; the second opening exposes the transistor.

15. The method of claim 14, wherein the chip is prepared by a method comprising: Before the part of the resistance protection film located below the first opening is removed, the preparation method further comprises: A first filling film and a second filling film are formed; the first filling film covers the sidewall of the first opening, and the second filling film covers the sidewall of the second opening.

16. The method of claim 15, wherein the chip is prepared by a method comprising: Before the second via hole is formed on the etching stop film, the preparation method further comprises: A second conductive column body is formed in the second opening, the second conductive column body is in contact with the transistor, and the part of the second filling film located at the side surface of the second conductive column body serves as a second filling layer.

17. The method of claim 15 or 16, wherein the chip is prepared by a method comprising: The first conductive column is formed in the first opening, and the second dielectric layer is formed, which comprises: A third filling film covering the second dielectric film is formed; A conductive film is formed on the third filling film; The third filling film, the conductive film and the second dielectric film are ground to form a first filling layer, a first conductive column body and a second dielectric layer; the first conductive column body is located in the first opening, the part of the third filling film located in the first opening and the remaining first filling film serve as the first filling layer; the first filling layer covers the bottom surface and the side surface of the first conductive column body; the first conductive column comprises the first filling layer and the first conductive column body.

18. The method of claim 17, wherein the chip is prepared by a method comprising: The third conductive column body and the third filling layer are formed at the same time when the first filling layer, the first conductive column body and the second dielectric layer are formed. The third conductive column body is arranged on the side of the second conductive column body away from the transistor, the part of the third filling film located in the second opening and the part of the second filling film located on the side surface of the third conductive column body serve as the third filling layer, and the third filling layer covers the bottom surface and the side surface of the third conductive column body.

19. The method of claim 13-18, wherein the chip is prepared by, The resistance protection film further comprises an oxidation barrier film; the oxidation barrier film is arranged on the side of the etching stop film facing the resistance layer; the preparation method further comprises forming a third via hole penetrating through the oxidation barrier film, and the third via hole is in communication with the second via hole.

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