Hardware and Software Co-Simulation Verification Platform for Accelerating the Verification and Location of Smart Network Card Chips

Abstract

The present invention relates to a software and hardware co - simulation verification platform for accelerating the verification and positioning of intelligent network card chips, belonging to the field of chip verification technology. The platform includes: a host - side QEMU virtual machine that simulates hardware devices, issues IO requests, responds to IO requests, and calls device drivers to implement the driving execution of host - side hardware devices; a host - side thread adapter that converts the multi - thread processing program of the host - side QEMU virtual machine into a single - thread processing program; a UVM verification platform that performs simulation reproduction of the FPGA prototype verification of the intelligent network card chip, generating simulation waveforms and simulation logs; a network - side data stream adapter that performs data type conversion on Ethernet packets; and a network - side packet transceiver that checks the legality of the Ethernet packets returned by the network - side data stream adapter. The platform of the present invention can improve the problem - positioning speed and chip verification efficiency, shorten the overall chip development cycle, and improve the chip quality.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip verification, and particularly relates to a software and hardware co-simulation verification platform for accelerating the verification and positioning of smart network card chips. Background Technique

[0002] A smart network card (Smart NIC) chip integrates an Ethernet interface, a PCIe (Peripheral Component Interconnect Express) bus interface, a multi-core processor (CPU), and an optional field programmable gate array (FPGA). It is mainly used to assist the host server to achieve functions such as virtual switching acceleration, network offloading acceleration, storage acceleration, and security acceleration, and is applied to cloud computing network virtualization solutions. The chip development cycle includes multiple stages such as functional requirement specification formulation, architecture design, code design, UVM (Universal Verification Methodology) functional simulation verification, FPGA prototype verification, software development and testing, and post-silicon product application testing of the chip.

[0003] The UVM functional simulation verification and FPGA prototype verification occupy most of the development cycle. Therefore, accelerating chip verification convergence means that the chip development cycle can be shortened and the chip product quality can be improved.

[0004] (1) UVM Functional Simulation Verification

[0005] The advantages of UVM functional simulation verification are as follows:

[0006] 1. The compilation and simulation speeds are fast. Especially for module-level functional verification, the compilation speed and simulation speed of the functional simulation tool are very fast, which will accelerate the verification speed of the overall project of the present invention to a certain extent;

[0007] 2. Problem location is convenient. The verification environment platform can enter any place of the DUT (Design Under Test) that needs to be verified, generate sufficiently accurate data packets at a specific moment for simulation verification, can pause or interrupt the operation of the verification tool at any time, and can also open the simulation waveform through a graphical interface and quickly locate problems in combination with the simulation log, improving the efficiency of problem location.

[0008] The disadvantages of UVM functional simulation verification are as follows:

[0009] 1. When the scale of the DUT is large, the simulation performance drops rapidly. When the design scale of the DUT is relatively large, the system-level functional simulation speed will become very slow, and the verification speed will be greatly reduced, thereby affecting the verification speed of the overall project;

[0010] 2. Limited simulation of the excitation source. Constraint-based stochastic simulation helps cover lower abstraction levels, including extreme cases of the system-level behavior of the design. However, in simulating software transaction-driven aspects, especially for intelligent network cards, which involve service functions such as network acceleration, storage acceleration, and security acceleration. Among them, network acceleration mainly includes OVS (Open vSwitch, an open-source virtual switch) acceleration, TCP offloading, Vxlan / GRE tunnel packet offloading, reliable UDP (User Datagram Protocol), NAT / PAT, RDMA (Remote Direct Memory Access), etc.; storage acceleration includes NVMe-OF (NVMe Over Fabrics), support for local PCIe SSD disks, support for remote NVMe arrays, etc.; security acceleration includes the offloading of IPSec encryption and decryption (Internet Protocol Security), packet filtering, firewalls, DPI, DDoS, etc. The software drivers used in these services include OVS virtual switching, SDN / NFV virtualization standard software, TCP / UDP offloading, SR-IOV (Single Root I / O Virtualzation), LinuxNet / DPDK (Intel Data Plane Development Kit), Express Virtio (XVIO), vPDA, etc. For such complex functional services and software drivers, there is still a gap between functional simulation and real software operation. Due to insufficient simulation of application scenarios, bugs may be missed, and the verification quality cannot be guaranteed.

[0011] Main advantages of FPGA prototype verification:

[0012] 1. The hardware simulation speed is extremely fast. By using FPGA hardware simulation, the verification speed can be increased, and the verification time can be shortened.

[0013] 2. Software development and testing can be carried out in advance. Software engineers can carry out software driver and application development on the FPGA prototype platform in advance. When the chip comes back, it only takes a few weeks to transplant the software and hardware, thus accelerating the product release.

[0014] Main disadvantages of FPGA prototype verification:

[0015] 1. The compilation time is relatively long. Since hardware simulation requires logical synthesis of the design files and mapping the synthesized results to the real hardware circuit for simulation acceleration, while software-based functional simulation does not require logical synthesis to generate a physical circuit, this makes its compilation time much longer than that of functional simulation.

[0016] 2. Problem location is inconvenient. Since the FPGA is also a chip product, the internal signals cannot be directly observed. It is necessary to select the signals to be observed before generating the Bit file with the help of the FPGA's Debug tool. At the same time, limited by the capacity of the Block RAM (block random access memory), only some signals can be observed. Each time the observed signals and trigger conditions are reselected, the Bit file needs to be recompiled and generated, and the debugging efficiency is very low, affecting the verification efficiency. This means that a large amount of time needs to be invested in problem reproduction, location, and solution, resulting in a longer development cycle and the overall product quality of the chip cannot be guaranteed.

[0017] In summary, traditional chip verification, UVM functional simulation verification is equivalent to a software simulation verification platform, and FPGA prototype verification is equivalent to a hardware simulation verification platform. These are two completely independent verification platforms. In the verification of complex services such as intelligent network card chips, UVM functional simulation verification cannot fully simulate all the services of the intelligent network card. Problems found in FPGA prototype verification are also very difficult to reproduce in the UVM functional simulation verification platform. Only by continuously adding location logic and signals and continuously releasing FPGA versions can problems be located. The verification method of locating problems through the FPGA prototype verification platform has a large positioning difficulty, requires a lot of time and effort, and the positioning efficiency is extremely low, ultimately affecting the development cycle of the entire project.

[0018] Therefore, how to reproduce the problems found in FPGA prototype verification in the UVM functional simulation platform, quickly locate the places where the DUT design goes wrong through simulation waveforms and simulation logs, and perform repair and solution, so as to accelerate chip verification convergence, improve verification quality, and shorten the overall development cycle of the chip, is the pain point that needs to be solved in the verification of intelligent network card chips currently. Summary of the Invention

[0019] In view of the above deficiencies of the prior art, the purpose of the invention is to provide a software and hardware co-simulation verification platform for accelerating the verification and location of intelligent network card chips, which improves the problem location speed, improves the chip verification efficiency, shortens the overall chip development cycle, and improves the chip quality.

[0020] The invention provides a software and hardware co-simulation verification platform for accelerating the verification and location of intelligent network card chips, including: a host-side QEMU virtual machine, a host-side thread adapter, a UVM verification platform, a network-side data flow adapter, and a network-side packet transceiver, where,

[0021] The host-side QEMU virtual machine is used to simulate hardware devices, issue IO requests, respond to IO requests, and call device drivers to implement the driving execution of host-side hardware devices;

[0022] The host - side thread adapter is used for inter - process communication, converting the multi - thread handler of the host - side QEMU virtual machine into a single - thread handler suitable for processing by the UVM verification platform, and realizing the interactive communication between the host - side QEMU virtual machine and the UVM verification platform;

[0023] The UVM verification platform is used to perform simulation reproduction of the FPGA prototype verification of the intelligent network card chip according to the Ethernet packets sent by the network - side data stream adapter, generate simulation waveforms and simulation logs, and send them to the network - side data stream adapter in the form of Ethernet packets;

[0024] The network - side data stream adapter performs data - type conversion on the Ethernet packets received from the network - side packet transceiver, and sends the converted data to the UVM verification platform; and performs data - type conversion on the Ethernet packets returned by the UVM verification platform, and sends the converted data to the network - side packet transceiver;

[0025] The network - side packet transceiver is used to simulate and generate Ethernet packets, send the Ethernet packets to the network - side data stream adapter in the packet format and data structure specified by the TCP / IP protocol, and perform packet - legality checks on the Ethernet packets returned by the network - side data stream adapter; reproduce, locate, correct, and perform regression testing on the scenario problems in the FPGA prototype verification according to the simulation waveforms and simulation logs dynamically simulated by the EDA simulation tool, and perform regression testing on the FPGA prototype verification.

[0026] Further, the host - side QEMU virtual machine simulates the IO requests sent to the front - end driver of the hardware device, and the host - side QEMU virtual machine implements back - end processing to respond to the IO requests.

[0027] Further, the host - side thread adapter realizes the interaction between the UVM SystemVerilog program and the C program of the host - side QEMU virtual machine through the DPI - C interface.

[0028] Further, the host - side QEMU virtual machine calls the device driver to initialize the host system and the design under test (DUT), including host - side system memory management and allocation, PCIe driver, Virtio driver, and OVS driver, and initializes the DUT through calling the intelligent network card - related driver.

[0029] Further, the UVM verification platform includes global environment configuration, APP component, MAC simulation model, DDR simulation model, reference model, scoreboard, and instantiated DUT.

[0030] Further, the network - side data stream adapter realizes data type conversion with the Ethernet packets transmitted and received by the UVM verification platform through the DPI - C interface.

[0031] Further, the network - side packet transceiver is also used to encapsulate Ethernet packets according to the control address, payload, packet length, and packet type.

[0032] Further, the network - side packet transceiver is also used to inject various abnormal Ethernet packets, generate damaged Ethernet data packets, and conduct network abnormal packet transmission and reception tests.

[0033] Further, the network - side packet transceiver performs a legality check on the Ethernet packets returned by the network - side data stream adapter, and performs the following processing according to the check results: packet reception, discard, or reply.

[0034] Further, for the simulation waveforms and simulation logs generated by the host - side QEMU virtual machine, UVM verification platform, and network - side packet transceiver, use a graphical interface tool to open the waveforms and the design code of the device under test (DUT) to be tested, and combine with the simulation logs to locate the scenario problems in the FPGA prototype verification.

[0035] The beneficial effects of the present invention are as follows:

[0036] (1) Solve the problem of insufficient UVM functional simulation excitation sources, and the driver software can directly run on the software - hardware co - simulation platform. The software driver can be directly used in the UVM functional simulation verification platform, reducing the repeated development of the driver software. At the same time, the simulation excitation source is not limited by the traditional UVM verification platform, and can more realistically simulate various network, storage, and security acceleration scenarios, reducing both the repeated driver development and improving the test scenario coverage rate, thereby improving the verification quality.

[0037] (2) Can reproduce the problems found in the FPGA prototype verification on the software - hardware co - simulation platform. Through the software - hardware co - simulation verification platform, the software driver program and application test program can directly run on the UVM functional simulation platform. The problems found in the FPGA prototype verification can be directly reproduced on the software - hardware co - simulation verification platform. Through the simulation waveforms and simulation logs, quickly locate the problems and repair the design defects of the DUT. At the same time, conduct regression tests on the software - hardware co - simulation platform and the FPGA prototype verification platform, thereby accelerating the problem location of the intelligent network card chip verification and accelerating the verification convergence of the chip.

[0038] (3) By introducing the host - side QEMU virtual machine, realize the simulation of various hardware devices and the execution of the host - side hardware device drivers.

[0039] (4) Through software and hardware co - simulation verification, the problem - location speed is improved, the chip verification efficiency is enhanced, the overall chip development cycle is shortened, and the chip quality is improved.

[0040] (5) By introducing a host - side thread adapter, inter - process communication between multi - threaded programs and single - threaded handlers is achieved. Through the DPI - C interface, interaction between the UVM SystemVerilog program and the QEMU virtual machine C program is realized, enabling communication between multiple processes and a single thread, and further realizing the interactive communication between the QEMU virtual machine and the UVM verification environment.

[0041] (6) By introducing a network - side data - stream adapter, data - type conversion for network packet sending and receiving is achieved, and further the interactive communication between the network packet transceiver and the UVM verification environment is realized.

[0042] (7) By introducing a network - side data - packet transceiver, the simulation generation and reception processing of Ethernet packets are realized.

[0043] (8) The software driver can be directly used in the UVM functional simulation verification platform, reducing the repeated development of driver software. At the same time, the simulation excitation source is not limited by the traditional UVM verification platform, more realistically simulating various network, storage, and security acceleration scenarios, reducing both the repeated driver development and improving the test - scenario coverage rate, thereby improving the verification quality. Description of the Drawings

[0044] The drawings are only for the purpose of showing specific embodiments and are not considered as limitations of the present invention. Throughout the drawings, the same reference signs denote the same components. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings.

[0045] Figure 1 It is a structural diagram of the software - hardware co - simulation verification platform for accelerating the verification and location of intelligent network card chips according to an embodiment of the present invention;

[0046] Figure 2 It is a schematic diagram of the software - hardware co - simulation verification platform for accelerating the verification and location of intelligent network card chips according to an embodiment of the present invention;

[0047] Figure 3 It is a data - flow schematic diagram of the software - hardware co - simulation platform under the problem - reproduction process of the network - packet sending scenario in the system verification of the intelligent network card chip according to an embodiment of the present invention;

[0048] Figure 4 It is a data - flow schematic diagram of the software - hardware co - simulation platform under the problem - reproduction process of the network - packet receiving scenario in the system verification of the intelligent network card chip according to an embodiment of the present invention. Detailed Embodiments

[0049] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0050] In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts disclosed in the present invention.

[0051] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. The terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are merely examples of methods and systems consistent with some aspects of the present invention as detailed in the appended claims.

[0053] Embodiments of the present invention propose a software and hardware co-simulation verification platform and a test method for accelerating the problem location in the verification of intelligent network card chips. By introducing a host-side QEMU virtual machine, a host-side thread adapter, a network-side packet transceiver, and a network-side data flow adapter, and combining with the UVM verification platform, a software and hardware co-simulation platform is constructed. The problems found in the FPGA prototype verification are reproduced on the software and hardware co-simulation platform. By viewing the simulation waveforms and simulation logs, various behaviors of the internal signals of the DUT are observed, and the design defects of the DUT are quickly located and repaired, thereby improving the problem location speed, improving the chip verification efficiency, shortening the overall chip development cycle, and improving the chip quality.

[0054] The following explains the technical terms involved in the embodiments of the present invention:

[0055] UVM: It is a verification platform development framework mainly composed of SystemVerilog libraries. It can be used to build a functional verification environment with a standardized hierarchical structure and interfaces using its reusable components.

[0056] QEMU (Quick EMUlator), a set of software for simulating processors. QEMU is a virtualization simulator implemented purely by software and can simulate almost any hardware device.

[0057] PCIe (Peripheral Component Interconnect express), a high-speed serial computer expansion bus standard, belonging to high-speed serial point-to-point dual-channel high-bandwidth transmission. The devices connected are allocated exclusive channel bandwidth and do not share the bus bandwidth. It mainly supports functions such as active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service (QOS).

[0058] DDR (Double Data Rate SDRAM), double data rate synchronous dynamic random access memory, which transfers data twice within one clock cycle. It can transfer data once during both the rising and falling edges of the clock.

[0059] MAC (Media Access Control), the media access control layer, which defines how data frames are transmitted on the medium. In a link sharing the same bandwidth, the access to the connected medium is "first come, first served". Physical addressing is defined here, and the logical topology (the path of the signal through the physical topology) is also defined here. Line control, error notification (without correction), frame transfer order, and optional flow control are also implemented in this sublayer.

[0060] Such as Figure 1 And Figure 2As shown in the figure, the present invention proposes a software and hardware co - simulation verification platform for accelerating the verification and positioning of intelligent network card chips, including: the host - side QEMU virtual machine 100, the host - side thread adapter 200, the UVM verification platform 300, the network - side data stream adapter 400, and the network - side packet transceiver 500.

[0061] The host - side QEMU virtual machine 100 is used to simulate hardware devices, issue IO requests, respond to IO requests, and call device drivers to implement the driving execution of host - side hardware devices.

[0062] First, determine the test scenarios for FPGA prototype verification. For example, storage - with - stream hot - plugging, the number of mounted disks, IO size, the number of plug - and - unplug operations, and the error - prone areas, etc. Then the host - side QEMU virtual machine 100 is started. The host - side QEMU virtual machine 100 simulates various hardware devices through QEMU software. The host - side QEMU virtual machine 100 simulates the IO requests sent to the front - end driver of the hardware device, and the host - side QEMU virtual machine 100 implements the back - end processing to respond to the IO requests.

[0063] The hardware devices are, for example, virtio - blk, virtio - net and other devices. The host - side QEMU virtual machine 100 sends IO requests to the front - end (frondend) drivers of virtio - blk and virtio - net devices, and QEMU implements the back - end processing program (backend) to respond to the IO requests.

[0064] The host - side QEMU virtual machine 100 can also directly call the device driver (device driver) through the QEMU virtual machine to implement the driving execution of host - side hardware devices, such as Virtio devices.

[0065] The host - side thread adapter 200 (Thread Adapter) is used for inter - process communication, converting the multi - thread processing program of the host - side QEMU virtual machine 100 into a single - thread processing program suitable for the UVM verification platform 300 to implement the interactive communication between the host - side QEMU virtual machine 100 and the UVM verification platform 300.

[0066] Specifically, the host - side thread adapter 200 realizes the interaction between the UVM SystemVerilog program and the QEMU virtual machine C program through the DPI - C (Direct Programming Interface) interface, thereby realizing the interactive communication between the host - side QEMU virtual machine 100 and the UVM verification platform 300.

[0067] The UVM verification platform 300 is used to simulate and reproduce the FPGA prototype verification of the intelligent network card chip according to the Ethernet packets sent by the data stream adapter 400 on the network side, generate simulation waveforms and simulation logs, and send them to the data stream adapter 400 on the network side in the form of Ethernet packets.

[0068] In an embodiment of the present invention, the UVM verification platform 300 includes a global environment configuration A, a PP component M, an AC simulation model, a DDR simulation model, a reference model, a scoreboard, and an instantiated design under test (DUT), etc.

[0069] The data stream adapter 400 (Data Streaming Adapter) on the network side converts the data type of the received Ethernet packets generated by the packet transceiver 500 on the network side through the DPI-C interface, and sends the converted data to the UVM verification platform 300; and converts the data type of the Ethernet packets returned by the UVM verification platform 300 through the DPI-C interface, and sends the converted data to the packet transceiver 500 on the network side.

[0070] The packet transceiver 500 (Packet Generator) on the network side is used to simulate and generate Ethernet packets, encapsulate Ethernet data packets by controlling the address, payload, packet length, packet type, etc., send Ethernet packets to the data stream adapter 400 on the network side in the packet format and data structure specified by the TCP / IP (Transmission Control Protocol / Internet Protocol) protocol, and perform packet legality checks on the Ethernet packets returned by the data stream adapter 400 on the network side. According to the simulation waveforms and simulation logs dynamically simulated by the EDA (Electronic Design Automation) simulation tool, reproduce, locate, correct, and perform regression tests on the scenario problems in the FPGA prototype verification, and perform regression tests on the FPGA prototype verification.

[0071] In addition, the packet transceiver 500 on the network side is also used to inject various abnormal Ethernet packets, generate damaged Ethernet data packets, and perform network abnormal packet sending and receiving tests.

[0072] In an embodiment of the present invention, the packet transceiver 500 on the network side performs packet legality checks on the Ethernet packets returned by the data stream adapter 400 on the network side according to the data format specified by the TCP / IP protocol. The following processing is performed according to the inspection results: packet reception, discard, or reply.

[0073] The host - side QEMU virtual machine 100, UVM verification platform 300, and network - side data packet transceiver 500 generate simulation waveforms and simulation logs. Through the graphical interface tool, the waveforms and the design code of the device under test (DUT) are opened, and combined with the simulation logs, the scenario problems in the FPGA prototype verification are located.

[0074] The software - hardware co - simulation verification platform for accelerating the verification and location of the intelligent network card chip in the embodiments of the present invention is used for problem reproduction testing. The main process is as follows: First, start QEMU and wait for a connection on its remote port (RP); start the simulator. The simulator can be mainstream simulators such as VCS, IRUN / Xcelium, ModelSim / QuestaSim, etc. The simulator will start compiling the DUT design code and UVM verification environment code. After compilation, it is ready to start the simulation; connect the QEMU virtual machine to the simulator, and QEMU starts and loads the Linux kernel; QEMU calls system - related driver programs and application programs; the network packet transceiver receives or sends network packets; the simulator runs the simulation to generate simulation waveforms and simulation logs; end the simulation, and through the graphical interface tool (Verdi), open the waveforms and design code, and combine with the simulation logs to locate the problems.

[0075] The following refers to Figure 3 The process of reproducing the scenario problem of network packet sending in the verification of the intelligent network card chip system in the embodiments of the present invention is described.

[0076] a) First, start QEMU and wait for a connection on its remote port (RP).

[0077] b) Start the simulator. Here, take the VCS simulator as an example. The VCS simulator will start compiling the DUT design code and UVM verification environment code. After compilation, it is ready to start the simulation.

[0078] c) Connect the QEMU virtual machine to the simulator, and QEMU starts and loads the Linux kernel.

[0079] d) The simulator starts running the simulation to generate simulation waveforms and simulation logs.

[0080] e) QEMU first calls system - related driver programs to initialize the host system and DUT, including host - side system memory management and allocation, PCIe driver, Virtio driver, OVS driver, etc., and initializes the DUT through calling the intelligent network card - related driver.

[0081] f) After initializing the DUT, QEMU calls the iperf application program to send network TCP or UDP network packets.

[0082] g) The thread adapter converts the DUT initialization configuration sent by QEMU and the multi-thread processing request for network packet sending into a single-thread processing request that can be processed by the UVM verification environment, and sends it to the app driver.

[0083] h) The app driver converts the request sent by the thread adapter into an interface timing that the DUT can recognize.

[0084] i) The DUT performs a series of related operations according to the driver configuration and application program sent by QEMU, including mode initialization, reading various initialized descriptors in the host-side memory, reading the data to be sent according to the descriptors, updating the descriptors, writing back relevant states to the host-side, reporting interrupts, etc. Finally, the network packet is sent to the mac agent through the MAC port.

[0085] j) The monitor in the mac agent sends the received network packet to the network-side data stream adapter 400. The data stream adapter converts the data type of the received network packet through the DPI-C interface and transfers it to the network packet transceiver after processing.

[0086] k) The network packet transceiver checks the legality of the received network packet and performs corresponding processing, including packet reception, discarding, reply, etc.

[0087] l) End the simulation, open the waveform and DUT design code through the graphical interface tool (Verdi), and combine with the simulation log to locate the problem.

[0088] Refer to the following Figure 4 The problem reproduction process for verifying the network packet reception scenario of the intelligent network card chip system according to the embodiments of the present invention is described.

[0089] a) First, start QEMU and wait for a connection on its remote port (RP).

[0090] b) Start the simulator. Here, the VCS simulator is taken as an example. The VCS simulator will start compiling the DUT design code and the UVM verification environment code, and start the simulation after compilation.

[0091] c) Connect the QEMU virtual machine to the simulator, and QEMU starts and loads the Linux kernel.

[0092] d) The simulator starts running the simulation, generating simulation waveforms and simulation logs.

[0093] e) QEMU first calls the system-related drivers to initialize the host system and the DUT, including host-side system memory management and allocation, PCIe drivers, Virtio drivers, OVS drivers, etc., and initializes the DUT through calling the intelligent network card-related drivers.

[0094] f) The thread adapter converts the multi-thread processing request for DUT initialization configuration sent by QEMU into a single-thread processing request that can be processed by the UVM verification environment and sends it to the app driver.

[0095] g) The app driver converts the request sent by the thread adapter into the interface timing that the DUT can recognize.

[0096] h) The DUT performs a series of related operations according to the driver configuration and application program sent by QEMU, including mode initialization, reading various initialized descriptors in the host-side memory, prefetching descriptors, updating descriptors, writing back relevant statuses to the host side, reporting interrupts, etc.

[0097] i) The network-side packet transceiver 500 simulates and generates Ethernet packets, defines the Ethernet data packets by controlling the address, payload, packet length, packet type, etc., and sends them to the network-side data stream adapter 400 in a fixed format and data structure.

[0098] j) The data stream adapter converts the received network packets through the DPI-C interface, processes them, and sends them to the mac driver.

[0099] k) The mac driver converts the request sent by the data stream adapter into the interface timing that the DUT can recognize.

[0100] l) The DUT sends the received network packets to the app agent after relevant processing.

[0101] m) The monitor in the app agent sends the received network packets to the thread adapter, and the thread adapter converts the received network packets through the DPI-C interface, processes them, and passes them to QEMU.

[0102] n) QEMU performs a legality check on the received network packets and makes corresponding processing, including packet reception, discarding, reply, etc.

[0103] o) End the simulation, open the waveform and DUT design code through the graphical interface tool (Verdi), and combine with the simulation log to locate problems.

[0104] The software and hardware co - simulation verification platform and test method for accelerating the verification and positioning of intelligent network card chips in the embodiments of the present invention run the software driver directly on the UVM functional verification platform, adopt the software - hardware co - simulation method, quickly reproduce the problems found in the FPGA prototype verification, and construct the software - hardware co - simulation verification platform by introducing the host - side QEMU virtual machine, the host - side thread adapter, the network - side data packet transceiver, the network - side data flow adapter, and combining with the UVM verification platform. The present invention can be directly applied to the intelligent network card chip verification project, and can also be used in different chip verification projects, including the verification of GPU and intelligent AI chips, which can significantly accelerate the problem positioning of chip verification, and thus accelerate the verification convergence of the chip.

[0105] The software and hardware co - simulation verification platform for accelerating the verification and positioning of intelligent network card chips according to the embodiments of the present invention has the following beneficial effects:

[0106] (1) Solve the problem of insufficient excitation sources in UVM functional simulation. The driver software can run directly on the software - hardware co - simulation platform. The software driver can be directly used on the UVM functional simulation verification platform, reducing the repeated development of the driver software. At the same time, the simulation excitation source is not limited to the traditional UVM verification platform, and more realistically simulates various network, storage, and security acceleration scenarios, reducing both the repeated driver development and improving the test scenario coverage rate, thereby improving the verification quality.

[0107] (2) Can reproduce the problems found in the FPGA prototype verification on the software - hardware co - simulation platform. Through the software - hardware co - simulation verification platform, the software driver program and the application test program can run directly on the UVM functional simulation platform. The problems found in the FPGA prototype verification can be directly reproduced on the software - hardware co - simulation verification platform. Through the simulation waveform and simulation log, quickly locate the problems and repair the DUT design defects. At the same time, perform regression tests on the software - hardware co - simulation platform and the FPGA prototype verification platform, thereby accelerating the problem positioning of intelligent network card chip verification and accelerating the verification convergence of the chip.

[0108] (3) By introducing the host - side QEMU virtual machine, realize the simulation of various hardware devices and the execution of the host - side hardware device drivers.

[0109] (4) Through software - hardware co - simulation verification, the problem - positioning speed is improved, the chip verification efficiency is improved, the overall chip development cycle is shortened, and the chip quality is improved.

[0110] (5) By introducing a host - side thread adapter, inter - process communication between a multi - threaded program and a single - threaded handler is achieved. Through the DPI - C interface, the UVM SystemVerilog program interacts with the QEMU virtual machine C program, realizing communication between multiple processes and a single thread, and further realizing the interactive communication between the QEMU virtual machine and the UVM verification environment.

[0111] (6) By introducing a network - side data - flow adapter, data - type conversion for network packet sending and receiving is achieved, and further the interactive communication between the network packet transceiver and the UVM verification environment is realized.

[0112] (7) By introducing a network - side packet transceiver, the simulation generation and reception processing of Ethernet packets are realized.

[0113] (8) The software driver can be directly used in the UVM functional simulation verification platform, reducing the repeated development of the driver software. At the same time, the simulation excitation source is not limited to the traditional UVM verification platform, more realistically simulating various network, storage, and security acceleration scenarios. This not only reduces the repeated driver development but also improves the test - scenario coverage rate, thereby improving the verification quality.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A software and hardware co - simulation verification platform for accelerating the verification and positioning of intelligent network card chips, characterized in that Including: The host - side QEMU virtual machine, the host - side thread adapter, the UVM verification platform, the network - side data stream adapter, and the network - side packet transceiver. Among them, The host - side QEMU virtual machine is used to simulate hardware devices, issue IO requests, respond to IO requests, and call device drivers to implement the drive execution of host - side hardware devices; The host - side thread adapter is used for inter - process communication, converting the multi - thread processing program of the host - side QEMU virtual machine into a single - thread processing program suitable for the UVM verification platform to achieve the interactive communication between the host - side QEMU virtual machine and the UVM verification platform; The UVM verification platform is used to perform simulation reproduction of the FPGA prototype verification of the intelligent network card chip according to the Ethernet packets sent by the network - side data stream adapter, generate simulation waveforms and simulation logs, and send them to the network - side data stream adapter in the form of Ethernet packets; The network - side data stream adapter performs data - type conversion on the received Ethernet packets generated by the network - side packet transceiver, and sends the converted data to the UVM verification platform; and performs data - type conversion on the Ethernet packets returned by the UVM verification platform, and sends the converted data to the network - side packet transceiver; The network - side packet transceiver is used to simulate and generate Ethernet packets, send the Ethernet packets to the network - side data stream adapter in the packet format and data structure specified by the TCP / IP protocol, and perform packet legality checks on the Ethernet packets returned by the network - side data stream adapter. According to the simulation waveforms and simulation logs dynamically simulated by the EDA simulation tool, reproduce and locate the scenario problems in the FPGA prototype verification, and perform correction and regression testing, and conduct regression testing on the FPGA prototype verification.

2. The software and hardware co-simulation verification platform for accelerating the verification and positioning of intelligent network card chips according to claim 1, characterized in that The host - side QEMU virtual machine simulates the IO requests sent by the front - end driver of the hardware device, and the host - side QEMU virtual machine implements back - end processing and responds to the IO requests.

3. The software and hardware co-simulation verification platform for accelerating the verification and positioning of an intelligent network card chip according to claim 1, wherein, The host - side thread adapter realizes the interaction between the UVM SystemVerilog program and the C program of the host - side QEMU virtual machine through the DPI - C interface.

4. The software and hardware co - simulation verification platform for accelerating the verification and positioning of intelligent network card chips according to claim 1, wherein The host - side QEMU virtual machine calls device drivers to initialize the host system and the design under test (DUT), including host - side system memory management and allocation, PCIe driver, Virtio driver, and OVS driver, and initializes the DUT through calling the intelligent network card - related drivers.

5. The software and hardware co-simulation verification platform for accelerating the verification and positioning of an intelligent network card chip according to claim 1, characterized in that, The UVM verification platform includes global environment configuration, APP components, MAC simulation models, DDR simulation models, reference models, scoreboards, and instantiation of the design under test (DUT).

6. The software and hardware co-simulation verification platform for accelerating the verification and positioning of intelligent network card chips according to claim 1, characterized in that The network - side data stream adapter realizes data - type conversion on the Ethernet packets received and sent by the UVM verification platform through the DPI - C interface.

7. The software and hardware co - simulation verification platform for accelerating the verification and positioning of an intelligent network card chip according to claim 1, characterized in that, The network - side packet transceiver is also used to encapsulate Ethernet packets according to the control address, payload, packet length, and packet type.

8. The software and hardware co-simulation verification platform for accelerating the verification and positioning of intelligent network card chips according to claim 1, wherein, The network - side packet transceiver is also used to inject various abnormal Ethernet messages, generate damaged Ethernet data messages, and perform network abnormal message sending and receiving tests.

9. The software and hardware co - simulation verification platform for accelerating the verification and positioning of intelligent network card chips according to claim 1, characterized in that, The network - side packet transceiver checks the message legality of the Ethernet messages returned by the network - side data stream adapter, and performs the following processing according to the check results: message reception, discard, or reply.

10. The software and hardware co - simulation verification platform for accelerating the verification and positioning of an intelligent network card chip according to claim 1, wherein, For the host - side QEMU virtual machine, UVM verification platform, and network - side packet transceiver, the generated simulation waveforms and simulation logs are used to open the waveforms and the design code of the device under test (DUT) through a graphical interface tool, and combined with the simulation logs, the scenario problems in the FPGA prototype verification are located.

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