A compound heterojunction p-type transistor and its preparation method

Abstract

The present invention provides a compound heterojunction p-type transistor and a preparation method thereof, belonging to the technical field of semiconductor devices. The p-type transistor includes a substrate and an active region located on the substrate, which is formed by sequentially stacking a buffer layer, a first channel layer, a barrier layer, and a second channel layer; a gate trench for depositing a gate is etched on the upper layer of the second channel layer, and the source and drain are located on both sides of the gate; an ohmic metal layer that forms an ohmic contact with both the source and drain is disposed from the upper surface of the second channel layer around the opening of the gate trench along the sidewall of the gate trench to a position adjacent to the sidewall at the bottom thereof; the source and drain are isolated from the upper surface of the second channel layer, and the gate is isolated from the bottom of the gate trench by a first dielectric layer; a second dielectric layer is disposed between the gate and the ohmic metal layer; the second channel layer is a p-type oxide layer and / or a p-type nitride layer. The structure of the p-type transistor can effectively reduce the device size and improve its current capacity, switching speed, and hole mobility in the channel.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a compound heterojunction p-type transistor and a preparation method thereof. Background Art

[0002] In the traditional compound heterojunction (for example, p-GaN / AlGaN / GaN heterojunction) plane, there is only a hole channel composed of a two-dimensional holes gas (2DHG) layer on the p-GaN / AlGaN interface and p-GaN. Limited by the hole mobility in GaN, the hole current density is greatly restricted. The multiple p-channels form multiple 2DHG channels by periodically repeating the p-GaN / AlGaN structure on the GaN buffer layer, and connect these 2DHG channels through a p-type ohmic metal layer. In order to control the deep channels in the multiple p-channels, the device adopts a fin-shaped gate, and controls the 2DHG in the channel through the metal on the sidewall of the fin structure, which not only realizes the switching control of the device but also increases the effective gate width. Through the above measures, the multiple p-channel structure can increase the device current density to 66 mA / mm, and its specific on-resistance (R on,sp ) is reduced to 86 mΩ·mm, which is basically equivalent to that of the existing GaN n-type transistors. However, the epitaxial structure adopted by this type of device cannot be compatible with electron transport structures such as two-dimensional electron gas (2DEG). If corresponding heterojunctions are not prepared by methods such as secondary epitaxy, GaN n-type transistors cannot be formed. Therefore, this technical solution cannot realize GaN CMOS circuits.

[0003] Due to the low hole mobility (<12 cm 2 / (V·s), the resistivity of the gate channel of the GaN p-type transistor is extremely high, increasing the on-resistance of the GaN p-type transistor. If the channel length of the device can be reduced, the on-resistance of the device can be effectively reduced and the current-carrying capacity of the device can be improved. However, the reduction of the device size is limited by the accuracy of processes such as patterning and lithography. For example, with the traditional recessed gate structure, the structural dimensions such as the gate-source spacing, gate-drain spacing, and gate length are all limited by the critical dimension of the lithography process, increasing the length of the device current path. Therefore, Nadim Chowdhury et al. from the Massachusetts Institute of Technology proposed a method for preparing a recessed gate of a GaN p-type transistor by using a p-type ohmic metal as a hard mask for GaN material etching in "First demonstration of a self-aligned GaN p-FET" (DOI: 10.1109 / IEDM19573.2019.8993569). In this way, the gate trench of the device is adjacent to the drain and source ohmic metals, eliminating the gate-source spacing and gate-drain spacing, and the patterning is not limited by the overlay accuracy; at the same time, the channel length is only limited by the ohmic metal spacing, enabling the device length to be greatly reduced without reducing the critical dimension of lithography. In this scheme, on the basis of self-alignment, the gate can also be fabricated into a Fin structure, thereby further increasing the device current density. However, the preparation of the Fin structure requires a lithography method that can achieve smaller critical dimensions, which is more demanding for existing power semiconductor production lines; if methods such as electron beam lithography are used, although the requirements for self-aligned structure patterning can be met, it poses a great challenge to production efficiency and is not conducive to the production of power semiconductor devices. Moreover, this structure still does not solve the problem of low hole mobility in the channel of the GaN p-type transistor.

[0004] Some scholars have carried out theoretical analysis based on first principles and proposed to change the biaxial stress in the

[0001] crystal plane of GaN to improve the hole mobility therein in "Hole mobility of strained Ga N from first principles" (DOI: https: / / doi.org / 10.1103 / PhysRevB.100.085204). According to this study, when the planar biaxial stress increases by 2% from full relaxation, the hole mobility can increase from 42 cm 2 / (V·s) to 113 cm 2 / (V·s). "High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN xIt is confirmed in "gate insulator for high hole mobility》(DOI: 10.1088 / 1674 - 4926 / 44 / 8 / 082801) that when using Si-rich LPCVD SiN as the p-type channel gate dielectric in a p-GaN / AlGaN / GaN heterojunction, a channel hole mobility as high as 20 cm² / V·s is obtained. In other reports, the hole mobility in the etched GaN p-type channel is mostly lower than 12 cm² / V·s. Compared with devices using metal oxide gate dielectrics and conventional trench gate structures, using Si-rich LP CVD SiN gate dielectric can obtain a higher current density under similar device dimensions. Although the existing solutions effectively improve the channel mobility and achieve a higher current density under similar device dimensions, the experiment also reveals that the high-temperature process of LPCVD depositing SiN has a negative impact on the hole transport ability of the p-GaN / AlGaN / GaN heterojunction. First, the high-temperature process increases the contact resistance of the p-type ohmic contact on the p-GaN / AlGaN / GaN heterojunction; second, the high-temperature process also increases the sheet resistance of the p-GaN / AlGaN / GaN heterojunction. This phenomenon indicates that the existing hole modulation technology is not yet perfect and there is still a large room for improvement. Based on mobility modulation, the device gate is fabricated by combining the method in the self-alignment scheme of the Massachusetts Institute of Technology. The ohmic metal layer formed by the device drain and source defines the device gate position, so that there is no gate-source or gate-drain connection area in the device, and the resistance of the gate-source / gate-drain area deteriorated by the high-temperature process can be avoided. However, due to the high temperature during the LPCVD SiN deposition process, this process cannot be compatible with the ohmic metal used as the hard mask for gate trench etching, and it is difficult to use the existing self-alignment method to achieve the purpose of reducing the device size. x As the p-type channel gate dielectric, a channel hole mobility as high as 20 cm² 2 / V·s is obtained. While in other reports, the hole mobility in the etched GaN p-type channel is mostly lower than 12 cm² 2 / V·s. Compared with devices using metal oxide gate dielectrics and conventional trench gate structures, using Si-rich LP CVD SiN x gate dielectric can obtain a higher current density under similar device dimensions. Although the existing solutions effectively improve the channel mobility and achieve a higher current density under similar device dimensions. However, the experiment also reveals that the LPCVD deposition of SiN x The high-temperature process will have a negative impact on the hole transport ability of the p-GaN / AlGaN / GaN heterojunction. First, the high-temperature process increases the contact resistance of the p-type ohmic contact on the p-GaN / AlGaN / GaN heterojunction; second, the high-temperature process also increases the sheet resistance of the p-GaN / AlGaN / GaN heterojunction. This phenomenon indicates that the existing hole modulation technology is not yet perfect and there is still a large room for improvement. Based on mobility modulation, the device gate is fabricated by combining the method in the self-alignment scheme of the Massachusetts Institute of Technology. The ohmic metal layer formed by the device drain and source defines the device gate position, so that there is no gate-source or gate-drain connection area in the device, and the resistance of the gate-source / gate-drain area deteriorated by the high-temperature process can be avoided. However, due to the high temperature during the LPCVD SiN x deposition process, this process cannot be compatible with the ohmic metal used as the hard mask for gate trench etching, and it is difficult to use the existing self-alignment method to achieve the purpose of reducing the device size. Summary of the Invention

[0005] To solve the problems in the above-mentioned prior art, the present invention provides a compound heterojunction p-type transistor. This compound heterojunction p-type transistor can effectively reduce the device size, improve the current capacity, switching speed and hole mobility in the channel of the device.

[0006] Specifically, the present invention adopts the following technical solutions to achieve the above purpose:

[0007] A compound heterojunction p-type transistor, which sequentially includes a substrate, a buffer layer, a first channel layer, a barrier layer, a second channel layer, as well as a source electrode, a drain electrode and a gate electrode from bottom to top; an active region is formed by the upper layer of the buffer layer, the first channel layer, the barrier layer and the second channel layer, and a passive region is around the active region; in the active region, a gate trench is etched on the side of the second channel layer facing away from the barrier layer, the gate electrode is arranged in the gate trench, and the source electrode and the drain electrode are located on both sides of the gate electrode; an ohmic metal layer is arranged from the upper surface of the second channel layer around the opening of the gate trench along the side wall of the gate trench to the position adjacent to the side wall at the bottom of the gate trench, and both the source electrode and the drain electrode form ohmic contacts with the second channel layer; a first dielectric layer is arranged between the source electrode and the upper surface of the second channel layer, between the drain electrode and the upper surface of the second channel layer, and between the gate electrode and the inner surface of the bottom of the gate trench; a second dielectric layer is arranged between the gate electrode and the ohmic metal layer; the material of the second channel layer is a p-type oxide semiconductor material or / and a p-type nitride semiconductor material. The first channel layer, the barrier layer and the second channel layer form a compound semiconductor heterojunction.

[0008] In some specific embodiments, the ohmic metal layer is a double-layer metal layer of Ni and Au or a triple-layer metal layer of Ni, Pb and Au.

[0009] In some specific embodiments, the second dielectric layer is an oxide layer formed by the metal in the ohmic metal layer during the oxidation annealing process.

[0010] In some specific embodiments, the second dielectric layer is an insulating layer formed by depositing an insulating material, and the insulating layer is located between the ohmic metal layer and the gate electrode and between the gate electrode and the first dielectric layer.

[0011] In some specific embodiments, the insulating layer is at least one of a Si3N4 layer, a SiO2 layer, a SiON layer, and an Al2O3 layer.

[0012] In some specific embodiments, the material of the first dielectric layer is at least one of Si3N4, SiO2, SiON, and Al2O3.

[0013] In some specific embodiments, the substrate is any one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium oxide substrate or a QST substrate. The QST substrate refers to a substrate produced by a substrate technology developed by Qromis, Inc. in the United States.

[0014] In some specific embodiments, the material of the barrier layer is aluminum gallium oxide or / and aluminum gallium nitride.

[0015] In some specific embodiments, the material of the first channel layer is gallium oxide or / and gallium nitride.

[0016] In some other specific embodiments, the material of the first channel layer is gallium oxide, the material of the barrier layer is aluminum gallium oxide, and the material of the second channel layer is p-type gallium oxide. Therefore, in the compound heterojunction p-type transistor, the first channel layer, the barrier layer, and the second channel layer form a p-GaO / AlGaO / GaO heterojunction structure.

[0017] In some other specific embodiments, the material of the first channel layer is gallium nitride, the material of the barrier layer is aluminum gallium nitride, and the material of the second channel layer is p-type gallium nitride. Therefore, in the compound heterojunction p-type transistor, the first channel layer, the barrier layer, and the second channel layer form a p-GaN / AlGaN / GaN heterojunction structure.

[0018] In some specific embodiments, the material of the buffer layer is gallium oxide or / and gallium nitride.

[0019] In some specific embodiments, in a direction perpendicular to the direction from the source to the drain, a plurality of the gate trenches are arranged in sequence to form a fin structure, and the gate is a fin-shaped gate.

[0020] The present invention also provides a method for manufacturing the compound heterojunction p-type transistor according to any one of the above, including the following steps:

[0021] S1. Prepare an epitaxial wafer having a heterojunction structure, which sequentially includes a substrate, a buffer layer, a first channel layer, a barrier layer, and a second channel layer from bottom to top; the material of the second channel layer is a p-type oxide semiconductor material or / and a p-type nitride semiconductor material;

[0022] S2. Perform a mesa process to define an active region and a passive region;

[0023] S3. Etch gate trenches in the second channel layer;

[0024] S4. Deposit a first dielectric layer on the upper surface of the structure obtained in step S3;

[0025] S5. Etch the first dielectric layer and deposit an ohmic metal material to obtain an ohmic metal layer;

[0026] S6. Anneal the ohmic metal layer to form an oxide layer on the surface of the ohmic metal layer as a second dielectric layer; or anneal the ohmic metal layer and deposit an insulating material on the upper surface of the structure obtained after annealing to form an insulating layer as a second dielectric layer;

[0027] S7. Deposit gate metal in the gate trench to obtain a gate;

[0028] S8. Etch the second dielectric layer, and deposit source metal and drain metal on the upper surface of the device structure obtained in step S7 to obtain a source and a drain respectively.

[0029] In some specific embodiments, the conditions for annealing the ohmic metal layer in step S6 are: annealing at 550 °C for 5 min in an oxygen atmosphere or a mixed atmosphere of nitrogen and oxygen.

[0030] In some specific embodiments, in the mixed atmosphere of nitrogen and oxygen, 25% ≤ the volume percentage content of oxygen < 100%.

[0031] In some specific embodiments, the material of the ohmic metal layer is a double-layer metal layer of Ni and Au or a triple-layer metal layer of Ni, Pb and Au.

[0032] In some specific embodiments, the insulating material in step S6 is at least one of Si3N4, SiO2, SiON, and Al2O3.

[0033] In some specific embodiments, in step S4, at least one of Si3N4, SiO2, SiON, and Al2O3 is deposited by any one of LPCVD, PECVD, PEALD, and ALD to form the first dielectric layer.

[0034] In some specific embodiments, the material of the barrier layer is aluminum gallium oxide or / and aluminum gallium nitride.

[0035] In some specific embodiments, the material of the first channel layer is gallium oxide or / and gallium nitride.

[0036] In some other specific embodiments, the material of the first channel layer is gallium oxide, the material of the barrier layer is aluminum gallium oxide, and the material of the second channel layer is p-type gallium oxide. Therefore, in the compound heterojunction p-type transistor, the first channel layer, the barrier layer, and the second channel layer form a p-GaO / AlGaO / GaO heterojunction structure.

[0037] In some other specific embodiments, the material of the first channel layer is gallium nitride, the material of the barrier layer is aluminum gallium nitride, and the material of the second channel layer is p-type gallium nitride. Therefore, in the compound heterojunction p-type transistor, the first channel layer, the barrier layer, and the second channel layer form a p-GaN / AlGaN / GaN heterojunction structure.

[0038] In some specific embodiments, the material of the buffer layer is gallium oxide or / and gallium nitride.

[0039] In some specific embodiments, in step S3, a plurality of gate trenches are sequentially etched on the second channel layer to form a fin structure, and the gate fabricated in step S7 is a fin gate.

[0040] The present invention has the following beneficial effects: 1. The compound heterojunction p-type transistor in the present invention realizes a device self-aligned gate structure through an ohmic metal layer extending into the gate trench, effectively reducing the spacing between the gate-source and gate-drain of the device, reducing the device size, and improving the current capacity and switching speed of the device. 2. The self-aligned method of the compound heterojunction p-type transistor in the present invention enables the device to be compatible with more types of dielectric layers. By using a dielectric material that modulates the hole mobility of the semiconductor, the hole mobility in the channel is improved, and the channel transport ability of the device is improved. Description of the Drawings

[0041] Figure 1 It is a three-dimensional structure schematic diagram of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0042] Figure 2 It is Figure 1 a cross-sectional view along the source-to-drain direction of the upper edge; and it is also a cross-sectional schematic diagram of the structure of the compound heterojunction p-type transistor obtained in step S8 in a preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0043] Figure 3 It is a three-dimensional structure schematic diagram of another compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0044] Figure 4 It is a top view of another compound heterojunction p-type transistor provided by an embodiment of the present invention, and the gate of the compound heterojunction p-type transistor is a fin gate;

[0045] Figure 5 It is Figure 4 a cross-sectional view along the AA' direction of the upper edge;

[0046] Figure 6 It is Figure 4 a cross-sectional view along the BB' direction of the upper edge;

[0047] Figure 7 It is a schematic diagram of the structure of an epitaxial wafer obtained in step S1 in a preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0048] Figure 8 It is a schematic diagram of the structure obtained in step S2 in a preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0049] Figure 9Schematic diagram of the structure obtained in step S3 in the preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0050] Figure 10 Schematic diagram of the structure obtained in step S4 in the preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0051] Figure 11 Schematic diagram of the structure obtained in step S5 in the preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0052] Figure 12 Schematic diagram of the structure obtained in step S6 in the preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0053] Figure 13 Schematic diagram of the structure obtained in step S7 in the preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0054] Figure 14 Schematic diagram of the structure obtained after etching the second dielectric layer in step S8 in the preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0055] Figure 15 Schematic diagram of the structure obtained in step S6 in another preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0056] Figure 16 Schematic diagram of the structure obtained in step S7 in another preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention;

[0057] Figure 17 Cross-sectional schematic diagram of the structure of the compound heterojunction p-type transistor obtained in step S8 in another preparation method of a compound heterojunction p-type transistor provided by an embodiment of the present invention, and at the same time Figure 3 Cross-sectional view along the source-drain direction.

[0058] In the figure: 101, substrate; 102, buffer layer; 103, first channel layer; 104, barrier layer; 105, second channel layer; 106, source electrode; 107, drain electrode; 108, gate electrode; 109, gate trench; 110, ohmic metal layer; 111, first dielectric layer; 112, second dielectric layer; C, active region; D, passive region. Detailed implementation manners

[0059] The following content describes the technical solution of the present invention clearly and completely in combination with embodiments, so that those skilled in the art can fully understand the present invention. Obviously, the described embodiments are only some preferred embodiments of the present invention, rather than all embodiments. Any equivalent transformation or substitution made to the following embodiments by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0060] The directional terms mentioned in the present invention, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship in the specification drawings, or the orientation or positional relationship in which the product of the present invention is usually placed during use. It is only for the convenience of describing and understanding the product structure of the present invention. Therefore, the directional terms should not be construed as a limitation to the present invention. In the present invention, unless otherwise clearly defined, expressions such as "on", "above", "over", and "upper surface" of the first feature with respect to the second feature mean that the first feature and the second feature can be in direct contact or indirectly in contact through an intermediate medium; it can be that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is at a higher horizontal height than the second feature. Expressions such as "under", "below", "beneath", and "lower surface" of the first feature with respect to the second feature mean that the first feature and the second feature can be in direct contact or indirectly in contact through an intermediate medium; it can be that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is at a lower horizontal height than the second feature. The ordinal numbers used in the present invention, such as "first", "second", etc., are only for descriptive purposes to distinguish similar objects, and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0061] For a better understanding of the present invention, the following combines Figures 1 to 17 to describe in detail the specific embodiments of the compound heterojunction p-type transistor of the present invention and its preparation method.

[0062] As Figure 1 and Figure 2 shown, it is a schematic structural diagram of a compound heterojunction p-type transistor provided by an embodiment of the present invention. Figure 2 is Figure 1Cross-sectional view along the source-to-drain direction. The compound heterojunction p-type transistor includes, from bottom to top, a substrate 101, a buffer layer 102, a first channel layer 103, a barrier layer 104, and a second channel layer 105; the upper layer of the buffer layer 102, the first channel layer 103, the barrier layer 104, and the second channel layer 105 form an active region C, and the passive region D is around the active region C. In the active region C, a gate trench is etched on the side of the second channel layer 105 facing away from the barrier layer 104, and the bottom of the gate trench is located in the second channel layer 105. In the direction perpendicular to the source-to-drain direction, the gate trench is a long strip-shaped trench. The gate 108 is deposited in the gate trench. The source 106 and the drain 107 are respectively located on both sides of the gate 108. An ohmic metal layer 110 is provided from the upper surface of the second channel layer 105 around the opening of the gate trench along the sidewall of the gate trench to the position adjacent to the sidewall at the bottom of the gate trench, that is, the ohmic metal layer 110 is provided on the upper surface of the second channel layer 105 around the opening of the gate trench, the inner wall of the gate trench, and the edge position near the sidewall at the bottom of the gate trench. Both the source 106 and the drain 107 form ohmic contacts with the second channel layer 105. The source 106 and the upper surface of the second channel layer 105, the drain 107 and the upper surface of the second channel layer 105, and the gate foot of the gate 108 and the second channel layer 105 are insulated and isolated by the first dielectric layer 111. An oxide layer is formed on the surface of the ohmic metal layer 110 through oxidation annealing, and this oxide layer serves as the second dielectric layer 112 for insulating and isolating the gate 108 and the ohmic metal layer 110. Among them, the material of the buffer layer 102 is gallium oxide (GaO), the material of the first channel layer 103 is GaO, the material of the barrier layer 104 is aluminum gallium oxide (AlGaO), the material of the second channel layer 105 is p-type gallium oxide (p-GaO), the material of the gate 108 is metal (such as Ni / Au), the material of the first dielectric layer 111 is Si3N4, and the material of the ohmic metal layer is a double-layer metal of Ni and Au. The gate 108 and the first dielectric layer 111 and the second channel layer 105 form a metal-insulator-semiconductor structure.

[0063] As Figure 3As shown, in other embodiments, other insulating materials (such as SiO2) are deposited on the upper surface of the ohmic metal layer 110 and along the inner walls (including sidewalls and bottom inner walls) of the gate trench to form an insulating layer as the second dielectric layer 112. That is, at the bottom of the gate trench, the second dielectric layer 112 is located on the upper surface of the first dielectric layer 111, and the gate feet of the gate 108 and the second channel layer 105 are insulated from each other by the first dielectric layer 111 and the second dielectric layer 112; the gate 108 and the ohmic metal layer 110 are insulated from each other by the second dielectric layer 112. Among them, the material of the buffer layer 102 is GaN, the material of the first channel layer 103 is gallium nitride (GaN), the material of the barrier layer 104 is aluminum gallium nitride (AlGaN), the material of the second channel layer 105 is p-type gallium nitride (p-GaN), and the material of the gate 108 is metal (such as Ni / Au). The gate 108, the first dielectric layer 111, the second dielectric layer 112, and the second channel layer 105 form a metal-insulator-semiconductor structure.

[0064] It can be understood that the material of the first dielectric layer 111 can also be other insulating materials, such as any one of SiO2, SiON, Al2O3 or their combination or their combination with Si3N4. The insulating material of the second dielectric layer 112 can also be any one of Si3N4, SiON, Al2O3 or their combination or their combination with SiO2.

[0065] As Figures 4 to 6 shown, in other embodiments, in the direction perpendicular to the source-to-drain direction, a plurality of gate trenches are arranged in sequence to form a fin structure, and the gate 108 is a fin gate.

[0066] As Figures 7 to 13 shown, an embodiment of the present invention provides a method for manufacturing a compound heterojunction p-type transistor, including the following steps:

[0067] S1. Epitaxially grow a buffer layer 102, a first channel layer 103, a barrier layer 104, and a second channel layer 105 on a substrate 101 in sequence to obtain an epitaxial wafer (as Figure 7 shown); among them, the material of the substrate 101 is silicon carbide, the material of the buffer layer 102 is GaO, the material of the first channel layer 103 is GaO, the material of the barrier layer 104 is AlGaO, and the material of the second channel layer 105 is p-GaO. Therefore, the prepared epitaxial wafer has a p-GaO / AlGaO / GaO heterojunction structure.

[0068] S2. Perform mesa technique to define the active region C and the passive region D, truncate the carrier transport structure in the heterojunction structure, and achieve electrical isolation between devices, enabling the devices to be isolated from each other, operate independently, and not affect each other. For example, obtain the mesa structure (i.e., the active region C) by removing the two end portions of the upper layer of the buffer layer 102, the two end portions of the first channel layer 103, the two end portions of the barrier layer 104, and the two end portions of the second channel layer 105 through a lithography process. As Figure 8 shown, in a preferred embodiment, the patterned buffer layer 102, the patterned first channel layer 103, the patterned barrier layer 104, and the patterned second channel layer 105 have equal widths and their edges are aligned. The width of the unpatterned buffer layer 102 (i.e., the lower layer of the buffer layer 102) is greater than the width of the mesa structure.

[0069] S3. Etch a gate trench 109 in the upper layer of the second channel layer 105 (see Figure 9 ), and the bottom of the gate trench 109 is located in the second channel layer 105.

[0070] S4. Deposit a first dielectric layer 111 on the upper surface of the structure obtained in step S3 (as Figure 10 shown). The deposition method uses a conventional method in the art, such as any one of LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PEALD (plasma-enhanced atomic layer deposition), and ALD (atomic layer deposition). The deposited material is Al2O3 or Si3N4 or SiO2 or SiON or a combination thereof.

[0071] S5. Etch the first dielectric layer 111 and deposit an ohmic metal material (such as Ni and Au, with a Ni layer thickness of 15 nm and an Au layer thickness of 30 nm) to obtain an ohmic metal layer 110 (as Figure 11 shown).

[0072] S6. Anneal the ohmic metal layer 110 to form an oxide layer (such as a nickel oxide layer) on the surface of the ohmic metal layer 110 as the second dielectric layer 112 (as Figure 12 shown). After annealing, ohmic contacts are formed between the ohmic metal layer 110 and the upper surface of the second channel layer 105, the sidewalls of the gate trench 109, and the edges near the sidewalls at the bottom. The annealing conditions are annealing at 550 °C for 5 min in an oxygen atmosphere or a mixed atmosphere of nitrogen and oxygen (such as a volume ratio of nitrogen to oxygen of 4:1, 3:2, 2:1...).

[0073] S7. Deposit a gate metal in the gate trench 109 to obtain a gate 108 (see Figure 13 ).

[0074] S8. Etch the second dielectric layer 112 (seeFigure 14 ), the source metal and the drain metal are deposited to obtain the source 106 and the drain 107 respectively, and the source 106 and the drain 107 are electrically connected to the ohmic metal layer 110 respectively (see Figure 2 ).

[0075] As Figures 15 to 17 shown, in other embodiments, after annealing the ohmic metal layer 110 in step S6, an insulating material (such as Si3N4 or SiO2 or SiON or Al2O3 or a combination thereof) is deposited on the upper surface of the device structure by LPCVD or PECVD or PEALD or ALD methods to obtain an insulating layer as the second dielectric layer 112. That is, the second dielectric layer 112 is deposited on the exposed surface of the ohmic metal layer 110 and the exposed surface of the first dielectric layer 111. Therefore, at the bottom of the gate trench 109, the second dielectric layer 112 is located on the upper surface of the first dielectric layer 111; after the gate 108 is fabricated in step S7, the gate feet of the gate 108 and the second channel layer 105 are insulated from each other by the first dielectric layer 111 and the second dielectric layer 112. The cross-sectional schematic diagram of the structure of the transistor finally obtained in step S8 is as Figure 17 shown, and the three-dimensional schematic diagram is as Figure 3 shown.

[0076] As Figure 2 and Figure 17 shown, in the structure of the compound heterojunction p-type transistor of the present invention, the ohmic contact is divided into three parts, which are respectively located at: (1) the unetched upper surface of the second channel layer 105; (2) the surface of the second channel layer 105 on the side wall of the gate trench; (3) the surface of the second channel layer 105 at the bottom of the gate trench. Affected by the etching damage, the contact resistance at (2) and (3) is higher than that at (1); but all three inject holes into the second channel layer 105 at the same time, and the ohmic contact is adjacent to the gate, and there is no resistance in the communication area between the gate source or the gate drain. Therefore, by fabricating an ohmic metal layer covering the upper surface of the second channel layer, the side wall and the bottom of the gate trench at one time, a self-alignment scheme for defining the position of the gate trench by the ohmic metal layer can be realized, and the communication structure between the gate source and the gate drain can be eliminated to improve the device current capacity and switching speed.

[0077] The above is only the preferred embodiment of the present invention and is not used to limit the protection scope of the present invention. For any person skilled in the art, the present invention can have various changes and modifications. Any simple equivalent changes and modifications made according to the protection scope of the present invention application and the content of the specification shall be included in the protection scope of the present invention.

Claims

1. A compound heterojunction p-type transistor, characterized in that, It includes a substrate, a buffer layer, a first channel layer, a barrier layer, a second channel layer, as well as a source electrode, a drain electrode, and a gate electrode from bottom to top in sequence; the upper layer of the buffer layer, the first channel layer, the barrier layer, and the second channel layer form an active region, and the periphery of the active region is a passive region; in the active region, a gate trench is etched on the side of the second channel layer facing away from the barrier layer, the gate electrode is disposed in the gate trench, and the source electrode and the drain electrode are located on both sides of the gate electrode; An ohmic metal layer is disposed from the upper surface of the second channel layer around the opening of the gate trench along the sidewall of the gate trench to the position adjacent to the sidewall at the bottom of the gate trench, and both the source electrode and the drain electrode form ohmic contacts with the second channel layer; a first dielectric layer is disposed between the source electrode and the upper surface of the second channel layer, between the drain electrode and the upper surface of the second channel layer, and between the gate electrode and the inner surface of the bottom of the gate trench; a second dielectric layer is disposed between the gate electrode and the ohmic metal layer; the material of the second channel layer is p-type oxide or p-type nitride.

2. The compound heterojunction p-type transistor according to claim 1, characterized in that, The second dielectric layer is an oxide layer formed by the metal in the ohmic metal layer during oxidation annealing.

3. The compound heterojunction p-type transistor according to claim 1, characterized in that The second dielectric layer is an insulating layer formed by depositing an insulating material, and the insulating layer is located between the ohmic metal layer and the gate electrode and between the gate electrode and the first dielectric layer.

4. The compound heterojunction p-type transistor according to claim 1, characterized in that, The material of the first dielectric layer is at least one of Si3N4, SiO2, SiON, and Al2O3.

5. The compound heterojunction p-type transistor according to claim 1, characterized in that, The substrate is any one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium oxide substrate, or a QST substrate.

6. The compound heterojunction p-type transistor according to claim 1, characterized in that, The material of the barrier layer is aluminum gallium oxide or aluminum gallium nitride.

7. The compound heterojunction p-type transistor according to claim 1, characterized in that, The material of the first channel layer is gallium oxide or gallium nitride.

8. The compound heterojunction p-type transistor according to claim 1, characterized in that In a direction perpendicular to the direction from the source electrode to the drain electrode, a plurality of the gate trenches are arranged in sequence to form a fin structure, and the gate electrode is a fin-shaped gate.

9. The preparation method of the compound heterojunction p-type transistor according to any one of claims 1 to 8, characterized in that, It includes the following steps: S1. Prepare an epitaxial wafer with a heterojunction structure, which includes a substrate, a buffer layer, a first channel layer, a barrier layer, and a second channel layer from bottom to top in sequence; the material of the second channel layer is p-type oxide or p-type nitride; S2. Perform a mesa process to define an active region and a passive region; S3. Etch a gate trench on the second channel layer; S4. Deposit a first dielectric layer on the upper surface of the structure obtained in step S3; S5. Etch the first dielectric layer and deposit an ohmic metal material to obtain an ohmic metal layer; S6. Anneal the ohmic metal layer to form an oxide layer on the surface of the ohmic metal layer as the second dielectric layer; or anneal the ohmic metal layer and deposit an insulating material on the upper surface of the structure obtained after annealing to form an insulating layer as the second dielectric layer; S7. Deposit a gate metal in the gate trench to obtain a gate electrode; S8. Etch the second dielectric layer and deposit a source metal and a drain metal on the upper surface of the device structure obtained in step S7 to obtain a source electrode and a drain electrode respectively.

10. The preparation method according to claim 9, characterized in that, The conditions for annealing the ohmic metal layer in step S6 are: annealing at 550 °C for 5 min in an oxygen atmosphere or a mixed atmosphere of nitrogen and oxygen.

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