Logarithmic response high dynamic range pixel based on charge compensation

Abstract

The application discloses a logarithmic response high dynamic range pixel based on charge compensation, which is realized based on a 4T pixel structure, wherein a transfer tube HDR and an FD2 node serving as a low gain node are arranged on the basis of the 4T pixel structure, an MIM capacitor C is circumscribed on the FD2 node, the 4T pixel is expanded into a 5T pixel structure with a DCG, the emitter of the transfer tube HDR is connected with an FD1 node serving as a high gain node, the collector is connected with the FD2 node, the emitter of the FD2 node is connected with the emitter of a reset tube RST, the collector of the reset tube RST is connected with VDD, the other end of the MIM capacitor C is connected with the ground; the emitter of a transfer tube TG is connected with the FD1 node, the collector of the transfer tube TG is connected with a photodiode PD, the collector of a source follower SF is connected with the ground, the emitter of the source follower SF is connected with the collector of a row selection tube SEL, and the emitter of the row selection tube SEL is connected with a column output line. The application realizes expansion of the dynamic range of the pixel.

Description

Technical Field

[0001] This invention relates to the field of CMOS image sensor pixel technology, and in particular to a high dynamic range pixel with logarithmic response based on charge compensation. Background Technology

[0002] High dynamic range (HDR) CMOS image sensors are widely used in aerospace, consumer electronics, industrial cameras, and biomedical fields. Methods to improve dynamic range include LOFIC (Low Dynamic Range Induction), multiple exposure, DCG (Distributed Direct Current Generation), and simultaneous exposure of large and small photodetectors. While LOFIC has a simple structure and can effectively collect a large amount of photogenerated charge, it requires a large pixel area. Multiple exposure effectively improves dynamic range by alternating long and short exposures, but its ability to handle moving objects is limited, and the design of subsequent readout circuits and related algorithms is often quite complex. DCG technology introduces dual conversion nodes in the pixel circuitry: reducing the capacitance value of high-gain nodes to detect weak light, and connecting a MIM capacitor in parallel for low-gain nodes to detect strong light. While large and small photodetectors significantly improve dynamic range by utilizing an equivalent full-well approach, the readout of multiple signals often leads to a decrease in the signal-to-noise ratio at the signal conversion nodes and significant power consumption.

[0003] In many specific applications, high dynamic range CMOS image sensors are often required to maintain good sensitivity in low light conditions while having a high dynamic range under strong light conditions. Therefore, DCG technology is an essential component. Due to the limitation of low-gain node capacitance, traditional DCG technology cannot effectively extend the dynamic range of CMOS image sensors under high light intensity. Summary of the Invention

[0004] The purpose of this invention is to overcome the defects in the existing technologies and provide a high dynamic range pixel with DCG function and charge compensation based on logarithmic response. While retaining the high-gain nodes of the original DCG structure, a heavy P-type doping layer is added to the N-type doping of the low-gain nodes to introduce a logarithmic structure, thereby expanding the dynamic range of the pixel.

[0005] The technical solution adopted to achieve the purpose of this invention is:

[0006] A high dynamic range (HDR) pixel based on charge compensation is implemented using a 4T pixel structure. This 4T pixel structure includes a transmission transistor (HDR) and a low-gain node (FD2). An external MIM capacitor (C) is connected to the FD2 node, expanding the 4T pixel structure into a 5T pixel structure with a DCG (high dynamic range transistor) to form a HDR pixel. Specifically, the emitter of the HDR is connected to the high-gain node (FD1), while its collector is connected to the FD2 node. The FD2 node is connected to the emitter of the reset transistor (RST), and the collector of the RST is connected to VDD. The other end of the MIM capacitor (C) is grounded. The emitter of the transmission transistor (TG) is connected to the FD1 node, and its collector is connected to the photodiode (PD). The collector of the source follower (SF) is grounded, and the emitter of the source follower (SF) is connected to the collector of the row select transistor (SEL). The emitter of the row select transistor (SEL) is connected to the column output line.

[0007] In this process, an additional layer of heavy P-type doping is injected on top of the N-type doping of the FD2 node. The heavy P-type doping, the N-type doping of the FD2 node, and the light P-type doping of the substrate form a PNP-type structure. A positive voltage VA less than the reset voltage is applied to the P-type layer of the heavy P-type doping. The heavy P-type doping does not completely cover the surface of the FD2 node.

[0008] The area of ​​the heavily P-type doped P-type layer is in a 1:1 ratio with the area of ​​the exposed N-type portion of the N-type doped layer.

[0009] The area of ​​the FD2 node is 1.5 times that of the FD1 node.

[0010] In low light conditions, the high dynamic range (HVR) pixel with logarithmic response utilizes the FD1 node for photoelectric conversion. In HCG mode, the voltage of the FD1 node decreases. As the light power gradually increases, the number of electrons generated by the photodiode (PD) gradually increases. The capacitance of the pixel's FD1 node is small, and the transmission transistor (HDR) is turned on to connect the FD1 and FD2 nodes, increasing the amount of charge stored in the pixel. This causes the common voltage value of the FD1 and FD2 nodes to gradually decrease, but remains higher than the external voltage VA. At this time, the pixel operates in LCG mode.

[0011] When the optical power is high, the electrons generated by the photodiode PD continuously overflow from the transmission tube TG to the FD1 node. After the FD1 node is full, they overflow from the transmission tube HDR to the FD2 node, causing the voltage of the FD2 node to continuously decrease and become less than the external voltage VA. This causes the PN junction formed by the N-type region and the surface P-type layer of the FD2 node to change from reverse bias to forward bias. At this time, the forward biased PN junction on the FD2 node region exhibits electrons being discharged from the FD2 node to the external voltage VA, causing the voltage of the FD2 node to rise. By continuously conducting away the photogenerated electrons transferred by the photodiode PD, the voltage drop of the FD2 node is slowed down, thereby increasing the dynamic range of the pixel in a logarithmic manner.

[0012] In situations with weak illumination where the pixel utilizes the FD1 node for photoelectric conversion, considering the reverse-biased current contributed by the reverse-biased diode formed by the N-region of the FD1 node and the substrate, the voltage equation for the FD1 node is expressed as:

[0013] V FD1 =V RST1 -V photo1 -V revd1 ;

[0014] Where V FD1 This represents the voltage at node FD1, V. RST1 V represents the reset voltage of node FD1. photo1 V represents the voltage drop at the FD1 node caused by the introduction of photogenerated electrons. revd1 This represents the voltage drop at the FD1 node caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the P-type substrate at the FD1 node; where,

[0015] V photo1 and V rev1 The expression is as follows:

[0016]

[0017]

[0018] Where, N ph C represents the number of photogenerated charges, q represents the charge of one electron, and C represents the charge of one electron. FD1 I represents the node capacitance of node FD1. S V represents the reverse saturation current generated by the reverse-biased PN junction formed between the N-region of node FD1 and the substrate. T For thermal voltage, t transfer N represents the turn-on time of the transmission tube TG, i.e., the photogenerated electron transport time; ph It can be expressed by the following formula:

[0019]

[0020] Where η is the PPD quantum efficiency, L is the light intensity, and S is the light intensity. PPD The area of ​​the photosensitive region of the PPD is represented by γ, and the conversion parameter from light intensity to light power is represented by t. int The exposure time is hv, which represents the energy of one photon.

[0021] When the pixel operates in LCG mode, the node voltage equations for nodes FD1 and FD2 are expressed as follows:

[0022] V FD1FD2 =V RST12 -V photo12-V revd12 -V revu12 ;

[0023] Where V FD1FD2 This represents the common voltage at nodes FD1 and FD2, V. RST12 This represents the common reset voltage value for both FD1 and FD2 nodes in LCG mode, V. photo12 V represents the voltage drop at nodes FD1 and FD2 caused by the introduction of photogenerated electrons. revd12 V represents the voltage drop at nodes FD1 and FD2 caused by the accumulation of electrons in the reverse PN junction formed by the N-type region of node FD1 and the P-type substrate. revu12 This represents the voltage drop at nodes FD1 and FD2 caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the surface P-type layer of nodes FD1 and FD2.

[0024] Wherein, the V photo12 V revd12 and V revu12 The expression is shown in the following formula:

[0025]

[0026]

[0027]

[0028] Among them, C FD1FD2 This represents the node capacitance shared by nodes FD1 and FD2.

[0029] When the PN junction formed by the N-type region and the surface P-type layer of the FD2 node changes from reverse bias to forward bias, the voltage of the FD2 node region is as follows:

[0030] V FD2 =V RST2 -V photo2 -V revd2 +V revu2 ,

[0031] Among them, V FD2 This represents the voltage at node FD2, V. RST2 This represents the reset voltage value of node FD2, V. photo2 V represents the voltage drop at the FD2 node caused by the introduction of photogenerated electrons. revd2 V represents the voltage drop at the FD2 node caused by the accumulation of electrons in the reverse PN junction formed by the N-type region of the FD2 node and the P-type substrate. revu2 This represents the decrease in node voltage caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the surface P-type layer of the FD2 node.

[0032] Wherein, the V photo2 V revd2 and V revu2 The expression is shown in the following formula:

[0033]

[0034]

[0035]

[0036] The present invention relates to a charge-compensated logarithmic response high dynamic range pixel, which combines the original DCG pixel and logarithmic pixel. It retains the high-gain node (FD1 node) of the original DCG pixel, while adding heavy P-type doping to the N-type doped surface of the low-gain node (FD2 node). The heavy P-type doping on the FD2 surface and the N-type doping of FD2, together with the light P-type doping of the substrate, form a PNP-type structure similar to PPD. At the same time, a positive voltage VA less than the reset voltage is applied to the P-type layer of the heavy P-type doped layer. When the voltage of the FD2 node drops below VA, the junction is forward biased, and a large number of electrons are discharged to VA, thus realizing the high dynamic range of the pixel. It can improve the dynamic range of CMOS image sensors to more than 150dB (the dynamic range of traditional DCG technology is within 100dB). Attached Figure Description

[0037] Figure 1 This is a schematic cross-sectional view of the high dynamic range pixel with logarithmic response based on charge compensation according to the present invention.

[0038] Figure 2 This is a schematic diagram of the light response curve of a high dynamic range pixel based on charge compensation and logarithmic response according to the present invention.

[0039] Figure 3 This is a diagram of the high dynamic range pixel circuit based on charge compensation and logarithmic response of the present invention.

[0040] Figure 4 This is a pixel timing diagram of a logarithmic response high dynamic range based on charge compensation according to the present invention.

[0041] Figure 5 This is a graph showing the potential variation of a pixel node based on charge compensation and logarithmic response high dynamic range.

[0042] illustrate:

[0043] Figure 1 In this context, Pwell represents a P-well, P-sub represents a P-type substrate, STI represents shallow trench isolation, PDN represents N-type doping of PPD, PDP represents P-type doping of the PPD surface, and n + Indicates n-type doping, p+ This indicates P-type doping at the FD2 node, and "Column output line" indicates the column output line.

[0044] Figure 2 In this context, DN represents the output code value of the pixel, HCG indicates that the pixel is operating in high gain mode, LCG indicates that the pixel is operating in low gain mode, logarithm indicates that the pixel is operating in logarithmic mode, weak indicates weak light, strong indicates strong light, high indicates high light, and pin (lux.s) indicates optical power density.

[0045] Figure 4 In this context, S-LOG represents the pixel logarithmic mode readout signal, R-LCG represents the pixel low gain mode reset signal, R-HCG represents the pixel high gain mode reset signal, S-HCG represents the pixel high gain mode readout signal, S-LCG represents the pixel low gain mode readout signal, R-LOG represents the pixel logarithmic mode reset signal, and Tint represents the exposure time period.

[0046] Figure 5 In the diagram, S-HG represents the high-gain readout signal of the pixel, S-LG represents the low-gain readout signal of the pixel, and S-LOG represents the logarithmic readout signal of the pixel. Detailed Implementation

[0047] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0048] In traditional DCG structures, the limitation to further improving the dynamic range of CMOS image sensors is often due to the limited size of the capacitors connected in parallel to low-gain nodes. Larger capacitors tend to occupy a larger area, limiting the fill factor of the photosensitive area in the pixel, and the achievable dynamic range is mostly around 100dB. Moreover, when the dynamic range reaches above 100dB, this method offers very limited improvement to the dynamic range.

[0049] This invention introduces a logarithmic structure into the low-gain nodes of the traditional DCG structure. This logarithmic structure is based on charge compensation technology, which enables the image sensor to detect greater light intensity and achieve a dynamic range of over 150dB, greatly improving the dynamic range performance of the traditional DCG structure.

[0050] This invention combines logarithmic pixels with DCG technology, which retains the high-gain nodes in the DCG structure for weak light detection, while introducing a logarithmic structure in the low-gain nodes to greatly expand the strong light detection range. This is very effective for improving the overall dynamic range of CMOS image sensors.

[0051] like Figure 1 , Figure 3 As shown, the high dynamic range pixel based on charge compensation in this embodiment of the invention is based on the most basic 4T pixel structure. On the basis of the 4T pixel structure, an HDR transmission tube and a low gain node (FD2 node, charge storage node Floating Diffusion) are added, and a MIM capacitor C is externally connected to the low gain node, thus expanding the original 4T pixel into a 5T pixel structure with DCG.

[0052] For the extended low-gain node (FD2 node), an additional layer of heavy P-type doping is injected on top of the existing N-type doping. This creates a PNP-type structure similar to a PPD, formed by the heavy P-type doping on the surface, the N-type doping of the FD2 node, and the light P-type doping of the substrate. A positive voltage VA, less than the reset voltage, is applied externally to the heavy P-type doped P-type layer. Due to the need for electron transport across the FD2 node, the added heavy P-type doping cannot completely cover the surface of the FD2 node.

[0053] In this application, the area of ​​node FD2 is set to 1.5 times that of node FD1 to meet the area requirements of the surface P-type region.

[0054] Preferably, the area of ​​the added P-type layer is approximately 1:1 to the area of ​​the exposed N-type portion, with a more preferred ratio of 1:1.

[0055] This application presents the relationship between the digital code value output of a pixel and the incident light power, wherein the incident light is divided into three stages: weak, strong, and high. The specific light response curves are shown below. Figure 2 As shown, for the original DCG 5T pixel, it is equivalent to adding a diode to the FD2 node, and applying a forward voltage VA to the P terminal of the diode. The pixel circuit diagram is as follows. Figure 3 As shown.

[0056] For the overall pixel workflow, under low light conditions, photoelectric conversion is mainly performed by the high-gain node—FD1 node. Considering the reverse-biased current contributed by the reverse-biased diode formed by the N-region of the FD1 node and the substrate, the voltage equation of the FD1 node can be expressed as:

[0057] V FD1 =V RST1 -V photo1 -V revd1 (1)

[0058] Where V FD1 This represents the voltage at node FD1, V. RST1 V represents the reset voltage of node FD1.photo1 V represents the voltage drop at the FD1 node caused by the introduction of photogenerated electrons. revd1 This represents the voltage drop at the FD1 node caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the P-type substrate at the FD1 node.

[0059] V photo1 and V rev1 The expressions are shown in equations (2) and (3):

[0060]

[0061]

[0062] Where q represents the charge of an electron, and C FD1 I represents the node capacitance of node FD1. S V represents the reverse saturation current generated by the reverse-biased PN junction formed between the N-region of node FD1 and the substrate. FD1 V is the voltage at node FD1. T For thermal voltage, t transfer N represents the transmission TG start time, i.e., the photogenerated electron transmission time. ph The number of photogenerated charges can be approximated by equation (4):

[0063]

[0064] Where η is the PPD quantum efficiency, L is the light intensity, and S is the light intensity. PPD The area of ​​the photosensitive region of the PPD is represented by γ, and the conversion parameter from light intensity to light power is represented by t. int The exposure time is hv, which represents the energy of one photon.

[0065] As shown in Equation (1), in the pixel HCG (high conversion gain) mode, the reason for the decrease in the voltage of the FD1 node of the pixel is the accumulation of photogenerated electrons in the FD1 node and the electrons accumulated in the reverse biased PN junction between the N region of the FD1 node and the P-type substrate. Generally speaking, the electrons accumulated in the latter are very small compared with the former. In the pixel HCG mode, the voltage of the FD1 node tends to be linearly negatively correlated with the accumulation of photogenerated electrons.

[0066] As the optical power gradually increases, the number of electrons generated by the photodiode (PD) gradually increases. The capacitance at the FD1 node is relatively small. By connecting the FD1 and FD2 nodes with the HDR transistor turned on, the pixel's charge storage capacity is improved. Since an external MIM capacitor is connected to the FD2 node, the overall charge stored in the pixel increases significantly. The pixel operates in LCG (Low Conversion Gain) mode. The node voltage equations for FD1 and FD2 can be expressed as:

[0067] V FD1FD2 =VRST12 -V photo12 -V revd12 -V revu12 (5)

[0068] Where V FD1FD2 This represents the common voltage at nodes FD1 and FD2, V. RST12 This represents the common reset voltage value for both FD1 and FD2 nodes in LCG mode, V. photo12 V represents the voltage drop at nodes FD1 and FD2 caused by the introduction of photogenerated electrons. revd12 V represents the voltage drop at nodes FD1 and FD2 caused by the accumulation of electrons in the reverse PN junction formed by the N-type region of node FD1 and the P-type substrate. revu12 This represents the voltage drop at nodes FD1 and FD2 caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the surface P-type layer of nodes FD1 and FD2.

[0069] Where V photo12 V revd12 and V revu12 The expressions are shown in equations (6), (7), and (8):

[0070]

[0071]

[0072]

[0073] Where C FD1FD2 V represents the node capacitance shared by nodes FD1 and FD2. FD1FD2 This is the common voltage value for nodes FD1 and FD2. During this process, the common voltage value of nodes FD1 and FD2 gradually decreases, but it is still higher than the external voltage VA of the P-type layer on the surface of node FD2. At this time, the pixel is operating in LCG mode.

[0074] When the optical power is high, before the transmission tube is turned on, because a small forward bias voltage has been applied to the transmission tubes TG and HDR, the electrons generated by the photodiode PD continuously overflow from the transmission tube TG to the FD1 node. Since the capacitance of the FD1 node is small, the electrons generated by the photodiode PD will overflow to the FD2 node through the transmission tube HDR after filling the FD1 node, causing the voltage of the FD2 node to continuously decrease, to the point that it is less than the external voltage VA of the P-type layer on the surface of the FD2 node, and the PN junction formed by the N-type region and the surface P-type layer of the FD2 node changes from reverse bias to forward bias. At this time, the voltage of the FD2 node region is as shown in (9):

[0075] V FD2 =VRST2 -V photo2 -V revd2 +V revu2 (9)

[0076] Where V FD2 This represents the voltage at node FD2, V. RST2 This represents the reset voltage value of node FD2, V. photo2 V represents the voltage drop at the FD2 node caused by the introduction of photogenerated electrons. revd2 V represents the voltage drop at the FD2 node caused by the accumulation of electrons in the reverse PN junction formed by the N-type region of the FD2 node and the P-type substrate. revu2 This represents the decrease in node voltage caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the surface P-type layer of the FD2 node. Where V... photo2 V revd2 and V revu2 The expressions are shown in equations (10), (11), and (12):

[0077]

[0078]

[0079]

[0080] In this case, the forward-biased PN junction in the FD2 node region exhibits electron extraction from the FD2 node to the VA. This process causes the voltage of the FD2 node to rise. By continuously conducting away the photogenerated electrons transferred from the PD, the voltage drop of the FD2 node is slowed down, significantly improving the dynamic range of the pixel in a logarithmic manner.

[0081] The foregoing has shown and described the basic principles and main features of the present invention and its advantages. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0082] Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of the equivalents of the claims be included within the invention.

[0083] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A high dynamic range pixel with logarithmic response based on charge compensation, characterized in that, Based on a 4T pixel structure, a transmission transistor (HDR) and a low-gain node (FD2) are added to this 4T pixel structure. An external MIM capacitor C is connected to the FD2 node, expanding the 4T pixel into a 5T pixel structure with a DCG (high dynamic range) to form a logarithmic response high dynamic range pixel. The emitter of the HDR transistor is connected to the FD1 node (high-gain node), while its collector is connected to the FD2 node. The FD2 node is connected to the emitter of the reset transistor (RST), and the collector of the RST transistor is connected to VDD. The other end of the MIM capacitor C is grounded. The emitter of the HDR transistor... The collector of the transmission transistor TG is connected to the photodiode PD, the collector of the source follower SF is grounded, the emitter of the source follower SF is connected to the collector of the row select transistor SEL, and the emitter of the row select transistor SEL is connected to the column output line. On the basis of the N-type doping of the FD2 node, an additional layer of heavy P-type doping is injected. The heavy P-type doping, the N-type doping of the FD2 node, and the light P-type doping of the substrate form a PNP structure. A positive voltage VA less than the reset voltage is applied to the P-type layer of the heavy P-type doping. The heavy P-type doping does not completely cover the surface of the FD2 node.

2. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 1, characterized in that, The area of ​​the heavily P-type doped P-type layer is 1:1 with the area of ​​the exposed N-type portion of the N-type doped layer.

3. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 1, characterized in that, The area of ​​the FD2 node is 1.5 times that of the FD1 node.

4. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 1, characterized in that, When the light is weak, the logarithmic response high dynamic range pixel uses the FD1 node for photoelectric conversion; when the pixel is in HCG mode, the voltage of the FD1 node decreases; as the light power gradually increases, the number of electrons generated by the photodiode PD gradually increases, the capacitance of the pixel FD1 node is small, the transmission tube HDR is turned on to connect the FD1 node and the FD2 node, which increases the amount of charge stored in the pixel, and the common voltage value of the FD1 node and the FD2 node gradually decreases, but is higher than the external voltage VA. At this time, the pixel is working in LCG mode. When the optical power is high, the electrons generated by the photodiode PD continuously overflow from the transmission tube TG to the FD1 node. After the FD1 node is full, they overflow from the transmission tube HDR to the FD2 node, causing the voltage of the FD2 node to continuously decrease and become less than the external voltage VA. This causes the PN junction formed by the N-type region and the surface P-type layer of the FD2 node to change from reverse bias to forward bias. At this time, the forward biased PN junction on the FD2 node region exhibits electrons being discharged from the FD2 node to the external voltage VA, causing the voltage of the FD2 node to rise. By continuously conducting away the photogenerated electrons transferred by the photodiode PD, the voltage drop of the FD2 node is slowed down, thereby increasing the dynamic range of the pixel in a logarithmic manner.

5. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 1, characterized in that, When the light intensity is low and the pixel uses the FD1 node for photoelectric conversion, considering the reverse bias current contributed by the reverse bias diode formed by the N-region of the FD1 node and the substrate, the voltage equation of the FD1 node is expressed as: ； in Indicates the voltage at node FD1 This represents the reset voltage of node FD1. This represents the voltage drop at the FD1 node caused by the introduction of photogenerated electrons. This represents the voltage drop at the FD1 node caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the P-type substrate at the FD1 node; where, and The expression is as follows: ； ； in, Indicates the number of photogenerated charges. This represents the amount of charge carried by one electron. This represents the node capacitance of node FD1. This represents the reverse saturation current generated by the reverse-biased PN junction formed between the N-region of node FD1 and the substrate. Thermoelectric voltage, The turn-on time of the transfer tube (TG), i.e., the photogenerated electron transport time, is expressed by the following formula: ； in, PPD is the quantum efficiency, and L is the light intensity. This indicates the area of ​​the photosensitive region of the PPD. This represents the conversion parameter from light intensity to light power. For the exposure time, This represents the energy of a photon.

6. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 5, characterized in that, When the pixel is operating in LCG mode, the node voltage equations for nodes FD1 and FD2 are expressed as follows: ； in This represents the common voltage at nodes FD1 and FD2. This represents the common reset voltage value for both FD1 and FD2 nodes in LCG mode. This represents the voltage drop at nodes FD1 and FD2 caused by the introduction of photogenerated electrons. This represents the voltage drop at nodes FD1 and FD2 caused by the accumulation of electrons in the reverse PN junction formed by the N-type region of node FD1 and the P-type substrate. This represents the voltage drop at nodes FD1 and FD2 caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the surface P-type layer of nodes FD1 and FD2.

7. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 6, characterized in that, The aforementioned , and The expression is shown in the following formula: ； ； ； in, This represents the node capacitance shared by nodes FD1 and FD2.

8. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 7, characterized in that, When the PN junction formed by the N-type region and the surface P-type layer of the FD2 node changes from reverse bias to forward bias, the voltage of the FD2 node region is as follows: ； in, This represents the voltage at node FD2. This indicates the reset voltage value of node FD2. This represents the voltage drop at the FD2 node caused by the introduction of photogenerated electrons. This represents the voltage drop at the FD2 node caused by the accumulation of electrons in the reverse PN junction formed by the N-type region of the FD2 node and the P-type substrate. This represents the decrease in node voltage caused by the accumulation of electrons in the reverse PN junction formed by the N-type region and the surface P-type layer of the FD2 node.

9. The high dynamic range pixel with logarithmic response based on charge compensation according to claim 8, characterized in that, The , and The expression is shown in the following formula: ； ； 。

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