Four-wheel hub motor driven chicken house inspection system and equipment based on domestic FPGA

Abstract

The present invention discloses a chicken house inspection system and equipment driven by four wheel hub motors based on domestic FPGA, including: a four-motor torque deviation coupling control subsystem and a target detection and tracking subsystem; wherein the four-motor torque deviation coupling control subsystem is used to provide drive for the independent movement and coordination between the four wheel hub motors of the equipment based on FPGA; the target detection and tracking subsystem is used to collect chicken house images while the four-motor torque deviation coupling control subsystem provides drive for the equipment, and perform real-time target detection on the chicken house images based on the FPGA to obtain chicken house inspection results. The invention designs a set of high-definition real-time target detection and tracking systems based on FPGA, uses parallel pipeline design optimization methods on the FPGA platform to accelerate the image processing algorithm, and has high real-time performance when detecting high-definition video targets.

Description

Technical Field

[0001] The present invention relates to the field of ASIC technology, and in particular to a chicken house inspection system and equipment driven by four-wheel hub motors based on domestic FPGA. Background Art

[0002] my country's research and development efforts and market size for inspection equipment are also constantly improving. The use of intelligent inspection equipment technology instead of manual inspection can not only collect various information such as equipment conditions and environmental data in important areas, and then screen and analyze the data, it can realize the detection of environmental anomalies and the diagnosis and early warning of equipment failures, and effectively reduce the repetitiveness and work intensity of manual inspections, avoiding problems such as fatigue, inadequate inspections, and misjudgment caused by manual inspections. In recent years, with the increasing development of hardware technology, more and more research has been conducted on hardware acceleration of various algorithms using FPGAs. It has both hardware parallel processing capabilities and software flexibility, making it more and more obvious in the fields of industrial control and image processing, and can solve the speed and bandwidth limitations faced by traditional platforms. Therefore, using FPGA to solve equipment driving problems, image processing and algorithm problems in visual systems has become a very meaningful work. Summary of the invention

[0003] The purpose of the present invention is to provide a chicken house inspection system and equipment driven by a four-wheel hub motor based on a domestic FPGA to solve the problems existing in the above-mentioned prior art.

[0004] The present invention provides a chicken house inspection system driven by four-wheel-hub motors based on domestic FPGA, comprising: a four-motor torque deviation coupling control subsystem and a target detection and tracking subsystem;

[0005] The four-motor torque deviation coupling control subsystem is used to provide drive for independent movement and coordinated cooperation between the four wheel hub motors of the equipment based on FPGA;

[0006] The target detection and tracking subsystem is used to collect chicken house images while the four-motor torque deviation coupling control subsystem provides drive for the equipment, and to perform real-time target detection on the chicken house images based on the FPGA to obtain chicken house inspection results.

[0007] Optionally, the four-motor torque deviation coupling control subsystem includes a bottom control module and a top control module;

[0008] The bottom control module is used to control a single wheel hub motor based on the FOC control algorithm to obtain torque feedback of the single motor;

[0009] The top-level control module is used to respectively calculate the difference between the torque feedback of the single motor and the torque feedback of other motors to obtain torque compensation, and to coordinately control the movements of the four wheel hub motors based on the torque compensation.

[0010] Optionally, the bottom control module includes: a first processing unit, a second processing unit, a third processing unit and a fourth processing unit;

[0011] Wherein, the first processing unit is used to convert the three-phase current in the stationary coordinate system into the two-phase direct current in the rotating coordinate system based on the coordinate transformation algorithm of the first formula;

[0012] The second processing unit is used to obtain the motor speed and the motor rotor position based on the encoder adaptive speed measurement algorithm;

[0013] The third processing unit is used for switching the three-loop control mode, wherein the three-loop control mode includes current loop control alone, current loop + speed loop control and current loop + speed loop + position loop control;

[0014] The fourth processing unit is used to set a bias in the hardware circuit to perform bias compensation on the current.

[0015] Optionally, the top-level control module includes: a branch relative torque feedback unit, a branch separation unit and a coupling unit;

[0016] Wherein, the branch relative torque feedback unit is used to calculate the average value of multiple data in a single cycle based on a counter and an accumulator;

[0017] The coupling unit is used to calculate the average value of the multi-channel data and the expected torque value based on the PI control algorithm to obtain the distribution current;

[0018] The branch separation unit is used to distribute the distribution current to each motor to control the motor output torque.

[0019] Optionally, the target detection and tracking subsystem includes: a target detection module and a target tracking module;

[0020] Wherein, the target detection module is used to obtain the coordinate information of the moving target based on the improved frame difference method;

[0021] The target tracking module is used to track the moving target in real time based on the Camshift target tracking algorithm.

[0022] A chicken house inspection device driven by a four-wheel motor based on a domestic FPGA, including an inspection vehicle with a vertical structure design;

[0023] The inspection vehicle includes: a chassis, several wheel hub motors, an FPGA chip, and a camera;

[0024] Wherein, the chassis is equipped with four wheel hub motors;

[0025] The camera is used to collect images of the chicken house and transmit the images of the chicken house to the FPGA chip;

[0026] The FPGA chip is used to control the wheel hub motor to provide drive for the inspection vehicle, and the FPGA chip performs image recognition and detection processing on the chicken house image.

[0027] Optionally, the inspection vehicle further includes a wheel hub rotating device;

[0028] Wherein, the wheel hub rotating device comprises: a steel bar with a through hole at one end, a steel shaft and bolts;

[0029] The end of the steel bar without a through hole is welded to the wheel hub; the other end of the steel bar with a through hole and the steel shaft are fixed to the chassis by the bolts.

[0030] Optionally, the inspection vehicle further includes a hardware integration platform and a loading platform;

[0031] The hardware integration platform is provided with a groove matching the shape of the FPGA, and a spring buckle is respectively provided on both sides of the groove wall, and the spring buckle and the groove fix the FPGA;

[0032] The loading platform is arranged on the upper part of the groove of the hardware integration platform, and the loading platform is connected to the hardware integration platform via welding columns.

[0033] Optionally, the camera is also equipped with an electric lifting shaft and a lens mounting plate;

[0034] The lower end of the camera is connected to the electric lifting shaft, the electric lifting shaft is welded to the hardware integration platform, and the camera is connected to the lens mounting plate by bolts;

[0035] The electric lifting shaft comprises a lifting inner shaft and an outer shell.

[0036] The present invention has the following technical effects:

[0037] The present invention uses domestic FPGA as the main control chip, and uses its powerful parallel computing advantages and customizable expansion pin advantages to control device driving and information collection at the same time. The invention designs a set of high-definition real-time target detection and tracking system based on FPGA, and uses parallel pipeline design optimization methods on the FPGA platform to accelerate the image processing algorithm, which has high real-time performance when detecting high-definition video targets. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 It is a composition diagram of a control algorithm module based on FPGA in an embodiment of the present invention;

[0040] Figure 2 Schematic diagram of a vector control system based on FPGA in an embodiment of the present invention;

[0041] Figure 3 It is a diagram of the module structure of a three-closed-loop vector control algorithm based on FPGA in an embodiment of the present invention;

[0042] Figure 4 It is a principle diagram of a torque deviation coupling control algorithm of a four-motor system combined with PID in an embodiment of the present invention;

[0043] Figure 5 A flowchart of a high-definition real-time target detection and tracking program based on FPGA in an embodiment of the present invention;

[0044] Figure 6 A flow chart for designing the Camshift algorithm in an embodiment of the present invention;

[0045] Figure 7 It is an overall schematic diagram of the inspection equipment in an embodiment of the present invention;

[0046] Figure 8 Schematic diagram of an information collection device in an embodiment of the present invention;

[0047] Figure numerals: 019, lens mounting plate; 027, FPGA chip; 116, chassis; 117, hardware integration platform; 141, camera; 158, battery box; 307, hub motor; 169, lifting inner shaft; 168, shell; 217, stage; 017, hub; 311 ultrasonic sensor; 115 sensor mounting shell; 187 angle adjustment base; 121 camera lighting. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Embodiment 1

[0050] like Figure 1 As shown, the technology designed by the present invention includes two aspects:

[0051] It includes a four-motor torque deviation coupling control subsystem and a target detection and tracking subsystem;

[0052] Among them, the four-motor torque deviation coupling control subsystem is used to provide drive for the independent movement and coordinated cooperation between the four wheel hub motors of the equipment based on FPGA;

[0053] The target detection and tracking subsystem is used to collect chicken house images while the four-motor torque deviation coupling control subsystem provides drive for the equipment, and to perform real-time target detection on the chicken house images based on FPGA to obtain chicken house inspection results.

[0054] On the one hand, domestic FPGA is used as the main control chip, according to the actual motion trajectory layout analysis, the Verilog language is used to build a four-motor system torque deviation coupling control algorithm combined with PID control, and the PID controller is used as the torque signal compensation. The overall structure and specific parameters of the motor controller are changed, thereby alleviating the contradiction between rapid responsiveness and smooth operation of ordinary PID control schemes, improving the performance of multi-motor control systems, and realizing coordinated synchronous control of multiple motors, so as to more accurately achieve independent movement and coordinated cooperation between the motors by compensating or reducing the output torque of the corresponding motors, and then realize the equipment's forward, backward, turning, reversing and other actions.

[0055] The torque deviation coupling control algorithm of four wheel hub motors is mainly divided into two modules: the bottom control module and the top control module. The bottom module is used as a submodule of the top module.

[0056] Among them, the underlying control module uses Verilog language to implement the FPGA and host computer serial port communication of a single hub motor, the motor vector control algorithm, the stator current signal acquisition interface and the photoelectric encoder signal interface.

[0057] The function of the bottom control module is to firstly adopt the FOC control algorithm to ideally control a single motor, such as Figure 7 Take the middle wheel hub motor 307 as an example.

[0058] The underlying control module is designed with pure Verilog language to implement a three-loop vector control algorithm with loop switching function. By utilizing the customizable design feature of FPGA, it can achieve highly efficient logic operations and flexible control function design, greatly improving the calculation accuracy.

[0059] like Figure 2As shown in the figure, the control idea of ​​the bottom control module is that the host computer is the control brain of the system and uses the SPI communication protocol to provide control instructions to the FPGA. After the ADC circuit collects the three-phase current, it converts the analog quantity into digital quantity after calculation and transmits it to the FPGA. At the same time, the decoding module calculates the motor speed and rotor position information and transmits it to the FPGA. The above signals are processed by the FOC algorithm inside the FPGA to drive the inverter circuit switch to change, and finally generate PWM signals to control the motor.

[0060] like Figure 3 As shown, the entire bottom-level control module is divided into: current conditioning module, coordinate transformation module, PI adjustment module, SVPWM block, encoder signal processing module, speed measurement module, and AD sampling module. As can be seen from the principle block diagram, in the system design, an AD chip is used to sample two currents Ia and Ib as two-phase inputs of the control system. Since there is no circuit on the FPGA to process the photoelectric encoder signal, the encoder signal is processed by a certain circuit in the peripheral circuit to become a signal that the FPGA can process, and then processed by the module to obtain the angle value, which is used to calculate the real-time sine and cosine values. The real-time speed obtained by the speed measurement module is used as the input of the speed outer loop, and the current after current processing and coordinate transformation is used as the input of the current inner loop, thereby realizing the three-closed-loop control of the motor control system.

[0061] The main control algorithms involved in the entire underlying control module include the following parts:

[0062] Coordinate transformation module: Clark transformation, the stator current obtained by AD sampling is transformed by the Clark algorithm, and the three-phase stationary coordinate system is transformed into a two-phase stationary coordinate system. The magnetic motive force before and after the transformation remains unchanged, and the calculated result is output to the park algorithm for calculation.

[0063] The park algorithm converts the two-phase AC current in a stationary coordinate system into a two-phase DC current in a rotating coordinate system, and outputs the calculated result to the PI regulator.

[0064] Coordinate transformation algorithm based on the formula: Different from the traditional coordinate transformation abc-αβ-dq process, this design uses the Verilog language to implement the trigonometric function formula method, which converts the three-phase current in the a, b, c coordinate system into the d, q axis current in one step, realizes the abc-dq one-step conversion, eliminates the intermediate calculation steps, simplifies the coordinate transformation process, and its calculation formula is shown in the figure below. The addition and subtraction operations of signed numbers are completed by unsigned addition through complement processing, and the multiplication operation of signed numbers is processed by defining the output as signed.

[0065]

[0066] Encoder calculation module: Speed ​​calculation: When the motor is working, the encoder pulse frequency is quadrupled by capturing the rising and falling edges of the encoder A and B phase pulses to improve the calculation accuracy. The M / T method is used to measure speed. The M method is used for high speed and the T method is used for low speed. Different speed measurement algorithms are used according to different speeds. At the same time, an eight-level cache of speed feedback is set to perform speed filtering to improve the speed calculation accuracy. Position calculation: By setting the counter cnt, counting is performed according to the detected rising or falling edge of the pulse to calculate the position of the motor rotor.

[0067] The specific process of using the encoder adaptive speed measurement algorithm for speed calculation includes: using pure Verilog language to design the encoder adaptive speed measurement algorithm, based on the M / T method, so that the measurement time and the number of measured photoelectric pulses change with the change of the speed, but the measurement time is always equal to the integer number of measured photoelectric pulses. In the program, four register variables A_H, A_L, B_H, B_L are set to store the rising and falling edges of the collected A-phase and B-phase pulses, thereby judging the direction of the motor's operation and performing quadruple frequency processing on the encoder pulse signal. At the same time, the counting direction of the encoder is determined by judging the sign of the direction, adding for forward rotation and subtracting for reverse rotation. According to the speed of the motor, the pulse edge difference and the corresponding clock count value are extracted and provided to the subsequent modules. According to the pulse edge difference and the FPGA clock count value, the floating-point multiplication and division modules in the PDS IP core of the domestic FPGA development software are called to perform floating-point multiplication and division, and finally the motor speed can be calculated in the FPGA.

[0068] SVPWM module (space level pulse width modulation algorithm): designed in pure Verilog language. The program prioritizes the calculation of beta / √3 to prepare for the subsequent unitization process. At the same time, the FSM_CAL_A_B_C and FSM_CAL_S registers are set to store the calculated sign bit, and the sector is determined according to the voltage beta sign bit, the difference sign bit of alpha and beta / √3, and the sum sign bit of alpha and beta / √3. When calculating the basic voltage vector action time, based on the traditional basic voltage vector action time relationship, After standardization, the basic voltage vector calculation is greatly simplified, and the calculation accuracy can be improved, making the SVPWM algorithm programming easy to implement. Finally, a clock synchronization signal sys_sync and a clock median signal sys_mid are set. The two signals are responsible for controlling the on and off time of the inverter circuit switch. A pwm signal counter r_pwm_cnt is set. When the clock synchronization signal is valid, the counter is incremented by 1. The output pwm wave is controlled according to the result of comparing the pwm counter with the on and off time of the switch.

[0069] The resource consumption comparison between the SVPWM algorithm designed by the present invention and the traditional SVWPM algorithm in FPGA is shown in Table 1:

[0070] Table 1

[0071]

[0072] By comparison, it can be seen that the SVPWM algorithm in the present invention has great advantages in terms of logic resource consumption and pin occupancy.

[0073] PI control and its amplitude limiting processing module: Considering that the integral link has inertia, this inertia will cause the system to produce a large overshoot, so a amplitude limiting process is performed on the integral link output here to avoid this overshoot phenomenon. The current loop PI amplitude limiting amplitude is determined according to the SVPWM modulation method, and the speed loop PI amplitude limiting amplitude is determined according to the current loop maximum torque output limit.

[0074] Three-loop control mode switching: used to control the mode switching of the three loops in FOC. The host computer can send switching instructions to achieve single current loop control, or current loop + speed loop control, or current loop + speed loop + position loop control, etc., so as to adapt to different working occasions. The specific process includes: using pure Verilog language to implement. Its core is to set three main registers: mode control register, control start register, and control stop register. Among them, the mode control register r_p_ctrl_mode is used to control the mode switching of the three loops in FOC. The host computer can send switching instructions. When the mode control register value is 2'b01, single current loop control is achieved; when the value is 2'b10, current loop + speed loop control is achieved; when the value is 2'b11, current loop + speed loop + position loop control is achieved to adapt to different working occasions.

[0075] AD7606 current sampling and filtering module (current bias compensation algorithm): AD7606 sampling hardware circuit has a certain bias, which is convenient for signal processing. The current bias value of the hardware circuit can be debugged through hardware. When writing a program, the current data collected by AD is subtracted from the current bias value of the hardware circuit to obtain the real current more accurately. Finally, after passing through four levels of current caching, the average value is taken to obtain the most accurate current.

[0076] The top-level control module implements the torque deviation coupling control strategy of the four-motor system in Verilog language, which aims to subtract the torque feedback of one motor from the torque feedback of other motors, and then add the obtained deviations and iteratively process the values ​​as torque compensation signals to input to the motor, thereby realizing differential torque control of multiple motors. Figure 7The four wheel hub motors form a multi-motor system, and the above control idea is used to coordinate and control the whole system.

[0077] The core of the top-level control module is the torque deviation coupling control algorithm of the four wheel hub motors. The torque deviation coupling control system of the present invention mainly includes three main parts: a multi-channel torque integration module (Mux module), a multi-channel torque decomposition module (Demux module) and a branch relative torque feedback module (Relative Torque). This control is suitable for controlling a multi-motor control system with an independent drive controller. The relative coupling control algorithm is mainly implemented in the relative torque feedback module, and then the operation of the motor is driven by each independent driver without the need for an additional slave driver.

[0078] The Relative Torque (branch relative torque feedback module) is characterized in that: the average calculation of the multi-channel output values ​​of the Demux module is implemented in the FPGA, and the result is given to the Mux module. In the Verilog design, a counter and an accumulator are first defined to record the total number and sum of the data stream respectively, and the input data is read in each clock cycle and added to the accumulator, and the counter is incremented at the same time. Finally, at the output port, the value of the accumulator is divided by the value of the counter to obtain the average value of the multi-channel data.

[0079] The Mux module (coupling module) is characterized in that: the output value processed by the Relative Torque module is compared with the given expected torque value, and multiple output channels are set to give the output value to the Demux module. In the Verilog program, a register variable in_a is set to store the input value, and a register variable in_b is defined to store the size of the given torque. At this time, the PI control algorithm is introduced, and the program adopts the shifting method to realize the proportional scaling of the data. In order to make the number of proportional and integral operation cycles the same, a beat operation is performed in the proportional program, and the integral operation is realized by the cumulative counting method. In the always block, the PI controller is calculated and updated according to the clock signal and the reset signal. In each clock cycle, the proportional term and the integral term are calculated according to the current error error, and they are added to obtain the control input value control_input. Then, in another always block, the control input value is limited to ensure that it is within the output range (between 0 and 3200) and output to the control_output signal.

[0080] The Demux module (branch separation module) is characterized in that each motor adopts closed-loop control to control the torque to remain stable, then detects the bus current on the corresponding winding, and uses the relationship between the motor torque and the winding current to control the motor output torque.

[0081] like Figure 4 As shown in the figure, this design is based on the torque deviation coupling control algorithm. On the basis of ordinary PID control, a control scheme combining deviation coupling control and PID is proposed. The PID controller is used as speed signal compensation, and the overall structure and specific parameters of the motor controller are changed, thereby alleviating the contradiction between rapid responsiveness and smooth operation of the ordinary PID control scheme, improving the performance of the multi-motor control system, and realizing coordinated synchronous control of multiple motors, which is used to drive and control the synchronous and coordinated operation of four motors.

[0082] like Figure 4 As shown in the figure: First, the position signal of the motor rotor is detected by the Hall sensor, and then the rotation speed of the motor is calculated by using the changing frequency of the rotor Hall signal. The value of this rotation speed is used as the input of the relative speed feedback module, and after the module operation, it is reflected in the closed-loop control of each motor. Each motor adopts closed-loop control to control the torque to remain stable, and then detects the bus current on the corresponding winding, and uses the relationship between the motor torque and the winding current to control the output torque of the motor. In the entire control system, the average speed of multiple motors is used as the input of the speed regulator for closed-loop control. A single independent motor adopts a control method with the current loop as the inner loop, and the torque of the motor is determined according to the load on the motor, so that the four motors can run according to the same target torque. At the same time, the four motors are allowed to use different power inputs under different load conditions, so as to ensure that the torque of each motor remains synchronized.

[0083] The motor torque is debugged through the host computer and the curve tracking diagram is displayed. Single-channel data acquisition and multi-channel data acquisition can be selected on the host computer debugging interface. When debugging the current loop alone, the single-channel data acquisition mode can be selected. If debugging the position loop, the three-channel data acquisition mode can be selected.

[0084] There is a command sending window on the right side of the debugging interface, which corresponds to motor enable, sampling, control mode, control parameters and other commands. When debugging the motor performance, you can send different types of signals such as step signals, square wave signals, sine signals, etc. You can also change the amplitude and frequency of the signal through the host computer, and you can test the motor stability in many aspects.

[0085] After determining the system control parameters, different torques are given to conduct detailed tests on the motor response time and steady-state error. At this time, the captured motor performance curve can be seen in the debugging interface of the host computer to achieve online debugging.

[0086] Another aspect is: using the powerful parallel processing data advantage of FPGA, image recognition and detection processing are performed on the information collected by the camera while controlling the driving of the equipment. This invention designs a set of high-definition real-time target detection and tracking systems based on FPGA. The system involves hardware drive, target detection, model update, target tracking, Kalman filtering and other algorithms. The parallel pipeline design optimization method is used on the FPGA platform to accelerate the image processing algorithm. It has high real-time performance when detecting high-definition video targets, making the detection of eggs and dead chickens clearer; the present invention uses Verilog language to design programs, and uses pipeline operations inside the FPGA to implement the optimized frame difference method, enhance the accuracy and efficiency of moving target detection, so that it can accurately and quickly identify the position coordinate information of the target in a very complex environment, and effectively combine detection and tracking.

[0087] The FPGA-based high-definition real-time target detection system uses RGB to HSV color space conversion to minimize the interference caused by lighting changes and target deformation.

[0088] The use of Mean shift algorithm will face a series of shortcomings such as the inability of the iteration window to adapt to itself. Therefore, the Camshift target tracking algorithm is used in this invention, and an adaptive kernel function weight is introduced on the basis of the algorithm to achieve the purpose of accelerating the iteration effect and fast convergence. All algorithm design and implementation are completed in FPGA.

[0089] Each pixel of the image is 16 bits. Calculation shows that the data size of a valid frame of image is 1280*720*16=15Mbit. The general on-chip RAM cannot meet this requirement. The hardware uses DDR3 chip as a buffer unit and divides the DDR3 storage space into two subspaces. Each subspace stores one frame of data and switches with real-time ping-pong operation.

[0090] The information collection camera 141 is connected to the FPGA chip 027 in the form of flying wires, and the surrounding environment information collected by the camera is processed by the FPGA for image recognition.

[0091] Figure 5 The figure shows the program design block diagram of the logic function of this system inside the FPGA, and the arrow points to the direction of data flow. The entire program workflow is as follows: First, when the camera is selected as the video source, the camera driver is initialized and configured inside the FPGA, and the image data in RGB888 format is converted and output. If HDMI is selected as the video source, the FPGA configures the decoding chip and outputs RGB888 format data. After the data enters the grayscale module for processing, it is input into the filtering module. After the filtering output is cached in DDR3, it is read out for moving target detection.

[0092] Secondly, during initialization, the detection output coordinates or the coordinates sent by the host computer through Ethernet are used as a reference for model update. After the model update is completed, the target tracking process begins. The tracking result uses Kalman prediction as a reference for the next frame tracking. The current target tracking output result is marked in the image and displayed using the HDMI protocol output or encoded using the fiber optic protocol to be sent to another fiber optic receiving module.

[0093] Finally, the received data enters the frame decoding module, and the data is buffered in DDR3 after word alignment and output using the HDMI protocol. At the end of each frame, the tracking result information is fed back to the host computer using the Ethernet UDP protocol.

[0094] Figure 6 This is the calculation flow chart of the Camshift algorithm. An improvement is made here. Instead of using the second-order moment as the scale estimate, the probability calculation method is used to estimate the height of the probability rectangle, and the parameters are determined by the initial template scale to equivalently adaptively adjust the length and width of the output tracking target.

[0095] At the beginning, the improved frame difference method is used to detect the moving target intruding the tracking area in real time. When the external button is pressed, the information such as the moving target position in the current frame is initialized. In the next frame, the tracking template is initialized using the image H channel feature based on this position information. In each subsequent frame, the template is reversely projected to the entire image to obtain the probability of the entire image. At the same time, the search box is expanded and the Camshift algorithm is used to iteratively calculate the probability center of mass. After the center of mass coordinate calculation is completed, it is mapped to the full image coordinates and the search boundary is expanded to wait for the next iterative calculation until the iteration converges to the tracking target area, that is, a single tracking task.

[0096] The FPGA-based high-definition real-time target detection system detects and identifies eggs in different environments, and can identify and capture eggs on the ground, in feathers, and even in the dark. The location of each egg will be framed and located in the captured image, and the identification and positioning of eggs greatly reduces the workload of employees.

[0097] like Figure 7 As shown, a four-wheel hub motor driven chicken house inspection equipment based on domestic FPGA includes: a small car based on a vertical architecture design, which adopts a layered architecture design mode and divides its main body into a drive chassis, a hardware integration platform, and a chip protection and loading platform.

[0098] The chassis 116 is equipped with four wheel hub motors 307. A steel bar is welded on each wheel hub. There is a through hole at the other end of the steel bar. The other end of the steel bar is fixed to the chassis 116 with a matching steel shaft and reinforced with bolts, thereby forming a wheel hub rotating device. A battery box 158 is provided at the end of the chassis to power hardware devices such as the FPGA chip 027.

[0099] Hardware integration platform 117: This platform is provided with a groove matching the shape of the FPGA used. A spring clip is provided on both sides of the groove wall to firmly fix the FPGA in the groove to prevent the wiring from falling off due to bumps. The front end of the groove is hollowed out to facilitate connecting the wires to the chassis motor. At the same time, a camera 141 with an electric lifting shaft 170 is installed at the front end of the platform for information collection.

[0100] Loading platform 217: A loading platform 217 is arranged above the groove of the hardware integration platform and is connected to the hardware integration platform via welded columns. The loading platform 217 can be used to carry objects and also provide protection for the FPGA below.

[0101] The device is equipped with a camera 141 with an electric lifting shaft 170. The information collection camera 141 and the lens mounting plate 019 are assembled with each other by bolts; the electric lifting cylindrical shaft includes: a lifting inner shaft 169 and an outer shell 168. The lifting inner shaft passes through the assembly body assembled with the information collection camera and the lens mounting plate by bolts, and is fixed with a gasket and a nut at the shaft end, and the bottom of the outer shell is welded to the hardware integration platform 117 for fixation.

[0102] During the inspection process, if you want to capture and shoot the chicken house environment at a higher location, you can use the electric extension and lowering shaft to raise the position of the camera. Figure 8 As shown, the inner shaft 169 of the electric extending and lowering shaft can drive the camera to move up and down, and the lifting height can be adjusted according to requirements. A large-capacity battery is provided on the hardware integration platform 117 to continuously power the electric extending and lowering shaft.

[0103] The above shows and describes the basic principles, main features and advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A chicken house inspection system driven by a four-wheel motor based on domestic FPGA, characterized in that: include: Four-motor torque deviation coupling control subsystem and target detection and tracking subsystem; The four-motor torque deviation coupling control subsystem is used to provide drive for independent movement and coordinated cooperation between the four wheel hub motors of the equipment based on FPGA; The target detection and tracking subsystem is used to collect chicken house images while the four-motor torque deviation coupling control subsystem provides drive for the device, and perform real-time target detection on the chicken house images based on the FPGA to obtain chicken house inspection results; The four-motor torque deviation coupling control subsystem includes a bottom control module and a top control module; The bottom control module is used to control a single wheel hub motor based on the FOC control algorithm to obtain torque feedback of the single motor; The top-level control module is used to respectively calculate the difference between the torque feedback of the single motor and the torque feedback of other motors to obtain torque compensation, and to coordinately control the movements of the four wheel hub motors based on the torque compensation; The bottom control module includes: a first processing unit, a second processing unit, a third processing unit and a fourth processing unit; Wherein, the first processing unit is used to convert the three-phase current in the stationary coordinate system into the two-phase direct current in the rotating coordinate system based on the coordinate transformation algorithm of the first formula; The second processing unit is used to obtain the motor speed and the motor rotor position based on the encoder adaptive speed measurement algorithm; The third processing unit is used for switching the three-loop control mode, wherein the three-loop control mode includes current loop control alone, current loop + speed loop control and current loop + speed loop + position loop control; The fourth processing unit is used to set a bias in the hardware circuit to perform bias compensation on the current; The top-level control module includes: a branch relative torque feedback unit, a branch separation unit and a coupling unit; Wherein, the branch relative torque feedback unit is used to calculate the average value of multiple data in a single cycle based on a counter and an accumulator; The coupling unit is used to calculate the average value of the multi-channel data and the expected torque value based on the PI control algorithm to obtain the distribution current; The branch separation unit is used to distribute the distribution current to each motor to control the motor output torque; The target detection and tracking subsystem includes: a target detection module and a target tracking module; Wherein, the target detection module is used to obtain the coordinate information of the moving target based on the improved frame difference method; The target tracking module is used to track the moving target in real time based on the Camshift target tracking algorithm.

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