Display panel

Abstract

A display panel that suppresses occurrence of malfunctions caused by ESD is provided. A display panel (1000a) has a display region (AA) defined by a plurality of pixels (P) and a peripheral region (NA) outside the display region. The display panel has a gate drive circuit that includes a shift register having a plurality of stages associated with each of a plurality of pixel rows in the peripheral region, and a first trunk (134) extending in a column direction. The first trunk has a first edge (ea) located on one side that is a display region side in the row direction, and a second edge (eb) located on the other side that is a side opposite the display region in the row direction. The first trunk includes a first portion (134A) and a second portion (134B) each having the first edge and the second edge, the first edge of the second portion being located on the other side in the row direction than the first edge of the first portion. The first portion is provided with no element, and the second portion includes a region provided with an element.

Description

Technical Field

[0001] This invention relates to a display panel. Background Technology

[0002] Liquid crystal display (LCD) panels are used in various LCD devices, including mobile terminals and televisions. From the perspectives of reducing manufacturing costs, design, and functionality, narrow bezels in LCD panels are required. By using Gate Driver Monolithic (GDM) technology, which integrates the gate driving circuitry (sometimes called "gate driver") onto the TFT substrate, compared to mounting the gate driving circuitry on the TFT substrate using COF (Chip-on-Foil) or COG (Chip-on-Glass), costs associated with driver mounting can be reduced, and narrow bezels can be achieved. GDM technology is sometimes also called GOA (Gate on Array).

[0003] Patent documents 1-3 disclose display devices that utilize GDM technology. In the display devices of patent documents 1-3, a trunk line group extending in the vertical direction for supplying signals to the gate drive circuit is provided in a region on the TFT substrate of the display panel corresponding to a region outside the display area of ​​the display device (sometimes referred to as the "peripheral region" or "bezel region"), for example, in the region to the left and / or right of the display area.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2011 / 104945

[0007] Patent Document 2: International Publication No. 2018 / 025412

[0008] Patent Document 3: U.S. Patent Application Publication No. 2021 / 272949 Summary of the Invention

[0009] The problem that the invention aims to solve

[0010] The goal is to improve the manufacturing yield of display devices employing GDM technology. A major cause of reduced manufacturing yield is, for example, damage caused by electrostatic discharge (ESD) during the display panel manufacturing process. Details will be discussed later.

[0011] The purpose of this invention is to provide a display panel that suppresses the occurrence of defects caused by ESD.

[0012] Solution for solving the problem

[0013] According to embodiments of the present invention, solutions described in the following items are provided.

[0014] [Project 1]

[0015] A display panel having a plurality of pixels arranged in a matrix having a plurality of pixel rows and a plurality of pixel columns.

[0016] It has a display area defined by the plurality of pixels and a peripheral area outside the display area.

[0017] It includes: a gate driving circuit disposed in the peripheral region, and a shift register having multiple stages associated with each of the multiple pixel rows; and

[0018] The first main line is located in the surrounding area and extends along the column direction.

[0019] The first trunk line has two edges in the row direction, a first edge located on one side as the display area side in the row direction, and a second edge located on the other side as the opposite side of the display area in the row direction.

[0020] The first trunk line includes a first portion and a second portion, each having the first edge and the second edge, respectively.

[0021] The first edge of the second portion is located on the other side in the row direction, which is further away from the first edge of the first portion.

[0022] The first part has no components.

[0023] The second part includes an area where elements are disposed.

[0024] [Item 2] The display panel according to Item 1 further includes a second trunk line, which is disposed in the peripheral area, extends along the column direction, and is located on the opposite side of the first trunk line from the display area.

[0025] The first trunk line supplies a common signal to one or more first-type stages included in the plurality of stages of the shift register.

[0026] The second trunk line supplies other common signals to one or more second-type stages included in the plurality of stages of the shift register.

[0027] The second trunk line has two edges in the row direction, a third edge on the display area side, and a fourth edge on the opposite side of the display area.

[0028] The second trunk line includes a third portion that is adjacent in the row direction to the first portion of the first trunk line and has the third edge and the fourth edge, and a fourth portion that is adjacent in the row direction to the second portion of the first trunk line and has the third edge and the fourth edge.

[0029] The third part includes an area where components are disposed.

[0030] The fourth part has no components.

[0031] The first trunk line supplies the common signal to the one or more first-level components via the element disposed in the second section.

[0032] The second trunk line supplies the other common signals to the one or more second levels via the element disposed in the third section.

[0033] [Item 3] According to the display panel described in Item 2, the second portion of the first trunk line is disposed within the forming area of ​​the unit circuit constituting the one or more first-level circuits.

[0034] The third portion of the second trunk line is configured within the forming region of the unit circuit constituting the one or more second-level stages.

[0035] [Item 4] In the display panel described in Item 2 or 3, the shape of the third edge of the second trunk line is consistent with the shape of the second edge of the first trunk line.

[0036] The distance between the third edge of the second trunk line and the second edge of the first trunk line is approximately constant.

[0037] [Item 5] In any one of Items 2 to 4, the width of the fourth portion of the second trunk line is smaller than the width of the third portion of the second trunk line.

[0038] [Item 6] In the display panel according to any one of Items 1 to 5, the first trunk line further has a connecting portion connecting the first part and the second part.

[0039] The first part and the second part extend in the column direction.

[0040] The connecting portion extends in a direction different from the column direction.

[0041] [Item 7] According to the display panel described in Item 6, the first trunk line bends between the first portion and the connecting portion and between the second portion and the connecting portion.

[0042] [Item 8] The display panel according to any one of Items 1 to 7, wherein the first trunk has a plurality of ESD sacrificial portions protruding toward the display area side.

[0043] [Item 9] According to Item 8 of Item 7, the plurality of ESD sacrificial portions include ESD sacrificial portions extending from the angle formed by the first portion of the first trunk and the connecting portion toward the display area side.

[0044] [Item 10] According to the display panel described in Item 8 or 9, the plurality of ESD sacrifices correspond to the plurality of level settings of the shift register.

[0045] [Item 11] In any one of items 1 to 10, the width of the second portion of the first trunk line is equal to the width of the first portion of the first trunk line.

[0046] [Item 12] A display panel according to any one of Items 1 to 11,

[0047] It also includes a substrate, a gate metal layer formed on the substrate, an insulating layer covering the gate metal layer, and a source metal layer formed on the insulating layer.

[0048] The first trunk line is contained within the gate metal layer.

[0049] [Item 13] The display panel according to any one of Items 1 to 12, wherein the element is a TFT contained in a unit circuit, the unit circuit constituting the stage of the shift register.

[0050] Invention Effects

[0051] According to an embodiment of the present invention, a display panel is provided to suppress the occurrence of defects caused by ESD. Attached Figure Description

[0052] Figure 1 This is a schematic diagram showing the configuration of a display device 1100a having a display panel 1000a according to Embodiment 1 of the present invention.

[0053] Figure 2 This is a schematic top view of the display device 1100a.

[0054] Figure 3 It is a schematic top view of the display panel 1000a, and a top view that schematically shows a portion of the display panel 1000a.

[0055] Figure 4It is a schematic top view of the display panel 1000a, and a schematic top view showing a portion of the surrounding area NA and the display area AA.

[0056] Figure 5 This is a schematic top view of the comparative example display panel 900a, and a schematic top view showing a portion of the peripheral area NA and the display area AA.

[0057] Figure 6 This is a schematic top view showing a display panel 1000n with a second embodiment of the present invention, and a schematic top view showing a portion of the peripheral area NA and the display area AA.

[0058] Figure 7 The comparative example is a schematic top view of the display panel 900a, which schematically shows a portion of the peripheral area NA and the display area AA. Detailed Implementation

[0059] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, a liquid crystal display panel is shown below as an example of a display panel according to an embodiment of the present invention, but the present invention is not limited to the following embodiments. In the following figures, constituent elements having substantially the same function are shown using the same reference numerals, and their descriptions are sometimes omitted.

[0060] (Implementation Method 1)

[0061] Reference Figures 1-4 The liquid crystal display panel 1000a and the liquid crystal display device 1100a having the liquid crystal display panel 1000a (hereinafter, sometimes referred to as "display panel 1000a" and "display device 1100a") according to this embodiment will be described. Figure 1 This is a schematic diagram showing the configuration of the display device 1100a. Figure 2 This is a schematic top view of the display device 1100a. Figure 3 It is a schematic top view of the display panel 1000a, and a top view that schematically shows a portion of the display panel 1000a. Figure 4 It is a schematic top view of the display panel 1000a, and a schematic top view showing a portion of the surrounding area NA and the display area AA.

[0062] like Figure 1 and Figure 2 As shown, the display panel 1000a has a plurality of pixels P, which are arranged in a matrix with a plurality of pixel rows and a plurality of pixel columns. Each pixel P has a pixel electrode 5 electrically connected to a TFT (Thin Film Transistor) 1. Pixel rows are in the row direction (…). Figure 2Multiple pixels P arranged in the X direction, where the pixel column is in the column direction ( Figure 2 The display panel 1000a has a plurality of pixels P arranged in the Y direction. The display panel 1000a has a TFT substrate 101 and a counter substrate 201 facing each other, and a liquid crystal layer disposed between these substrates. The display panel 1000a has a display area AA defined by the plurality of pixels P and a peripheral area NA outside the display area AA. The peripheral area NA includes a first peripheral area NA1 located further outward in the row direction than the display area AA and a second peripheral area NA2 located further outward in the column direction than the display area AA. The display device 1100a has a display panel 1000a and a circuit board 510 connected to the display panel 1000a.

[0063] In this example, each of the multiple pixel rows is associated with a gate bus GL, and each of the multiple pixel columns is associated with a source bus SL. The TFT1 of each pixel P receives a gate signal from the corresponding gate bus GL and a source signal from the corresponding source bus SL. The pixel rows are denoted from top to bottom as row 1, row 2, ..., row rx, and the gate bus associated with the pixel row r (1 ≤ r ≤ rx) is denoted as gate bus GL(r) (see reference). Figure 1 Here, rx is the number of pixel rows in the display panel 1000a. The pixels in the r-th pixel row are selected by a scan signal voltage supplied to the gate bus GL(r). The gate bus GL(r) associated with the r-th pixel row is connected to the gate electrode of the TFT, which is connected to the pixels contained in the r-th pixel row. Pixel columns can be denoted from left to right as first column, second column, ..., qy-th column, and the source bus SL associated with the q-th pixel column is denoted as source bus SL(q). Here, qy is the number of pixel columns in the display panel 1000a. Display signal voltages are supplied from the source bus SL(q) to the pixels in the q-th pixel column (1≤q≤qy). The source bus SL(q) associated with the q-th pixel column is connected to the source electrode of the TFT, which is connected to the pixels contained in the q-th pixel column.

[0064] Display panel 1000a has a gate driving circuit GD. Here, the gate driving circuit GD is integrally formed on the TFT substrate 101 (gate driver monolithic). The gate driving circuit GD is disposed in a first peripheral region NA1 of display panel 1000a and includes a shift register 110 having multiple stages associated with each of multiple pixel rows. The outputs of each stage of shift register 110 are connected to a gate bus GL associated with each of the multiple pixel rows. Typically, shift register 110 has rx stages, which are sequentially designated as first stage, second stage, ..., rx stages from top to bottom, with the output of the rth stage (1 ≤ r ≤ rx) connected to the gate bus GL(r). In addition to the rx stages, shift register 110 may also include one or more virtual stages adjacent to the rx stages in the column direction that do not contribute to the display. Shift register 110 is constructed by vertically connecting (cascading) multiple unit circuits QC. Each stage of shift register 110 is composed of individual unit circuits QC. Each stage of the shift register 110 has a unit circuit QC with at least one TFT (semiconductor element).

[0065] Display panel 1000a has a first trunk line 134 disposed in the peripheral area NA and extending along the column direction. The first trunk line 134 has the following shape. The first trunk line 134 has a first edge ea on the display area AA side of the two edges on both sides of the first trunk line 134 in the row direction and a second edge eb on the opposite side of the display area. Sometimes the display area AA side in the row direction is referred to as one side, and the side opposite to the display area AA is referred to as the other side. That is, the first edge ea is located on one side in the row direction, and the second edge eb is located on the other side in the row direction. The first trunk line 134 includes a first portion 134A and a second portion 134B having the first edge ea and the second edge eb, respectively. The second portion 134B may also be located in the column direction of the first portion 134A. In this specification, unless otherwise specified, "column direction" includes directions parallel to the +Y direction and -Y direction. Here, the direction of the arrow of the Y-axis in the figure is defined as the +Y direction, and its opposite direction is defined as the -Y direction. Similarly, unless otherwise specified, "row direction" also includes directions selected from the +X direction and -X direction. Here, the direction of the arrow on the X-axis in the attached diagram is set to the +X direction, and its opposite direction is set to the -X direction. In the example shown, for the peripheral area NA located to the left of the display area AA ( Figure 3 and Figure 4The horizontal direction is +X on one side and -X on the other. For the peripheral area NA located to the right of the display area AA, the horizontal direction is -X on one side and +X on the other. The first edge ea of ​​the second part 134B is located further to the other side of the horizontal direction than the first edge ea of ​​the first part 134A. For example, the first edge ea of ​​the second part 134B is farther away from the display area AA than the first edge ea of ​​the first part 134A. In the first part 134A, no element (here, the TFT of the unit circuit QC) is provided. The second part 134B includes an area where an element (here, the TFT 10b of the unit circuit QC) is provided. The first part 134A and the second part 134B may be discontinuous. In this example, the first trunk line 134 also has a connecting portion 134c between the first part 134A and the second part 134B. The first trunk line 134 may have portions other than the first part 134A, the second part 134B, and the connecting portion 134c. Here, as an example, the TFTs included in the unit circuit QC of each of the multiple stages of the shift register 110 are shown, but it is not limited to this, and other circuit elements (such as capacitor elements) may also be used.

[0066] The display panel 1000a also includes a second trunk line 132 disposed in the peripheral area NA and extending along the column direction. The second trunk line 132 is located on the side of the first trunk line 134 opposite to the display area AA. That is, the first trunk line 134 is located between the display area AA and the second trunk line 132. The first trunk line 134 and the second trunk line 132 are used to supply signals to each of the plurality of stages of the shift register 110. The first trunk line 134 provides a common signal to one or more first stages included in the plurality of stages. The second trunk line 132 provides a common signal to one or more second stages included in the plurality of stages. That is, the stage of the plurality of stages of the shift register 110 that receives signals from the first trunk line 134 is called the "first stage", and the stage that receives signals from the second trunk line 132 is called the "second stage". Since the first trunk line 134 and the second trunk line 132 are electrically independent, different signals can be supplied to the first stage and the second stage. The first trunk line 134 and the second trunk line 132 are used, for example, to supply clear signals (reset signals) to each stage of the shift register 110. As clear signals, the gate start pulse signal GSP and / or the gate end pulse signal GEP can also be used. For example, the gate end pulse signal GEP is supplied as a clear signal to the first stage, and the gate start pulse signal GSP is supplied as a clear signal to the second stage.

[0067] exist Figure 4The diagram shows the (n+1)th level S(n+1) to the (n+4)th level S(n+4) of the multiple levels of the shift register 110. The initial number x in parentheses following the reference symbol of level S corresponds to the xth level of the shift register 110. The character (“A” or “B”) following the number x in parentheses indicates whether the xth level is a first type of level or a second type of level; “B” indicates the first type of level, and “A” indicates the second type of level. The unit circuits constituting the first type of level, i.e., levels (n+3) and (n+4) respectively, include TFT 10b. The unit circuits constituting the second type of level, i.e., levels (n+1) and (n+2) respectively, include TFT 10a. The second portion 134B of the first trunk line 134 includes a region where the TFT 10b is disposed, i.e., includes the portion constituting the TFT 10b (e.g., the portion that functions as the gate electrode of the TFT 10b). The comb-shaped electrodes formed by electrodes 36b and 36d are the source and drain electrodes of the TFT 10b, with the first trunk line 134 as the gate electrode. The first trunk line 134 supplies a common signal to the first stage via the TFT 10b disposed in the second portion 134B. The first portion 134A of the first trunk line 134 is disposed, for example, in the forming region of the unit circuit QC constituting the second stage. In addition, the second portion 134B of the first trunk line 134 is disposed, for example, in the forming region of the unit circuit QC constituting the first stage. However, the first trunk line 134 may also be disposed on the opposite side of the horizontal direction, closer to the shift register 110 (i.e., the side opposite to the display area AA). In addition, the portion of the first trunk line 134 disposed in the forming region of the unit circuit QC constituting the first stage may also include portions other than the second portion 134B (e.g., the portion where the position of the first edge ea in the horizontal direction is the same as that of the first portion 134A, the portion where the position of the first edge ea in the horizontal direction changes (connection portion 134c), etc.). Similarly, the portion of the first trunk 134 arranged in the forming area of ​​the unit circuit QC constituting the second level may also include the portion other than the first portion 134A.

[0068] The second trunk line 132 includes a third portion 132A adjacent in the row direction to the first portion 134A of the first trunk line 134 and having a third edge ec and a fourth edge ed, and a fourth portion 132B adjacent in the row direction to the second portion 134B of the first trunk line 134 and having a third edge ec and a fourth edge ed. The third portion 132A includes a region where a TFT 10a of a unit circuit QC is provided. That is, the third portion 132A includes a portion constituting the TFT 10a (e.g., a portion that functions as the gate electrode of the TFT 10a). The comb-shaped electrodes formed with electrodes 36a and 36c are the source and drain electrodes of the TFT 10a with the second trunk line 132 as the gate electrode. The TFT of the unit circuit QC is not provided in the fourth portion 132B. The second trunk line 132 supplies other common signals to the second level via the TFT 10a provided in the third portion 132A. The third portion 132A of the second trunk line 132 is, for example, disposed in the forming region of the unit circuit QC constituting the second level. Furthermore, the fourth portion 132B of the second trunk line 132 may be disposed, for example, within the forming area of ​​the unit circuit QC constituting the first level. However, the second trunk line 132 may also be disposed on the opposite side of the row direction from the shift register 110 (i.e., the side opposite to the display area AA). Additionally, the portion of the second trunk line 132 disposed within the forming area of ​​the unit circuit QC constituting the second level may include portions other than the third portion 132A (e.g., portions where the third edge ec is at the same position in the row direction as the fourth portion 132B, portions where the position of the third edge ec changes in the row direction (connection portion 132c), etc.). Similarly, the portion of the second trunk line 132 disposed within the forming area of ​​the unit circuit QC constituting the first level may also include portions other than the fourth portion 132B.

[0069] The display panel 1000a will be compared with the display panel of the comparative example, and the reasons why the display panel 1000a can suppress the occurrence of defects caused by ESD will be explained. Figure 5 This is a schematic top view of the comparative example display panel 900a, and is compared with... Figure 4 The diagram corresponds to a schematic top view of the display panel 1000a shown. Figure 4 and Figure 5 The first peripheral region NA1 and the display region AA are partially shown on the left side of the display region AA. The same applies hereinafter in the same figures. The display panel 900a of the comparative example differs from the first trunk line 134 and second trunk line 132 of the display panel 1000a in shape of the first trunk line 934 and second trunk line 932. According to the inventors' research, in the display panel 900a of the comparative example, defects caused by ESD cannot be sufficiently suppressed.

[0070] An insulating layer (gate insulating layer) and a semiconductor layer (34a, 34b) are formed on the gate metal layer (first trunk line 134 or first trunk line 934, second trunk line 132 or second trunk line 932, conductive part 32a), and a source metal layer (electrodes 36a, 36b, 36c, 36d) is formed thereon.

[0071] For example, in the process of manufacturing the TFT substrate 101, during the process of forming the TFT on the substrate, after forming the gate metal layer on the substrate, a gate insulating film and a semiconductor film are formed. When these are patterned, ESD may occur between the patterns of the gate metal layer. In particular, when the display panel becomes larger, the area occupied by the gate metal (the portion that actually contains the conductor) of the gate metal layer increases, and the amount of charge accumulated in the gate metal increases. The charge accumulated in the gate metal provided in the display area AA of the gate metal layer flies outward from the display area AA side (i.e., towards the peripheral area side), and the gate metal on the side receiving the charge is melted, and the insulating film is damaged. In a subsequent process, if source metal is formed on the melted part, a short circuit will occur at the melted part. When the charge accumulated in the gate metal (gate bus GL) provided in the display area AA flies towards the first trunk line 934 ( Figure 5 (The dashed arrow indicates that) part of the first main line 934 was melted, and the insulation film was damaged. Figure 5 The ESD occurs after the gate metal layer is formed (i.e., after the gate metal film is deposited and patterned), when the gate insulating film and semiconductor film are formed and patterned, between adjacent patterns of the gate metal layer. There is a tendency for the probability of ESD to be higher as the distance between the patterns of the gate metal layer is smaller. In a subsequent process, when the source metal is formed on the fused portion of the gate metal, a short circuit between the source and gate is generated on the fused portion (hereinafter referred to as "SG short circuit" for simplicity). The probability of ESD occurring between the first trunk line 934 and the conductive portion 32a is high, thus, the SG short circuit is prone to occur in the TFT10b formed overlapping with the first trunk line 934. The conductive portion 32a is part of the gate metal and is disposed near the first edge ea of ​​the first trunk line 934. The conductive portion 32a is not electrically connected to the gate bus GL. By repeatedly sending the charge accumulated in the gate bus GL to the adjacent, unconnected gate metal, the conductive portion 32a can become the starting point of ESD to the first trunk line 934.

[0072] In contrast, the display panel 1000a according to an embodiment of the present invention can suppress the occurrence of SG short circuits in the TFT 10b. In the display panel 1000a, since the first edge ea of ​​the second portion 134B of the first trunk line 134 is farther from the display area AA than the first edge ea of ​​the first portion 134A, SG short circuits in the TFT 10b caused by ESD can be suppressed. The display panel 1000a can improve manufacturing yield. Figure 4 The diagram shows the distance between the second portion 134B of the first trunk line 134 and the display area AA, and the difference D1z between the distance between the first portion 134A of the first trunk line 134 and the display area AA. In the display panel 1000a, compared with the comparative example display panel 900a, the distance between the first trunk line 134 and the conductive portion 32a is larger by D1z, thus suppressing the probability of ESD generation between the first trunk line 134 and the conductive portion 32a.

[0073] In this example, the first trunk line 134 also has a connecting portion 134c that connects the first portion 134A and the second portion 134B. The first portion 134A and the second portion 134B extend along the column direction (the Y direction in the figure), and the connecting portion 134c that connects them extends in a direction different from the column direction. The first trunk line 134 bends between the first portion 134A and the connecting portion 134c, and between the second portion 134B and the connecting portion 134c. The width of the first portion 134A of the first trunk line 134 and the width of the second portion 134B of the first trunk line 134 can be equal to or different from each other. The shape of the first trunk line 134 is not limited to the example shown in the figure, as long as it forms the difference D1z between the distance of the second portion 134B of the first trunk line 134 and the distance of the first portion 134A of the first trunk line 134 and the display area AA. For example, the first trunk line 134 can be smoothly bent between the second portion 134B and the first portion 134A. When the first trunk line 134 has a connecting portion 134c, the second trunk line 132 also has a connecting portion 132c that is adjacent to the connecting portion 134c of the first trunk line 134 in the row direction.

[0074] The edge on the display area AA side of the two edges in the row direction of the second trunk line 132 is called the third edge ec, and the edge on the opposite side of the display area AA is called the fourth edge ed. The shape of the third edge ec of the second trunk line 132 is the same as the shape of the second edge eb of the first trunk line 134. Therefore, the third edge ec of the fourth portion 132B of the second trunk line 132 is farther away from the display area AA than the third edge ec of the third portion 132A of the second trunk line 132. The distance between the third edge ec of the second trunk line 132 and the second edge eb of the first trunk line 134 is approximately constant. Here, it is assumed that the distance between the third edge ec of the second trunk line 132 and the second edge eb of the first trunk line 134 is the same as the distance between the third edge ec of the second trunk line 932 and the second edge eb of the first trunk line 934 of the comparative example display panel 900a. The width D2b of the fourth portion 132B of the second trunk line 132 is smaller than the width D2a of the third portion 132A of the second trunk line 132. The display panel 1000a has a shape via the second trunk line 132 such that, compared to the display panel 900a of the comparative example, it can suppress the increase in the area of ​​the peripheral region NA (especially the first peripheral region NA1), that is, it can suppress the occurrence of defects caused by ESD without sacrificing the realization of the narrow bezel of the display panel.

[0075] The structure of the display panel 1000a and the display device 1100a will be described in more detail.

[0076] like Figure 2 As shown, the circuit board 510 has a control circuit CNTL that supplies control signals to the gate drive circuit GD. For example, the control circuit CNTL is mounted on the circuit board 510. The circuit board 510 is connected to a terminal portion TP formed in the second peripheral region NA2 of the display panel 1000a via a source substrate 520. The circuit board 510 is connected to the source substrate 520 via a flexible printed circuit (FPC) 512. Terminals are provided on the terminal portion TP, which are respectively electrically connected to trunk lines for supplying signals to the gate drive circuit GD. The circuit board 510 supplies signals from the terminal portion TP of the display panel 1000a to each trunk line via the source substrate 520, each trunk line being used to supply signals to the gate drive circuit GD. In this example, the circuit board 510 is connected to the display panel 1000a via multiple source substrates 520. The source substrate 520 (printed wiring substrate) is connected to the display panel 1000a via multiple flexible circuit boards 522. A source drive circuit SD, which supplies display signal voltage to the source bus SL, is mounted on the flexible circuit board 522. Furthermore, Figure 2For ease of observation, the source bus SL is omitted from the diagram. The control circuit CNTL also supplies control signals to the source drive circuit SD, for example. The control signals supplied by the control circuit CNTL to the gate drive circuit GD include, for example, the gate start pulse signal GSP, the gate clock signal GCK, and the gate end pulse signal GEP. The control signals supplied by the control circuit CNTL to the source drive circuit SD include, for example, the source start pulse signal SSP and the source clock signal SCK. Furthermore, the configuration and connection methods of the source drive circuit SD and the control circuit CNTL are not limited to the methods shown in the diagram. Additionally, in... Figure 2 In this configuration, gate drive circuits GD and wiring for supplying signals to the gate drive circuits GD are provided on both the left and right sides of the display area AA. However, it is also possible to provide gate drive circuits GD and wiring for supplying signals to the gate drive circuits GD only on either the left or right side of the display area AA.

[0077] Figure 3 The wiring for inputting signals to the shift register 110 is shown in more detail. The display panel 1000a also includes the following wiring provided in the first peripheral region NA1 to supply signals to the gate drive circuit GD. Specifically, the display panel 1000a has n clock trunks CKL1 to CKLn that extend along the column direction and supply n different (n is an integer greater than 2) clock signals with different phases to multiple stages of the shift register 110, an outer trunk 122 and an inner trunk 124 that extend along the column direction and supply a common signal to multiple stages of the shift register 110, and multiple branch wirings 140 that are electrically connected to the outer trunk 122 and the inner trunk 124, respectively. On the terminal portion TP of the second peripheral region NA2 of the display panel 1000a, terminals (n clock trunk terminals and outer trunk terminals) are provided that are electrically connected to the n clock trunks CKL1 to CKLn and the outer trunk 122, respectively. Sometimes, the n clock trunks CKL1 to CKLn are collectively referred to as clock trunks CKL.

[0078] As n clock trunks CKL1~CKLn, Figure 3In the example, eight clock lines CKL1 to CKL8 (n = 8) are provided. If the gate clock signals GCK supplied from the clock lines CKL1 to CKL8 are set to GCK1 to GCK8, then the gate clock signals GCK1 to GCK8 have, for example, a period of 8H (1H is one horizontal scan period), a duty cycle of 1:1 (4H is high level and 4H is low level in one period of 8H), and a phase difference of 1H between each. For example, the low level potential Vgl = -7V, and the high level potential Vgh = 35V. On the terminal portion TP of the second peripheral area NA2 of the display panel 1000a, there are terminals (eight clock line terminals) that are electrically connected to the clock lines CKL1 to CKL8 respectively. The gate clock signals GCK1 to GCK8 are supplied to the clock lines CKL1 to CKL8 connected from the control circuit CNTL via the clock line terminals. Since the inputs (input terminals) of each clock line CKL1 to CKL8 and each stage of shift register 110 are electrically connected via wiring 154 extending in the row direction, gate clock signals GCK1 to GCK8 are supplied to the inputs of each stage of shift register 110. An example of the connection relationship between the inputs of each stage of shift register 110 and the n clock lines CKL1 to CKLn is as follows. For example, gate clock signals GCK1 to GCK8 are supplied from clock lines CKL1 to CKL8 to the inputs of stages 1 to 8, respectively; gate clock signals GCK1 to GCK8 are supplied from clock lines CKL1 to CKL8 to the inputs of stages 9 to 16, respectively; gate clock signals GCK1 to GCK8 are supplied from clock lines CKL1 to CKL8 to the inputs of stages 17 to 24, respectively; and so on. That is, the input of the {(a×n)+k}th stage of the shift register 110 is supplied with the gate clock signal GCKk from the clock trunk CKLk (here, a is an integer above 0 and k is an integer above 0 and below n-1).

[0079] The outer trunk line 122 and the inner trunk line 124 are used, for example, to supply signals providing a low-level potential (e.g., VSS = -7V) to multiple stages of the shift register 110. A signal providing a fixed potential (e.g., a signal providing a low-level potential VSS) is supplied to the outer trunk line 122, which is connected to the control circuit CNTL via terminals connected to the outer trunk line. The outer trunk line 122 and the inner trunk line 124 are electrically connected via branch wiring 140, and the inner trunk line 124 is electrically connected to the inputs (input terminals) of each stage of the shift register 110 via wiring 152, thus supplying a signal providing a low-level potential VSS to the inputs of each stage of the shift register 110.

[0080] The display panel 1000a may further include additional trunks 121 disposed in the first peripheral region NA1, extending in the column direction and supplying other common signals to multiple stages of the shift register 110. In this case, signals providing two low-level potentials (e.g., VSS1 = -12V, VSS2 = -7V) are supplied from the control circuit CNTL. The outer trunk 122 and the inner trunk 124 supply the signal providing the low-level potential VSS2 to multiple stages of the shift register 110, while trunk 121 supplies the signal providing the low-level potential VSS1 to multiple stages of the shift register 110.

[0081] Furthermore, the outer trunk line 122 and the inner trunk line 124 can also be used, for example, to supply a high-level signal VD (which may be different from Vgh) to multiple stages of the shift register 110. The high-level signal VD can also be supplied to the outer trunk line 122, which is connected from the control circuit CNTL via an external trunk line terminal.

[0082] In this example, the inner trunk 124 is configured further away from the display area AA than the shift register 110, and the outer trunk 122 is configured further away from the display area AA than the inner trunk 124. Eight clock trunks CKL1 to CKL8 are positioned between the outer trunk 122 and the inner trunk 124. Typically, the width of the outer trunk 122 in the row direction is greater than the width of the inner trunk 124 in the row direction.

[0083] (Implementation Method Two)

[0084] Reference Figure 6 This describes the liquid crystal display 1000b according to this embodiment. Figure 6 It is a schematic top view of the display panel 1000a, and a schematic top view showing a portion of the surrounding area NA and the display area AA. Figure 6 Is with Figure 4 The diagram shows a schematic top view of the display panel 1000a. The following mainly describes the differences from the previous embodiment.

[0085] In the display panel 1000b, the first trunk line 134 has a plurality of ESD sacrificial portions 134x protruding toward the display area AA side. The plurality of ESD sacrificial portions 134x are provided, for example, corresponding to each stage of the shift register 110. An "ESD sacrificial portion" is an unnecessary additional part for the wiring or electrode to perform its function, and is provided at a location where ESD failure is more likely to occur than the part (wiring body or electrode body) required for the wiring or electrode to perform its function.

[0086] In display panel 1000b, similarly to display panel 1000a, the occurrence of defects caused by ESD can be suppressed. This will be explained while comparing display panel 1000b with display panel 900b of the comparative example. Figure 7 The comparative example is a schematic top view of display panel 900a, which schematically shows a portion of the peripheral area NA and the display area AA. The comparative example display panel 900b differs from the first trunk 134 and second trunk 132 of display panel 1000b in the shape of the first trunk 934 and the second trunk 932.

[0087] On the side of the first trunk line 934 of the conductive portion 32a (opposite to the display area AA side), a plurality of ESD sacrificial portions 32x are also provided, opposite to the plurality of ESD sacrificial portions 134x provided on the first trunk line 934. Since the ESD sacrificial portions 134x of the first trunk line 934 are close to the ESD sacrificial portions 32x of the conductive portion 32a, the possibility of ESD occurring between them increases. That is, the charge accumulated in the gate metal provided in the display area AA is very likely to fly towards the ESD sacrificial portions 134x of the first trunk line 934. According to the inventors' research, sometimes by causing the charge flying towards the ESD sacrificial portions 134x of the first trunk line 934 to further fly towards the part that functions as the gate electrode of the TFT 10b of the first trunk line 934, a portion of the first trunk line 934 is melted, and the insulating film is damaged. Figure 7 (ESD). In subsequent processes, if source metal is formed on the fused portion of the gate metal, an SG short circuit occurs on the fused portion. Thus, an SG short circuit sometimes occurs in TFT10b.

[0088] In contrast, in the display panel 1000b, the first edge ea of ​​the second portion 134B of the first trunk line 134 is farther from the display area AA than the first edge ea of ​​the first portion 134A. Therefore, since the distance from the front end of the ESD sacrificial portion 134x disposed on the first trunk line 134 to the TFT 10b is large, SG short circuits of the TFT 10b can be suppressed. Preferably, the distances from the front end of the ESD sacrificial portion 134x disposed on the first portion 134A and the ESD sacrificial portion 134x disposed on the second portion 134B of the first trunk line 134 to the display area AA are equal.

[0089] For example, if the display panel is large, the area occupied by the gate metal of the gate metal layer of the first trunk 134 is large, so charge will accumulate in the first trunk 134, becoming one of the main causes of ESD. In order to suppress charge from flying out from the corner formed by the first portion 134A and the connecting portion 134c of the first trunk 134, the plurality of ESD sacrificial portions 134x preferably include ESD sacrificial portions 134x extending from the corner formed by the first portion 134A and the connecting portion 134c of the first trunk 134 towards the display area AA side.

[0090] Practicality in industry

[0091] The display panel according to embodiments of the present invention is widely used in active-matrix display panels such as liquid crystal display panels and organic EL display panels. When the display panel according to embodiments of the present invention is used, the manufacturing yield of active-matrix display panels can be improved.

[0092] Explanation of reference numerals in the attached figures

[0093] 101: TFT substrate, 110: shift register, 132: second trunk line, 132A: third section of the second trunk line, 132B: fourth section of the second trunk line, 134: first trunk line, 134A: first section of the first trunk line, 134B: second section of the first trunk line, 134x: ESD sacrificial part, 201: relative substrate, 510: circuit board, 1000a, 1000b: display panel, 1100a: display device.

Claims

1. A display panel characterized by: having a plurality of pixels arranged in a matrix shape having a plurality of pixel rows and a plurality of pixel columns, having a display region defined by the plurality of pixels and a peripheral region outside the display region, having a gate driver circuit provided in the peripheral region and including a shift register having a plurality of stages associated with each of the plurality of pixel rows; and a first trunk provided in the peripheral region and extending in the column direction, the first trunk having edges as both sides in the row direction of the first trunk, a first edge on the display region side in the row direction and a second edge on the other side in the row direction opposite the display region, the first trunk including a first portion and a second portion each having the first edge and the second edge, the first edge of the second portion being on the other side in the row direction further than the first edge of the first portion, the first portion being free of elements, the second portion including a region provided with elements, further having a second trunk provided in the peripheral region, extending in the column direction, and located on the other side of the first trunk opposite the display region, the first trunk supplying a common signal to one or more first stages included in the plurality of stages of the shift register, the second trunk supplying another common signal to one or more second stages included in the plurality of stages of the shift register, the second trunk having edges as both sides in the row direction of the second trunk, a third edge on the display region side and a fourth edge on the other side opposite the display region, the second trunk including a third portion adjacent in the row direction to the first portion of the first trunk and having the third edge and the fourth edge, and a fourth portion adjacent in the row direction to the second portion of the first trunk and having the third edge and the fourth edge, the third portion including a region provided with elements, the fourth portion being free of elements, the first trunk supplying the common signal to the one or more first stages via the elements provided in the second portion, the second trunk supplying the another common signal to the one or more second stages via the elements provided in the third portion.

2. The display panel according to claim 1, characterized in that: the second portion of the first trunk is disposed within a formation region of a unit circuit constituting the one or more first stages, the third portion of the second trunk is disposed within a formation region of a unit circuit constituting the one or more second stages.

3. The display panel according to claim 1 or 2, characterized in that: a shape of the third edge of the second trunk coincides with a shape of the second edge of the first trunk, a distance between the third edge of the second trunk and the second edge of the first trunk is substantially constant.

4. The display panel according to claim 3, characterized in that: ​ A width of the fourth portion of the second trunk is smaller than a width of the third portion of the second trunk.

5. The display panel according to claim 1 or 2, wherein The first trunk further has a connection portion connecting the first portion and the second portion, The first portion and the second portion extend in a column direction, The connection portion extends in a direction different from the column direction.

6. The display panel according to claim 5, wherein The first trunk is bent between the first portion and the connection portion and between the second portion and the connection portion.

7. The display panel according to claim 6, wherein The first trunk has a plurality of ESD sacrifice portions protruding toward the display region side.

8. The display panel according to claim 7, wherein The plurality of ESD sacrifice portions include an ESD sacrifice portion disposed extending toward the display region side from a corner formed by the first portion of the first trunk and the connection portion.

9. The display panel according to claim 7, wherein The plurality of ESD sacrifice portions are provided corresponding to the plurality of stages of the shift register.

10. The display panel according to claim 1 or 2, wherein A width of the second portion of the first trunk is equal to a width of the first portion of the first trunk.

11. The display panel according to claim 1 or 2, wherein Further having a substrate, a gate metal layer formed on the substrate, an insulating layer covering the gate metal layer, and a source metal layer formed on the insulating layer, The first trunk is included in the gate metal layer.

12. The display panel according to claim 1 or 2, wherein The element is a TFT included in a unit circuit, the unit circuit constituting the stage of the shift register.

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