An RSSI circuit

Abstract

This application relates to the field of optical communication and proposes an RSSI circuit, comprising: a first control loop including a first operational amplifier, a first input terminal configured to receive a first reference signal, and a second input terminal coupled to a first electrode of an external photosensitive element; in a first operating mode, the first operational amplifier is connected in a negative feedback manner and configured to clamp the first electrode of the external photosensitive element at the level of the first reference signal; in a second operating mode, the first operational amplifier is disconnected from other parts of the first control loop; a second control loop coupled to the first control loop and configured to replicate the current flowing through the external photosensitive element to obtain a first current; and a control signal generation circuit coupled to the first and second control loops and configured to replicate the current flowing through the external photosensitive element to obtain a second current, compare it with a second reference signal, and control the operating mode of the first control loop based on the comparison result. This application also relates to an electronic device.

Description

Technical Field

[0001] This application relates to the field of optical communication, and in particular to a signal strength indication (RSSI) circuit for an optical module. Background Technology

[0002] An optical module is an integrated component that packages together components such as lasers, detectors, and modulators. It can transmit and receive optical signals and is an important part of optical communication systems.

[0003] In optical communication systems, to ensure the reliability of optical signal transmission and reception, it is necessary to monitor analog quantities such as the received optical power, transmitted optical power, and bias current of the optical module. By monitoring the strength of the received optical signal, bit errors caused by excessive or insufficient optical power during optical communication, as well as damage to the optical module due to excessive optical power, can be effectively avoided.

[0004] The aforementioned monitoring functions are typically implemented by a Received Signal Strength Indication (RSSI) circuit.

[0005] Figure 1 The diagram shows a typical optical module. The photodiode in the diagram is a common detector, a semiconductor device that converts optical signals into electrical signals. In practical applications, the received optical power of the optical module is typically monitored by tracking the current in the photodiode.

[0006] Transimpedance amplifier chips are key components in the optical receiver front-end of optical communication. Their function is to amplify the weak current signal (AC signal) converted by the photodiode to a suitable voltage range. In practical applications, optical module manufacturers typically require the RSSI circuit to be integrated into the transimpedance amplifier chip. Summary of the Invention

[0007] To address the technical problems existing in the prior art, this application proposes an RSSI circuit, comprising: a first control loop including a first operational amplifier, the first input of which is configured to receive a first reference signal, and the second input of which is coupled to a first electrode of an external photosensitive element; in a first operating mode, the first operational amplifier is connected in a negative feedback manner and configured to clamp the first electrode of the external photosensitive element at the level of the first reference signal; in a second operating mode, the first operational amplifier is disconnected from other parts of the first control loop; a second control loop coupled to the first control loop and configured to replicate the current flowing through the external photosensitive element to obtain a first current; a control signal generation circuit coupled to the first and second control loops and configured to replicate the current flowing through the external photosensitive element to obtain a second current, compare it with the second reference signal, and control the operating mode of the first control loop based on the comparison result; and a first resistor coupled between the second control circuit and ground.

[0008] Specifically, the first control loop further includes: a first transistor, the source of which is connected to a power supply and the drain of which is coupled to the first electrode of an external photosensitive element; a first switch coupled between the gate and drain of the first transistor; and a second switch coupled between the output of the first operational amplifier and the gate of the first transistor.

[0009] Specifically, the second control circuit includes: a second operational amplifier whose positive input terminal is coupled to the first terminal of an external photosensitive element; a second transistor whose gate is coupled to the gate of a first transistor, whose source is connected to a power supply, and whose drain is coupled to the negative input terminal of the second operational amplifier; and a third transistor whose gate is coupled to the output terminal of the second operational amplifier, whose source is coupled to the drain of the second transistor, and whose drain is coupled to the ungrounded end of the first resistor.

[0010] Specifically, the control signal generation module includes: a fourth transistor, whose gate is coupled to the gate of the second transistor and whose source is connected to a power supply; a fifth transistor, whose gate is coupled to the gate of the third transistor and whose source is coupled to the drain of the fourth transistor; a comparator, whose positive input is configured to receive a second reference signal, whose negative input is coupled to the drain of the fifth transistor, and whose output is configured to output a control signal based on the comparison result; and a second resistor coupled between the drain of the fifth transistor and ground; wherein the control signal controls the opening / closing of the first switch, and the inversion of the control signal controls the opening / closing of the second switch.

[0011] Specifically, the second reference signal corresponds to the upper limit of the dark current of the external photosensitive element.

[0012] Specifically, it also includes a reference voltage unit configured to provide a first reference signal to the first control loop; the reference voltage unit includes: a current source, one end of which is grounded; a third resistor coupled between the power supply and the ungrounded end of the current source; wherein the negative input of the first operational amplifier is coupled to the node between the current source and the third resistor.

[0013] Specifically, when the voltage generated by the second current flowing through the second resistor is greater than or equal to the second reference signal, the inverted control signal output by the comparator is effective, the first switch is open, the second switch is closed, and the RSSI circuit operates in the first operating mode; when the voltage generated by the second current flowing through the second resistor is less than the second reference signal, the control signal output by the comparator is effective, the first switch is closed, the second switch is open, and the RSSI circuit operates in the second operating mode.

[0014] This application also proposes an electronic device comprising: any of the above-described RSSI circuits; a photosensitive element, the first electrode of which is coupled to the RSSI circuit; and a transimpedance amplifier, the input of which is coupled to the second electrode of an external photosensitive element. Attached Figure Description

[0015] The preferred embodiments of this application will now be described in further detail with reference to the accompanying drawings, wherein:

[0016] Figure 1 This is a structural diagram of a common optical module; and

[0017] Figure 2 This is a schematic diagram of a TIA chip and related circuitry integrating RSSI circuitry according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0020] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0021] A transistor can refer to a transistor of any structure, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When a transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polycrystalline silicon, organic transistors, etc. Based on whether the charge carrier is electrons or holes, they can be divided into N-type transistors and P-type transistors. The gate of a field-effect transistor is its control electrode, and the first electrode can be either the drain or source, while the corresponding second electrode can be either the source or drain. When a transistor is a bipolar junction transistor (BJT), its control electrode is its base, and the first electrode can be either the collector or emitter, while the corresponding second electrode can be either the emitter or collector. Transistors can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductors, organic semiconductors, NMOS / PMOS processes, or CMOS processes.

[0022] Existing RSSI circuits integrated into transimpedance amplifier chips typically include two control loops, each containing a transistor and an operational amplifier, with one transistor in each loop forming a current mirror. The basic operating principle of this type of RSSI circuit is as follows:

[0023] (1) A control loop uses loop control negative feedback to maintain the cathode bias voltage of the photodiode in the optical module where the RSSI circuit is located at a suitable potential, so that the cathode bias voltage of the photodiode is stable and not affected by the change of current flowing through the photodiode.

[0024] (2) The current flowing through the photodiode is replicated through the current mirror. At the same time, another control loop maintains the voltage at the output of the current mirror at a suitable potential, which is equal to the cathode bias voltage of the photodiode, so that the current mirror can accurately replicate the current.

[0025] (3) The replicated current flows to the resistor arranged outside the transimpedance amplifier chip. By monitoring the voltage on the external resistor, the optical power received by the optical module is finally monitored.

[0026] Because the photodiode in the optical module is a PIN photodiode, its dark current (i.e., the current in the photodiode when the optical module is not receiving light) is typically less than 100nA, with a common value of 10nA. However, when the optical module is working normally, the current flowing through the photodiode can reach 2mA or even greater. Furthermore, the stability of the control loop is still affected by the current flowing through the photodiode in practical applications, especially when the optical module is not receiving light. Compared to the photocurrent when the optical module is receiving light normally, the dark current in the photodiode is smaller, causing a larger impedance in the transistor coupled to the photodiode's cathode. This leads to loop oscillation in the control loop containing the transistor, resulting in a significant decrease in the accuracy of the RSSI circuit monitoring or even its failure to function properly.

[0027] Therefore, existing RSSI circuit structures have difficulty simultaneously ensuring the stability of the control loop and the accuracy of current replication within a current range of 10nA to 2mA.

[0028] Especially in practical applications, optical module manufacturers require that even when the optical module is not receiving light, for example when the average current of the photodiode is below 10uA, the RSSI circuit should be able to determine whether the optical module is damaged by monitoring the dark current of the photodiode, providing a basis for mass production of optical modules. Specifically, in the mass production of optical modules, when the dark current of the photodiode is detected to be greater than 100nA, it is considered that the photodiode is damaged and the optical module needs to replace the photodiode. Existing RSSI circuits cannot meet the requirements of this type of application.

[0029] To address the aforementioned problems of existing RSSI circuits and meet the needs of practical applications, this application proposes a new RSSI circuit that can simultaneously meet the requirements of RSSI circuit control loop stability and current replication accuracy over a wide current range.

[0030] Typically, in an optical communication link, the minimum useful optical signal received corresponds to an average photodiode current of approximately 10µA. When the average current flowing through the photodiode is greater than 10µA, the primary purpose of the RSSI circuit is to monitor the received optical power of the optical module by replicating and monitoring this average current. When the average current flowing through the photodiode is less than 10µA (i.e., the optical module is not receiving light, and there is dark current in the photodiode), the cathode bias voltage of the photodiode can tolerate larger voltage fluctuations compared to when the optical module is operating normally, while the circuit function remains unaffected. In this case, the RSSI circuit can maintain a stable cathode bias voltage of the photodiode even without a control loop, while also avoiding control loop oscillations caused by dark current in the photodiode.

[0031] Therefore, this application proposes an RSSI circuit that adopts different circuit connection methods to correspond to different circuit operating modes when the average current of the photodiode is greater than or less than the current corresponding to the minimum useful light signal (e.g., 10uA), so that the RSSI circuit can achieve accurate monitoring under normal illumination or dark current conditions.

[0032] Figure 2 This is a schematic diagram of a TIA chip and related circuitry integrating RSSI circuitry according to an embodiment of this application.

[0033] According to one embodiment, Figure 2 The TIA chip is shown, along with a photodiode PD and a resistor R1 arranged outside the TIA chip.

[0034] According to one embodiment, Figure 2 The TIA chip shown may include the RSSI circuit except for resistor R1, and the transimpedance amplifier TIA.

[0035] According to one embodiment, the anode of the PD is coupled to the input terminal IN of the TIA.

[0036] According to one embodiment, one end of resistor R1 is coupled to ground.

[0037] According to one embodiment, Figure 2 The RSSI circuit shown may include a reference voltage unit.

[0038] According to one embodiment, the reference voltage unit may include a series-connected current source I. S and resistor R0, where current source I S The other end of the resistor is coupled to ground, and the other end of the resistor R0 is coupled to the power supply.

[0039] According to one embodiment, Figure 2 The RSSI circuit shown may include control loop 1.

[0040] According to one embodiment, control loop 1 may include operational amplifier AMP1 and P-type transistor M1.

[0041] In one embodiment, the negative input terminal of AMP1 is coupled to point B of the reference voltage cell, where point B is the current source I. S The node between the resistor R0 and the positive input terminal of AMP1 is coupled to the drain of M1.

[0042] According to one embodiment, the source of M1 is coupled to a power supply; the drain of M1 is coupled to the cathode of a photodiode PD disposed outside the TIA chip.

[0043] According to one embodiment, control loop 1 may further include switches SW1 and SW2.

[0044] According to one embodiment, SW1 is coupled between the gate and drain of M1; SW2 is coupled between the output of AMP1 and the gate of M1.

[0045] According to one embodiment, Figure 2 The RSSI circuit shown may include control loop 2.

[0046] According to one embodiment, control loop 2 may include amplifier AMP2, P-type transistors M2 and M3.

[0047] According to one embodiment, the negative input terminal of AMP2 is coupled to point C of control loop 2, which is the node between the drain of M2 and the source of M3; the positive input terminal of AMP2 is coupled to point A of control loop 1, which is the node between the drain of M1 and the cathode of PD; and the output terminal of AMP2 is coupled to the gate of M3.

[0048] According to one embodiment, the source of M2 is coupled to a power supply; the gate of M2 is coupled to the gate of M1; and the drain of M2 is coupled to the source of M3.

[0049] According to one embodiment, the drain of M3 is coupled to the ungrounded end of resistor R1, which is located outside the TIA chip.

[0050] According to one embodiment, Figure 2 The RSSI circuit shown may include a control signal generation circuit.

[0051] According to one embodiment, the control signal generation circuit may include P-type transistors M4 and M5, a comparator CMP, and a resistor R2.

[0052] According to one embodiment, the gate of M4 is coupled to the gate of M2; the source of M4 is coupled to a power supply; and the drain of M4 is coupled to the source of M5.

[0053] According to one embodiment, the gate of M5 is coupled to the gate of M3; the drain of M5 is coupled to one end of R2.

[0054] According to one embodiment, the positive input terminal of the CMP is configured to receive a reference voltage VREF; the negative input terminal of the CMP is coupled to point E of the control signal generation circuit, which is the node between the drain of M5 and R2; the output terminal of the CMP is configured to output a control signal VCTL based on the comparison result of the signals received at its positive and negative input terminals.

[0055] According to one embodiment, the end of R2 that is not coupled to the drain of M5 is coupled to ground.

[0056] In one embodiment, transistors M1, M2, and M4 form a current mirror, replicating the current flowing through the PD into two currents, I1 and I2. Due to the channel length modulation effect of MOS transistors, the accuracy of the current mirror is significantly affected when the drain voltages of the transistors forming the current mirror are different. Therefore, operational amplifier AMP2 and transistor M3 in control loop 1 form a loop, and the voltage at point C of control loop 2 is made equal to the voltage at point A of control loop 1 through loop control, ensuring that the current I1 output from the drain of M2 is an accurate replication of the current flowing through the PD. At the same time, the gate of transistor M5 in the control signal generation circuit is coupled to the gate of M3 in control loop 2, and the channel width / length (W / L) of M5 and M3 are equal or proportional, ensuring that the voltage at point D of the control signal generation circuit is equal to the voltage at point C of control loop 2, ensuring that the current I2 output from the drain of M4 is an accurate replication of the current flowing through the PD.

[0057] According to one embodiment, the positive input of the CMP in the control signal generation circuit is configured to receive a pre-set reference voltage VREF, where VREF corresponds to the current IREF. IREF can be a fixed value, such as 1uA, that is slightly less than 10uA (typically, the average current generated when the smallest useful light signal illuminates the photodiode is about 10uA).

[0058] According to one embodiment, the negative input terminal of the CMP is configured to receive the voltage generated by the current I2 flowing through R2, i.e., the voltage V at point E. E and V E Compared with VREF, when V E When V is less than VREF, the output VTCL of CMP is high; when V... E When the value is greater than VREF, the output VTCL of CMP is low.

[0059] According to one embodiment, the opening / closing of SW1 is controlled by the output VTCL of CMP, and the opening / closing of SW2 is controlled by the inverted VTCL_BAR of the output VTCL of CMP.

[0060] According to one embodiment, when VTCL is high (i.e., the average current of PD is less than, for example, 1uA), SW1 is closed and SW2 is open. At this time, control loop 1 is disconnected (i.e., AMP1 is disconnected from other parts of control loop 1), and the cathode bias voltage of PD, i.e., V... A It equals the power supply VCC.

[0061] If control loop 1 is not disconnected at this time, the average current of the PD is its dark current, which makes the impedance looking upwards from point A relatively large. This will cause control loop 1 to oscillate and fail to stabilize the voltage at point A. Ultimately, this will lead to a significant decrease in the accuracy of the RSSI circuit monitoring or even failure to work properly. Disconnecting control loop 1 at this time avoids the stability problem caused by the PD in the dark current state. At the same time, the cathode bias voltage of the PD in the dark current state can tolerate larger voltage fluctuations than when the optical module is working normally, and the function of the circuit is not affected. Therefore, even if control loop 1 is disconnected in this case, the cathode of the PD is directly connected to the power supply through M1, and the voltage at point A is basically stable. Meanwhile, control loop 2 can still work normally.

[0062] Control loop 2 uses the loop control formed by AMP2 and M3 to control the voltage V at point C. C Equal to the cathode bias voltage of PD, i.e., the voltage at point A, V A As mentioned above, the voltage at point A is basically stable at this time, so the voltage at point C is also basically stable. The current mirror can still accurately replicate the average current flowing through the PD. The replicated current I1 flows through resistor R1, and by monitoring the voltage across resistor R1, the dark current of the PD at this time can be monitored.

[0063] According to one embodiment, when VTCL is low (i.e., the average current of the PD is greater than, for example, 1uA), SW1 is open and SW2 is closed. At this time, control loop 1 operates normally. Simultaneously, under these conditions, the average current of the PD varies from approximately 1uA to 2mA, which corresponds to the range of photocurrent variation of the PD after normal illumination. This is approximately three orders of magnitude smaller than the range of 10nA to 2mA, which includes the dark current variation. Within the range of photocurrent after normal illumination, the voltage at point A needs to be kept stable through loop control of control loop 1. At this time, AMP1 receives the voltage V generated by the reference voltage unit. B V is controlled through loop. A equals V B And it remains stable. Since the voltage fluctuation that the PD can tolerate under normal illumination is small, if the PD is directly connected to the power supply through M1 without control loop 1, the voltage at point A will be affected by the voltage generated by the photocurrent in the PD and will not be able to remain stable, ultimately leading to a significant decrease in the monitoring accuracy of the RSSI circuit.

[0064] At this time, control loop 2, through the loop control formed by AMP2 and M3, controls the voltage V at point C. C Equal to the voltage V at point A A The current mirror accurately replicates the average current flowing through the PD. The replicated current I1 flows through resistor R1, and the received optical power is ultimately monitored by monitoring the voltage across resistor R1.

[0065] This application also proposes an electronic device including the RSSI circuit, photodiode, and transimpedance amplifier as described above. The cathode of the photodiode is coupled to the RSSI circuit, and the anode is coupled to the input terminal of the transimpedance amplifier.

[0066] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. An RSSI circuit, comprising: A first control loop includes a first operational amplifier, whose first input is configured to receive a first reference signal, and whose second input is coupled to a first electrode of an external photosensitive element. In a first operating mode, the first operational amplifier is connected in a negative feedback manner and configured to clamp the first electrode of the external photosensitive element at the level of the first reference signal. In a second operating mode, the first operational amplifier is disconnected from other parts of the first control loop. A second control loop, coupled to the first control loop, is configured to replicate the current flowing through the external photosensitive element to obtain a first current; A control signal generation circuit, coupled to the first control loop and the second control loop, is configured to replicate the current flowing through the external photosensitive element to obtain a second current, and compare the voltage corresponding to the second current with a second reference signal. When the voltage corresponding to the second current is greater than or equal to the second reference signal, the first control loop operates in the first operating mode; when the voltage corresponding to the second current is less than the second reference signal, the first control loop operates in the second operating mode. as well as The first resistor is coupled between the second control loop and ground.

2. The RSSI circuit according to claim 1, wherein the first control loop further comprises: The first transistor has its source connected to the power supply and its drain coupled to the first electrode of the external photosensitive element; A first switch is coupled between the gate and drain of the first transistor; as well as The second switch is coupled between the output of the first operational amplifier and the gate of the first transistor.

3. The RSSI circuit according to claim 2, wherein the second control loop comprises: The second operational amplifier has its positive input terminal coupled to the first pole of the external photosensitive element; The second transistor has its gate coupled to the gate of the first transistor, its source connected to the power supply, and its drain coupled to the negative input terminal of the second operational amplifier. as well as The third transistor has its gate coupled to the output of the second operational amplifier, its source coupled to the drain of the second transistor, and its drain coupled to the ungrounded end of the first resistor.

4. The RSSI circuit according to claim 3, wherein the control signal generation circuit comprises: The fourth transistor has its gate coupled to the gate of the second transistor, and its source is connected to the power supply. The fifth transistor has its gate coupled to the gate of the third transistor and its source coupled to the drain of the fourth transistor; A comparator, whose positive input is configured to receive the second reference signal, whose negative input is coupled to the drain of the fifth transistor, and whose output is configured to output a control signal based on the comparison result; as well as The second resistor is coupled between the drain of the fifth transistor and ground; The control signal controls the opening / closing of the first switch, and the inversion of the control signal controls the opening / closing of the second switch.

5. The RSSI circuit according to claim 1, wherein the current corresponding to the second reference signal is the upper limit of the dark current of the external photosensitive element.

6. The RSSI circuit according to claim 4 further includes a reference voltage unit configured to provide the first reference signal to the first control loop; The reference voltage unit includes: A current source, one end of which is grounded; The third resistor is coupled between the power supply and the ungrounded end of the current source; The negative input terminal of the first operational amplifier is coupled to the node between the current source and the third resistor.

7. The RSSI circuit according to claim 6, wherein when the voltage generated by the second current flowing through the second resistor is greater than or equal to the second reference signal, the inversion of the control signal output by the comparator is effective, the first switch is open, the second switch is closed, and the RSSI circuit operates in the first operating mode; When the voltage generated by the second current flowing through the second resistor is less than the second reference signal, the control signal output by the comparator is valid, the first switch is closed, the second switch is opened, and the RSSI circuit operates in the second operating mode.

8. An electronic device, comprising: The RSSI circuit according to any one of claims 1-7; An external photosensitive element, the first electrode of which is coupled to the RSSI circuit; as well as A transimpedance amplifier, the input of which is coupled to the second pole of the external photosensitive element.

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