Display substrate and its driving method, display device

Abstract

A display substrate and its driving method and display device are disclosed. The display substrate includes multiple circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a compensation transistor (T2), a driving transistor (T3), a data writing transistor (T4), a first storage capacitor (10), and a second storage capacitor (20). The gate electrode of the data writing transistor (T4) is connected to a first scan signal line (21), the gate electrode of the compensation transistor (T2) is connected to a second scan signal line (22), the first end of the first storage capacitor (10) is connected to the gate electrode of the driving transistor (T3), the first end of the second storage capacitor (20) is connected to the first electrode of the driving transistor (T3), and the second ends of the first storage capacitor (10) and the second ends of the second storage capacitor (20) are connected to a first power supply line (53).

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including multiple circuit units constituting multiple unit rows and multiple unit columns. At least one circuit unit includes a pixel driving circuit. The pixel driving circuit includes at least a compensation transistor, a driving transistor, a data writing transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor. The pixel driving circuit is connected to a first scan signal line, a second scan signal line, a first power supply line, and a data signal line, respectively. The gate electrode of the driving transistor is connected to the second node, the first electrode of the driving transistor is connected to the first node, and the second electrode of the driving transistor is connected to the second electrode of the compensation transistor. The gate electrode of the data writing transistor is connected to the first scan signal line, the first electrode of the data writing transistor is connected to the data signal line, and the second electrode of the data writing transistor is connected to the first node. The gate electrode of the compensation transistor is connected to the second scan signal line, and the first electrode of the compensation transistor is connected to the second node. The first terminal of the first storage capacitor is connected to the second node, and the second terminal of the first storage capacitor is connected to the first power supply line. The first terminal of the second storage capacitor is connected to the first node, and the second terminal of the second storage capacitor is connected to the first power supply line.

[0005] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a substrate; a first end of the first storage capacitor includes a first electrode plate, and a second end of the first storage capacitor includes a second electrode plate, the first electrode plate being disposed in the first conductive layer, and the second electrode plate being disposed in the second conductive layer; a first end of the second storage capacitor includes at least a third electrode plate, and a second end of the second storage capacitor includes a fourth electrode plate, the third electrode plate being disposed in the semiconductor layer, and the fourth electrode plate being disposed in the second conductive layer.

[0006] In an exemplary embodiment, the first end of the second storage capacitor further includes a fifth electrode plate, which is disposed in the third conductive layer and connected to the fifth electrode plate.

[0007] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a substrate; a first end of the first storage capacitor includes a first electrode plate, and a second end of the first storage capacitor includes a second electrode plate, the first electrode plate being disposed in the first conductive layer, and the second electrode plate being disposed in the second conductive layer; a first end of the second storage capacitor includes at least a fifth electrode plate, and a second end of the second storage capacitor includes a fourth electrode plate, the fifth electrode plate being disposed in the third conductive layer, and the fourth electrode plate being disposed in the second conductive layer.

[0008] In an exemplary embodiment, the semiconductor layer further includes the active layer of the driving transistor, and the third electrode plate and the active layer of the driving transistor are an integral structure interconnected.

[0009] In an exemplary embodiment, the second electrode plate and the fourth electrode plate are an integral structure that is interconnected.

[0010] In an exemplary embodiment, the first node is disposed in the third conductive layer, and the first node and the fifth electrode plate are an integral structure connected to each other. The first node is connected to the third electrode plate through a via.

[0011] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a substrate; a first end of the first storage capacitor includes a first electrode plate, and a second end of the first storage capacitor includes a second electrode plate, the first electrode plate being disposed in the first conductive layer and the second electrode plate being disposed in the second conductive layer; a first end of the second storage capacitor includes a third electrode plate, and a second end of the second storage capacitor includes a fourth electrode plate, the third electrode plate being disposed in the first conductive layer and the fourth electrode plate being disposed in the second conductive layer.

[0012] In an exemplary embodiment, the second conductive layer further includes a first electrode connecting block, and the second electrode and the fourth electrode are interconnected through the first electrode connecting block.

[0013] In an exemplary embodiment, the third conductive layer further includes a second electrode connecting block and the first node, the first node being connected to the second electrode connecting block, and the second electrode connecting block being connected to the third electrode through a via.

[0014] In an exemplary embodiment, the distance between the first electrode plate and the third electrode plate is greater than or equal to 2 μm, and the distance is the dimension in the cell row direction.

[0015] In an exemplary embodiment, the capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor.

[0016] In an exemplary embodiment, the capacitance value of the second storage capacitor is 20% to 70% of the capacitance value of the first storage capacitor.

[0017] In an exemplary embodiment, the pixel driving circuit is also connected to a first initial signal line and a second initial signal line, the first initial signal line and the second initial signal line being line shapes extending along a first direction; the first initial signal line is connected to a first connecting line extending along a second direction to form a mesh structure for transmitting a first initial signal, and the second initial signal line is connected to a second connecting line extending along a second direction to form a mesh structure for transmitting a second initial signal, wherein the first direction and the second direction intersect.

[0018] In an exemplary embodiment, at least one cell row of circuit cells is provided with the first initial signal line and the second initial signal line; the odd-numbered cell columns of circuit cells are provided with the first connecting line, and the even-numbered cell columns of circuit cells are provided with the second connecting line, or the even-numbered cell columns of circuit cells are provided with the first connecting line, and the odd-numbered cell columns of circuit cells are provided with the second connecting line.

[0019] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate; the first initial signal line and the second initial signal line are disposed in the second conductive layer, and the first connecting line and the second connecting line are disposed in the fourth conductive layer.

[0020] In an exemplary embodiment, the third conductive layer in at least one circuit unit further includes a first initial electrode, the first connection line is connected to the first initial electrode through a via, and the first initial electrode is connected to the first initial signal line through a via.

[0021] In an exemplary embodiment, the third conductive layer in at least one circuit unit further includes a second initial electrode, the second connection line is connected to the second initial electrode through a via, and the second initial electrode is connected to the second initial signal line through a via.

[0022] In an exemplary embodiment, the display substrate further includes a fifth conductive layer disposed on the side of the fourth conductive layer away from the substrate, the data signal line being disposed in the fifth conductive layer, at least one data signal line having its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the first connecting line on the substrate, and at least one data signal line having its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the second connecting line on the substrate.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] In another aspect, this disclosure also provides a driving method for driving the aforementioned display substrate, comprising:

[0025] During the data writing period, the first scan signal line and the second scan signal line output a conduction signal, the compensation transistor and the data writing transistor are turned on, and the data voltage output by the data signal line is written into the first storage capacitor and the second storage capacitor;

[0026] During the threshold compensation period, the first scan signal line outputs a disconnect signal, the second scan signal line outputs a conduction signal, the compensation transistor is turned on, the data writing transistor is turned off, the data voltage stored in the second storage capacitor is written into the first storage capacitor, and threshold compensation is performed on the driving transistor.

[0027] In an exemplary embodiment, the duration of the threshold compensation period is greater than or equal to the duration of the data writing period.

[0028] In an exemplary embodiment, the time of the threshold compensation period is n times the time of the data writing period, where n is a positive integer greater than or equal to 1 and less than or equal to 9.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0031] Figure 1 This is a schematic diagram of the structure of a display device;

[0032] Figure 2 This is a schematic diagram of the structure of a display substrate;

[0033] Figure 3 This is a schematic diagram of the planar structure of a display area in a display substrate;

[0034] Figure 4 This is a schematic cross-sectional view of a display area in a display substrate.

[0035] Figure 5 An equivalent circuit diagram of a pixel driving circuit is provided as an exemplary embodiment of this disclosure.

[0036] Figure 6 This is a schematic diagram of the driving timing of a pixel driving circuit as an exemplary embodiment of the present disclosure;

[0037] Figure 7A This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0038] Figure 7B This is a schematic diagram of the structure of the initial signal lines of the mesh structure, as an exemplary embodiment of this disclosure.

[0039] Figure 8 This is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed.

[0040] Figure 9A and Figure 9B This is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0041] Figure 10A and Figure 10B This is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0042] Figure 11 This is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0043] Figure 12A and Figure 12B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0044] Figure 13 This is a schematic diagram of a display substrate after the formation of a fifth insulating layer pattern according to the present disclosure;

[0045] Figure 14A and 14B This is a schematic diagram of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure;

[0046] Figure 15 This is a schematic diagram of a display substrate after the formation of a first planarization layer pattern according to the present disclosure;

[0047] Figure 16A and 16B This is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed;

[0048] Figure 17 This is a schematic diagram of another planar structure of a display substrate, as an exemplary embodiment of the present disclosure;

[0049] Figure 18 This is a schematic diagram of another display substrate after a semiconductor layer pattern has been formed;

[0050] Figure 19 This is a schematic diagram of another display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0051] Figure 20 This is a schematic diagram of another display substrate after the formation of the second conductive layer pattern according to the present disclosure;

[0052] Figure 21 This is a schematic diagram of another display substrate after the fourth insulating layer pattern has been formed;

[0053] Figure 22 This is a schematic diagram of another display substrate after the formation of the third conductive layer pattern according to the present disclosure;

[0054] Figure 23 This is a schematic diagram of another display substrate after the fifth conductive layer pattern has been formed;

[0055] Figure 24 This is a graph showing the test results of the inter-row brightness difference when the present disclosure uses a one-to-two structure;

[0056] Figure 25 The figure shows the test results of threshold sensitivity for different threshold compensation periods in this disclosure.

[0057] Explanation of reference numerals in the attached figures:

[0058] 10 - First storage capacitor; 11 - First active layer; 12 - Second active layer;

[0059] 13-Third active layer; 14-Fourth active layer; 15-Fifth active layer;

[0060] 16-Sixth active layer; 17-Seventh active layer; 18-Third electrode plate;

[0061] 20 - Second storage capacitor; 21 - First scan signal line; 22 - Second scan signal line;

[0062] 23-Third scan signal line; 24-Emitting light control line; 25-First electrode plate;

[0063] 31-First initial signal line; 32-Second initial signal line; 33-Second electrode plate;

[0064] 34 - Fourth electrode plate; 35 - Electrode plate connecting wire; 36 - Opening;

[0065] 37 - Shielding electrode; 38 - First electrode plate connecting block; 41 - First connecting electrode;

[0066] 42 - Second connecting electrode; 43 - Third connecting electrode; 44 - Fourth connecting electrode;

[0067] 45 - Fifth connecting electrode; 46 - Sixth connecting electrode; 47 - Seventh connecting electrode;

[0068] 48 - Fifth electrode plate; 49 - Second electrode plate connecting block; 51 - Eleventh connecting electrode;

[0069] 52 - Twelfth connecting electrode; 53 - First power supply line; 61 - Data signal line;

[0070] 62 - Anode connection electrode; 71 - First initial electrode; 72 - Second initial electrode;

[0071] 81 - First connecting line; 82 - Second connecting line; 100 - Display area;

[0072] 101 - Substrate; 102 - Driving circuit layer; 103 - Light-emitting structure layer;

[0073] 104 - Encapsulation structure layer; 200 - Bonding area; 300 - Border area. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0075] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0076] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0077] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0078] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0079] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0080] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0081] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0082] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0083] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0084] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0085] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0086] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0087] Figure 2 This is a schematic diagram of the structure of a display substrate. (Example) Figure 2As shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display moving images or still images, and the display area 100 may be referred to as the effective area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0088] In an exemplary embodiment, the bonding region 200 may include a fan-out region, a bending region, a driver chip region, and a bonding pin region arranged sequentially along a direction away from the display area. The fan-out region is connected to the display area 100 and includes at least data fan-out lines, with multiple data fan-out lines configured to connect to the data signal lines of the display area in a fan-out routing manner. The bending region is connected to the fan-out region and may include a composite insulating layer with grooves, configured to bend the bonding region to the back side of the display area. The driver chip region may include an integrated circuit (IC) configured to connect to the multiple data fan-out lines. The bonding pin region may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0089] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region sequentially arranged along a direction away from the display region 100. The circuit region, connected to the display region 100, may include at least a plurality of cascaded gate driving circuits connected to multiple scan lines of the pixel driving circuits in the display region 100. The power line region, connected to the circuit region, may include at least bezel power leads extending parallel to the edge of the display region and connected to the cathode in the display region 100. The crack dam region, connected to the power line region, may include at least a plurality of cracks formed on the composite insulating layer. The cutting region, connected to the crack dam region, may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting grooves respectively.

[0090] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the binding area or the border area of ​​the display area.

[0091] Figure 3 This is a schematic diagram of a planar structure of a display area in a display substrate. For example... Figure 3 As shown, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. Each sub-pixel may include a light-emitting unit, which may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of its respective sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0092] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0093] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0094] Figure 4 This is a schematic cross-sectional view of a display area in a display substrate, illustrating the structure of three sub-pixels within the display area. Figure 4 As shown, on a plane perpendicular to the display substrate, the display area may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0095] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit, and the pixel driving circuit can include multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include at least a light-emitting device. The light-emitting device can include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0096] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers that are connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.

[0097] With the rapid and widespread application of displays, consumers have increasingly higher demands for display quality, especially high refresh rates and even ultra-high refresh rates, which are gradually being required by various industries. A major challenge with high refresh rates (high frame rates) is insufficient charging time. For example, when the refresh rate is increased to 144Hz / 165Hz, the shortened data writing time per line within a frame leads to difficulties in data writing and insufficient compensation, resulting in issues such as high black-state voltage and decreased threshold sensitivity.

[0098] This disclosure provides an exemplary embodiment of a display substrate. In a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. In a plane parallel to the display substrate, the driving circuit layer of the display area may include multiple circuit units constituting multiple unit rows and multiple unit columns, and the light-emitting structure layer of the display area may include multiple light-emitting units constituting multiple pixel rows and multiple pixel columns. At least one circuit unit includes a pixel driving circuit, and at least one light-emitting unit may include a light-emitting device connected to a corresponding pixel driving circuit. The light-emitting device is configured to emit light of a corresponding brightness in response to a current output by the connected pixel driving circuit.

[0099] In exemplary embodiments, the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device, and the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0100] An exemplary embodiment of this disclosure provides a display substrate including multiple circuit units constituting multiple cell rows and multiple cell columns. At least one circuit unit includes a pixel driving circuit. The pixel driving circuit includes at least a compensation transistor, a driving transistor, a data writing transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor. The pixel driving circuit is connected to a first scan signal line, a second scan signal line, a first power supply line, and a data signal line, respectively. The gate electrode of the driving transistor is connected to the second node, the first electrode of the driving transistor is connected to the first node, and the second electrode of the driving transistor is connected to the second electrode of the compensation transistor. The gate electrode of the data writing transistor is connected to the first scan signal line, the first electrode of the data writing transistor is connected to the data signal line, and the second electrode of the data writing transistor is connected to the first node. The gate electrode of the compensation transistor is connected to the second scan signal line, and the first electrode of the compensation transistor is connected to the second node. The first terminal of the first storage capacitor is connected to the second node, and the second terminal of the first storage capacitor is connected to the first power supply line. The first terminal of the second storage capacitor is connected to the first node, and the second terminal of the second storage capacitor is connected to the first power supply line.

[0101] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a substrate; the first end of the first storage capacitor includes a first electrode plate, the second end of the first storage capacitor includes a second electrode plate, the first electrode plate is disposed in the first conductive layer, and the second electrode plate is disposed in the second conductive layer.

[0102] In one exemplary embodiment, the first end of the second storage capacitor includes a third electrode plate, the second end of the second storage capacitor includes a fourth electrode plate, the third electrode plate is disposed in the semiconductor layer, and the fourth electrode plate is disposed in the second conductive layer.

[0103] In another exemplary embodiment, the first end of the second storage capacitor includes a fifth electrode plate, the second end of the second storage capacitor includes a fourth electrode plate, the fourth electrode plate is disposed in the second conductive layer, and the fifth electrode plate is disposed in the third conductive layer.

[0104] In another exemplary embodiment, the first end of the second storage capacitor includes a third electrode and a fifth electrode, the second end of the second storage capacitor includes a fourth electrode, the third electrode is disposed in the semiconductor layer, the fourth electrode is disposed in the second conductive layer, the fifth electrode is disposed in the third conductive layer, and the third electrode and the fifth electrode are connected.

[0105] In another exemplary embodiment, the first end of the second storage capacitor includes a third electrode plate, and the second end of the second storage capacitor includes a fourth electrode plate, wherein the third electrode plate is disposed in the first conductive layer, and the fourth electrode plate is disposed in the second conductive layer.

[0106] In an exemplary embodiment, the pixel driving circuit is also connected to a first initial signal line and a second initial signal line, the first initial signal line and the second initial signal line being line shapes extending along a first direction; the first initial signal line is connected to a first connecting line extending along a second direction to form a mesh structure for transmitting a first initial signal, and the second initial signal line is connected to a second connecting line extending along a second direction to form a mesh structure for transmitting a second initial signal, wherein the first direction and the second direction intersect.

[0107] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0108] Figure 5 This is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 5 As shown, the pixel driving circuit of the exemplary embodiment of this disclosure may include 7 transistors (first transistor T1 to seventh transistor T7) and 2 storage capacitors (first storage capacitor C1 and second storage capacitor C2). The pixel driving circuit is connected to 8 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, data signal line D and first power supply line VDD).

[0109] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, the second terminal of the fifth transistor T5, and the second terminal of the second storage capacitor C2. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the second terminal of the first storage capacitor C1. The third node N3 is connected to the second terminals of the second transistor T2, the second terminals of the third transistor T3, and the first terminal of the sixth transistor T6. The fourth node N4 is connected to the second terminals of the sixth transistor T6 and the second terminal of the seventh transistor T7.

[0110] In an exemplary embodiment, the first end of the first storage capacitor C1 is connected to the second node N2, the second end of the first storage capacitor C1 is connected to the first power line VDD, the first end of the second storage capacitor C2 is connected to the first node N1, the second end of the second storage capacitor C2 is connected to the first power line VDD, and the signal of the first power line VDD is a continuously provided high-level signal.

[0111] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first terminal of the first transistor T1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor is connected to the second node N2. When a conduction level scan signal is applied to the third scan signal line S3, the first transistor T1 transmits the first initial voltage to the gate electrode of the third transistor T3 to initialize the charge on the gate electrode of the third transistor T3.

[0112] In an exemplary embodiment, the gate electrode of the second transistor T2 (compensation transistor) is connected to the second scan signal line S2, the first terminal of the second transistor T2 is connected to the second node N2, and the second terminal of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the second scan signal line S2, the second transistor T2 connects the gate electrode of the third transistor T3 to its second terminal.

[0113] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the second terminal of the first storage capacitor C1, the first terminal of the third transistor T3 is connected to the first node N1, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as the driving transistor, and the magnitude of the driving current is determined by the potential difference between its gate electrode and its first terminal.

[0114] In an exemplary embodiment, the gate electrode of the fourth transistor T4 (data write transistor) is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When a pass-through scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0115] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0116] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0117] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS, wherein the signal of the second power line VSS is a continuously provided low-level signal.

[0118] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0119] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polysilicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS thin-film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0120] Figure 6 This is a schematic diagram illustrating the driving timing of a pixel driving circuit according to an exemplary embodiment of this disclosure. Figure 6 As shown. Figure 5 Taking the pixel driving circuit shown, where the first transistor T1 to the seventh transistor T7 are all P-type transistors, as an example, the operation of the pixel driving circuit can include:

[0121] The first time period A1 is called the reset period. The signal on the third scan signal line S3 is low, while the signals on the first scan signal line S1, the second scan signal line S2, and the light-emitting signal line E are high. The low-level signal on the third scan signal line S3 turns on the first transistor T1, and the first initial voltage on the first initial signal line INIT1 is provided to the second node N2 to initialize the first storage capacitor C1, clearing the original data voltage in the first storage capacitor. Since the second terminal of the first storage capacitor C1 is low, the third transistor T3 turns on. The high-level signals on the first scan signal line S1, the second scan signal line S2, and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0122] The second time period, A2, is called the data writing period. The signals on the first scan signal line S1 and the second scan signal line S2 are low-level signals, while the signals on the third scan signal line S3 and the light-emitting signal line E are high-level signals. The data signal line D outputs a data voltage. The low-level signal on the first scan signal line S1 turns on the fourth transistor T4 and the seventh transistor T7, and the low-level signal on the second scan signal line S2 turns on the second transistor T2. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output from the data signal line D to flow through the first node N1 to charge the second terminal of the second storage capacitor C2, and through the first node N1, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, and the second node N2 to supply the second terminal of the first storage capacitor C1. The turn-on of the seventh transistor T7 causes the second initial voltage of the second initial signal line INIT2 to be supplied to the fourth node N4 (the first electrode of the OLED), initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, and completing the initialization. The signals of the third scan signal line S3 and the light emission signal line E are high-level signals, causing the first transistor T1, the fifth transistor T5, and the sixth transistor T6 to turn off. In an exemplary embodiment, the data writing period can be referred to as the single-line data writing time (1h), and the refresh rate of the display substrate refers to the frequency at which the first scan signal line S1 provides the conduction signal.

[0123] The third time period, A3, is called the threshold compensation period. The signal of the second scan signal line S2 remains low, while the signals of the first scan signal line S1, the third scan signal line S3, and the light-emitting signal line E are high. The low-level signal of the second scan signal line S2 keeps the second transistor T2 conducting. The voltage charged into the second storage capacitor C2 during the second time period is supplied to the second terminal of the first storage capacitor C1 via the first node N1, the conducting third transistor T3, the third node N3, the conducting second transistor T2, and the second node N2. This allows the data voltage to be continuously written into the first storage capacitor C1 and compensate for the third transistor T3, charging the first storage capacitor C1 with the difference between the data voltage and the threshold voltage of the third transistor T3. The voltage at the second terminal (second node N2) of the first storage capacitor C1 is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. In an exemplary embodiment, the duration of the threshold compensation period can be greater than or equal to the duration of the data writing period.

[0124] The fourth time period, A4, is called the light-emitting period. The signal on the light-emitting signal line E is a low-level signal, while the signals on the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0125] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0126] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0127] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0128] In an exemplary implementation, the threshold compensation period can be approximately n times the data writing period, where n can be a positive integer greater than or equal to 1 and less than or equal to 9.

[0129] Table 1 shows the test results of the threshold compensation period time and data voltage range. It represents the data voltage range of R / G / B pixels corresponding to different threshold compensation periods. The data voltages in parentheses are the data voltages corresponding to grayscale 255 and grayscale 0, respectively. As shown in Table 1, at a 165Hz high-frequency display, as the threshold compensation period time increases, not only does the black state voltage decrease, ensuring data writing at high frequencies, but the data voltage range also increases, ensuring clearer definition of different grayscale levels and improving the screen's image quality at high frequencies.

[0130] Table 1: Test results of the time and data voltage range during the threshold compensation period.

[0131]

[0132] In a pixel driving circuit scheme using a 7T1C transistor, since the second transistor T2 and the fourth transistor T4 are controlled by the same scan signal line, the data writing and threshold compensation time consists of only a single-line data writing time. When the refresh rate is high, the sub-pixels cannot display a lower grayscale image. The pixel driving circuit provided in the exemplary embodiment of this disclosure uses the fourth transistor T4 controlled by the first scan signal line S1 and the second transistor T2 controlled by the second scan signal line S2. The second scan signal line S2 outputs a conduction signal for a longer time than the first scan signal line S1 outputs a conduction signal. Furthermore, a second storage capacitor C2 is provided between the first and second terminals of the fifth transistor T5. This separates the data writing period and the threshold compensation period, which not only extends the data writing time but also ensures sufficient compensation time. In the pixel driving circuit of this disclosure, the first scan signal line S1 corresponding to the fourth transistor T4 controls normal data writing within a single-line data writing time, and the second scan signal line S2 corresponding to the second transistor T2 controls data writing and threshold compensation within multiple single-line data writing times, thus extending the data writing time. The newly added second storage capacitor C2 not only allows the data voltage to be stored in the second storage capacitor C2 during the data writing period, making the data writing period insensitive to source loading, but also ensures that data writing continues during the period when the fourth transistor T4 is off and the second transistor T2 is on, achieving low grayscale image quality. Compared with the existing 7T1C pixel driving circuit scheme, this disclosure effectively improves the problems of insufficient charging time and insufficient compensation time in the existing scheme by adjusting the writing and compensation methods, ensuring clearer definition of different grayscale images, ensuring high-frequency display image quality, and improving display effect and display quality.

[0133] Figure 7A This is a schematic diagram of a planar structure of a display substrate, illustrating the structure of pixel driving circuits in two circuit units within the display area, as an exemplary embodiment of this disclosure. Figure 7A As shown, the pixel driving circuit of at least one circuit unit may include at least a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a third connection electrode 43 as a first node, a first connection electrode 41 as a second node, a first storage capacitor 10 and a second storage capacitor 20. The pixel driving circuit is connected to a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emission control line 24, a first initial signal line 31, a second initial signal line 32, a first power supply line 53 and a data signal line 61, respectively.

[0134] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light emission control line 24, the first initial signal line 31, and the second initial signal line 32 can be lines extending along a first direction X, and the shapes of the first power line 53 and the data signal line 61 can be lines extending along a second direction Y, with the first direction X intersecting the second direction Y. The first scan signal line 21 and the second scan signal line 22 are configured to provide a first scan signal and a second scan signal to the pixel driving circuit, the data signal line 51 is configured to provide a data signal to the pixel driving circuit, the first power line 52 is configured to provide a first power signal to the pixel driving circuit, and the first initial signal line 31 and the second initial signal line 32 are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively. The first initial signal can be configured to initialize (reset) the first storage capacitor, and the second initial signal can be configured to initialize (reset) the light-emitting device.

[0135] In this disclosure, A extending along the direction of B means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along the direction of B, and the length of the main part extending along the direction of B is greater than the length of the secondary part extending in other directions.

[0136] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the second scan signal line 22, the first electrode of the second transistor T2 is connected to the first connection electrode 41 (second node), and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3. The gate electrode of the third transistor T3 is connected to the first connection electrode 41 (second node), and the first electrode of the third transistor T3 is connected to the third connection electrode 43 (first node). The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 61, and the second electrode of the fourth transistor T4 is connected to the third connection electrode 43 (first node). The first terminal of the first storage capacitor 10 is connected to the first connection electrode 41 (second node), and the second terminal of the first storage capacitor 10 is connected to the first power supply line 53. The first terminal of the second storage capacitor 20 is connected to the third connection electrode 43 (first node), and the second terminal of the second storage capacitor 20 is connected to the first power supply line 53.

[0137] In an exemplary embodiment, the first end of the first storage capacitor 10 may include a first electrode plate, and the second end of the first storage capacitor 10 may include a second electrode plate. The first electrode plate may be disposed in a first conductive layer, and the second electrode plate may be disposed in a second conductive layer. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate.

[0138] In an exemplary embodiment, the first end of the second storage capacitor 20 may include a third electrode plate and a fifth electrode plate, and the second end of the second storage capacitor 20 may include a fourth electrode plate. The third electrode plate may be disposed in a semiconductor layer, the fourth electrode plate may be disposed in a second conductive layer, and the fifth electrode plate may be disposed in a third conductive layer. The orthographic projection of the fourth electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate, and the orthographic projection of the fifth electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate. The third electrode plate and the fifth electrode plate are connected.

[0139] In an exemplary embodiment, the capacitance value of the second storage capacitor 20 may be less than the capacitance value of the first storage capacitor 10.

[0140] In an exemplary embodiment, the capacitance value of the second storage capacitor 20 can be approximately 20% to 70% of the capacitance value of the first storage capacitor 10. For example, the capacitance value of the second storage capacitor 20 can be approximately 30% to 50% of the capacitance value of the first storage capacitor 10.

[0141] In an exemplary embodiment, the semiconductor layer may include at least the active layer of the third transistor T3, and the third electrode and the active layer of the third transistor T3 may be an integral structure interconnected with each other.

[0142] In an exemplary embodiment, the second electrode plate and the fourth electrode plate can be an integral structure that is interconnected.

[0143] In an exemplary embodiment, the third connecting electrode 43 (first node) may be disposed in the third conductive layer. The third connecting electrode 43 and the fifth electrode plate are an integral structure that are interconnected. The third connecting electrode 43 is connected to the third electrode plate through a via.

[0144] Figure 7B This is a schematic diagram of the initial signal lines of the mesh structure, as described in an exemplary embodiment of this disclosure. Figure 7B As shown, the first initial signal line 31 is connected to the first connecting line 81 extending along the second direction Y, and the second initial signal line 32 is connected to the second connecting line 82 extending along the second direction Y. A mesh structure for transmitting the first initial signal and a mesh structure for transmitting the second initial signal are simultaneously formed on the display substrate.

[0145] In one exemplary embodiment, at least one cell row has a first initial signal line 31 and a second initial signal line 32 in its circuit cells, an odd-numbered cell column (the N+1th column) has a first connecting line 81 in its circuit cells, and an even-numbered cell column (the Nth column) has a second connecting line 82 in its circuit cells. The multiple first connecting lines 81 of the odd-numbered cell columns are connected to the first initial signal lines 31 of the multiple cell rows, and the multiple second connecting lines 82 of the even-numbered cell columns are connected to the second initial signal lines 32 of the multiple cell rows.

[0146] In another exemplary embodiment, at least one unit row of circuit units is provided with a first initial signal line 31 and a second initial signal line 32, even-numbered unit columns (Nth column) of circuit units are provided with a first connecting line 81, odd-numbered unit columns (N+1th column) of circuit units are provided with a second connecting line 82, multiple first connecting lines 81 of even-numbered unit columns are connected to the first initial signal lines 31 of multiple unit rows, and multiple second connecting lines 82 of odd-numbered unit columns are connected to the second initial signal lines 32 of multiple unit rows.

[0147] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. The active layers of the second transistor T2, the third transistor T3, and the fourth transistor T4 may be disposed in the semiconductor layer. The first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission control line 24 may be disposed in the first conductive layer. The first initial signal line 31 and the second initial signal line 32 may be disposed in the second conductive layer. The first connecting electrode 41 and the third connecting electrode 43 may be disposed in the third conductive layer. The first power line 53, the first connecting line 81, and the second connecting line 84 may be disposed in the fourth conductive layer.

[0148] In an exemplary embodiment, the third conductive layer in at least one circuit unit may further include a first initial electrode 71, the first connection line 81 in the fourth conductive layer is connected to the first initial electrode 71 in the third conductive layer through a via, and the first initial electrode 71 in the third conductive layer is connected to the first initial signal line 31 in the second conductive layer through a via.

[0149] In an exemplary embodiment, the third conductive layer in at least one circuit unit may further include a second initial electrode 72, the second connection line 82 in the fourth conductive layer is connected to the second initial electrode 72 in the third conductive layer through a via, and the second initial electrode 72 in the third conductive layer is connected to the second initial signal line 32 in the second conductive layer through a via.

[0150] In an exemplary embodiment, the orthographic projection of the data signal line 61 on the substrate at least partially overlaps with the orthographic projection of the first connecting line 81 on the substrate, and the orthographic projection of the data signal line 61 on the substrate at least partially overlaps with the orthographic projection of the second connecting line 82 on the substrate.

[0151] In an exemplary embodiment, the display substrate may further include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a first planarization layer. The first insulating layer is disposed between the substrate and the semiconductor layer, the second insulating layer is disposed between the semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the third conductive layer, the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer, and the first planarization layer is disposed between the fourth conductive layer and the fifth conductive layer.

[0152] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0153] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0154] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 8 As shown.

[0155] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the third active layer 13 of the third transistor T3, the fourth active layer 14 of the fourth transistor T4, the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, the seventh active layer 17 of the seventh transistor T7, and the third electrode plate 18 of the second storage capacitor. The first active layer 11 to the third active layer 13, the fifth active layer 15 to the seventh active layer 17 and the third electrode plate 18 may be an integral structure interconnected with each other, and the fourth active layer 14 may be set separately.

[0156] In an exemplary embodiment, in order to avoid the third electrode plate 18 provided with the semiconductor layer, the fourth active layer 14 is separately provided on one side of the third electrode plate 18 in the second direction Y.

[0157] In an exemplary embodiment, the first active layer 11 and the second active layer 12 may be located on the side opposite to the second direction Y of the third active layer 13 of the circuit unit, and the fourth active layer 14, the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be located on the side of the second direction Y of the third active layer 13 of the circuit unit.

[0158] In an exemplary embodiment, the first active layer 11 can be shaped like an "n", the second active layer 12 and the fifth active layer 15 can be shaped like an "L", the third active layer 13 can be shaped like an "Ω", and the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 can be shaped like an "I".

[0159] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the second region 14-2 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer can be configured individually. The second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer, the first region 13-1 of the third active layer can serve as the second region 15-2 of the fifth active layer, the second region 13-2 of the third active layer can simultaneously serve as the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer.

[0160] In an exemplary embodiment, the third electrode 18 of the second storage capacitor can be rectangular, with chamfered corners. The third electrode 18 can be located on one side of the third active layer 13 in the first direction X of this circuit unit, and is an integral structure interconnected with the first region 13-1 of the third active layer and the second region 15-2 of the fifth active layer. In an exemplary embodiment, the third electrode 18 can serve as one electrode of the second storage capacitor.

[0161] In an exemplary embodiment, the first region 13-1 of the third active layer can serve as the first electrode of the third transistor T3, and the second region 15-2 of the fifth active layer can serve as the second electrode of the fifth transistor T5. The first electrodes of the third transistor T3, the second electrodes of the fifth transistor T5, and the third electrode plate 18 are interconnected, with the connection point being the first node N1 of the pixel driving circuit. The second region 12-2 of the second active layer can serve as the second electrode of the second transistor T2, and the second region 13-2 of the third active layer can serve as the second electrode of the third transistor T3. The first region 16-1 of the sixth active layer can serve as the first electrode of the sixth transistor T6. The second electrodes of the second transistor T2, the second electrodes of the third transistor T3, and the first electrodes of the sixth transistor T6 are interconnected, with the connection point being the third node N3 of the pixel driving circuit. The second region 16-2 of the sixth active layer can serve as the second electrode of the sixth transistor T6, and the second region 17-2 of the seventh active layer can serve as the second electrode of the seventh transistor T7. The second electrodes of the sixth transistor T6 and the second electrodes of the seventh transistor T7 are interconnected, with the connection point being the fourth node N4 of the pixel driving circuit.

[0162] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0163] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emission control line 24, and a first electrode 25 of a first storage capacitor.

[0164] In an exemplary embodiment, the first electrode 25 of the first storage capacitor can be rectangular in shape, with chamfered corners. The orthographic projection of the first electrode 25 onto the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 onto the substrate. In an exemplary embodiment, the first electrode 25 can simultaneously serve as both an electrode of the first storage capacitor and the gate electrode of the third transistor T3.

[0165] In an exemplary embodiment, the area of ​​the third electrode plate 18 projected onto the substrate may be smaller than the area of ​​the first electrode plate 25 projected onto the substrate.

[0166] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission control line 24 can be line shapes extending along the first direction X of the main body portion. The first scan signal line 21 and the light emission control line 24 can be located on one side of the first electrode plate 25 of this circuit unit in the second direction Y, and the second scan signal line 22 and the third scan signal line 23 can be located on the opposite side of the first electrode plate 25 of this circuit unit in the second direction Y. The first scan signal line 21 can be located on the side of the light emission control line 24 of this circuit unit away from the first electrode plate 25, and the third scan signal line 23 can be located on the side of the second scan signal line 22 of this circuit unit away from the first electrode plate 25.

[0167] In an exemplary embodiment, the region where the first scan signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, the region where the first scan signal line 21 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, the region where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 with a dual-gate structure, the region where the light emission control line 24 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the region where the light emission control line 24 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0168] In an exemplary embodiment, the second scan signal line 22 may be provided with a gate block 22-1 that protrudes toward the third scan signal line 23. The area where the second scan signal line 22 and the gate block 22-1 overlap with the second active layer may serve as the gate electrode of the second transistor T2, forming a second transistor T2 with a dual-gate structure.

[0169] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission control line 24 can extend along the first direction X to the frame area on one or both sides of the display area, connect with the corresponding gate driving circuit, and output the corresponding conduction control signal according to the set driving timing.

[0170] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A A schematic diagram of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0171] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a first initial signal line 31, a second initial signal line 32, a second electrode 33 of a first storage capacitor, a fourth electrode 34 of a second storage capacitor, an electrode connection line 35, and a shielding electrode 37.

[0172] In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 can be line shapes in which the main body portion can extend along the first direction X. The first initial signal line 31 can be located between the second scan signal line 22 and the third scan signal line 23 of this circuit unit, and the second initial signal line 32 can be located on the side of the first scan signal line 21 of this circuit unit away from the light emission control line 24.

[0173] In an exemplary embodiment, the outline shape of the second electrode plate 33 can be rectangular, and the corners of the rectangle can be chamfered. It is located between the second scan signal line 22 and the light emission control line 24 of this circuit unit. The orthographic projection of the second electrode plate 33 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 25 on the substrate. The second electrode plate 33 can serve as another electrode plate of the first storage capacitor. The first electrode plate 25 and the second electrode plate 33 constitute the first storage capacitor of the pixel driving circuit.

[0174] In an exemplary embodiment, the outline shape of the fourth electrode plate 34 can be rectangular, and the corners of the rectangle can be chamfered. It is located between the second scan signal line 22 and the light emission control line 24 of this circuit unit. The orthographic projection of the fourth electrode plate 34 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 18 on the substrate. The fourth electrode plate 34 can serve as another electrode plate of the second storage capacitor. The third electrode plate 18 and the fourth electrode plate 34 constitute a second storage capacitor of the pixel driving circuit.

[0175] In an exemplary embodiment, the area of ​​the fourth electrode plate 34 projected onto the substrate may be smaller than the area of ​​the first electrode plate 25 projected onto the substrate, and the area of ​​the fourth electrode plate 34 projected onto the substrate may be smaller than the area of ​​the second electrode plate 33 projected onto the substrate.

[0176] In an exemplary embodiment, the second electrode plate 33 and the fourth electrode plate 34 can be an integral structure that is interconnected, and the overall outline shape of the integral structure of the second electrode plate 33 and the fourth electrode plate 34 can be rectangular.

[0177] In an exemplary embodiment, the electrode connecting line 35 can be disposed on one side of the fourth electrode 34 in the first direction X or on the side opposite to the first direction X of the second electrode 33. The first end of the electrode connecting line 35 is connected to the fourth electrode 34 of this circuit unit, and the second end of the electrode connecting line 35 extends along the first direction X and connects to the second electrode 33 of an adjacent circuit unit. Alternatively, the first end of the electrode connecting line 35 is connected to the second electrode 33 of this circuit unit, and the second end of the electrode connecting line 35 extends along the opposite direction X and connects to the fourth electrode 34 of an adjacent circuit unit. This interconnects the second electrode 33 and the fourth electrode 34 of adjacent circuit units in a unit row. In an exemplary embodiment, the second and fourth plates of multiple circuit units in a unit row can be interconnected into an integrated structure through the plate connection line. The integrated second and fourth plates can be reused as power signal connection lines, ensuring that the multiple second and fourth plates in a unit row have the same potential. This helps to improve the uniformity of the panel, avoid display defects in the display substrate, and ensure the display effect of the display substrate.

[0178] In an exemplary embodiment, the second electrode plate 33 has an opening 36, which may be located in the middle of the second electrode plate 33. The opening 36 may be rectangular, forming an annular structure with the second electrode plate 33. The opening 36 exposes a third insulating layer covering the first electrode plate 25, and the orthographic projection of the first electrode plate 25 onto the substrate includes the orthographic projection of the opening 36 onto the substrate. In an exemplary embodiment, the opening 36 is configured to accommodate a subsequently formed first via, which is located within the opening 36 and exposes the first electrode plate 25, allowing a subsequently formed first connection electrode to be connected to the first electrode plate 25.

[0179] In an exemplary embodiment, the shielding electrode 37 may be located on the side of the first initial signal line 31 close to the second scan signal line 22 and connected to the first initial signal line 31. The orthographic projection of the shielding electrode 37 on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 on the substrate. The shielding electrode 37 is configured to shield the influence of data voltage jumps on the second transistor T2, avoid the data voltage jumps from affecting the normal operation of the pixel driving circuit, and improve the display effect.

[0180] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 11 As shown.

[0181] In an exemplary embodiment, the plurality of vias of each circuit unit in the display area include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a twelfth via V12.

[0182] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the opening 36 of the second electrode plate 33 onto the substrate. The fourth and third insulating layers within the first via V1 are etched away, exposing the surface of the first electrode plate 25. The first via V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 25 through the via.

[0183] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second electrode plate 33 onto the substrate. The fourth insulating layer within the second via V2 is etched away, exposing the surface of the second electrode plate 33. The second via V2 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the second electrode plate 33 through the via.

[0184] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fifth active layer. The third via V3 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the first region of the fifth active layer through the via.

[0185] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the sixth active layer. The fourth via V4 is configured to allow the second electrode of the subsequently formed sixth transistor T6 (which is also the second electrode of the seventh transistor T7) to be connected to the sixth active layer through the via.

[0186] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the fourth active layer. The fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the first region of the fourth active layer through the via.

[0187] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the seventh active layer. The sixth via V6 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the first region of the seventh active layer through the via.

[0188] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is located within the orthographic projection of the first region of the third active layer (which is also the second region of the fifth active layer) onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the third active layer. The seventh via V7 is configured to allow the first electrode of the subsequently formed third transistor T3 (which is also the second electrode of the fifth transistor T5) to be connected to the first region of the third active layer through the via.

[0189] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the second region of the fourth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the eighth via V8 are etched away, exposing the surface of the second region of the fourth active layer. The eighth via V8 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the second region of the fourth active layer through the via.

[0190] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate. The fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the first active layer. The ninth via V9 is configured to allow the second electrode of the subsequently formed first transistor T1 (which is also the first electrode of the second transistor T2) to be connected to the first active layer through the via.

[0191] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via V10 are etched away, exposing the surface of the first region of the first active layer. The tenth via V10 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first region of the first active layer through the via.

[0192] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the first initial signal line 31 onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the first initial signal line 31. The eleventh via V11 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first initial signal line 31 through the via.

[0193] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the second initial signal line 32 on the substrate. The fourth insulating layer inside the twelfth via V12 is etched away, exposing the surface of the second initial signal line 32. The twelfth via V12 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the second initial signal line 32 through the via.

[0194] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 12A and Figure 12B As shown, Figure 12B for Figure 12A A schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0195] In an exemplary embodiment, the third conductive layer pattern of multiple circuit units in the display area may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, and a fifth electrode plate 48.

[0196] In an exemplary embodiment, the first connecting electrode 41 can be a strip shape in which the main body extends along the second direction Y. The first end of the first connecting electrode 41 is connected to the first electrode plate 25 through the first via V1, and the second end of the first connecting electrode 41 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the ninth via V9. In an exemplary embodiment, the first connecting electrode 41 can serve as the second node N2 in the pixel driving circuit of this disclosure. The first connecting electrode 41 can also serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, so that the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode plate 25 (the gate electrode of the third transistor T3) have the same potential.

[0197] In an exemplary embodiment, the second connecting electrode 42 can be a strip shape in which the main body extends along the second direction Y. The first end of the second connecting electrode 42 is connected to the second electrode plate 33 through the second via V2, and the second end of the second connecting electrode 42 is connected to the first region of the fifth active layer through the third via V3. In an exemplary embodiment, the second connecting electrode 42 can serve as the first electrode of the fifth transistor T5, so that the second electrode plate 33, the fourth electrode plate 34, and the first electrode of the fifth transistor T5 have the same potential. The second connecting electrode 42 is configured to be connected to the subsequently formed first power line. Since the second electrode plate 33 has the potential of the first power line, and the first electrode plate 25 has the potential of the second node N2, the first electrode plate 25 and the second electrode plate 33 constitute the first storage capacitor of the pixel driving circuit.

[0198] In an exemplary embodiment, the third connecting electrode 43 can be a strip shape extending along the second direction Y of the main body. The first end of the third connecting electrode 43 is connected to the first region of the third active layer through the seventh via V7, and the second end of the third connecting electrode 43 is connected to the second region of the fourth active layer through the eighth via V8. In an exemplary embodiment, the third connecting electrode 43 can serve as the first node N1 of the pixel driving circuit of this disclosure. The third connecting electrode 43 can simultaneously serve as the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, so that the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 have the same potential.

[0199] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape, and the fourth connection electrode 44 is connected to the first region of the fourth active layer through the fifth via V5. The fourth connection electrode 44 may serve as the first electrode of the fourth transistor T4, and the fourth connection electrode 44 is configured to be connected to the subsequently formed eleventh connection electrode.

[0200] In an exemplary embodiment, the fifth connection electrode 45 may be rectangular in shape, and is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fourth via V4. The fifth connection electrode 45 may serve as the second electrode of the sixth transistor T6 (which is also the second electrode of the seventh transistor T7), and is configured to connect to the subsequently formed twelfth connection electrode.

[0201] In an exemplary embodiment, the sixth connection electrode 46 can be a strip shape extending along the second direction Y of the main body. The first end of the sixth connection electrode 46 is connected to the first region of the first active layer through the tenth via V10, and the second end of the sixth connection electrode 46 is connected to the first initial signal line 31 through the eleventh via V11. The sixth connection electrode 46 can serve as the first electrode of the first transistor T1, thus enabling the first initial signal line 31 to write the first initial signal into the first electrode of the first transistor T1.

[0202] In an exemplary embodiment, the seventh connection electrode 47 can be a strip shape extending along the second direction Y of the main body. The first end of the seventh connection electrode 47 is connected to the first region of the seventh active layer through the sixth via V6, and the second end of the seventh connection electrode 47 is connected to the second initial signal line 32 through the twelfth via V12. The seventh connection electrode 47 can serve as the first electrode of the seventh transistor T7, thus enabling the second initial signal line 32 to write the second initial signal to the first electrode of the seventh transistor T7.

[0203] In an exemplary embodiment, the fifth electrode plate 48 may be rectangular in shape, with chamfered corners. It may be located on the side opposite to the second direction Y of the third connection electrode 43 of this circuit unit (the side away from the fourth transistor T4). The orthographic projection of the fifth electrode plate 48 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 34 on the substrate. The fifth electrode plate 48 may serve as another electrode plate of the second storage capacitor. The fourth electrode plate 34 and the fifth electrode plate 48 constitute another second storage capacitor of the pixel driving circuit.

[0204] In an exemplary embodiment, the area of ​​the fifth electrode plate 48 projected onto the substrate may be smaller than the area of ​​the first electrode plate 25 projected onto the substrate.

[0205] In an exemplary embodiment, the third connecting electrode 43 and the fifth electrode plate 48 can be an integral structure interconnected. Since the third electrode plate 18 is directly connected to the second region of the fifth active layer, and the fifth electrode plate 48 is connected to the third connecting electrode 43, and the third connecting electrode 43 is connected to the first region of the fifth active layer through a via, the third electrode plate 18 and the fifth electrode plate 48 have the same potential. The fourth electrode plate 34 has the potential of the first power supply. The third electrode plate 18 and the fourth electrode plate 34 constitute one second storage capacitor of the pixel driving circuit, and the fifth electrode plate 48 and the fourth electrode plate 34 constitute another second storage capacitor of the pixel driving circuit. The two second storage capacitors are connected in parallel to form the complete second storage capacitor of the pixel driving circuit. This disclosure, by employing a parallel structure for the second storage capacitor, not only effectively utilizes the wiring space but also effectively increases the capacitance value of the second storage capacitor, allowing for more sufficient data voltage writing and ensuring data writing quality.

[0206] In an exemplary embodiment, the capacitance value of the second storage capacitor may be less than the capacitance value of the first storage capacitor.

[0207] In an exemplary embodiment, the capacitance value of the second storage capacitor can be approximately 20% to 70% of the capacitance value of the first storage capacitor. For example, the capacitance value of the second storage capacitor 20 can be approximately 30% to 50% of the capacitance value of the first storage capacitor 10.

[0208] In some possible exemplary embodiments, the second storage capacitor may include only the third plate 18 and the fourth plate 34, or the second storage capacitor may include only the fifth plate 48 and the fourth plate 34, which is not limited herein.

[0209] In an exemplary embodiment, the third conductive layer pattern of at least one circuit unit may further include a first initial electrode 71 and a second initial electrode 72.

[0210] In an exemplary embodiment, the first initial electrode 71 may be a strip shape with its main body extending along the first direction X, and may be disposed on one side of the sixth connecting electrode 46 along the first direction X. A first end of the first initial electrode 71 is connected to the sixth connecting electrode 46, and a second end of the first initial electrode 71 extends along the first direction X to an adjacent circuit cell. The first initial electrode 71 is configured to connect to a subsequently formed first connecting line, such that the first initial signal line and the first connecting line form a mesh-like interconnected structure. For example, the first end of the first initial electrode 71 is connected to the sixth connecting electrode 46 in the Nth column of circuit cells, and the second end of the first initial electrode 71 is located in the (N+1)th column of circuit cells and is configured to connect to a subsequently formed first connecting line in the (N+1)th column of circuit cells.

[0211] In an exemplary embodiment, the second initial electrode 72 can be block-shaped, disposed on the opposite side of the seventh connecting electrode 47 in the first direction X, and connected to the seventh connecting electrode 47. The second initial electrode 72 is configured to connect to the subsequently formed second connecting line, such that the second initial signal line and the second connecting line form a mesh-like interconnected structure. For example, the second initial electrode 72 can be located in the Nth column of circuit units, connected to the sixth connecting electrode 46 in the Nth column of circuit units, and configured to connect to the second connecting line subsequently formed in the Nth column of circuit units.

[0212] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 13 As shown.

[0213] In an exemplary embodiment, the plurality of vias of each circuit unit in the display area includes at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0214] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second connection electrode 42 on the substrate. The fifth insulating layer inside the 21st via V21 is removed, exposing the surface of the second connection electrode 42. The 21st via V21 is configured to allow a subsequently formed first power line to be connected to the second connection electrode 42 through the via.

[0215] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the fourth connecting electrode 44 onto the substrate. The fifth insulating layer within the 22nd via V22 is removed, exposing the surface of the fourth connecting electrode 44. The 22nd via V22 is configured to allow the subsequently formed 11th connecting electrode to be connected to the fourth connecting electrode 44 through the via.

[0216] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the fifth connecting electrode 45 on the substrate. The fifth insulating layer within the 23rd via V23 is removed, exposing the surface of the fifth connecting electrode 45. The 23rd via V23 is configured to allow the subsequently formed 12th connecting electrode to be connected to the fifth connecting electrode 45 through the via.

[0217] In an exemplary embodiment, the fifth insulating layer of at least one circuit unit is further provided with a twenty-fourth via V24, and the fifth insulating layer of at least another circuit unit is further provided with a twenty-fifth via V25.

[0218] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate lies within the orthographic projection of the first initial electrode 71 onto the substrate. The fifth insulating layer within the 24th via V24 is removed, exposing the surface of the first initial electrode 71. The 24th via V24 is configured to allow subsequently formed first connecting lines to connect to the first initial electrode 71 through this via. For example, the 24th via V24 may be located in a circuit cell in the (N+1)th column, allowing first connecting lines in the (N+1)th column of circuit cells to connect to the first initial electrode 71 in multiple cell rows through multiple 24th via V24s.

[0219] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate lies within the range of the orthographic projection of the second initial electrode 72 onto the substrate. The fifth insulating layer within the 25th via V25 is removed, exposing the surface of the second initial electrode 72. The 25th via V25 is configured to allow subsequently formed second connection lines to connect to the second initial electrode 72 through this via. For example, the 25th via V25 may be located in a circuit cell in the Nth column, allowing second connection lines located in the Nth column circuit cell to connect to the second initial electrode 72 in multiple cell rows through multiple 25th via V25s.

[0220] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, such as... Figure 14A and 14B As shown, Figure 14B for Figure 14A A schematic diagram of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0221] In an exemplary embodiment, the fourth conductive layer pattern of the plurality of circuit units in the display area may include: an eleventh connecting electrode 51, a twelfth connecting electrode 52, and a first power line 53.

[0222] In an exemplary embodiment, the eleventh connecting electrode 51 may be rectangular in shape. The eleventh connecting electrode 51 is connected to the fourth connecting electrode 44 through the twenty-second via V22. The eleventh connecting electrode 51 is configured to connect to a subsequently formed data signal line.

[0223] In an exemplary embodiment, the twelfth connecting electrode 52 may be rectangular in shape. The twelfth connecting electrode 52 is connected to the fifth connecting electrode 45 through the twenty-third through-hole V23. The twelfth connecting electrode 52 is configured to be connected to the subsequently formed anode connecting electrode.

[0224] In an exemplary embodiment, the first power line 53 can be shaped as a broken line extending along the second direction Y. The first power line 53 is connected to the second connection electrode 42 through the twenty-first via V21. Since the second connection electrode 42 is connected to the second electrode plate and the first region of the fifth active layer through the via, the first power line 53 writes the power signal to the first electrode of the fifth transistor T5, and the first power line 53, the second electrode plate of the first storage capacitor, and the fourth electrode plate of the second storage capacitor have the same potential.

[0225] In an exemplary embodiment, the orthographic projection of the first power line 53 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate. The first power line 53 can effectively shield the influence of other signals in the pixel driving circuit on the second node N2, avoid the data voltage jump affecting the potential of the second node N2 of the pixel driving circuit, and improve the display effect.

[0226] In an exemplary embodiment, since there is only a thin fifth insulating layer between the third conductive layer and the fourth conductive layer, the parasitic capacitance between the first connecting electrode 41 and the first power line 53 is large, which can better stabilize the second node N2.

[0227] In an exemplary embodiment, the first power line 53 can be designed with non-uniform width. The non-uniform width design of the first power line 53 can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power line and the data signal line.

[0228] In an exemplary embodiment, the fourth conductive layer pattern of at least one circuit unit may further include a first connection line 81.

[0229] In an exemplary embodiment, the first connecting line 81 can be located in the (N+1)th column of circuit cells. The shape of the first connecting line 81 can be a line shape extending along the second direction Y of the main body. The first connecting line 81 is connected to the first initial electrode 71 through the twenty-fourth via V24. Since the first initial electrode 71 is connected to the sixth connecting electrode 46, and the sixth connecting electrode 46 is connected to the first initial signal line 31 through a via, the first initial signal line 31 extending along the first direction X of the main body and the first connecting line 81 extending along the second direction Y of the main body are interconnected. In this way, the first connecting line 81 can be connected to the first initial signal line 31 in multiple cell rows through the first initial electrode 71 and the sixth connecting electrode 46, so that the first initial signal line 31 and the first connecting line 81 form a mesh structure for transmitting the first initial signal in the display area. This can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0230] In an exemplary embodiment, the fourth conductive layer pattern of at least one circuit unit may further include a second connecting line 82.

[0231] In an exemplary embodiment, the second connecting line 82 can be located in the Nth column of circuit units. The shape of the second connecting line 82 can be a line shape extending along the second direction Y of the main body. The second connecting line 82 is connected to the second initial electrode 72 through the twenty-fifth via V25. Since the second initial electrode 72 is connected to the seventh connecting electrode 47, and the seventh connecting electrode 47 is connected to the second initial signal line 32 through the via, the interconnection of the second initial signal line 32 extending along the first direction X of the main body and the second connecting line 82 extending along the second direction Y of the main body is realized. In this way, the second connecting line 82 can be connected to the second initial signal line 32 in multiple unit rows through the second initial electrode 72 and the seventh connecting electrode 47, so that the second initial signal line 32 and the second connecting line 82 form a mesh structure for transmitting the second initial signal in the display area. This can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0232] In an exemplary embodiment, the first connecting line 81 may be disposed in the circuit unit of the odd-numbered unit column (the N+1th column), and the second connecting line 82 may be disposed in the circuit unit of the even-numbered unit column (the Nth column). Alternatively, the first connecting line 81 may be disposed in the circuit unit of the even-numbered unit column (the Nth column), and the second connecting line 82 may be disposed in the circuit unit of the odd-numbered unit column (the N+1th column).

[0233] In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 of the second conductive layer can be disposed in each cell row, and the first connecting line 81 and the second connecting line 82 of the fourth conductive layer are alternately disposed in each cell column. Multiple first connecting lines 81 in multiple odd-numbered cell columns are respectively connected to multiple first initial signal lines 31 in multiple cell rows, and multiple second connecting lines 82 in multiple even-numbered cell columns are respectively connected to multiple second initial signal lines 32 in multiple cell rows. Thus, a mesh structure for transmitting the first initial signal and a mesh structure for transmitting the second initial signal are simultaneously formed in the display area, reducing the voltage drop of the first initial signal and the second initial signal. The second node N2 can be reset in a shorter time, which is beneficial for high-frequency display. The fourth node N4 has a shorter reset time, which is beneficial for improving the low grayscale display effect.

[0234] (18) Forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, patterning the first planarization film using a patterning process to form a first planarization layer covering a fourth conductive layer, wherein a plurality of vias are provided on the first planarization layer, such as... Figure 15 As shown.

[0235] In an exemplary embodiment, the plurality of vias of each circuit unit in the display area includes at least: a thirty-first via V31 and a thirty-second via V32.

[0236] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the 11th connecting electrode 51 on the substrate. The first planarization layer within the 31st via V31 is removed, exposing the surface of the 11th connecting electrode 51. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the 11th connecting electrode 51 through the via.

[0237] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the 12th connecting electrode 52 on the substrate. The first planarization layer within the 32nd via V32 is removed, exposing the surface of the 12th connecting electrode 52. The 32nd via V32 is configured to allow a subsequently formed anode connecting electrode to be connected to the 32nd via V32 through the via.

[0238] (19) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on a first planarization layer, such as... Figure 16A and 16B As shown, Figure 16B for Figure 16A A schematic diagram of the fifth conductive layer. In an exemplary embodiment, the fifth conductive layer may be referred to as the third source / drain metal (SD3) layer.

[0239] In an exemplary embodiment, the fifth conductive layer pattern of each circuit unit in the display area may include: a data signal line 61 and an anode connection electrode 62.

[0240] In an exemplary embodiment, the data signal line 61 can be a straight line extending along the second direction Y, with the main body portion extending along the second direction Y. The data signal line 61 is connected to the eleventh connecting electrode 51 through the thirty-first via V31. Since the eleventh connecting electrode 51 is connected to the fourth connecting electrode 44 through the via, and the fourth connecting electrode 44 is connected to the first region of the fourth active layer through the via, the data signal line 61 writes the data signal to the first electrode of the fourth transistor T4. By placing the data signal line in the fifth conductive layer and the first connecting line and the second connecting line in the fourth conductive layer, this disclosure avoids signal interference caused by the data signal line and the initial signal line being placed in the same conductive layer. Since there is a relatively thick first planarization layer between the fifth conductive layer and the fourth conductive layer, the parasitic capacitance between the data signal line and the signal lines and electrodes in other film layers can be reduced. This not only improves the quality of data writing but also reduces the impact of data switching voltage on key nodes of the pixel driving circuit.

[0241] In an exemplary embodiment, the orthographic projection of at least one data signal line 61 on the substrate at least partially overlaps with the orthographic projection of the first connecting line 81 on the substrate, and the orthographic projection of at least one data signal line 61 on the substrate at least partially overlaps with the orthographic projection of the second connecting line 82 on the substrate.

[0242] In an exemplary embodiment, the orthographic projection of at least one data signal line 61 on the substrate may be within the range of the orthographic projection of the first connecting line 81 on the substrate, and the orthographic projection of at least one data signal line 61 on the substrate may be within the range of the orthographic projection of the second connecting line 82 on the substrate. That is, the data signal lines of the fifth conductive layer completely overlap with the initial signal connecting lines of the fourth conductive layer to increase the transmittance of the display substrate.

[0243] In an exemplary embodiment, the anode connection electrode 62 can be rectangular in shape, and it is connected to the twelfth connection electrode 52 via a thirty-second via V32. Since the twelfth connection electrode 52 is connected to the fifth connection electrode 45 via a via, and the fifth connection electrode 45 is connected to the second region of the sixth active layer via a via, the anode connection electrode 62 is connected to the second electrode of the sixth transistor T6. In this exemplary embodiment, the anode connection electrode 62 is configured to connect to a subsequently formed anode, thus enabling the pixel driving circuit to drive the light-emitting device.

[0244] Subsequent fabrication processes may include: forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: coating a second planarization film on a substrate with the aforementioned pattern, patterning the second planarization film using a patterning process to form a second planarization layer covering a fifth conductive layer, wherein a plurality of anode vias are provided on the second planarization layer, the orthogonal projection of the anode vias onto the substrate may be located within the range of the orthogonal projection of the anode connection electrode onto the substrate, the second planarization layer within the anode vias is removed to expose the surface of the anode connection electrode, and the anode vias are configured to allow the subsequently formed anode to be connected to the anode connection electrode through the vias.

[0245] At this point, the driving circuit layer is fabricated on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a light emission control line, a data signal line, a first power supply line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may at least include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, and a second planarization layer, sequentially stacked on the substrate.

[0246] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0247] In an exemplary embodiment, the first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, and fifth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, the second and third insulating layers are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The first and second planarization layers can be made of organic materials, such as resin. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0248] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be elaborated here.

[0249] As can be seen from the structure and fabrication process of the display substrate described above, the embodiments of this disclosure use the fourth transistor T4 controlled by the first scan signal line 21 and the second transistor T2 controlled by the second scan signal line 22. A second storage capacitor is set in the pixel driving circuit, which separates the data writing period and the threshold compensation period. This not only extends the data writing time but also ensures sufficient compensation time, effectively improving the problems of insufficient charging time and insufficient compensation time in existing solutions. It can ensure clearer definition of different grayscale images, guarantee the image quality of high-frequency displays, and improve the display effect and display quality.

[0250] This disclosure provides a first initial signal line and a second initial signal line extending along a first direction in a second conductive layer, and a first connecting line and a second connecting line extending along a second direction in a fourth conductive layer. The first connecting line is connected to the first initial signal line, and the second connecting line is connected to the second initial signal line. This creates a mesh structure between the first initial signal line transmitting the first initial signal and the second initial signal line transmitting the second initial signal. This not only effectively reduces the resistance of the first and second initial signal lines and decreases the voltage drop of the first and second initial voltages, but also effectively improves the uniformity of the first and second initial voltages in the display substrate, thus improving display uniformity, display quality, and display performance. Furthermore, the second node N2 can reset in a shorter time, which is beneficial for high-frequency displays, and the fourth node N4 has a shorter reset time, which is beneficial for improving low grayscale display effects. This disclosure also utilizes the first and second conductive layers to form a first storage capacitor, and utilizes the semiconductor layer, the second conductive layer, and the third conductive layer to form two second storage capacitors in parallel. This effectively increases the capacitance of the second storage capacitors, allowing for more complete data voltage writing and ensuring data writing quality. The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0251] Figure 17 This is a schematic diagram of another planar structure of a display substrate, illustrating the structure of pixel driving circuits in two circuit units within the display area, as an exemplary embodiment of this disclosure. Figure 17 As shown, the structure of the pixel driving circuit in this exemplary embodiment is basically the same as that in the previous embodiment. The difference is that the second storage capacitor 20 in this embodiment is composed of a first conductive layer and a second conductive layer.

[0252] In an exemplary embodiment, the first end of the first storage capacitor 10 may include a first electrode plate, and the second end of the first storage capacitor 10 may include a second electrode plate. The first electrode plate may be disposed in a first conductive layer, and the second electrode plate may be disposed in a second conductive layer. The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate.

[0253] In an exemplary embodiment, the first end of the second storage capacitor 20 may include a third electrode plate, and the second end of the second storage capacitor 20 may include a fourth electrode plate. The third electrode plate may be disposed in the first conductive layer, and the fourth electrode plate may be disposed in the second conductive layer. The orthographic projection of the fourth electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate at least partially overlap.

[0254] In an exemplary embodiment, the capacitance value of the second storage capacitor 20 may be less than the capacitance value of the first storage capacitor 10.

[0255] In an exemplary embodiment, the capacitance value of the second storage capacitor 20 can be approximately 20% to 70% of the capacitance value of the first storage capacitor 10. For example, the capacitance value of the second storage capacitor 20 can be approximately 30% to 50% of the capacitance value of the first storage capacitor 10.

[0256] In an exemplary embodiment, the second conductive layer may further include a first electrode connecting block 38, through which the second electrode and the fourth electrode can be connected to each other.

[0257] In an exemplary embodiment, the third conductive layer may further include a third connecting electrode 43 (first node) and a second electrode plate connecting block 49, wherein the third connecting electrode 43 is connected to the second electrode plate connecting block 49, and the second electrode plate connecting block 49 is connected to the third electrode plate through a via.

[0258] In an exemplary embodiment, the substrate fabrication process of this embodiment may include the following operations.

[0259] (21) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 18 As shown.

[0260] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the third active layer 13 of the third transistor T3, the fourth active layer 14 of the fourth transistor T4, the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, and the seventh active layer 17 of the seventh transistor T7.

[0261] In an exemplary embodiment, the structure and connection relationship of the first active layer 11 to the seventh active layer 17 are basically the same as those of the aforementioned embodiment. The difference is that, since the semiconductor layer does not form a third electrode plate, the first region 13-1 of the third active layer and the second region 15-2 of the fifth active layer are not connected to the third electrode plate.

[0262] (22) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 19 As shown.

[0263] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emission control line 24, a first electrode 25 of a first storage capacitor, and a third electrode 18 of a second storage capacitor.

[0264] In an exemplary embodiment, the structure and connection relationship of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light emission control line 24, and the first electrode plate 25 of the first storage capacitor are substantially the same as those in the foregoing embodiments.

[0265] In an exemplary embodiment, the third plate 18 of the second storage capacitor can be rectangular in shape, with chamfered corners, and can be located on one side of the first plate 25 in the first direction X. The third plate 18 can serve as one plate of the second storage capacitor.

[0266] In an exemplary embodiment, the distance L between the first electrode plate 25 and the third electrode plate 18 can be greater than or equal to 2 μm, and the distance L can be the dimension in the first direction X (cell row direction). For example, the distance L can be approximately 2.5 μm.

[0267] In an exemplary embodiment, the area of ​​the third electrode plate 18 projected onto the substrate may be smaller than the area of ​​the first electrode plate 25 projected onto the substrate.

[0268] In an exemplary embodiment, the dimension of the first electrode plate 25 in the second direction Y is larger than that of the first electrode plate 25 in the second direction Y in the aforementioned embodiment, so as to leave a larger margin for the second storage capacitor while ensuring the capacitance value of the first storage capacitor.

[0269] (23) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 20 As shown.

[0270] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a first initial signal line 31, a second initial signal line 32, a second electrode 33 of a first storage capacitor, a fourth electrode 34 of a second storage capacitor, an electrode connecting line 35, a shielding electrode 37, and a first electrode connecting block 38.

[0271] In an exemplary embodiment, the structure and connection relationship of the first initial signal line 31, the second initial signal line 32, the second electrode 33, the fourth electrode 34, the electrode connecting line 35, and the shielding electrode 37 are basically the same as those in the previous embodiment. The difference is that the second electrode 33 of the first storage capacitor and the fourth electrode 34 of the second storage capacitor are connected to each other through the first electrode connecting block 38, so that the second electrode 33, the fourth electrode 34, and the first electrode connecting block 38 in the circuit unit are an integral structure that is interconnected.

[0272] In an exemplary embodiment, the area of ​​the fourth electrode plate 34 projected onto the substrate may be smaller than the area of ​​the first electrode plate 25 projected onto the substrate, and the area of ​​the fourth electrode plate 34 projected onto the substrate may be smaller than the area of ​​the second electrode plate 33 projected onto the substrate.

[0273] In an exemplary embodiment, the capacitance value of the second storage capacitor may be less than the capacitance value of the first storage capacitor.

[0274] In an exemplary embodiment, the capacitance value of the second storage capacitor can be approximately 20% to 70% of the capacitance value of the first storage capacitor. For example, the capacitance value of the second storage capacitor 20 can be approximately 30% to 50% of the capacitance value of the first storage capacitor 10.

[0275] (24) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 21 As shown.

[0276] In an exemplary embodiment, the plurality of vias of each circuit unit in the display area include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0277] In an exemplary embodiment, the structure and connection relationship of the first via V1 to the twelfth via V12 are substantially the same as those in the aforementioned embodiments. The orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the third electrode plate 18 onto the substrate. The fourth and third insulating layers within the thirteenth via V13 are etched away, exposing the surface of the third electrode plate 18. The thirteenth via V13 is configured to allow the subsequently formed second electrode plate connector block to be connected to the third electrode plate 18 through this via.

[0278] (25) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 22 As shown.

[0279] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display area may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, and a second electrode plate connecting block 49.

[0280] In an exemplary embodiment, the structure and connection relationship of the first connecting electrode 41 to the seventh connecting electrode 47 are basically the same as those of the aforementioned embodiment, except that the third connecting electrode 43 is connected to the second electrode plate connecting block 49.

[0281] In an exemplary embodiment, the second electrode connecting block 49 may be rectangular in shape and may be located on one side of the third connecting electrode 43 in the first direction X (the side away from the first storage capacitor). The orthographic projection of the second electrode connecting block 49 on the substrate at least partially overlaps with the orthographic projection of the third electrode 18 on the substrate. The first end of the second electrode connecting block 49 is connected to the third connecting electrode 43. After the second end of the second electrode connecting block 49 extends along the first direction X, it is connected to the third electrode 18 through the thirteenth via V13.

[0282] In an exemplary embodiment, the third connecting electrode 43 and the second electrode plate connecting block 49 can be an integral structure that is interconnected. Since the third connecting electrode 43 serves as the first node N1 in the pixel driving circuit, the third electrode plate 18, which is connected to the third connecting electrode 43 via the second electrode plate connecting block 49, has the potential of the first node N1. The third electrode plate 18 and the fourth electrode plate 34 constitute the second storage capacitor of the pixel driving circuit.

[0283] In an exemplary embodiment, the third conductive layer pattern of at least one circuit unit may further include a first initial electrode 71 and a second initial electrode 72, the structure and connection relationship of the first initial electrode 71 and the second initial electrode 72 being substantially the same as the structure and connection relationship of the foregoing embodiments.

[0284] (26) The pattern of the fifth insulating layer, the fourth conductive layer, the first planarization layer, the fifth conductive layer, and the second planarization layer is formed sequentially, as follows: Figure 23 As shown. In the exemplary embodiment, the preparation process and related structures are basically the same as those in the foregoing embodiments, and will not be described again here.

[0285] The display substrate provided in this exemplary embodiment, on the one hand, separates the data writing period and the threshold compensation period, extending the data writing time and compensation time, effectively improving the problems of insufficient charging time and insufficient compensation time in existing solutions. On the other hand, it realizes the simultaneous formation of a mesh structure for transmitting the first initial signal and the second initial signal, reducing voltage drop and improving display uniformity. Furthermore, it utilizes the first conductive layer and the second conductive layer to simultaneously form the first storage capacitor and the second storage capacitor, occupying a small space, which is beneficial to increasing the capacitance value of the second storage capacitor and improving the stability of the potential of the first node N1. This disclosure uses two metal layers to form the second storage capacitor, which is beneficial to the flatness of the third conductive layer, the fourth conductive layer, and the fifth conductive layer, and avoids the impact of process fluctuations on the capacitance value of the storage capacitor.

[0286] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0287] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0288] In an exemplary embodiment, the border area of ​​the display substrate may be provided with at least a plurality of cascaded gate driver on array (GOA) circuits, each gate driver circuit being connected to a first scan signal line, a second scan signal line, a third scan signal line and a light emission signal line in each cell row.

[0289] In an exemplary embodiment, at least one gate driving circuit may include at least a first gate circuit group, a second gate circuit group, and a third gate circuit group. The first gate circuit group may be connected to the first scan signal line and the third scan signal line, respectively; the second gate circuit group may be connected to the second scan signal line; and the third gate circuit group may be connected to the light-emitting signal line. That is, the first scan signal line and the third scan signal line are driven by one set of gate circuits, and the second scan signal line is driven by another set of gate circuits.

[0290] In an exemplary embodiment, the first gate circuit group, the second gate circuit group, and the third gate circuit group may be driven simultaneously on both sides, or they may be driven on one side to meet the narrow bezel requirement. This disclosure does not limit the scope of the invention.

[0291] In an exemplary embodiment, the second gate circuit group can adopt a one-to-two structure, that is, one second gate circuit group can be connected to the second scan signal line of two cell rows to control the conduction or disconnection of multiple second transistors T2 in the two cell rows, so as to reduce the number of gate drive circuits and wiring in the frame area, which is beneficial to achieving a narrow frame.

[0292] Figure 24 This is a graph showing the test results of the inter-row brightness difference when using a one-to-two structure in this disclosure. Figure 24 As shown, the second gate circuit group adopts a one-to-two structure. At grayscale levels of 32 and 500 nits, when the threshold compensation period is greater than or equal to four times the data writing period (n=4), the inter-line brightness difference is greater than 95%. This disclosure solves the problem of inter-line brightness difference in the existing one-to-two structure by increasing the threshold compensation period.

[0293] Figure 25 This is a graph showing the test results of threshold sensitivity for different threshold compensation periods in this disclosure. Figure 25 As shown, when the threshold compensation period is equal to the data writing period (n=1), the threshold sensitivity (VthSensitivity) is relatively large. When the threshold compensation period is 3 times (n=3) and 7 times (n=7) the data writing period, the threshold sensitivity is significantly reduced, which can improve the compensation effect.

[0294] In an exemplary embodiment, when the threshold compensation period is approximately nine times the data writing period, the inter-line brightness difference and threshold sensitivity change are relatively small. Considering factors such as refresh rate, this disclosure sets the threshold compensation period to n times the data writing period, where n is a positive integer greater than or equal to 1 and less than or equal to 9. For example, the threshold compensation period is 3 times, 5 times, or 7 times the data writing period.

[0295] This disclosure also provides a driving method for a display substrate to drive the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns. At least one circuit unit includes a pixel driving circuit. The pixel driving circuit includes at least a compensation transistor, a driving transistor, a data writing transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor. The pixel driving circuit is connected to a first scan signal line, a second scan signal line, a first power supply line, and a data signal line, respectively. The gate electrode of the driving transistor is connected to the second node, the first electrode of the driving transistor is connected to the first node, and the second electrode of the driving transistor is connected to the second electrode of the compensation transistor. The gate electrode of the data writing transistor is connected to the first scan signal line, the first electrode of the data writing transistor is connected to the data signal line, and the second electrode of the data writing transistor is connected to the first node. The gate electrode of the compensation transistor is connected to the second scan signal line, and the first electrode of the compensation transistor is connected to the second node. The first terminal of the first storage capacitor is connected to the second node, and the second terminal of the first storage capacitor is connected to the first power supply line. The first terminal of the second storage capacitor is connected to the first node, and the second terminal of the second storage capacitor is connected to the first power supply line. The driving method may include:

[0296] During the data writing period, the first scan signal line and the second scan signal line output a conduction signal, the compensation transistor and the data writing transistor are turned on, and the data voltage output by the data signal line is written into the first storage capacitor and the second storage capacitor;

[0297] During the threshold compensation period, the first scan signal line outputs a disconnect signal, the second scan signal line outputs a conduction signal, the compensation transistor is turned on, the data writing transistor is turned off, the data voltage stored in the second storage capacitor is written into the first storage capacitor, and threshold compensation is performed on the driving transistor.

[0298] In an exemplary embodiment, the duration of the threshold compensation period is greater than or equal to the duration of the data writing period.

[0299] In an exemplary embodiment, the time of the threshold compensation period is n times the time of the data writing period, where n is a positive integer greater than or equal to 1 and less than or equal to 9.

[0300] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0301] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a compensation transistor, a driving transistor, a data writing transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor, the pixel driving circuit being connected to a first scan signal line, a second scan signal line, a first power supply line, and a data signal line respectively; the gate electrode of the driving transistor is connected to the second node, the first electrode of the driving transistor is connected to the first node, and the second electrode of the driving transistor is connected to the second electrode of the compensation transistor; the gate electrode of the data writing transistor is connected to the first scan signal line, the first electrode of the data writing transistor is connected to the data signal line, and the second electrode of the data writing transistor is connected to the first node; the gate electrode of the compensation transistor is connected to the second scan signal line, and the first electrode of the compensation transistor is connected to the second node; a first terminal of the first storage capacitor is connected to the second node, and a second terminal of the first storage capacitor is connected to the first power supply line; a first terminal of the second storage capacitor is connected to the first node, and a second terminal of the second storage capacitor is connected to the first power supply line; in, On a plane perpendicular to the display substrate, the display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a substrate; a first end of the first storage capacitor includes a first electrode plate, a second end of the first storage capacitor includes a second electrode plate, the first electrode plate is disposed in the first conductive layer, and the second electrode plate is disposed in the second conductive layer; a first end of the second storage capacitor includes a third electrode plate and / or a fifth electrode plate; a second end of the second storage capacitor includes a fourth electrode plate; the third electrode plate is disposed in the semiconductor layer or the first conductive layer, the fourth electrode plate is disposed in the second conductive layer, and the fifth electrode plate is disposed in the third conductive layer.

2. The display substrate according to claim 1, wherein, In the case where the first end of the second storage capacitor includes a third electrode plate and a fifth electrode plate, and the third electrode plate is disposed in the semiconductor layer, the third electrode plate is connected to the fifth electrode plate.

3. The display substrate according to claim 1, wherein, When the first end of the second storage capacitor includes a third electrode plate and the third electrode plate is disposed in the semiconductor layer, the semiconductor layer further includes the active layer of the driving transistor, and the third electrode plate and the active layer of the driving transistor are an integral structure interconnected.

4. The display substrate according to claim 1, wherein, When the first end of the second storage capacitor includes a third electrode plate and the third electrode plate is disposed in the semiconductor layer, the second electrode plate and the fourth electrode plate are an integral structure that is interconnected.

5. The display substrate according to claim 2, wherein, In the case where the first end of the second storage capacitor includes a third electrode plate and a fifth electrode plate and the third electrode plate is disposed in the semiconductor layer, the first node is disposed in the third conductive layer, the first node and the fifth electrode plate are an integral structure connected to each other, and the first node is connected to the third electrode plate through a via.

6. The display substrate according to claim 1, wherein, When the first end of the second storage capacitor includes a third electrode plate and the third electrode plate is disposed in the first conductive layer, the second conductive layer further includes a first electrode plate connecting block, and the second electrode plate and the fourth electrode plate are connected to each other through the first electrode plate connecting block.

7. The display substrate according to claim 1, wherein, When the first end of the second storage capacitor includes a third electrode plate and the third electrode plate is disposed in the first conductive layer, the third conductive layer further includes a second electrode plate connecting block and the first node, the first node is connected to the second electrode plate connecting block, and the second electrode plate connecting block is connected to the third electrode plate through a via.

8. The display substrate according to claim 1, wherein, When the first end of the second storage capacitor includes a third electrode plate and the third electrode plate is disposed in the first conductive layer, the distance between the first electrode plate and the third electrode plate is greater than or equal to 2 μm, and the distance is the dimension in the cell row direction.

9. The display substrate according to any one of claims 1 to 8, wherein, The capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor.

10. The display substrate according to claim 8, wherein, The capacitance value of the second storage capacitor is 20% to 70% of the capacitance value of the first storage capacitor.

11. The display substrate according to any one of claims 1 to 8, wherein, The pixel driving circuit is also connected to a first initial signal line and a second initial signal line, respectively. The first initial signal line and the second initial signal line are line shapes extending along a first direction. The first initial signal line is connected to a first connecting line extending along a second direction to form a mesh structure for transmitting the first initial signal. The second initial signal line is connected to a second connecting line extending along a second direction to form a mesh structure for transmitting the second initial signal. The first direction and the second direction intersect.

12. The display substrate according to claim 11, wherein, At least one unit row of circuit units is provided with the first initial signal line and the second initial signal line; the odd-numbered unit columns of circuit units are provided with the first connecting line, and the even-numbered unit columns of circuit units are provided with the second connecting line, or the even-numbered unit columns of circuit units are provided with the first connecting line, and the odd-numbered unit columns of circuit units are provided with the second connecting line.

13. The display substrate according to claim 11, wherein, On a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate; the first initial signal line and the second initial signal line are disposed in the second conductive layer, and the first connecting line and the second connecting line are disposed in the fourth conductive layer.

14. The display substrate according to claim 13, wherein, The third conductive layer in at least one circuit unit further includes a first initial electrode, the first connection line is connected to the first initial electrode through a via, and the first initial electrode is connected to the first initial signal line through a via.

15. The display substrate according to claim 13, wherein, The third conductive layer in at least one circuit unit further includes a second initial electrode, the second connection line is connected to the second initial electrode through a via, and the second initial electrode is connected to the second initial signal line through a via.

16. The display substrate according to claim 13, wherein, The display substrate further includes a fifth conductive layer disposed on the side of the fourth conductive layer away from the substrate. The data signal lines are disposed in the fifth conductive layer. The orthographic projection of at least one data signal line on the substrate at least partially overlaps with the orthographic projection of the first connecting line on the substrate. The orthographic projection of at least one data signal line on the substrate at least partially overlaps with the orthographic projection of the second connecting line on the substrate.

17. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 16.

18. A driving method for driving a display substrate as described in any one of claims 1 to 16, comprising: During the data writing period, the first scan signal line and the second scan signal line output a conduction signal, the compensation transistor and the data writing transistor are turned on, and the data voltage output by the data signal line is written into the first storage capacitor and the second storage capacitor; During the threshold compensation period, the first scan signal line outputs a disconnect signal, the second scan signal line outputs a conduction signal, the compensation transistor is turned on, the data writing transistor is turned off, the data voltage stored in the second storage capacitor is written into the first storage capacitor, and threshold compensation is performed on the driving transistor.

19. The driving method according to claim 18, wherein, The duration of the threshold compensation period is greater than or equal to the duration of the data writing period.

20. The driving method according to claim 19, wherein, The threshold compensation period is n times the data writing period, where n is a positive integer greater than or equal to 1 and less than or equal to 9.

Images