Circuit system for analyte measurement

Abstract

A circuit system for measuring a characteristic of an electrochemical cell, the circuit system comprising: a hysteresis comparator having a first comparator input, a second comparator input, and a comparator output; a feedback path between the comparator output and the second comparator input and configured to provide a feedback signal to the second comparator input; and a loop filter configured to apply filtering to the feedback path to generate a feedback signal, wherein the loop filter comprises an electrochemical cell.

Description

Technical Field

[0001] The present disclosure relates to a circuit system for measuring a property in an electrochemical sensor. Background Art

[0002] Electrochemical sensors are widely used to detect one or more specific chemical substances, analytes, as an oxidation or reduction current. Such sensors include an electrochemical cell consisting of two or more electrodes configured to contact the analyte whose concentration is to be determined. Such sensors also include circuitry for driving one or more of the electrodes and for measuring the response at one or more of the electrodes.

[0003] Conventional drive and measurement circuitry in an electrochemical sensor includes several amplifiers, feedback and / or feedback loops, and additional processing circuitry such as an analog-to-digital converter (ADC). Such circuitry can take up a lot of space on a chip and is relatively process intensive, thereby utilizing a lot of power. When an electrochemical sensor is powered by a battery, such as when used for continuous glucose monitoring, it is desirable that such a sensor be as small as possible and use as little power as possible. Summary of the invention

[0004] Embodiments of the present disclosure are intended to solve or at least improve one or more of the above-mentioned problems by reducing the total power and size of the drive and measurement circuit systems required to measure the analyte concentration in the electrochemical sensor. Specifically, embodiments of the present disclosure utilize the filtering characteristics of the electrochemical cell as a filter in a pulse width modulation (PWM) circuit, thereby saving both power and space. By reducing the size and power of the drive and measurement circuit systems, multiple electrochemical sensors can be integrated into a single device, thereby providing redundancy or being able to sense multiple analytes in a single chip. Multiple analyte sensors may be particularly advantageous in applications such as continuous glucose monitoring, where it may be desirable to measure the concentration of glucose, ketones, oxygen, lactate, etc.

[0005] According to a first aspect of the present disclosure, there is provided a circuit system for measuring characteristics of an electrochemical cell, the circuit system comprising: a comparator having a first comparator input, a second comparator input and a comparator output; a feedback path located between the comparator output and the second comparator input and configured to provide a feedback signal to the second comparator input; and a loop filter configured to filter the feedback path to generate a feedback signal, wherein the loop filter comprises an electrochemical cell.

[0006] The comparator may be a hysteresis comparator. The hysteresis comparator may be voltage hysteresis or time hysteresis.

[0007] The electrochemical cell may include at least one working electrode, a counter electrode, and a reference electrode. The comparator output may be coupled to the counter electrode. The reference electrode may be coupled to a second comparator input.

[0008] The electrochemical cell may include at least one working electrode and a counter electrode. The comparator output may be coupled to the counter electrode via a first impedance. The counter electrode may be coupled to a second comparator input.

[0009] The first impedance can be provided by an inductor. Alternatively, the first impedance can be provided by a current digital-to-analog converter (IDAC). The IDAC can be arranged in series between the comparator output and the counter electrode. The IDAC can be unipolar or bipolar. Alternatively, the first impedance can be provided by a finite impulse response digital-to-analog converter (FIR DAC).

[0010] The circuit system may also include a sample-and-hold circuit coupled between the comparator output and the first impedance.

[0011] The circuit system may further include control circuitry configured to adapt a hysteresis of the comparator based on a limit cycle frequency or a limit cycle period of a comparator output signal derived from the comparator output.

[0012] The circuit system may further include a decoding circuit system configured to decimate the comparator output signal and output a data signal.

[0013] The decoding circuit system may be further configured to determine a limit cycle frequency of the limit cycle period and output the limit cycle frequency or the limit cycle period to the control circuit system.

[0014] The control circuitry may also be configured to estimate a load capacitance of the electrochemical cell based on the limit cycle frequency or the limit cycle period.

[0015] The circuit system may also include an external capacitor coupled between the counter electrode and the working electrode.

[0016] At least one working electrode may be coupled to a reference voltage, which may be variable.

[0017] The circuit system may also include a multiplexer configured to switchably couple the reference voltage between the counter electrode and one or more additional counter electrodes.

[0018] The circuit system may also include one or more additional pairs of electrodes. In this case, the circuit system may also include an additional comparator for each of the one or more additional pairs of electrodes, each additional comparator including an additional first comparator input, an additional second comparator input, and an additional comparator output. An additional feedback path may be provided between each additional comparator output and each additional second comparator input, the additional feedback path being configured to provide an additional feedback signal to the corresponding additional second comparator input. Each additional comparator output may be coupled to a corresponding additional pair of electrodes.

[0019] The circuit system may also include one or more additional working electrodes.

[0020] The circuit system may also include a multiplexer configured to switchably couple the reference voltage between the working electrode and one or more additional working electrodes.

[0021] The circuit system may also include: an additional hysteresis comparator, which is used for each of one or more additional working electrodes, each additional hysteresis comparator includes an additional first comparator input, an additional second comparator input and an additional comparator output; an additional feedback path, which is located between each additional comparator output and each additional second comparator input and is configured to provide an additional feedback signal to the corresponding additional second comparator input, wherein each additional comparator output is coupled to the corresponding additional working electrode.

[0022] The comparator and each additional comparator may be hysteretic. Hysteretic switching of the comparator and each additional comparator may be controlled to minimize interference between the comparator output and each additional comparator output. Controlling the hysteretic switching may include staggering the hysteretic switching of the comparator and each additional comparator.

[0023] The working electrode or counter electrode and each additional working electrode or counter electrode can each be configured to sense a different analyte. In other words, the electrochemical cell can be configured to sense a variety of different analytes. In this way, the circuit system can be configured to measure the concentration of multiple analytes simultaneously. The different analytes can be selected from a non-exhaustive list including two or more of glucose, lactate and ketones. These analytes are of particular concern in the monitoring and treatment of diabetes.

[0024] Comparators can be synchronous or asynchronous.

[0025] In an embodiment where the comparator is asynchronous, the circuit system may further include a counter, the comparator output coupled to a data input of the counter. To reduce quantization errors associated with the counter, the circuit system may further include a voltage controlled oscillator (VCO) disposed between the comparator output and the data input of the counter.

[0026] Bias circuitry may be provided for applying a bias voltage to the first comparator input. The bias circuitry may include a filter configured to receive an input voltage and generate a bias voltage.

[0027] The filter may include an integrator having a first integrator input for receiving an input voltage, a second integrator input, and an integrator output. The integrator output may be coupled to the first comparator input and the first integrator input via a first capacitor. The second integrator input may be coupled to the second comparator input.

[0028] The bias voltage may be controlled to vary the limit cycle frequency. The limit cycle may be controlled to provide an alternating current (AC) at the comparator output. The limit cycle may be controlled to provide a sinusoidal signal at the comparator output.

[0029] The circuit system may further include a holding circuit system configured to hold the electrode of the electrochemical cell at a predetermined voltage. The holding circuit system may also be configured to de-energize the comparator when the electrode of the electrochemical cell is held at the predetermined voltage.

[0030] In some embodiments, chopping can be used to stabilize the circuit system to prevent its components from drifting (or DC biasing). For example, the polarity of the comparator can be reversed every other switching cycle of the comparator. Chopping (such as polarity reversal of the comparator) can be synchronized with the rising edge or falling edge of the output signal at the output of the comparator. Preferably, chopping is synchronized with the falling edge of the output signal.

[0031] According to another aspect of the present disclosure, an electronic device including the above-mentioned circuit system is provided. The electronic device may be a continuous glucose monitor. The device may include a mobile computing device, a laptop computer, a tablet computer, a game console, a remote control device, a home automation controller or a household appliance, a toy, a robot, an audio player, a video player or a mobile phone, and one of a smart phone.

[0032] Throughout the specification, the word "comprise" (or variations such as "comprises" or "comprising") will be understood to imply the inclusion of stated elements, integers or steps, or groups of elements, integers or steps, but not the exclusion of any other elements, integers or steps, or groups of elements, integers or steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Embodiments of the present disclosure will now be described by way of non-limiting examples with reference to the accompanying drawings, in which:

[0034] Figure 1A schematic diagram and electrical equivalent circuit of a three-electrode electrochemical cell are shown;

[0035] FIG2 is a schematic diagram of an exemplary prior art measurement circuit;

[0036] Figure 3 is a schematic diagram of a pulse width modulation (PWM) circuit;

[0037] Figure 4 It is the timing diagram of PWM signal;

[0038] Figure 5A is a schematic diagram of a measurement circuit for measuring the characteristics of an electrochemical cell;

[0039] Figure 5B is a schematic diagram of a measurement circuit for measuring the characteristics of an electrochemical cell;

[0040] Figure 6 is a schematic diagram of a measurement circuit for measuring electrical equivalent characteristics of the electrochemical cell shown in FIG5 ;

[0041] Figure 7 It is a diagram of the Randles equivalent circuit;

[0042] Figure 8 is a schematic diagram of a decoder configured to decode the output of the measurement circuit shown in FIG5 ;

[0043] Fig. 9 is a schematic diagram of a synchronous measurement circuit for measuring characteristics of an electrochemical cell;

[0044] Fig.10 is a schematic diagram of a measurement circuit for measuring the characteristics of an electrochemical cell;

[0045] Fig.11 is a schematic diagram of a measurement circuit for measuring the characteristics of an electrochemical cell;

[0046] Fig.12 is a schematic diagram of a measurement circuit for measuring characteristics of a two-electrode electrochemical cell;

[0047] Fig.13 is a schematic diagram of a measurement circuit for measuring characteristics of a two-electrode electrochemical cell;

[0048] Fig.14A is a schematic diagram of a measurement circuit for measuring a characteristic of a two-electrode electrochemical cell including a current digital-to-analog converter (IDAC);

[0049] Fig. 14B is a schematic diagram of a measurement circuit for measuring a characteristic of a three-electrode electrochemical cell including a current digital-to-analog converter (IDAC);

[0050] Fig.15 is a schematic diagram of the measurement circuit of FIG. 14 showing the IDAC in more detail;

[0051] Fig.16 is a schematic diagram of a measurement circuit for measuring a characteristic of a two-electrode electrochemical cell including a holding circuit;

[0052] Fig.17 is a schematic diagram of a measurement circuit for measuring characteristics of a two-electrode electrochemical cell having a second-order feedback loop;

[0053] Fig.18 is a schematic diagram of a multi-analyte measurement circuit for measuring properties of multiple analytes in an electrochemical cell;

[0054] Fig.19 is a schematic diagram of a multi-analyte measurement circuit for measuring properties of multiple analytes in an electrochemical cell;

[0055] Fig. 20 is a schematic diagram of a measurement circuit for measuring characteristics of a two-electrode electrochemical cell;

[0056] Fig.21 is a schematic diagram of a measurement circuit for measuring the characteristics of a three-electrode electrochemical cell;

[0057] Fig. 22 is an exemplary circuit model of an electrochemical cell;

[0058] Fig.23 is based on Fig. 22 The circuit model of Fig. 20 or Fig.21 Illustration of the load voltage waveform of an electrochemical cell;

[0059] Fig.24 is an exemplary circuit model of an electrochemical cell;

[0060] Fig.25 It is a system with a chopper circuit added Fig. 20 Schematic diagram of the measurement circuit;

[0061] Fig.26 It is a system with a chopper circuit added Fig. 20 Schematic diagram of the measurement circuit;

[0062] Fig. 27 Is a multi-analyte electrode Fig.21 Variations of the measurement circuit; and

[0063] Fig.28 Is a multi-analyte electrode Fig.21 Other variations of the measurement circuit. DETAILED DESCRIPTION

[0064] Figure 1 is a schematic diagram of an electrochemical cell 100 including three electrodes, namely, a counter electrode CE, a working electrode WE, and a reference electrode RE. Figure 1 Also shown is an equivalent circuit 102 of an electrochemical cell including a counter electrode inductance ZCE, a working electrode inductance ZWE, and a reference electrode inductance ZRE.

[0065] In order to determine the characteristics of the electrochemical cell, and therefore determine the analyte concentration, a measurement current is injected at the counter electrode CE, and the current at the working electrode is measured. The reference electrode RE is used to measure the voltage drop between the working electrode WE and the reference electrode RE. The measurement current is then adjusted to keep the voltage drop constant. When the resistance in the battery 100 increases, the voltage drop measured at the reference electrode increases. In response, the measurement current injected at the counter electrode CE decreases. Similarly, when the resistance in the battery 100 decreases, the voltage drop measured at the reference electrode decreases. In response, the measurement current injected at the counter electrode CE increases. Therefore, the electrochemical cell 100 reaches a state of equilibrium, in which the voltage drop between the reference electrode RE and the working electrode WE is maintained constant. Since the current and voltage drop injected at the counter electrode CE are known, the resistance of the battery 100 can be determined.

[0066] FIG. 2 shows an exemplary prior art drive and measurement circuit 200, which is configured to implement the battery characteristics described above, and in particular to measure Figure 1 Analyte concentration in the electrochemical cell 100 shown in . Circuit 200 includes a comparator 202 and a non-inverting operational amplifier 204. The non-inverting input of comparator 202 is coupled to a bias voltage VBIAS. The inverting input of comparator 202 is coupled to a reference electrode RE. The output of the comparator is coupled to a counter electrode CE and is configured to inject a measurement current. The measurement current injected by comparator 202 at the counter electrode CE is proportional to the difference between the bias voltage VBIAS and the voltage at the reference electrode RE. In this way, the comparator is used to maintain the voltage between the reference electrode RE and the working electrode WE close to the bias voltage VBIAS. The non-inverting input of operational amplifier 204 is coupled to the working electrode WE, and the inverting input of operational amplifier 204 is coupled to a reference voltage (ground in this case). A feedback loop including a sensing resistor RSENSE is coupled between the non-inverting input and the output of operational amplifier 204. Therefore, operational amplifier 204 is operable to output a voltage VO proportional to the current IWE at the working electrode WE. The output voltage VO is then provided to an analog-to-digital converter (ADC) 206 which outputs a digital output Q representative of the current IWE at the working electrode WE.

[0067] It can be seen that the conventional driving and measuring circuit 200 shown in Fig. 2 includes two operational amplifiers and one ADC. Each of these components not only occupies space on the chip, but also consumes a relatively large amount of power.

[0068] As described above, embodiments of the present disclosure are intended to solve or at least ameliorate one or more of the above-mentioned problems by reducing the total power and size of the drive and measurement circuitry required to measure the analyte concentration in an electrochemical sensor. Specifically, embodiments of the present disclosure utilize the inductive and filtering properties of an electrochemical cell to act as a filter in a pulse width modulation (PWM) circuit, thereby saving both power and space.

[0069] Figure 3 is a schematic diagram of a PWM circuit 300 (also called a time encoder).

[0070] In general, the PWM circuit 300 is configured to receive an input signal SIN, which may be, for example, a bias voltage, and generate a pulse width modulated (PWM) signal SPWM that alternates between different signal levels to encode the difference between the signal level of the input signal SIN and the signal level of the feedback signal SFB by the proportion of time spent in each output state. In general, the PWM signal SPWM may switch between a first output state and a second output state, and the signal level of the input signal may be encoded by the duty cycle of the first output state (i.e., the proportion of the total cycle period corresponding to the first output state, or equivalently, the amount of time the PWM signal SPWM spends in the first output state compared to the second output state).

[0071] The PWM circuit 300 includes a hysteresis comparator 302. In this embodiment, the hysteresis comparator 302 is arranged to receive an input signal SIN at a first comparator input (in this example, input (+)). The hysteresis comparator 302 compares the input signal SIN at the first comparator input with a feedback signal SFB received at a second comparator input (in this example, input (-)), and applies hysteresis to the comparison to generate a PWM signal SPWM at a comparator output node 304. The feedback path also extends from the comparator output node 304 to the second comparator input (in this example, input (-)), which is used to provide the feedback signal SFB to the second comparator input. The loop filter arrangement 306 is arranged to apply filtering to the feedback path to provide the feedback signal SFB. In this embodiment, the loop filter arrangement 306 includes a resistor-capacitor (RC) filter having an impedance 308 in the feedback path and a capacitor 310 coupled between the feedback path and a reference voltage (e.g., ground).

[0072] The hysteresis comparator 302 compares the signal at the first comparator input and the second comparator input (i.e., the input signal SIN) with the feedback signal SFB, and outputs either of the two output states VH and VL according to the comparison result. The hysteresis comparator 302 is operable to apply hysteresis to the comparison, so that the differential voltage between the signals SIN and SFB at the first comparator input and the second comparator input must be greater than a first threshold (i.e., more positive or less negative) to transition from one output state to another output state, such as from output state VL to output state VH, but must be lower than a second different threshold (i.e., less positive or more negative) to make the opposite transition, such as switching from output state VH to output state VL. The difference between these first and second thresholds corresponds to the amount of hysteresis applied. In some embodiments, the first and second thresholds may be equal in magnitude and opposite in polarity, i.e., the difference between the input signal SIN and the feedback signal SFB must be greater than an amount of +H to transition to one state (e.g., VH), and must be less than -H to transition to another state (e.g., VL). In this case, the magnitude of H can be viewed as a measure of the hysteresis applied by the hysteresis comparator 302, and the applied hysteresis is symmetrical. However, it should be understood that the applied hysteresis may be asymmetrical in some embodiments.

[0073] In some embodiments, the output states VH and VL may be high and low voltage levels, such as a power supply voltage VDD (VH) and ground (VL), or a positive voltage V+ (VH) and a negative voltage V- (VL), respectively, which may have equal magnitudes. Thus, the PWM signal SPWM transitions between two output voltage states.

[0074] Thus, the input signal SIN is compared with a feedback signal SFB derived from the output PWM signal SPWM. The feedback signal SFB corresponds to a filtered version of the PWM signal SPWM, and the filter arrangement 306 provides a certain delay and signal averaging over time. Thus, if the PWM signal SPWM transitions to a high state VH, the feedback signal SFB will initially be lower than the current state of the PWM signal SPWM, and will start to increase, i.e. become more positive, over a period of time. Thus, the delay and signal averaging applied to the PWM signal SPWM depends on the characteristics of the filter arrangement 306, and any change in the characteristics of the filter arrangement 306 will result in a change in the feedback signal SFB. This phenomenon is the basis for the operation of the PWM circuit 300 for measuring the characteristics of the electrochemical cell 100, which will be described in more detail below.

[0075] If the input signal SIN itself is constant over this time period, and the filter characteristics of the filter arrangement 306 are also constant, the difference between the input signal SIN and the feedback signal SFB will decrease, i.e. become less positive / more negative, until the relevant threshold is reached and the PWM signal SPWM transitions to another output state VL. At this point, the value of the feedback signal SFB will start to decrease. The hysteresis comparator 302 will maintain the low state VL until the difference between the input signal SIN and the feedback signal SFB increases to a second threshold, i.e. becomes less negative / more positive.

[0076] Notice, Figure 3 The arrangement shown in assumes that the input signal SIN and the feedback signal SFB are within the voltage range of the output states VH and VL and are referenced to a midpoint voltage VMID equal to the midpoint voltage between VH and VL. If desired, level shifting and / or scaling may be applied to at least one of the input signal SIN or the feedback signal SFB.

[0077] Thus, if the input signal SIN and the feedback signal SFB maintain constant levels, the output of the hysteresis comparator 302 will continuously cycle between a first output state VH and a second output state VL. The time spent in each output state will depend on the time it takes for the feedback signal SFB to change by an amount defined by the hysteresis (e.g., from a value equal to SIN-H to a value of SIN+H or vice versa). This will depend on the amount of hysteresis and the rate of change of the feedback signal SFB, which itself depends on the filter characteristics of the filter arrangement 306. However, the rate of change of the feedback signal SFB will depend on the current value of the feedback signal SFB, in particular the difference between the level of the output state (i.e., VH or VL) and the value of the feedback signal SFB, which in turn depends on the level of the input signal SIN and the characteristics of the filter arrangement 306.

[0078] The duration of the pulse corresponding to the high state VH in the PWM signal SPWM (and correspondingly the duration of the pulse corresponding to the low state VL in the PWM signal SPWM) therefore depends on the level of the input signal SIN and the characteristics of the filter arrangement 306. In the case where the input signal SIN is constant, PWM encodes the filter characteristics of the filter arrangement 306 as the duty cycle of the PWM signal SPWM, i.e. the ratio between the duration of the pulse of the first output state (e.g. VH) and the duration of the cycle period.

[0079] Figure 4The principle of the PWM signal SPWM of the PWM circuit 300 shown in FIG2 is shown. The PWM signal SPWM changes between two output states VH and VL. The duration of the pulse of the high state VH is represented by α, and the duration of the pulse of the low state VL is represented by β. The cycle period T is equal to α+β. For cycles that do not correspond to a duty cycle of 100% or 0%, the cycle period T can also be regarded as the period between an instance of a transition from one output state to another output state and the next instance of the same transition.

[0080] As described above, the duration α of the pulse of the high state VH depends on the level of the input signal SIN and the characteristics of the filter arrangement 306, as does the duration of the pulse of the low state VL. For a signal of zero magnitude (which corresponds to a signal reference voltage value equal to the mid-level voltage VMID between VH and VL), Figure 4 The period of the pulse of each state shown as α0 and β0 in will be equal to each other, that is, each period is equal to T0 / 2, where T0 is the cycle period at zero magnitude. If the delay of the filter arrangement 306 is increased, the duration of the pulse of one state will increase, while the duration of the pulse of the other state will decrease.

[0081] Therefore, any increase in the delay of the filter arrangement 306 will result in an increase in the cycle period, as shown by the durations α1 and β1 of the cycle periods at non-zero input signal magnitude and the duration T1. Therefore, the cycle period T0 (equal to α0+β0) corresponding to an input signal of zero magnitude will be the cycle period of the shortest duration. This condition is called a limit cycle, and the period T0 is the limit cycle period. This corresponds to the fastest cycle frequency f0=1 / T0, which is called the limit cycle frequency.

[0082] Embodiments of the present disclosure will at least in part Figure 3 The filter arrangement 306 shown in FIG. 1 is replaced by an electrochemical cell such as Figure 1 The battery 100 shown in FIG. 1 is used as a filter having an RC characteristic. When the input signal Sin is set to a constant bias voltage VBIAS, the change in the impedance characteristic of the battery 100 is converted into a change in the cycle period of the PWM signal SPWM.

[0083] Figure 5A and Figure 6 They are shown respectively including Figure 1 An exemplary measurement circuit 500 of an electrochemical cell 100 and also in Figure 15 . The same measurement circuit 500 with an equivalent impedance circuit 102 shown in FIG. 5 . The circuit 500 includes a hysteresis comparator 502 and an electrochemical cell 100. A bias voltage VBIAS is provided to a first (e.g., non-inverting) input of the comparator 502. The output of the comparator 502 is coupled to a counter electrode CE of the cell 100 and is provided as an output of the circuit 500. The working electrode of the cell 100 is coupled to a reference voltage (in this case, ground GND). The reference electrode RE is coupled to a second (e.g., inverting) input of the comparator 502. It can be seen that in this arrangement, the electrochemical cell 100 forms a filter in the feedback path between the output of the hysteresis comparator 502 and the first input (in this case, inverting). The second input (in this case, non-inverting) is coupled to a known bias voltage VBIAS. Since the bias voltage is known, the PWM output Q is encoded by the impedances ZRE, ZCE, ZWE of the electrochemical cell 100.

[0084] exist Figure 5A and Figure 6 In the embodiment shown in (and other embodiments described throughout this application), the voltage difference between the counter electrode CE and the working electrode WE is positive (i.e., the voltage at the working electrode WE, ground is less than the voltage at the counter electrode CE). However, in some embodiments, it may be advantageous to reverse the bias between the counter electrode CE and the working electrode. For example, for an oxygen-based sensor implemented as cell 100, the voltage at the working electrode WE should be lower than the voltage at the reference electrode RE. In contrast, for a hydrogen peroxide (H2O2) sensor, the voltage at the working electrode WE should be higher than the voltage at the reference electrode RE.

[0085] In order to switch between different measurement modes, the voltages provided at the comparator 502 and the working electrode WE may preferably be controlled independently. Figure 5B Shows Figure 5A The measuring cell 500 of the embodiment of the present invention is provided. However, in this example, the non-inverting input of the comparator 502 is coupled to the first bias voltage VBIAS1, and the working electrode WE is set to the second voltage VBIAS2. The first bias voltage VBIAS1 and the second bias voltage VBIAS2 can be set to positively bias or negatively bias the cell 100. For example, when the first bias voltage VBIAS1 is less than the second bias voltage VBIAS2, the cell 100 can operate as a hydrogen peroxide-based sensor. For example, when the first bias voltage VBIAS1 is greater than the second bias voltage VBIAS2, the cell 100 can operate as an oxygen-based sensor.

[0086] It should be appreciated that any of the following arrangements may be modified for negative or positive bias, depending on the application.

[0087] Figure 7 An equivalent circuit 700 is shown, which can be used to approximate the impedance ZCE of the counter electrode CE, the impedance ZWE of the working electrode WE, and the impedance ZRE of the reference electrode RE. The circuit 700 incorporates a Randles circuit (a known equivalent circuit for modeling electrodes immersed in an electrolyte). The circuit 700 includes an electrolyte (or ion) resistance Rs in series with a parallel combination of a double layer capacitance Cdl and the impedance of a Faraday reaction. The impedance of the Faraday reaction includes an effective charge transfer resistance Rct in series with an electrochemical diffusion resistance known as the Warburg impedance Zw. The Randles circuit is known in the art, and therefore will not be described in more detail here. The combined impedance of the counter electrode CE and the reference electrode RE is represented by a resistance Rcr.

[0088] As can be seen from the circuit, as the analyte concentration in the battery 100 increases, the charge transfer resistance Rct decreases, resulting in a change in the impedance associated with the feedback path. This in turn results in a change in the time that the output signal Q stays in each output state VH, VL. As such, the output signal Q is a PWM signal that encodes information about the analyte concentration in the battery 100.

[0089] Compared to a conventional non-hysteresis comparator, the use of the hysteresis comparator 502 results in less toggling of the comparator 502 and thus reduces power consumption. In addition, the PWM output Q from the hysteresis comparator 502 can be easily decoded by viewing it as a single bit output or by viewing it directly as a PWM waveform. This further reduces the processing power required to characterize the battery 100.

[0090] Figure 8 An exemplary decoder 800 for decoding the PWM signal Q output from the hysteresis comparator 502 is shown. The decoder 800 includes a counter timed by a clock signal Fs, which has a frequency higher than the frequency of the output signal Q. The output signal Q from the comparator 502 is provided to the decoder 800 as a data input. The decoder 800 is configured to count the number of cycles or oscillations of the clock signal Fs in a single cycle of the output signal Q. The decoder 800 then outputs the count as a digital count output DS. It should be understood that the quantization error of the decoder 800 is determined by the time resolution of the counter, which itself depends on the frequency of the clock signal Fs. In some embodiments, the rising edge of the output signal Q can be synchronized with the clock signal Fs.

[0091] In order to reduce the quantization error, a voltage controlled oscillator (VCO) (not shown) can be arranged at the input of the decoder 800 and configured to output an oscillating signal, wherein the frequency of the oscillation depends on the level of the input to the VCO. Then, a counter is arranged to receive the oscillating signal from the VCO and count the number of oscillations in a frame period defined by the clock signal Fs. Over the course of several frames, the average count value will depend on the amount of time the time-coded signal Q spends in one state, thus controlling the VCO to output a first frequency, compared to the amount of time the output signal Q spends in another state, thus controlling the VCO to output a second frequency. Therefore, the average count value is related to the duty cycle of the output signal Q.

[0092] As will be appreciated by those skilled in the art, the use of a VCO provides some noise shaping. Quantization errors at low frequencies associated with the decoder 800 are reduced because any error in one frame (e.g., any difference between the clock edge defining the end of a frame and the end of an oscillation at the end of the frame) is carried forward to the next frame. Quantization noise at higher frequencies increases, but this can be easily removed by downstream digital filtering without affecting the audio signal band. Thus, the use of a VCO allows accurate conversion at clock rates significantly lower than the clock rate required when using a counter alone.

[0093] In Figure 5 and Figure 6 In the embodiment of the present invention, the hysteresis comparator 502 is asynchronous. When the output Q is decoded by a decoder such as the decoder 800 described above, quantization error will be introduced. To improve the quantization error, some embodiments of the present disclosure may implement a synchronous hysteresis comparison, in which the transitions of the time-coded signal are synchronized with the clock signal.

[0094] Fig. 9 5 , but includes a synchronous (or latched) hysteresis comparator 902 in place of the (asynchronous) comparator 502. In practice, the synchronous hysteresis comparator 902 may be implemented using a combination of asynchronous hysteresis comparators configured with latches at their outputs.

[0095] The synchronous hysteresis comparator 902 is clocked with the clock signal Fs. Therefore, the transitions of the output signal Q are synchronized with the clock signal Fs, and thus the period α of the pulses of the output signal Q in one state and the period β of the pulses in another state are synchronized with the clock signal Fs. By synchronizing the transitions in the time-coded signal with the clock signal Fs, a signal such as Figure 8 The counter shown in is used to directly generate a count value corresponding to the duration of the time-coded signal without any quantization error introduced by the counter.

[0096] During operation, when the output Q of the hysteresis comparator 902 is in a high state, the capacitance of the battery 100 will charge until the voltage at the second (inverting) comparator input is equal to Q+H. At this point, at the next relevant clock edge of the clock signal Fs, the output of the hysteresis comparator 902 will switch to a low state, and the capacitance of the battery 100 will begin to discharge until the voltage drops to SIN-H. The rate of charging and discharging will depend on the voltage difference across the resistance of the battery 100. As described above, the voltage across the capacitance of the battery 100 will vary between SIN-H and SIN+H, and therefore the rate at which the capacitance of the battery is charged or discharged therefore depends on the error between the output state and the voltage VBIAS at the first (non-inverting) input of the comparator 902.

[0097] Although Figure 5, Figure 8 and Fig. 9 The embodiment shown in is voltage hysteretic, but embodiments of the present disclosure are not limited to voltage hysteresis.

[0098] Fig.10 is a schematic diagram of a measurement circuit 1000, the measurement circuit being Figure 4 A variation of the measurement circuit 500 shown in , but is delayed in time. The same parts are given the same reference numerals. The measurement circuit 1000 also includes a delay element 1002, which is configured to apply a controlled delay in the feedback loop of the comparator 502. In this way, there is a delay between the change of the output state of the comparator 502 (i.e., the change of the state of the PWM signal from the high output state VH to the low output state VL or vice versa) and the corresponding change of the state of the second input signal provided to the comparator 502 (i.e., the change from ramping to ramping down or vice versa). In some embodiments, the delay element 1002 may include a variable delay element, which may be controlled to selectively change the amount of delay applied. By controlling the delay applied by the delay element 1002, the cyclic frequency of the output signal Q can be controlled. The benefits of this control will be described in more detail below.

[0099] In this embodiment, both hysteresis and controlled delay are applied in the feedback loop. Thus, the frequency of the cycle of the output signal Q from the comparator 502 depends on both the delay applied by the delay element 1002 and the amount of hysteresis applied by the comparator 502, which in turn (as described above) depends on the impedance characteristics of the battery 100.

[0100] In this case, the output signal Q is a delayed version of the PWM signal SPWM. In other embodiments, there may also (or alternatively) be a delay element in the feedback path, for example between the reference electrode RE and the second input of the comparator 1102 .

[0101] The effects of using delays in PWM circuits are described in detail in US Pat. No. 10,348,282 Bl, the contents of which are hereby incorporated by reference in their entirety.

[0102] Fig.11 A measurement circuit 1100 is shown. Fig.10 The synchronous variation of the measurement circuit 1000 shown in FIG. The measurement circuit 1100 includes a synchronous (or latched) comparator 1102 and a synchronous delay element 1104. The comparator 1102 is configured to synchronize any signal transitions in the output of the modulator with the clock signal Fs, and the delay element 1104 includes a digital delay element synchronized with the clock signal Fs.

[0103] The above embodiments are described with reference to a three-electrode battery 100 including a counter electrode CE, a working electrode WE, and a reference electrode RE. However, the embodiments of the present disclosure are not limited to having three electrodes. The concepts described herein are also applicable to two-electrode batteries. Specifically, in any of the above embodiments, the three-electrode battery 100 can be replaced with a two-electrode battery.

[0104] Fig.12 A measurement circuit 1200 is shown including a two-electrode battery 1202, a hysteresis comparator 1204, and an impedance ZCE. Figure 3 , the PWM circuit 300 includes a loop filter arrangement 306 having an impedance 308 in the feedback path and a capacitor 310 coupled between the feedback path and a reference voltage. The measurement circuit 1200 also has an impedance Zce in the feedback path. However, compared to the PWM circuit 300, the capacitor 310 is replaced by a two-electrode battery 1202 coupled between the feedback path and a reference voltage (ground in this example). The counter electrode CE of the two-electrode battery 1202 is coupled to the feedback path, and the working electrode WE of the two-electrode battery 1202 is coupled to the reference voltage.

[0105] Therefore, the impedance Zce and the impedance of the battery 1202 are equal to Figure 3 1204 acts as a loop filter arrangement in a similar manner to the loop filter arrangement 306 of the PWM circuit 300 shown in FIG. 1204. In this way, a change in the impedance of the battery 1202 results in a change in the delay applied in the feedback path between the output terminal and the second input terminal of the hysteresis comparator 1204. Preferably, the impedance Zce is much larger than the impedance of the battery 1202, so that the current injected at the counter electrode CE of the battery 1202 can be accurately controlled.

[0106] Measuring the impedance Zce of the circuit 1200 may be implemented in several ways. Fig.13 Two non-limiting examples are shown in and 14 .

[0107] Fig.13 for Fig.12 A first example of a measurement circuit 1200 is shown in FIG. 1 . In this example, the impedance Zce is provided by an inductor 1302 , which provides a high output impedance Zce for the comparator 1204 .

[0108] Fig.14A 1 is a second example of a measurement circuit 1200, wherein the impedance Zce is provided by a current digital-to-analog converter (IDAC) 1402. The output of the comparator 1204 is coupled to the input of the IDAC 1402. The output of the IDAC 1402 is coupled to the counter electrode CE of the battery 1202 and is also coupled to a second input of the comparator 1204. Therefore, the IDAC 1402 is configured to inject a current at the counter electrode CE, which depends on the respective durations α1 and β1 of the output signal Q output from the comparator 1204.

[0109] Fig. 14B Shows Fig.14A 1. A three-electrode battery variation of the measurement circuit 1200 shown in FIG. 1. Instead of a two-electrode battery 1202, a three-electrode battery 100 is provided. In this example, the output of the IDAC 1402 is not coupled to the second input of the comparator 1204. Instead, the output of the IDAC 1402 is coupled to the counter electrode CE of the battery 100, while the reference electrode RE of the battery 100 is coupled to the second input of the comparator 1204.

[0110] It will be appreciated that an IDAC or equivalent current source may be provided at the input of the counter electrode CE in any of the arrangements described above. Fig.10 In , an IDAC (or other current source) may optionally be provided between the counter electrode CE and the output of the delay element 1002. Fig.11 In the embodiment, an IDAC (or other current source) may optionally be provided between the counter electrode CE and the output of the delay element 1104. Providing a controlled current source at the counter electrode CE of each battery 100, 1202 has the advantage of enabling the measurement circuit 1200 to exhibit a linear response to changes in impedance and / or current associated with the battery 100.

[0111] Fig.15 An exemplary embodiment of IDAC 1402 is shown, particularly with respect to Fig.14A The exemplary embodiment of the two-electrode battery arrangement shown in FIG. 1 (although such embodiments may also be Fig. 14B). The IDAC 1402 includes a pair of transistors N1, N2, whose respective drains are coupled to a current source 1404. The source of the first transistor N1 is coupled to a ground reference voltage. The source of the second transistor N2 is coupled to a counter electrode CE. The gates of the first transistor N1 and the second transistor N2 are provided with an output signal Q and a complement Q' of the output signal Q, respectively. An inverter 1406 is provided to generate a complement Q' of the output signal Q. Thus, the output of the current source 1404 switches between the counter electrode CE (via the first transistor N1) and the ground reference (via the second transistor N2). The duration spent in each state depends on the respective durations α1 and β1 of the output signal Q. Fig.15 In the embodiment shown in , the first transistor N1 and the second transistor N2 are PMOS devices. In embodiments, NMOS devices (or any other suitable switching devices known in the art) may be used. Fig.15 In the embodiment shown in , IDAC 1402 switches the counter electrode CE between Iref and ground. In other embodiments, a two-electrode implementation of IDAC 1402 can be used to switch the counter electrode between Iref and -Iref, for example.

[0112] The embodiments of the present disclosure described herein are intended to reduce the overall power and size of the drive and measurement circuitry required to measure the analyte concentration in an electrochemical sensor. Therefore, it should be understood that it is advantageous to be able to disconnect or power down one or more components of the above-described measurement circuits 500, 900, 1000, 1100, 1200 without substantially affecting the performance of the electrochemical cell 100.

[0113] In a variation of the embodiment shown in FIG. 14 , and all other embodiments that include an IDAC, the IDAC 1402 may be replaced with a finite impulse response DAC (FIR DAC).

[0114] Therefore, in some embodiments, a holding circuit system can be introduced to enable each of the measurement circuits 500, 900, 1000, 1100, 1200 to switch to a holding mode. The holding mode can be used to pause the measurement so that one or more components can be powered off. To this end, the holding circuit system preferably holds the electrode at a predetermined voltage.

[0115] Fig.16 Shown in Figures 12 to 151200. The holding circuit 1600 includes a switch 1604 (a transistor in this example) coupled between the inverting input of the comparator 1204 and the non-inverting input of the comparator 1204. The switch 1604 is controlled by the hold signal HOLD. By closing the switch 1604 (using the hold signal HOLD) to keep the electrode CE at a predetermined voltage (Vbias in this case), the measurement circuit 1200 can be moved to a hold state. The comparator 1204 can then be powered off between measurements to minimize power consumption between measurement events. For measurement, the comparator 1204 can be powered on, and the switch 1604 is disconnected to resume measurement.

[0116] In the above-described embodiments, a single-order loop filter is provided in each of the measurement circuits 500, 900, 1000, 1100, 1200. In some applications, it may be advantageous to increase the order of the loop filter for hysteresis.

[0117] Fig.17 One such exemplary measurement circuit 1700 is shown, which includes a hysteresis comparator 1702, a measurement cell 100, and an operational amplifier-based integrator 1704. In this example, the output signal Q is used as a feedback signal, which is filtered by the measurement cell 100 and the integrator 1704. The integrator 1704 is arranged between the input bias voltage VBIAS and the first (non-inverting) input of the comparator 1702. The bias voltage VBIAS is provided to the first (inverting) input of the integrator 1704. The second (non-inverting) input of the integrator is coupled to the reference electrode. In this way, the integrator 1704 is configured to integrate the input voltage VBIAS in the forward path. It should be understood that Fig.15 Only one of several exemplary topologies for implementing multi-order filtering in a feedback loop is provided.

[0118] As mentioned previously, by reducing the size and power of the drive and measurement circuitry, multiple electrochemical sensors can be integrated into a single device, providing redundancy or the ability to sense multiple analytes in a single chip. This may be particularly advantageous in applications such as continuous glucose monitoring, where it may be desirable to measure the concentration of several analytes including, but not limited to, two or more of glucose, ketones, oxygen, lactate, etc.

[0119] Fig.18A multi-analyte measurement circuit 1800 configured to measure two analytes is shown. The measurement circuit 1800 includes a measurement cell 1802, which includes a first pair of electrodes CE1 and a second pair of electrodes CE2, a common working electrode WE, and a common reference electrode RE. The measurement circuit 1800 also includes a first hysteresis comparator 1804 and a second hysteresis comparator 1806. Each of the first hysteresis comparator 1804 and the second hysteresis comparator 1806 is configured in a manner similar to the comparator 502 of Figure 5.

[0120] A first input terminal of the first hysteresis comparator 1804 is coupled to a first bias voltage VBIAS1. An output terminal of the first hysteresis comparator 1804 is coupled to the first pair of electrodes CE1, and a reference electrode RE is coupled to a second input terminal of the first hysteresis comparator 1804. In this way, a feedback loop is formed between the output terminal and the second input terminal of the first hysteresis comparator 1804 via the first pair of electrodes CE1. Therefore, the first hysteresis comparator 1804 is configured to output a first output signal Q1, which is a PWM signal representing a first analyte concentration associated with a current between the first pair of electrodes CE1 and the working electrode WE.

[0121] A first input terminal of the second hysteresis comparator 1806 is coupled to a second bias voltage VBIAS2. The second bias voltage VBIAS2 may be different from or the same as the first bias voltage VBIAS1. The output terminal of the second hysteresis comparator 1806 is coupled to the second pair of electrodes CE2, and the reference electrode RE is coupled to the second input terminal of the second hysteresis comparator 1806. In this way, a feedback loop is formed between the output terminal and the second input terminal of the second hysteresis comparator 1806 via the second pair of electrodes CE2. Therefore, the second hysteresis comparator 1806 is configured to output a second output signal Q1, which is a PWM signal representing a second analyte concentration associated with the current between the second pair of electrodes CE2 and the working electrode WE. The working electrode WE is coupled to a reference voltage (ground GND in this case).

[0122] Thus, the measurement circuit 1800 is capable of measuring two different analyte concentrations using a common measurement cell 1802 and only two hysteresis comparators 1804, 1806. Although the measurement circuit 1800 shown in FIG. 2 is configured to characterize two different analytes, in other embodiments, any number of analytes may be measured by providing an additional counter electrode and hysteresis comparator for each additional analyte to be characterized. It should also be understood that Fig.18 The hysteresis comparators 1804, 1806 shown in FIG. 5 can be used as described above with reference to FIG. Fig.17 Any of the arrangements described may be substituted without departing from the scope of the present disclosure.

[0123] Fig.19A multi-analyte measurement circuit 1900 configured to measure two analytes is shown. Fig.18 5 . The same parts are given the same reference numerals. The measurement circuit 1900 includes a measurement cell 1902, which includes a first working electrode WE1 and a second working electrode WE2, a common counter electrode CE and a common reference electrode RE. The measurement circuit 1900 also includes a first hysteresis comparator 1804 and a second hysteresis comparator 1806. Each of the first hysteresis comparator 1804 and the second hysteresis comparator 1806 is configured in a manner similar to the comparator 502 of Figure 5.

[0124] A first input terminal of the first hysteresis comparator 1804 is coupled to a first bias voltage VBIAS1. An output terminal of the first hysteresis comparator 1804 is coupled to the first working electrode WE1, and a reference electrode RE is coupled to a second input terminal of the first hysteresis comparator 1804. In this way, a feedback loop is formed between the output terminal and the second input terminal of the first hysteresis comparator 1804 via the first working electrode WE1. Therefore, the first hysteresis comparator 1804 is configured to output a first output signal Q1, which is a PWM signal representing a first analyte concentration associated with a current between the first working electrode WE1 and the counter electrode CE.

[0125] A first input terminal of the second hysteresis comparator 1806 is coupled to a second bias voltage VBIAS2. The second bias voltage VBIAS2 may be different from or the same as the first bias voltage VBIAS1. An output terminal of the second hysteresis comparator 1806 is coupled to a second working electrode WE2, and a reference electrode RE is coupled to a second input terminal of the second hysteresis comparator 1806. In this way, a feedback loop is formed between the output terminal and the second input terminal of the second hysteresis comparator 1806 via the second working electrode WE2. Therefore, the second hysteresis comparator 1806 is configured to output a second output signal Q2, which is a PWM signal representing a second analyte concentration associated with a current between the second working electrode WE2 and the counter electrode CE.

[0126] from Fig.19 It can be seen that the counter electrode CE is coupled to a third bias voltage VBIAS3, which is different from the first bias voltage VBIAS1 and the second bias voltage VBIAS2. The third bias voltage VBIAS3 can, for example, be greater than the first bias voltage VBIAS1 and the second bias voltage VBIAS2. Alternatively, the third bias voltage VBIAS3 can, for example, be less than the first bias voltage VBIAS1 and the second bias voltage VBIAS2 (e.g., ground GND).

[0127] Thus, similar to measurement circuit 1800, measurement circuit 1900 is capable of measuring two different analyte concentrations using a common measurement cell 1902 and two hysteresis comparators 1804, 1806. Although measurement circuit 1900 shown in FIG. 2 is configured to characterize two different analytes, in other embodiments, any number of analytes may be measured by providing an additional working electrode and hysteresis comparator for each additional analyte to be characterized. It should also be understood that Fig.19 The hysteresis comparators 1804, 1806 shown in FIG. 5 can be used as described above with reference to FIG. Fig.17 Any of the arrangements described may be substituted without departing from the scope of the present disclosure.

[0128] As mentioned above about Fig.14A , Fig. 14B and Fig.15 As mentioned, in some embodiments a feedback DAC may be provided in the feedback path between the output of a respective comparator and the input of such comparator. Further embodiments of such an arrangement will now be described.

[0129] Fig. 20 An exemplary measurement circuit 2000 is schematically shown, which is a variation of the measurement circuit 1200 described above. Like parts are given the same reference numerals. The measurement circuit 2000 includes a measurement cell 1202 and a hysteresis comparator 2001. The measurement circuit 2000 further includes an IDAC 2002, a sample-and-hold circuit 2004, a decoder 2006, and a control module 2008. In other embodiments, the IDAC 2002 can be replaced with a FIR DAC.

[0130] A first (e.g., non-inverting) input of comparator 2001 is coupled to bias voltage VBIAS. A second (e.g., inverting) input of comparator 2001 is coupled to the output of IDAC 2002 and the counter electrode CE of battery 1202. The working electrode WE of battery 1202 is coupled to a reference voltage (ground GND in this case). The output of comparator 2001 is coupled to the input of sample-and-hold circuit 2004, which samples the PWM output and provides the sampled value to IDAC 2002 and decoder 2006.

[0131] The sample and hold circuit 2004 is used to synchronize the forward path so that the decoder 2006 can successfully decode. In an alternative embodiment, the comparator 2001 and the sample and hold circuit 2004 can be synchronized (e.g., latched or clocked) with a comparator (e.g., Fig. 9 The comparator 902 shown is replaced.

[0132] The output of the decoder 2006 is provided to the control module 2008. Optionally, an external capacitor CEXT can be coupled between the counter electrode CE and the working electrode WE. For example, in the case where the inherent capacitance of the battery 1202 is low, an external capacitor CEXT can be provided. In order to maximize the linearity of the measurement circuit 2000, the limit cycle frequency FLC is preferably on the transition band in the loop filter (in the feedback path). Such a transition band can be a band where the impedance of the loop filter decreases with frequency, rather than a band where the impedance is constant relative to the frequency. In a practical embodiment, the measurement battery 1202 (or battery 100) can have a complex impedance, presenting a region of constant impedance (for example, to minimize power consumption) at the frequency of the limit cycle frequency FLC of the measurement circuit 2000 that may be desired to be set. Adding an external capacitor CEXT with a sufficiently large capacitance can help ensure that the impedance of the loop filter decreases with the increase of frequency, thereby providing more degrees of freedom to set the limit cycle frequency FLC at a desired level.

[0133] It should be understood that power minimization requirements may require very large capacitance. However, an increase in the capacitance of the external capacitor CEXT may result in an increase in circuit area, power consumption, and noise. To ameliorate this problem, in some embodiments, the external capacitor CEXT may be implemented as a capacitance multiplier or other active capacitive arrangement. Capacitance multipliers are known in the art and therefore will not be described in more detail here.

[0134] During operation, the IDAC 2002 generates a current according to the PWM signal ID output from the sample-and-hold circuit 2004. The generated current flows through the measurement battery 1202, so that the voltage across the battery 1202 is equal to the bias voltage VBIAS. At the same time, the decoder decodes (e.g., extracts) the PWM signal ID and outputs a decoded data signal Q proportional to the current flowing through the battery 1202.

[0135] As explained above, due to the hysteresis in the comparator 2001, the output ID from the sample and hold circuit 2004 is a PWM signal that transitions between a high output state (e.g., VH) and a low output state (e.g., VL) at the limit cycle frequency FLC (or cycle frequency or carrier frequency). Figure 4 , the limit cycle frequency FLC is the inverse of the cycle period T. It should be understood that, especially in Fig. 20 In the embodiment shown in , it is advantageous to control the limit cycle frequency FLC of the signal output from the comparator 2001 within a predetermined frequency range. For example, the sample-and-hold circuit 2004 is configured to sample the PWM signal output from the comparator 2001 at a sampling rate R. A limit cycle frequency FLC having a much larger sampling rate R may result in information loss and / or aliasing of the PWM signal output from the IDAC.

[0136] In this way, the limit cycle frequency FLC (or cycle period) of the PWM signal ID output from the sample and hold circuit 2004 is determined by the decoder 2006 , and the decoder outputs the determined limit cycle frequency FLC to the control module 2008 .

[0137] The control module 2008 can then be configured to control the hysteresis in the comparator 2001 based on the limit cycle frequency FLC of the PWM signal ID to stabilize the limit cycle frequency FLC within a predetermined range. Such a predetermined range can, for example, depend on the sampling rate R of the sample and hold circuit 2004. The control module 2008 can, for example, adapt the hysteresis of the comparator 2001 based on a comparison between the limit cycle frequency FLC and the target frequency FT. The target frequency FT can be set to a frequency that compromises power consumption and linearity. The lower the limit cycle frequency FLC, the less linear the circuit 2000 is. On the contrary, the higher the limit cycle frequency FLC, the higher / better the linearity, which is at the expense of additional switching and thus increases power consumption.

[0138] Fig.21 Shown as Fig. 20 A measurement circuit 2100 is a variation of the measurement circuit 2000 of FIG. 2100 , in which the two-electrode battery 1202 has been replaced by the three-electrode battery 100. The same parts are denoted by the same reference numerals. Compared to the measurement circuit 2000 , instead of coupling the second input terminal of the comparator 2001 to the output terminal of the IDAC 2002, the second input terminal of the comparator 2001 is coupled to the reference electrode RE of the two-electrode battery 100.

[0139] In addition to controlling the hysteresis of the comparator 2001 , the control module 2008 may be configured to determine one or more characteristics of the battery 1202 based on the limit cycle frequency / period FLC / TLC, as explained in more detail below.

[0140] It should be understood that either of the measurement cells 100, 1202 can be modeled as a current load or a resistive load. For example, when the measurement cell 1202 is biased with a constant bias voltage, the measurement cell 1202 can be best modeled as a current load. In contrast, when the measurement cell 1202 is biased with a varying bias voltage, the measurement cell 1202 can be best modeled as a resistive load.

[0141] Therefore, in some embodiments, Fig. 22 As shown in FIG. 1 , the measurement battery 1202 can be modeled as a current load 2200, which includes a current source 2202 that generates a current ILoad in parallel with a load capacitor CLoad, as shown in FIG. Fig. 22 as shown in . Fig.232001 is a graph showing an exemplary waveform of the load voltage VLoad at the inverting input terminal of the comparator 2001. The load voltage Vload rises during the time TH and falls during the time TL. For the current load 2200, the duration of the rise time TH and the fall time TL can be defined as follows.

[0142]

[0143]

[0144] Thus, the decoded current Q output from the decoder 2006 can be defined as follows, where IDAC is the current provided to the IDAC 2002 and the decoder 2006 .

[0145]

[0146] The PWM cycle period TLC of the output signal ID can be defined as follows:

[0147]

[0148] Assume that the voltage domain hysteresis VHYS in comparator 2001 is the voltage required to switch comparator 2001 (i.e., the hysteresis of the comparator). Therefore, since the load current ILOAD is known from the decoded output Q, the estimated capacitance CLOAD of battery 1202 can be determined from the limit cycle period TLC (or frequency FLC) using the above equation.

[0149] Therefore, the control module 2008 may be configured to output the value of the capacitor CLOAD based on the limit cycle frequency FLC or the limit cycle period TLC.

[0150] As mentioned above, in some embodiments, the battery 1202 (or battery 100) can be modeled as a resistive load 2400, such as Fig.24 As shown in , including a resistor 2402 having a resistance RLOAD connected in parallel with a load capacitor CLoad, as shown in Fig. 22 as shown in .

[0151] For a resistive load 2400, the duration of the rise time TH and the fall time TL may be defined as follows.

[0152]

[0153]

[0154] The decoded output signal Q can then be defined as:

[0155]

[0156] According to the above equation, since Q, VBIAS and IDAC are known, the resistance RLOAD of the battery 1202 (or battery 100) can be determined.

[0157] In addition, the limit cycle period TLC of the comparator 2001 can be defined as:

[0158]

[0159] Since RLOAD is known from the decoded output Q, CLOAD can be derived from the limit cycle frequency FLC (or period TLC) determined by the decoder 2006.

[0160] In this way, the modeled resistance RLOAD and capacitance CLOAD of the battery 1202 (or battery 100 ) may be determined, thereby characterizing the battery 1202 .

[0161] It should be understood that in practical implementations of any of the measurement circuits described above, inherent flicker noise and DC offset will be present. Embodiments of the present disclosure may also implement chopping (or other auto-zeroing techniques) to reduce or substantially eliminate sensitivity to DC offset.

[0162] Referring to FIG. 5 , as an example, the polarity of the comparator 502 can be reversed every other cycle to convert any DC offset associated with the loop filter (e.g., the battery 100) into a variable DC output voltage (e.g., a square wave at the chopping frequency). This square wave present in the output signal Q can be easily filtered out by a downstream filter (not shown), thereby producing a filtered output signal without the effects of the DC offset. Preferably, the chopping is synchronized with the limit cycle of the comparator 502. For example, the polarity of the comparator 502 can be reversed during the falling edge of the output Q or during the rising edge of the output Q. It should be understood that the falling edge of the output signal Q is an edge that varies with time to adjust the limit cycle of the comparator 502, while the rising edge is substantially periodic (i.e., the frequency of the rising edge is constant). Thus, advantageously, the chopping is synchronized with the falling edge of the output signal Q so that the chopping frequency is extended over a frequency range (consistent with the falling edge of the output Q). It should be understood that the technique can be implemented with respect to any measurement circuit described in the present disclosure.

[0163] Fig.25 Shows relative to Fig. 20 The exemplary chopping circuit system 2500 of the measurement circuit 2000 of FIG. The chopping circuit system 2500 is used to solve the DC offset and flicker noise in the feedforward path of the measurement circuit 2000. The chopping circuit system 2500 includes a chopping control module 2502, a chopping module 2504 and a summing module 2506. The chopping module 2504 is coupled to the input terminal of the comparator 2001. The summing module 2506 can be set as follows: Fig.25At the output of the sample-and-hold circuit 2004 shown, or alternatively at the output of the comparator 2001 between the comparator 2001 and the sample-and-hold circuit 2004 .

[0164] The chopping module 2504 and the summing module 2506 can be controlled by the chopping control module 2502 to implement chopping stabilization as known in the art. The chopping circuit system 2500 can operate in a manner similar to that described above with reference to FIG. 5. For example, by switching the polarity of the circuit 2000 at a chopping frequency significantly higher than the signal bandwidth, the DC offset associated with the comparator 2001 becomes a square wave at the chopping frequency, which can be easily filtered out by the decoder 2006. In order to correct the polarity of the circuit 2000, reverse switching can be implemented at the summing module (at the same chopping frequency). In this way, the DC measurement error caused by the comparator 2001 can be reduced or substantially eliminated.

[0165] It should be understood that the bias voltage VBIAS applied to the first input of the comparator 2001 may also be affected by flicker noise and DC offset / drift. Such effects can be reduced by biasing the IDAC 2002 with the same voltage as the bias voltage VBIAS. By biasing the IDAC with the bias voltage VBIAS, the decoded output signal Q can be defined as follows:

[0166]

[0167] As such, the decoded output Q is independent of the bias voltage VBIAS, so that variations in the bias voltage VBIAS due to DC drift or flicker noise do not affect the decoded output Q.

[0168] Fig.26 Shows relative to Fig. 20 2000 of the measuring circuit 2000 of the embodiment of the present invention. The chopping circuit system 2600 is used to solve the DC offset and flicker noise in both the feedforward path and the feedback path of the measuring circuit 2000. The chopping circuit system 2600 includes a chopping control module 2602, a first chopping module 2604, a second chopping module 2606 and a summing module 2608. The first chopping module 2604 is coupled at the input end of the comparator 2001. The second chopping module 2606 is coupled between the IDAC 2002 and the counter electrode CE of the battery 1202 at the output end of the IDAC 2002. In addition, the summing module 2608 is arranged at the input end of the decoder 2006.

[0169] The first chopping module 2604, the second chopping module 2606 and the summing module 2608 can be controlled by the chopping control module 2602 to implement chopper stabilization as known in the art. Providing the second chopping module 2606 in the feedback path reduces the effects of flicker noise and / or DC offset due to nonlinearities associated with the IDAC 2002.

[0170] As reference Fig.18 and Fig.19 As mentioned, in some embodiments, an electrochemical cell comprising multiple working electrodes or multiple counter electrodes may be used.

[0171] Fig. 27 FIG. 2 shows a multi-analyte measurement circuit 2700 configured to measure two analytes. The multi-analyte measurement circuit 2700 is substantially similar to Fig.21 The measurement circuit 2000 shown in FIG. 27 is the same as that shown in FIG. 27, except that the three-electrode battery 100 has been replaced by a measurement battery 2702 including a first working electrode WE1 and a second working electrode WE2, a common counter electrode CE, and a common reference electrode RE. The counter electrode CE is coupled to the output of the IDAC 2002. The measurement circuit 2700 also includes a multiplexer 2704 having an input coupled to the first working electrode WE1 and the second working electrode WE2 and an output coupled to a reference voltage (ground GND in this case). The multiplexer 2704 is configured to selectively couple the first working electrode WE1 or the second electrode WE2 to the reference voltage based on a working electrode selection signal WESELECT received at the multiplexer 2704. The WE selection signal WESELECT can be provided by the control module 2008 or another module or circuit (not shown). During operation, the measurement circuit 2700 can select to measure the characteristics of the battery 2702 using the first working electrode WE1 by controlling the multiplexer 2704 to couple the first working electrode WE1 to the reference voltage. Likewise, the measurement circuit 2700 may select to measure the characteristics of the battery 2702 using the second working electrode WE2 by controlling the multiplexer 2704 to couple the second working electrode WE2 to a reference voltage.

[0172] Fig.28 A multi-analyte measurement circuit 2800 is shown, which is Fig. 27 A variation of the measurement circuit 2700 shown in FIG. 2800 and Fig. 27The difference in the measurement circuit in is the configuration of the battery 2702, the multiplexer 2704 and the IDAC 2002. The multiplexer 2704 is replaced by a multiplexer 2804 configured to multiplex a pair of output terminals to an input terminal. The electrode CE is coupled to a reference voltage Vref (e.g., a power supply voltage VDD). The working electrodes WE1, WE2 are each coupled to a corresponding output terminal of the multiplexer 2804. A separate input terminal of the multiplexer 2804 is coupled to an output terminal of the IDAC 2002. The multiplexer is configured to couple the input terminal of the multiplexer 2804 (i.e., the output terminal of the IDAC 2002) to one of the output terminals of the multiplexer 2804 (i.e., the first working electrode WE1 or the second working electrode WE2) based on a working electrode selection signal WESELECT. Similar to Fig. 27 The multiplexer 2704 of WE selection signal WESELECT can be provided by the control module 2008 or another module or circuit (not shown). During operation, the measurement circuit 2800 can select to use the first working electrode WE1 to measure the characteristics of the battery 2702 by controlling the multiplexer 2804 to couple the first working electrode WE1 to the reference voltage. Similarly, the measurement circuit 2800 can select to use the second working electrode WE2 to measure the characteristics of the battery 2802 by controlling the multiplexer 2804 to couple the second working electrode WE2 to the reference voltage.

[0173] The comparator described in the above-mentioned embodiments is usually operated in a hysteresis mode. Operating the comparator in this mode can significantly save power because the output of the comparator can be easily decoded using a low-power signal processing technique for measuring the duty cycle of the output waveform. However, this is at the expense of increasing noise in the form of PWM tones. In some cases, it may be advantageous to suppress PWM tones to improve the measurement accuracy and / or quality of electrochemical cell characteristics. To this end, in some embodiments, the comparator described herein can be switched from a (low power) hysteresis mode to a (higher power) ∑-Δ mode, in which the comparator does not implement hysteresis. When doing so, decoding becomes more time and / or processor intensive due to the output being equivalent to a one-bit ordinal number running at a frequency latched by the comparator. However, any PWM tone will be suppressed, thereby improving the performance of any measurement circuit in which a switchable comparator is implemented.

[0174] In the above-mentioned embodiment, DC current is applied to the counter electrode CE of the various measurement cells shown. However, in some cases, in order to irradiate or excite the measurement cell at a given frequency, it may be advantageous to apply alternating current (AC) to the counter electrode CE of any measurement cell. For simplicity, with reference to FIG5 , one way of applying AC to the counter electrode CE in the measurement cell 100 is to change the limit cycle of the hysteresis comparator 502. This can be achieved by controlling the hysteresis amount applied by the hysteresis comparator 502.

[0175] As previously described, the output Q of the hysteresis comparator 502 will change state when the feedback signal SFB reaches a relevant threshold (e.g. exceeds +H or falls below -H), and will remain in that state until another threshold is reached. Therefore, the time the signal remains in one state, i.e. the duration α or β, will depend on the time it takes for the feedback signal to change by the amount 2H. This will depend on the bias signal VBIAS, and therefore on the difference between the input signal SIN and the feedback signal SFB, but will also clearly depend on the threshold and the amount of hysteresis applied.

[0176] In some embodiments, the amount of hysteresis applied by the comparator 502 can be controlled. As will be appreciated by those skilled in the art, there are many ways in which the hysteresis applied by a hysteresis comparator can be varied.

[0177] The hysteresis applied by comparator 502 can be controlled in order to control the cycle period (and cycle frequency). To this end, the output cycle period of output signal Q can be monitored and used to adjust the applied hysteresis. For example, a slave decoder (such as Figure 8 The current cycle period (or frequency) of the output signal Q is determined by the count value α+β generated or derived by the decoder 800).

[0178] Therefore, the limit cycle period / frequency can be controlled so as to apply a time-varying current to the counter electrode CE at a predetermined frequency. This can be achieved by adjusting the bias voltage VBIAS or by setting a delay element (such as Fig.10 In the case of the delay element 1002 shown in FIG. 1 , the limit cycle is changed by changing the delay of the delay element.

[0179] Control of the applied hysteresis also allows the cycle period of the output signal Q to be controlled to remain substantially constant on a cycle-by-cycle basis. Additionally, or alternatively, hysteresis control can be used to enable operation in different modes, such as to provide a tradeoff between performance and power consumption. For example, under certain conditions, such as when fewer analyte concentration samples are required, the limit cycle frequency of the time-encoded signal can be reduced to save power. When it is determined that more samples are required in a shorter period, the limit cycle can be increased. Adaptive hysteresis control is described in more detail in U.S. Patent No. 10,256,837, the entire contents of which are incorporated by reference in their entirety.

[0180] In some embodiments, the characteristics of the loop filter (e.g., electrochemical cell 100) can be inferred from known variables and measured parameters. Referring to FIG. 5, as an example, the hysteresis applied by the comparator 502 can be known, and the limit cycle of the output signal Q can be measured. Since the impedance of the loop filter including the battery 100 is proportional to the hysteresis and the limit cycle, the total impedance of the system can be determined. If the loop filter includes N circuit elements (for example), by measuring the limit cycle at each of N different hysteresis values ​​(implemented by the comparator), N equations can be derived and solved to fully define the parameters of each of the N elements of the loop filter. In some embodiments, the relationship between hysteresis and limit cycle can be defined in a lookup table, which can be used to determine one or more characteristics of the battery 100. It should be understood that the technology can be implemented with respect to any measurement circuit described in the present disclosure.

[0181] Those skilled in the art will recognize that some aspects of the above-described apparatus and methods may be embodied as processor control code on, for example, a non-volatile carrier medium such as a disk, CD or DVD-ROM, a program memory such as a read-only memory (firmware), or a data carrier such as an optical or electrical signal carrier. For many applications, embodiments of the present invention will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit) or an FPGA (field programmable gate array). Thus, the code may include conventional program code or microcode, or, for example, code for setting or controlling an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device such as a reprogrammable logic gate array. Similarly, the code may include code for a hardware description language such as Verilog TM or VHDL (very high speed integrated circuit hardware description language). As will be understood by those skilled in the art, the code may be distributed between multiple coupled components that communicate with each other. Where appropriate, the embodiments may also be implemented using code running on a field (re)programmable analog array or similar device to configure analog hardware.

[0182] Note that as used herein, the term module will be used to refer to a functional unit or block that may be implemented at least in part by a dedicated hardware component such as a custom circuit system, and / or at least in part by one or more software processors or appropriate code running on an appropriate general-purpose processor, etc. A module may itself include other modules or functional units. A module may be provided by multiple components or sub-modules that need not be co-located, and may be provided on different integrated circuits and / or run on different processors.

[0183] Embodiments may be implemented in a host device, particularly a portable and / or battery-powered host device, such as a mobile computing device (e.g., a laptop or tablet computer), a game console, a remote control device, a home automation controller or household appliance including a home temperature or lighting control system, a toy, a machine (such as a robot), an audio player, a video player, or a mobile phone (e.g., a smartphone).

[0184] It should be noted that the above embodiments illustrate rather than limit the present invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may perform the functions of several units recited in the claims. Any reference numbers or signs in the claims should not be construed as limiting their scope.

Claims

1. A circuit system for measuring a characteristic of an electrochemical cell, the circuit system comprising: a hysteresis comparator having a first comparator input, a second comparator input, and a comparator output; a feedback path located between the comparator output and the second comparator input and configured to provide a feedback signal to the second comparator input; as well as a loop filter configured to apply filtering to the feedback path to produce the feedback signal, wherein the loop filter includes the electrochemical cell; in: The electrochemical cell comprises at least one working electrode, a counter electrode and a reference electrode, and the comparator output is coupled to the counter electrode and the reference electrode is coupled to the second comparator input; or The electrochemical cell includes at least one working electrode and a counter electrode, wherein the comparator output is coupled to the counter electrode via a first impedance. 2 . The circuit system of claim 1 , wherein the hysteresis comparator is hysteresis in voltage or hysteresis in time.

3. A circuit system as described in claim 1, wherein the electrochemical cell includes the at least one working electrode and the counter electrode, wherein the comparator output is coupled to the counter electrode via the first impedance, and wherein the counter electrode is coupled to the second comparator input. The circuit system of claim 1 , wherein the first impedance comprises an inductor. 5 . The circuit system of claim 1 , wherein the first impedance comprises a current digital-to-analog converter (IDAC). 6 . The circuit system of claim 5 , wherein the IDAC is arranged in series between the comparator output and the counter electrode.

7. The circuit system of claim 1, wherein the first impedance comprises a finite impulse response digital-to-analog converter (FIR DAC).

8. The circuit system of claim 1, further comprising a sample-and-hold circuit coupled between the comparator output and the first impedance.

9. The circuit system of claim 1 or 2, further comprising a control circuit system configured to adapt the hysteresis of the comparator based on a limit cycle frequency or a limit cycle period of a comparator output signal derived from the comparator output terminal.

10. The circuit system of claim 9, further comprising decoding circuitry configured to extract the comparator output signal and output a data signal.

11. The circuit system of claim 10, wherein the decoding circuit system is further configured to determine the limit cycle frequency of the limit cycle period and output the limit cycle frequency or the limit cycle period to the control circuit system.

12. The circuit system of claim 9, wherein the control circuit system is further configured to estimate a load capacitance of the electrochemical cell based on the limit cycle frequency or the limit cycle period.

13. A circuit system as described in claim 1, wherein the electrochemical cell includes the at least one working electrode, the counter electrode and the reference electrode, wherein the comparator output is coupled to the counter electrode and the reference electrode is coupled to the second comparator input, and wherein the circuit system also includes an external capacitor coupled between the counter electrode and the working electrode.

14. A circuit system as described in claim 1, wherein the electrochemical cell includes the at least one working electrode, the counter electrode and the reference electrode, wherein the comparator output is coupled to the counter electrode and the reference electrode is coupled to the second comparator input, and wherein the at least one working electrode is coupled to a reference voltage.

15. The circuit system of claim 14, wherein the reference voltage is variable.

16. A circuit system as described in claim 1, wherein the electrochemical cell includes the at least one working electrode, the counter electrode and the reference electrode, wherein the comparator output is coupled to the counter electrode and the reference electrode is coupled to the second comparator input, and wherein the circuit system also includes one or more additional counter electrodes.

17. The circuit system of claim 16, further comprising a multiplexer configured to switchably couple a reference voltage between the counter electrode and the one or more additional counter electrodes.

18. The circuit system of claim 16, further comprising: an additional hysteresis comparator for each of the one or more additional pairs of electrodes, each additional hysteresis comparator comprising an additional first comparator input, an additional second comparator input, and an additional comparator output; An additional feedback path is located between each additional comparator output and each additional second comparator input and is configured to provide an additional feedback signal to the corresponding additional second comparator input, wherein each additional comparator output is coupled to a corresponding additional pair of electrodes.

19. A circuit system as described in claim 1, wherein the electrochemical cell includes the at least one working electrode, the counter electrode and the reference electrode, wherein the comparator output is coupled to the counter electrode and the reference electrode is coupled to the second comparator input, and wherein the circuit system also includes one or more additional working electrodes.

20. The circuit system of claim 19, further comprising a multiplexer configured to switchably couple a reference voltage between the working electrode and the one or more additional working electrodes.

21. The circuit system of claim 19, further comprising: an additional hysteresis comparator for each of the one or more additional working electrodes, each additional hysteresis comparator comprising an additional first comparator input, an additional second comparator input, and an additional comparator output; An additional feedback path is located between each additional comparator output and each additional second comparator input and is configured to provide an additional feedback signal to the corresponding additional second comparator input, wherein each additional comparator output is coupled to a corresponding additional working electrode.

22. The circuit system of claim 16, wherein hysteresis switching of the hysteretic comparator and each additional hysteretic comparator is controlled to minimize interference between the comparator output and each additional comparator output.

23. The circuit system of claim 22, wherein controlling the hysteretic switching comprises interleaving hysteretic switching of the comparator and each additional comparator.

24. The circuit system of claims 1 or 2, wherein the electrochemical cell is configured to sense a plurality of different analytes.

25. The circuit system of claim 24, wherein the different analytes are selected from a list consisting of two or more of glucose, lactate, and ketones.

26. The circuit system of claim 1 or 2, wherein the comparator is synchronous.

27. The circuit system of claim 1 or 2, wherein the comparator is asynchronous.

28. The circuit system of claim 27, further comprising a counter, the comparator output being coupled to a data input of the counter.

29. The circuit system of claim 28, further comprising a voltage controlled oscillator arranged between the comparator output and the data input.

30. The circuit system of claim 1 or 2, further comprising bias circuitry for applying a bias voltage to the first comparator input.

31. The circuit system of claim 30, wherein the bias circuit system comprises a filter configured to receive an input voltage and generate the bias voltage.

32. A circuit system as described in claim 31, wherein the filter includes an integrator having a first integrator input terminal for receiving the input voltage, a second integrator input terminal and an integrator output terminal, wherein the integrator output terminal is coupled to the first comparator input terminal and the first integrator input terminal via a first capacitor, and wherein the second integrator input terminal is coupled to the second comparator input terminal.

33. The circuit system of claim 31, wherein the bias voltage is controlled to vary a limit cycle frequency of the comparator.

34. The circuit system of claim 33, wherein the limit cycle is controlled to provide an alternating current (AC) at the comparator output.

35. The circuit system of claim 33, wherein the limit cycle is controlled to provide a sinusoidal signal at the comparator output.

36. The circuit system of claims 1 or 2, further comprising a holding circuit system configured to hold an electrode of the electrochemical cell at a predetermined voltage.

37. The circuit system of claim 36, wherein the hold circuit system is further configured to de-energize the comparator while the electrode of the electrochemical cell is held at a predetermined voltage.

38. A circuit system as described in claim 1 or 2, wherein the polarity of the comparator is reversed every switching cycle of the comparator.

39. The circuit system of claim 38, wherein the reversal of the polarity of the comparator is synchronized with a rising edge or a falling edge of an output signal at an output terminal of the comparator.

40. An electronic device comprising a circuit system as claimed in any preceding claim.

41. The electronic device of claim 40, wherein the device comprises a continuous glucose monitor.

42. An electronic device as described in claim 40 or 41, wherein the device comprises a mobile computing device, a laptop computer, a tablet computer, a game console, a remote control device, a home automation controller or household appliance, a toy, a robot, an audio player, a video player, or one of a mobile phone and a smart phone.

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