Dynamically allocate cache memory as RAM

Abstract

An apparatus includes a cache controller circuit and a cache memory circuit, the cache memory circuit further comprising a cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a currently in-use portion of the cache memory circuit. The request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured to, in response to the request, convert the one or more cache lines to directly addressable random access memory (RAM) by excluding the one or more cache lines from caching operations.

Description

Technical Field

[0001] The embodiments described herein relate to a system on a chip (SoC), and more particularly, to a method for operating a cache memory. Background Art

[0002] A system on chip (SoC) integrated circuit (IC) typically includes one or more processors serving as the central processing unit (CPU) of the system, as well as various other components, such as memory controllers and other agents. As used herein, an "agent" refers to a functional circuit capable of initiating a transaction via a bus circuit or serving as a destination for a transaction. Thus, a general-purpose processor, a graphics processor, a network interface, a memory controller, and other similar circuits may be referred to as an agent. As used herein, a "transaction" refers to an exchange of data across one or more bus circuits between two agents. Transactions from an agent that read data from a memory circuit or store data to a memory circuit are typical types of transactions and can include large amounts of data. A memory circuit can use multiple clock cycles to access data within its memory cells.

[0003] Cache memory is frequently used in SoCs to support the increased performance of processors by reducing the latency associated with transactions with system memory and / or non-volatile storage memory. Cache memory can store local copies of information stored at frequently accessed memory addresses. These local copies can have a shorter latency for accessing cached values ​​to agents compared to performing memory accesses to the target memory address. When a memory access is made to a target address that is not currently cached, the addressed memory can be accessed, and values ​​from multiple consecutive addresses (including the target address) can be read as a group and then cached to reduce future access times. When cached information in a cache line becomes invalid or it is determined that the cached information has not been accessed frequently, the cached information can be invalidated and marked for eviction, allowing it to be overwritten by other information being accessed by the processor of the SoC. Summary of the Invention

[0004] In an embodiment, an apparatus includes a cache controller circuit and a cache memory circuit, the cache memory circuit further comprising a cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. The request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may also be configured to, in response to the request, convert one or more cache lines to directly addressable random access memory (RAM) by excluding the one or more cache lines from cache operations.

[0005] In another example, the cache controller circuitry may be further configured to support a real-time virtual channel for memory transactions in the identified address region and prioritize memory transactions received via the real-time virtual channel over memory transactions received via the bulk virtual channel. In an example, the cache controller circuitry may be further configured to determine that the address region is included in the secure access region. In response to this determination, the cache controller circuitry may be further configured to ignore memory transactions in the address region from agents that are not authorized to access the secure access region.

[0006] In another example, the cache controller circuitry may be further configured to flush one or more cache lines before converting to directly addressable RAM. In an example, the cache controller circuitry may be further configured to issue a write-back request for the active cache line in response to data in the active cache line being written. The cache controller circuitry may also be configured to exclude one or more cache lines from the write-back request.

[0007] In one embodiment, the cache controller circuitry may be further configured to receive a different request to deallocate a portion of the cache memory from the directly addressable RAM. In response to the different request, the cache controller circuitry may be further configured to include one or more cache lines in the cache operation without copying the data stored in the directly addressable RAM while reallocating the one or more cache lines. In another embodiment, the cache controller circuitry may be further configured to generate an error in response to a memory transaction in the directly addressable RAM received after the portion of the cache memory is deallocated. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0009] Figure 1 A block diagram of an embodiment of a system including cache memory and address mapping at two points in time is shown.

[0010] Figure 2 A block diagram of an embodiment of a system including a processor, a cache memory with multiple ways, and an address map is shown.

[0011] Figure 3 Depicts the Figure 1 A block diagram of an implementation scheme of a system.

[0012] Figure 4 shows receiving two write requests Figure 1 A block diagram of an implementation scheme of a system.

[0013] Figure 5A block diagram illustrating an embodiment of a system including two agents sending memory transactions to a cache memory via a network arbiter is shown.

[0014] Figure 6 A block diagram of an embodiment of a system including two agents, one trusted agent and one untrusted agent, that send memory transactions to a cache memory is shown.

[0015] Figure 7 A flow chart illustrating an embodiment of a method for reallocating a portion of a cache memory system to a directly addressable address region.

[0016] Figure 8 A flow chart of an embodiment of a method for receiving a memory transaction from an unauthorized agent and for deallocating a portion of a cache memory system from a directly addressable address region is depicted.

[0017] Figure 9 A block diagram of an embodiment of a system is shown at two points in time where a buffer located in system memory is allocated to cache memory.

[0018] Figure 10 Shown at two different time points Figure 9 A block diagram of an embodiment of a system in which attempts to allocate storage locations to a cache memory are repeated.

[0019] Figure 11 Depicted is a block diagram of an embodiment of a system including a processor core and a DMA that allocates buffers to cache memory.

[0020] Figure 12 Shows the Figure 9 A block diagram of an embodiment of a system in which batch transactions and real-time transactions are used in conjunction with buffers and cache memories.

[0021] Figure 13 A flow chart illustrating an embodiment of a method for allocating buffers to a cache memory system.

[0022] Figure 14 A flow chart depicting an embodiment of a method for using batch transactions and real-time transactions in conjunction with buffer and cache memory is depicted.

[0023] Figure 15 A flow chart illustrating an embodiment of a method for determining a cache miss rate when accessing a buffer allocated to a cache memory is shown.

[0024] Figure 16 Various embodiments of systems including coupled integrated circuits are shown.

[0025] Figure 17 A block diagram of an exemplary computer-readable medium is depicted, according to some embodiments.

[0026] While the embodiments described in this disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and detailed description thereof are not intended to limit the embodiments to the particular forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. DETAILED DESCRIPTION

[0027] Transactions can be categorized into two or more priority levels, such as "real-time" and "batch." Real-time transactions can have a higher priority level than batch transactions and, therefore, can be processed more quickly by the bus circuits and any intermediate agents through which the real-time transactions pass. Agents can use real-time transactions to meet deadlines for completing processing that, if not met, can result in poor performance, incorrect calculations, or even failures in the system. For example, if a low-latency deadline is not met, playback of a video may stall or glitches. Competition for access to the bus circuits and memory circuits from other agents is one source of complexity in meeting such low-latency deadlines.

[0028] Cache memories can be used to alleviate some of the complexity of meeting low-latency deadlines by storing copies of memory locations closer to corresponding agents, thereby reducing bus circuits and / or the number of intermediate agents that real-time transactions must traverse when being processed. Additionally, if multiple cache memories are available, a given cache memory can be accessed by fewer agents, thereby increasing the probability that an agent can access the cache memory while meeting low-latency deadlines. However, cache values ​​can be evicted from a cache memory if they are not being accessed frequently and / or if there is competition for the cached value in the cache memory from other agents.

[0029] Therefore, there is a need for techniques for using cache memory to store values ​​that are used and / or will be used for real-time transactions. Two general methods for using cache memory to achieve faster access to memory areas are presented herein. In the first method, a portion of the cache memory can be allocated to a system bus accessible address area, where the addressable cache memory can be accessed in a manner similar to random access memory (RAM). In order to implement such a technique, a control circuit can be used to allocate a portion of the cache memory as RAM. The cache lines in the allocated portion of the cache memory are refreshed and any dirty data (e.g., data that has been modified in the cache memory without updating the corresponding memory location in the system memory) is written back to the system memory. The cache lines in the allocated portion are enabled for access via the memory mapped address area and are removed from the available cache memory lines. The agent may then be able to directly access the memory mapped address area using real-time transactions, which can be processed in a similar amount of time as the cache location. Since the memory mapped address area is not considered part of the cache during allocation, the values ​​stored in the area are not at risk of being evicted if not accessed for an extended period of time. Figures 1 to 8 Various details of this cache as RAM approach are shown.

[0030] In the second approach, a buffer is allocated within the system memory, where the buffer is intended for use with low-latency memory transactions. In order to reduce the latency for accessing values ​​in the buffer, a buffer can also be allocated within the cache memory. In some embodiments, the cache may include support for high-priority data, including techniques for associating specific cache lines with low-latency transactions. This support may include limiting or eliminating the eviction of associated cache lines. However, cache allocations of large buffers (e.g., buffers sized to be used with video frames, other images, audio files, etc.) may begin to suffer from cache misses because the portion of the buffer allocated toward the end of the cache allocation process has a higher probability of mapping to a cache line now occupied by a previously cached portion of the buffer. If cache allocations begin at one end of the buffer, the opposite end will suffer a higher number of cache misses, making cache misses more frequent as access to the buffer moves toward the last portion to be allocated.

[0031] The disclosed technique attempts to spread cache allocations of portions of a buffer across various locations in the buffer. To accomplish this, the buffer can be logically divided into multiple blocks. An attempt can then be made to allocate the first sub-block from each block into the cache. Subsequently, a further attempt can be made to allocate the second sub-block from each block into the cache. This can be repeated for multiple sub-blocks in each block until attempts have been made to cache all sub-blocks. Such a technique can distribute cache misses for the various sub-block allocations across the entire buffer so that misses are not concentrated toward the end of the buffer. For example, if the buffer is used to process an image, cache misses may occur more consistently throughout the processing of the image, but in a less concentrated manner, rather than having a few misses at the beginning of the image processing and then more frequent misses as the processing approaches the end of the image. As misses occur more frequently, more real-time transactions can be generated to retrieve requested data from system memory. Having a greater number of real-time transactions being processed simultaneously can increase the likelihood of missing low-latency deadlines, which in turn increases the likelihood that users of the system will experience poor performance or system failures. As described later in this disclosure Figures 9 to 13 Details about the distributed caching method are shown.

[0032] Figure 1 A block diagram of one embodiment of a cache memory system at two points in time is shown. As shown, system 100 includes cache controller circuitry 101, cache memory circuitry 105, and address map 110. Cache memory circuitry 105 includes cache lines 120-127. Address map 110 is shown as having four address regions 115a-115d (collectively, address regions 115). System 100 may correspond to a processor circuit, such as a microprocessor, microcontroller, or other form of system on chip (SoC). System 100 may be implemented on a single integrated circuit or by using multiple circuit elements coupled to a circuit board.

[0033] As shown, cache memory circuit 105 can be implemented using any suitable type of memory circuit design, such as static random access memory (SRAM), dynamic RAM (DRAM), ferroelectric RAM (FeRAM or FRAM), magnetoresistive RAM (MRAM), flash memory, etc. Cache memory circuit 105 can be organized using any suitable cache structure, including using multiple ways and / or sets. Cache controller circuit 101 includes circuitry for performing cache operations in cache memory circuit 105, such as maintaining cache tags, determining whether an address associated with a memory transaction is a hit (a cache line currently corresponds to the address) or a miss (no cache line has been filled with data corresponding to the address), issuing cache line fill requests in response to a miss, marking cache lines for eviction, etc. Address mapping 110 includes any suitable combination of software, firmware, and hardware circuitry for determining memory mapping registers and physical addresses for memory circuits. In some embodiments, address mapping 110 includes a translation table for translating logical addresses into physical addresses.

[0034] As shown, cache controller circuitry 101 receives allocation request 145 at time t0. Cache controller circuitry 101 is configured to receive allocation request 145 to reallocate a portion of cache memory circuitry 105 that is currently in use. Allocation request 145 identifies an address region (e.g., address region 115b) in address region 115 that corresponds to one or more of cache lines 120-127 (e.g., cache line 123). Cache controller circuitry 101 receives allocation request 145 at time t0, at which point cache memory circuitry 105 is already in use and one or more of cache lines 120-127 may be in use to cache a location in system memory (not shown). Allocation request 145 may indicate address region 115b by including an address value corresponding to address region 115b. In other embodiments, other forms of indication may be used to identify address region 115b, such as an index value corresponding to address region 115b.

[0035] Each of the address regions 115, when active, may correspond to a plurality of addresses corresponding to memory locations in the cache memory circuit 105, such as one or more of the cache lines 120-127. When a particular one of the address regions 115 is active, the corresponding cache line is not used to cache data, but is instead used as RAM. When the address region is inactive, the corresponding cache line may be used to cache data values. Addresses associated with inactive address regions may be considered illegal addresses and, therefore, may generate an exception if included in a transaction. At time t0, address region 115b is not active (e.g., Figure 1), and therefore no data values ​​can be stored in this region. Address regions 115c and 115d are also inactive, while address region 115a is currently active. In some embodiments, address region 115a may correspond to main system memory and include the addresses of all memory locations and memory-mapped registers that are always enabled when system 100 is active.

[0036] In response to the allocation request 145, the cache controller circuit 101 may be further configured to convert cache line 123 to directly addressable random access memory (RAM) by excluding cache line 123 from cache operations at time t1. Cache line 123 may then be directly addressed using memory transactions addressed to locations within address region 115b. For example, activating address region 115b may include modifying address map 110 such that transactions addressed to locations within address region 115b are routed to memory cells corresponding to cache line 123. Additionally, the cache controller circuit 101 may also set an indication that cache line 123 is unavailable and that no cache data is currently stored in cache line 123. For example, the cache controller circuit 101 may set one or more bits in a cache tag corresponding to cache line 123 that provide such an indication.

[0037] Using such a cache-to-RAM technique enables a process executing in system 100 to allocate a portion of cache memory circuit 105 for use as directly addressable RAM at any point in time during system activity. As previously described, such an allocation can allow a particular agent to reserve memory space with low-latency access times for use with data associated with high-priority transactions, such as real-time transactions. Allocating this space in cache memory circuit 105 can further prevent other agents from gaining use of the allocated portion until the particular agent completes the real-time transaction and can deallocate the portion for use as a cache line 123 again.

[0038] Please note that Figure 1 The system 100 shown in FIG. 1 is only one example. Figure 1 The illustration is simplified to highlight the features relevant to the present disclosure. Various embodiments may include additional components and / or different configurations of components. For example, only eight cache lines and four address regions are shown. In other embodiments, any suitable number of cache lines and address regions may be implemented. Although address region 115b is shown as corresponding to a single cache line, in other embodiments, the address region may correspond to any suitable number of cache lines and portions of cache lines.

[0039] Figure 1The system shown is shown in a simplified depiction. The cache memory system can be implemented in various ways. Another example of a system with a cache memory is shown in Figure 2 Shown in.

[0040] Move to Figure 2 , a block diagram illustrating an embodiment of a cache memory system that employs the use of pathways in cache memory circuitry. As shown, system 200 includes cache controller circuitry 201, cache memory circuitry 205, address mapping 210, and processor 230. Processor 230 may correspond to a general-purpose processing core, or other type of processing circuitry capable of processing data and issuing memory requests. Except as described below, the elements of system 200 perform the functions described for Figure 1 The functions described by similarly named and numbered components.

[0041] As shown, cache memory circuit 205 includes a cache memory having multiple paths 240a-240d and multiple sets 250-257. Processor 230 is configured to use an address map 210 including active and inactive address regions 215 to issue memory requests. In the illustrated embodiment, when system 200 is active, address region 215m is always active and can include addresses for main system memory and various registers. When processor 230 issues a memory request (e.g., an address in address region 215m) to system memory, cache controller circuit 201 uses the extraction address included in the memory extraction to determine whether the cache line in cache memory circuit 205 currently maintains a valid value corresponding to the system memory location of the extraction address. In order to make such a determination, cache controller circuit 201 can use the extraction address to identify a specific set in set 250-257. For example, cache controller circuit 201 circuit can use at least a portion of the extraction address in a hash algorithm to determine a specific hash value. This hash value can then be used to identify a specific set in set 250-257. Each of the sets 250-257 includes at least one cache line from each of the ways 240. If the cache line in any of the ways 240 for a particular set holds a valid value corresponding to the fetched address, the memory request is said to be a "hit" in the cache memory circuit 205. Otherwise, the memory request is a "miss" in the cache memory circuit 205. The use of multiple ways allows for some flexibility in how the cache controller circuit 201 maps fetched values ​​to cache lines of the cache memory circuit 205.

[0042] As described above, cache memory circuitry 205 can provide lower latency access (also referred to as higher quality of service (QoS)) than access to system memory (such as in address region 215m). Under certain conditions, processor 230 may be required to process a block of data with a high QoS deadline. Because processing data outside of system memory may jeopardize successful processing of the data within the constraints of the high QoS deadline, processor 230 may send an allocation request 245 to cache controller circuitry 201 to request reallocation of a portion of cache memory circuitry 205.

[0043] As shown, cache controller circuitry 201 is configured to receive an allocation request 245 from processor 230 to reallocate a portion of cache memory circuitry 205 as directly addressable memory. Allocation request 245 identifies an address region 215b that is inactive at the time allocation request 245 is received. For example, allocation request 245 may include a specific address value or other type of indication identifying address region 215b. Based on allocation request 245, cache controller circuitry is further configured to select a portion of paths 240 for conversion. As depicted, each of paths 240 may correspond to one of address ranges 215, including path 240b corresponding to address region 215b, as indicated. In other embodiments, cache memory circuitry 205 may include additional paths so that two or more paths may be associated with a given address region. Allocation request 245 may also indicate more than one address region, such as address regions 215b and 215c. In some embodiments, a portion of a path 240 may be half or some other proportion of a particular path. For example, way 240b may include multiple cache lines in each of sets 250-257, such as two lines per set. In such an embodiment, one of the two cache lines from each of sets 250-257 may be reallocated, thereby leaving half of way 240b for use as cache and the other half reallocated to address region 215b.

[0044] To convert path 240b, cache controller circuitry 201 may be configured to set corresponding indications in cache tags corresponding to specific cache lines included in the selected portion of the path. Cache lines 250b-257b are included in path 240b and, as shown, are selected for reallocation to address region 215b. Adding corresponding indications to the cache tags for each of cache lines 250b-257b removes the corresponding cache line from use as cache memory. Such indications may cause cache controller circuitry 201 to ignore cache lines 250b-257b when determining whether a received memory request is a hit or miss in cache memory circuitry 205, and may further prevent cache controller circuitry 201 from mapping an address resulting from a cache miss to any of cache lines 250b-257b. Thus, when these indications in the cache tags are set, cache lines 250b-257b are effectively removed from cache memory use.

[0045] The cache controller circuit 201 is further configured to map cache lines 250b-257b in path 240b for use in the identified address region 215b. As shown, address region 215b includes multiple addresses that may be reserved for use with the reallocated cache lines 250b-257b and therefore may not be mapped to any other memory location or register. When address region 215b is inactive, attempts to access these addresses may result in the generation of an exception and / or the return of default values. The cache controller circuit 201 may be further configured to set a corresponding realtime indicator in the cache tag corresponding to a particular cache line 250b-257b. Such a realtime indicator may indicate that the cache line 250b-257b, and therefore the addresses in address region 215b, are associated with a realtime transaction having a higher priority than a batch transaction. Therefore, a memory access to any of the reallocated cache lines 250b-257b may be treated as a realtime transaction, even if a realtime transaction is not explicitly used in a memory access.

[0046] In addition, cache controller circuitry 201 may be further configured to flush one or more of cache lines 250b-257b in path 240b for use in address region 215b prior to mapping path 240b. Since cache memory circuitry 205 may be in use before processor 230 issues allocation request 245, one or more of the cache lines in path 240b may be available for cache memory locations, such as locations in address region 215m. If the current cached value matches the value in the corresponding location in address region 215m, then when the corresponding cache line is mapped to address region 215b, these values ​​may be simply cleared or ignored. However, if a value cached in path 240b has been modified but not yet written back to address region 215m, such a value may be referred to as "dirty," and a flush command may be issued to write the dirty value back to the system memory location in address region 215m. For example, in the illustrated example, cache lines 251b, 254b, and 257b contain dirty data. Cache controller circuitry 201 issues flush commands 248 to write dirty values ​​in these cache lines back to corresponding locations in address region 215m. One or more flush commands may be issued before translating cache lines of way 240b to directly addressable memory locations in address region 215b.

[0047] After processing a data block with a high QoS deadline, processor 230 may not immediately use the high QoS directly addressable memory in address region 215 b and may be configured to issue a request to deallocate path 240 b. Cache controller circuitry 201 may be further configured to include path 240 b in cache operations in response to receiving a request to deallocate directly addressable memory in address region 215 b. In response to the request to deallocate directly addressable memory, values ​​stored in the directly addressable memory when path 240 b was deallocated are not relocated. Any values ​​written to address region 215 b during the deallocation period may be deleted or ignored and subsequently overwritten upon returning path 240 b for use in cache memory circuitry 205 operations.

[0048] It is noted that using the paths 240 of the cache memory circuit 205 to reallocate cache memory to directly addressable memory can be implemented with an acceptable amount of additional logic circuitry while allowing the cache memory circuit 205 to continue operating with little or no interruption. In contrast, implementing cache memory reallocation on an individual cache line basis may require additional, larger logic circuitry, particularly where the cache memory is large and / or has many sets and paths. On the other hand, further limiting the amount of cache memory that can be reallocated may not provide an adequate solution to manage the need for high QoS memory locations with ongoing cache operations. For example, if the reallocation of the cache memory circuit 205 is limited to half of the cache, the amount of memory being allocated may be much larger than necessary to process high QoS data, further reducing the capacity of the cache and potentially reducing the efficiency of agents utilizing the cache.

[0049] Also note that Figure 2 The embodiment of FIG. 2 is a depiction of a cache memory system. Although only four ways and eight sets are shown, in other embodiments, any suitable number of cache ways and sets may be included. Additionally, although five address regions are depicted, address map 210 may be divided into any suitable number of regions.

[0050] Figure 2 The description of describes the deallocation of a directly addressable memory location. Deallocation of a directly addressable memory region back to cache memory can be implemented in various ways. Figure 3 Depicted this way.

[0051] Steering Figure 3 , Figure 1 The system is again shown at two different points in time. Figure 1 As shown, system 100 includes cache controller circuitry 101, cache memory circuitry 105, and address mapping 110. At time t0, cache line 123 is mapped to directly addressable memory in address region 115b and is therefore unavailable for cache operations. As shown, cache controller circuitry 101 is configured to, for example, receive cache requests from an agent such as Figure 2115b). The processor 230 in FIG. 115b receives a deallocation request 345 to deallocate cache line 123 from directly addressable memory in address region 115b. In response to the deallocation request 345, the cache controller circuit 101 is further configured to include cache line 123 in cache operations without copying the data stored in the directly addressable memory while cache line 123 is reallocated to address region 115b. For example, as described above, the cache controller circuit 101 may set an indication in a cache tag associated with cache line 123 to indicate that cache line 123 is reallocated to directly addressable memory. To deallocate cache line 123, the cache controller circuit 101 may clear the indication, thereby removing cache line 123 from address region 115b and including cache line 123 in subsequent cache operations.

[0052] When the indication in the associated cache tag is cleared, the values ​​written to cache line 123 when allocated to address region 115b may be deleted or ignored. Because the addresses in address region 115b may not be realized elsewhere in address map 110, no write-back request may be issued to copy these values. Unless the agent utilizing address region 115b explicitly copies the data from address region 115b to another location in address map 110 while it is active, the values ​​in address region 115b may be lost after the deallocation is complete.

[0053] At time t1, a memory transaction 350 is issued by an agent to access a value in address region 115b. Cache controller circuitry 101 is configured to generate an error message 355 in response to receiving memory transaction 350 after address region 115b has been deallocated. In some embodiments, error message 355 may be generated if memory transaction 350 includes a write or modification to an address in address region 115b. Otherwise, if memory transaction 350 only includes a read access to address region 115b, cache controller circuitry 101 may return a specific default value, such as all zero bits or all one bits, to the requesting agent, instead of or in addition to generating error message 355. Generating error message 355 may be implemented using various techniques. For example, error message 355 may be generated by asserting an exception signal, which in turn causes a specific process to be executed by one or more processor cores in system 100. Generating error message 355 may include returning a specific value to the agent that issued memory transaction 350 indicating that address region 115b has been deallocated.

[0054] Figure 3 Depicts the deallocation of cache lines from directly addressable address regions. Continue to Figure 4, system 100 is depicted with address region 115b active (using cache line 123) and illustrates how cache operations and accesses to address region 115b may be processed simultaneously. Figure 4 System 100 in FIG. 4 shows cache controller circuit 101 receiving write requests 445 and 446 .

[0055] As shown, write request 445 comprises a write request to write data to one or more locations currently cached in cache line 121 of cache memory circuit 105. Similarly, write request 446 comprises a write request to write data to one or more locations in address region 115b, which is implemented by reallocating cache line 123 from cache memory circuit 105 to address map 110. Cache controller circuit 101 is configured to issue a write-back request 447 for cache line 121 in response to write request 445. The modified values ​​in cache line 121 are included in write-back request 447 along with the corresponding target address in system memory. Write-back request 447 causes these modified values ​​to be updated at the target address in system memory. If cache line 121 is evicted and then mapped to a different address in system memory, the target address in system memory may still have the most recent value.

[0056] As shown, cache controller circuit 101 is further configured to exclude cache line 123 from write-back requests. Write request 446 may modify one or more values ​​in address region 115b (including cache line 123). Although the values ​​in cache line 123 are modified, cache controller circuit 101 is configured to ignore these modifications with respect to the write-back command. Address region 115b, although including cache line 123, is treated as an endpoint memory destination. No target address in system memory corresponds to the address in address region 115b. Therefore, in response to write request 446, the modified value stored in cache line 123 may not be updated in another memory circuit.

[0057] Note, however, that different cache memories may reside between cache memory circuitry 105 and the processing circuitry issuing write request 446. For example, cache memory circuitry 105 may be an L2 cache, and the processing circuitry issuing write request 446 may include an L1 cache. In such an embodiment, the L1 cache may cache at least some of the values ​​stored in address region 115 b (e.g., in cache line 123).

[0058] Also note that Figure 3 and Figure 4The embodiments shown are merely examples for illustrating the disclosed concepts. For the sake of clarity, the system 100 shown in these figures is simplified. In other embodiments, additional elements may be included, such as one or more agents that issue memory transactions that cause the described operations. In addition, although Figure 3 and Figure 4 use Figure 1 system 100, but the described techniques may be applied to Figure 2 system 200.

[0059] The use of real-time transactions for use with the disclosed technology is described above in various capacities.Both real-time and batch transactions can be used for memory requests targeting the cache-based address regions described herein. Figure 5 An example is shown of how using transactions with different QoS levels can be implemented.

[0060] Now move to Figure 5 , depicts a system in which an arbiter is used to schedule transactions on a system network. System 500 includes cache controller circuitry 501 and address mapping 510, which may correspond to Figure 1 、 Figure 3 and Figure 4 System 500 also includes agents 530a and 530b (collectively, agents 530), network arbiter circuit 540, and bus circuit 545. Figure 5 Flow is shown for two memory transactions (memory transactions 550 and 555 , respectively, an immediate transaction and a batch transaction) addressed to address region 515 b , which is implemented using one or more cache lines from cache controller circuitry 501 using techniques such as described above.

[0061] At a first point in time, agent 530b issues a bulk memory transaction 555 with a destination in address region 515b. Figure 1 and Figure 2 5. As shown in FIG5 , address region 515b comprises a portion of cache memory associated with cache controller circuitry 501, as illustrated in FIG5 . As illustrated, memory transaction 555 is received by network arbiter circuitry 540 on its way to cache controller circuitry 501. Because memory transaction 555 is a batch transaction, network arbiter circuitry 540 places memory transaction 555 in batch queue 565a until bus circuitry 545 has available bandwidth to forward memory transaction 555 to cache controller circuitry 501.

[0062] Bus circuitry 545 includes a set of conductors that couple cache controller circuitry 501 to network arbiter circuitry 540. In some embodiments, bus circuitry 545 may include a sufficient number of conductors to support independent physical bulk and real-time channels. However, as shown, bus circuitry 545 does not include such a number of conductors and, therefore, uses the same set of conductors to transmit both real-time and bulk memory transactions, utilizing virtual bulk and real-time channels to support the respective QoS levels for each type of transaction. Accordingly, network arbiter circuitry 540 uses a prioritization scheme to select between real-time (RT) queue 560a and bulk queue 565a for the next transaction to be sent via bus circuitry 545. For example, network arbiter circuitry 540 may first send transactions in RT queue 560a and then, after RT queue 565a is empty, send transactions in bulk queue 560a. In other embodiments, additional considerations may be included in the selection process to avoid allowing bulk queue 565a to reach a full state or stalling bulk transactions in bulk queue 565a for an excessive amount of time.

[0063] As used herein, a "channel" is a medium for transmitting information between a source agent (e.g., a processor circuit) and a destination agent (e.g., a memory circuit). A channel may include wires (including conductive traces on a circuit board or integrated circuit) and various other circuit elements. In some embodiments, a channel may also include an antenna and electromagnetic waves of a specific frequency or frequency range. A "physical" channel refers to the circuit elements that comprise the channel. A "virtual" channel refers to two or more different "channels" implemented on the same physical channel. Various technologies can be used to implement virtual channels. For example, channel virtualization can be implemented in a channel interface by including a corresponding queue for each virtual channel. An agent uses the queue for the corresponding channel to send and receive transactions on a given channel. Other circuits can then control channel arbitration between the corresponding queues to select a specific transaction to be sent when the channel is available. In other embodiments, an agent may be responsible for associating various transactions with corresponding virtual channels. In such embodiments, the agent may maintain appropriate data structures for assigning transactions to appropriate virtual channels and then arbitrate to select a given transaction to be sent when the channel is available.

[0064] At a second point in time, the network arbiter circuit 540 selects a memory transaction 555 from the bulk queue 565a and forwards it to the cache controller circuit 501. The cache controller circuit 501 may then place the memory transaction 555 in the bulk queue 565b until bandwidth is available to process the memory transaction 555 in the address region 515b. Simultaneously, at a third point in time after the second point in time, the agent 530a sends the memory transaction 550 to the cache controller circuit 501 via the bus circuit 545. The network arbiter circuit 540 receives the real-time memory transaction 550 and places it in the RT queue 560a. At a subsequent fourth point in time, the memory transaction 550 is selected by the network arbiter circuit 540 and sent to the cache controller circuit 501, which places the received memory transaction 550 in the RT queue 560b.

[0065] In the illustrated example, memory transactions 550 and 555 are both in RT queue 560b and bulk queue 565b, respectively. Cache controller circuitry 501 is configured to support both real-time and bulk virtual channels for memory transactions in address regions 515a-515d. Therefore, cache controller circuitry 501 prioritizes memory transactions 550 received via the real-time virtual channel over memory transactions 550 received via the bulk virtual channel, using a selection scheme similar to that of network arbiter circuitry 540. At a fifth point in time, following the fourth point in time, cache controller circuitry 501 skips memory transaction 555 waiting in bulk queue 560b and instead selects memory transaction 550 waiting in RT queue 565b. Subsequently, at a sixth point in time, memory transaction 555 meets the selection criteria and is processed in address region 515b.

[0066] Note that system 500 is an example used to highlight the disclosed technology. For the sake of clarity, Figure 5 In other embodiments, additional elements may be included, such as additional agents, multiple bus circuits, associated network arbiter circuits, etc.

[0067] Figure 5 Describes how the disclosed technology can be used to handle memory transactions with different QoS levels. The disclosed cache controller circuit can be further configured to manage address regions that fall within different types of secure memory regions. A description of such an embodiment is presented next.

[0068] Go to Figure 6, shows an embodiment of a system that includes support for open access and secure access memory regions. System 600 includes cache controller circuitry 601, address map 610, system memory map 620, trusted agent 630, and untrusted agent 635. As shown, system memory map 620 is divided into two regions, an open access region 623 and a secure access region 627. Address region 615b in address map 610 corresponds to reallocated cache memory, as previously described, and is mapped within secure access region 627. Trusted agent 630 and untrusted agent 635 issue memory transactions 650 and 655, respectively, both targeting a destination address in address region 615b.

[0069] As shown, the system memory map 620 includes a memory map of all address regions included in the system 600. These address regions can be categorized into two types of security regions: an open access region 623 and a secure access region 627. The open access region includes all memory ranges to which any agent within the system 600 (including both trusted agents 630 and untrusted agents 635) can issue memory transactions. The open access region can include memory for general application use, including, for example, memory for processing images, audio files, and executing general applications. The secure access region 627 includes memory ranges with restricted access. Only agents categorized as trusted (such as trusted agent 630) can access memory locations within the secure access region 627. Memory transactions from untrusted agents to addresses in the secure access region 627 can be ignored or can result in the generation of an error indication, such as an exception.

[0070] In the example shown, both the trusted agent 630 and the untrusted agent 635 issue respective memory transactions 650 and 655 for a destination address in the address region 615 b. To support secure access regions, the cache controller circuitry 601 is configured to determine that the address region 615 b is included in the secure access region 627. In response to this determination, the cache controller circuitry 601 is configured to ignore the memory transaction 655 from the untrusted agent 635, which is not authorized to access the secure access region 627. However, the trusted agent 630 is authorized to access the secure access region 627, and therefore, the cache controller circuitry 601 is configured to process the memory transaction 650 in the address region 615 b.

[0071] In response to receiving the memory transaction 655, the cache controller circuit 601 may be further configured to generate an error indication. For example, the cache controller circuit 601 may return an error code to the untrusted agent 635, the error code including a specific value indicating an access to an unauthorized address. Alternatively or additionally, the cache controller circuit 601 may be further configured to assert one or more exception signals, such as an illegal address exception and / or a security violation exception.

[0072] It should be noted that system 600 is merely an example. For clarity, various components may be omitted from system 600. In other embodiments, system 600 may include additional secure access zones. For example, multiple different secure access zones may be implemented, each corresponding to a different level of secure access and, therefore, accessible by different combinations of trusted agents.

[0073] The above about Figures 1 to 6 The described circuits and techniques describe various techniques for reallocating a portion of cache memory to a directly addressable address region. Various methods can be used to implement these disclosed techniques. Figures 7 and 8 Two such methods are described.

[0074] Now move to Figure 7 , a flow chart illustrating an embodiment of a method for reallocating a portion of a cache memory circuit to a directly addressable address region. Method 700 may be performed by cache controller circuitry, such as, respectively Figure 1 、 Figure 2 、 Figure 5 and Figure 6 The method 700 may be performed by a processing circuit executing software or firmware, by a hardware circuit including, for example, logic gates, or a combination thereof. Figure 1 and Figure 7 , method 700 starts in block 710 .

[0075] At block 710, method 700 includes receiving, by cache controller circuitry 101, an allocation request 145 to reallocate a currently in-use portion of cache memory circuitry 105 to directly addressable memory space. As shown, allocation request 145 identifies inactive address region 115b. Allocation request 145 may be received at time t0, at which time cache memory circuitry 105 is already in use and one or more of cache lines 120-127 may be in use to cache locations in system memory. Address region 115b may be indicated by including an address value in address region 115b or an index value corresponding to address region 115b in allocation request 145.

[0076] At block 720, method 700 further includes selecting a cache line 123 of cache memory circuit 105 for conversion based on the identified address region 115b. As shown, cache line 123 may be associated with address region 115b due to software executed in system 100 (such as an operating system). In other embodiments, cache line 123 may be hard-coded into address region 115b based on the circuit design of system 100. Although only one cache line is shown as being selected for use in address region 115b, any suitable number of cache lines may be selected. For example, as shown in reference Figure 2 As described above, the cache memory circuit may include a plurality of ways, and an entire way or a plurality of ways may be selected for use in the directly addressable address region.

[0077] At block 730, method 700 further includes setting, by cache controller circuitry 101, a corresponding indication of the selected cache line 123 to exclude cache line 123 from further cache operations. For example, cache controller circuitry 101 may set a particular bit or bits in a cache tag corresponding to cache line 123 to indicate the use of cache line 123 in address region 115b. Additionally, cache controller circuitry 101 may set a real-time memory indicator indicating that cache line 123 is associated with a real-time transaction having a higher priority than a batch transaction. Such an indication may prevent cache controller circuitry 101 from performing an eviction of the contents of cache line 123 after the cache line 123 has been reassigned to address region 115b. The real-time indication may further prioritize any transaction destined for an address in address region 115b over any batch transaction in the cache controller circuitry 101's queue.

[0078] In some embodiments, method 700 may further include flushing cache line 123 by cache controller circuitry 101 before setting the corresponding indication. Because cache memory circuitry 105 was already in use prior to receiving allocation request 145, valid data may be cached in cache line 123. If any value cached in cache line 123 has been modified and the modification has not yet been written back to the destination location in system memory, a flush command may be issued by cache controller circuitry 101, which generates a write-back request for any location with a modified value currently cached in cache line 123. After the write-back request has been issued, cache line 123 is available for use in address region 115b.

[0079] Using a portion of the cache memory as a directly addressable address region can implement a low-latency memory range that can be used by a particular agent to perform memory accesses with high QoS deadlines that may not be achieved by direct addressing to system memory even if typical cache techniques are used for system memory accesses. By using cache memory circuitry to create a low-latency memory region, a particular agent may be able to buffer data to be processed in the low-latency memory region without the risk of the buffered data being evicted from the cache if it is not accessed within a particular time frame.

[0080] When address region 115 b is active, cache lines 120-122 and 124-127 may be used for cache operations in cache memory circuit 105. For example, data written to a specific address currently cached in cache memory circuit 105 may be written back to a specific address in system memory. However, cache line 123 is not used for cache operations. For example, data written to a different address in cache line 123 in address region 115 b is not written back to system memory. Instead, cache line 123 may serve as the final destination for data written to address region 115 b.

[0081] Method 700 may end at block 730, or may repeat some or all operations. For example, method 700 may return to block 710 in response to cache controller circuit 101 receiving another allocation request. In some embodiments, multiple instances of method 700 may be executed concurrently. For example, cache controller circuit 101 may be able to process a second allocation request while still executing a first allocation request. If system 100 includes multiple cache controller circuits (e.g., for respective cache memory circuits), each cache controller circuit may be able to execute method 700 in parallel. Note that Figure 7 The method is merely an example for allocating a portion of the cache memory as a directly addressable address area.

[0082] Now go to Figure 8 , a flow chart illustrating an embodiment of a method for operating and deallocating a directly addressable address region utilizing a portion of a cache memory. In a manner similar to method 700, method 800 may be performed by cache controller circuitry, such as, respectively, Figure 1 、 Figure 2 、 Figure 5 and Figure 6 The cache controller circuits 101, 201, 501, and 601 shown in FIG. 800 may also be performed by a processing circuit executing software or firmware, by a hardware circuit, or a combination thereof. Figure 1 、 Figure 3 and Figure 8 , the method 800 begins at block 810 , where the cache line 123 has been reallocated to the address region 115 b .

[0083] At block 810, method 800 includes receiving, by cache controller circuitry 101, a memory transaction from an unauthorized agent for address region 115b. Figure 6 As described above, the system memory map of system 100 may include an open access region and one or more secure access regions. Various agents may attempt to access address region 115b, some of which may be authorized to access one or more secure regions, while other agents may not be authorized to access any addresses other than those in the open access region.

[0084] At block 820, method 800 includes ignoring, by cache controller circuitry 101, a memory transaction from an unauthorized agent in response to determining that address region 115b is part of a secure access region. As shown, the address included in the received memory transaction targets a location within address region 115b. Address region 115b may be determined to be within a secure access region of the system memory map that is inaccessible to unauthorized agents. In response to this determination, the received memory transaction is ignored. As described above, an error message may be returned to the unauthorized agent and / or an exception signal may be asserted to indicate, for example, to an operating system, that unauthorized access was attempted.

[0085] At block 830, the method further includes receiving, by the cache controller circuitry 101, a deallocation request 345 to deallocate a cache line 123 of the cache memory circuitry 105 from the directly addressable address region 115b. The activity initiating the request to reallocate a cache line 123 to the address region 115b may be completed by an agent currently using the address region 115b. For example, a processor may request activation of the address region 115b in response to launching a particular application or process within the application. Once the application or process has completed, the address region 115b may no longer be needed and may therefore be returned to use in the cache memory circuitry 105, thereby increasing the amount of data that can be cached at a given time.

[0086] At block 840, method 800 further includes including cache line 123 in the cache operation in response to deallocation request 345. As shown, cache line 123 is returned to cache memory circuitry 105 for use as cache memory. For example, if one or more bits in the cache tag corresponding to cache line 123 are set to include cache line 123 in address region 115b, these bits may be cleared to return cache line 123 to cache memory circuitry 105. When reallocating cache line 123, data stored in address region 115b may be overwritten without needing to be written back to system memory circuitry. Before deallocating cache line 123, it may be necessary to explicitly copy the values ​​stored in address region 115b to other memory locations using corresponding memory transactions. Otherwise, any values ​​from address region 115b may be lost after the deallocation.

[0087] At block 850, the method further includes returning a default value in response to a read request for an address in address region 115 b received after deallocation of cache line 123 of cache memory circuit 105. As shown, if a memory transaction 350 is directed to an address in address region 115 b after deallocation request 345 has been executed, a default value indicating an access to an inactive address is returned to the agent that issued the memory transaction 350.

[0088] At block 860, method 800 further includes generating an error by cache controller circuit 101 in response to a write request to an address in address region 115b received after deallocation. In addition to block 850, or in some embodiments, in place of block 850, an error may be generated, such as assertion of an exception signal. Such an error may provide an indication to a supervisory processor, security circuitry, exception handler circuitry or process, and / or other hardware circuitry or software process that an access to an inactive address has been made. In some cases, such an access may indicate an improperly operating system and may initiate recovery operations, such as a system reset or an exception routine.

[0089] In some embodiments, method 800 may end at block 860, or in other embodiments, some or all operations may be repeated. For example, method 800 may return to block 830 to deallocate different address regions in response to different deallocation requests. Note that the operations of method 800 may be performed in whole or in part in a different order. For example, blocks 810 and 820 may be performed one or more times before initially executing block 830. Blocks 830-860 may be performed without executing blocks 810 and 820.

[0090] The execution of the various operations of methods 700 and 800 can be performed simultaneously and / or in an interleaved manner. For example, cache controller circuit 101 can be configured to manage multiple address regions simultaneously, thereby allowing different processor circuits to utilize different directly addressable address regions in an overlapping manner. Thus, method 800 can be executed in whole or in part while method 700 is being performed.

[0091] Figures 1 to 8 Various implementations of cache as RAM technology are depicted, where a portion of the cache memory is allocated to a system bus accessible address region, thereby enabling a low latency memory region for a given agent or group of agents. Figures 9 to 15 A distributed buffer technique is depicted in which buffers are allocated within system memory and then allocated into cache memory using a specific order that attempts to distribute cache misses across the buffers.

[0092] Continue to Figure 9 , a block diagram of an embodiment of a system including a cache memory at two points in time is shown. As shown, system 900 includes processing circuitry 901, cache memory circuitry 905, and system memory circuitry 910. Cache memory circuitry 905 includes cache lines 920a-920h (collectively, cache lines 920). System memory circuitry 910 is shown as having nine storage locations 935a-935i (collectively, locations 935). System 900 may correspond to a processor, such as a microprocessor, microcontroller, or other form of system on a chip (SoC). System 900 may be implemented on a single integrated circuit or by using multiple circuit elements coupled to a circuit board.

[0093] As shown, the processing circuit 901 may be a processor core in a single-core or multi-core processor complex. The system 900 may include a non-transitory computer readable medium having stored thereon instructions that can be executed by the processing circuit 901 to perform the following Figures 9 to 15 Such non-transitory computer-readable media may include non-volatile memory circuitry included in and / or coupled to system memory circuitry 910. Non-volatile memory circuitry may include, for example, a flash memory array, a solid-state drive, a hard disk drive, a universal serial bus (USB) drive, an optical drive, a floppy disk drive, and the like. System memory circuitry 910 and cache memory circuitry 905 may each include one or more types of RAM, such as SRAM, DRAM, and the like.

[0094] As shown, processing circuitry 901 is configured to allocate storage location 935 in system memory circuitry 910 of system 900 to buffer 915. In various embodiments, processing circuitry 901 and / or another agent (not shown) in system 900 may use buffer 915 to process information associated with an application executing on system 900. To meet the expected performance of the application, access to buffer 915 may have specific quality of service (QoS) requirements. To increase the probability that the QoS requirements are met, processing circuitry 901 is further configured to allocate storage location 935 to cache memory circuitry 905. Access to cache memory circuitry 905 may generally have a higher QoS level than access to system memory circuitry 910.

[0095] To allocate buffer 915 to cache memory circuit 905, processing circuit 901 is configured to select a specific order for allocating storage locations 935 to cache memory circuit 905. This specific order may increase the uniformity of cache miss rates compared to a linear order. Allocating storage locations 935 in a linear order (e.g., starting with allocation location 935a and proceeding to storage location 935i in the order of storage locations 935b, 935c, 935d, etc.) may result in more frequent cache misses for storage locations at the end of buffer 915. For example, storage locations 935g, 935h, and 935i may have a higher probability of not being allocated because their corresponding cache lines have already been allocated to different storage locations. Therefore, selecting a specific order for allocating storage locations 935 to cache memory circuit 905 that allocates storage locations 935 in a more equitable manner increases the likelihood that locations at the end of buffer 915 will be successfully allocated to cache memory circuit 905.

[0096] After selecting the particular order, processing circuitry 901 is further configured to cache some of storage locations 935 of buffer 915 in the particular order in cache memory circuitry 905. In some embodiments, processing circuitry 901 may be further configured to select and allocate subsets of storage locations 935, each subset having multiple storage locations, rather than selecting and allocating individual storage locations.

[0097] As an example, at time t0, processing circuit 901 allocates buffer 915 including storage location 935 to system memory circuit 910. At time t1, processing circuit 901 is configured to partition buffer 915 into a plurality of blocks based on a specific order. The plurality of blocks correspond to storage locations 935 and have a serial logical order as shown.

[0098] Each storage location 935 can include any suitable number of bytes of the system memory circuit 910, such as one byte, sixteen bytes, 128 bytes, etc. In some embodiments, different storage locations 935 can include different numbers of bytes. For this example, one storage location 935 has the same number of bytes as one cache line 920. The size of the storage locations 935 can be determined by the processing circuit 901 based on a specific order. As shown, the buffer 915 is divided into nine storage locations, and the specific order includes allocating every third storage location, starting with storage location 935a, then 935d, and then 935g. The order wraps around to storage location 935b, then 935e, and then 935h. The last three storage locations are then allocated, starting with 935c, then 935f, and ending with 935i.

[0099] Processing circuitry 901 is further configured to cache storage locations 935 using increments that select some of storage locations 935 in a specific order, different from a serial order. In the illustrated example, the increment is three, but any suitable number may be used. Storage location 935a is assigned to cache line 920c, followed by storage location 935d assigned to cache line 920f, and then storage location 935g assigned to cache line 920h. As shown, cache memory circuitry 905 is configured to map a given storage location 935 to a corresponding cache line 920 based on a specific system address included in the given storage location 935. For example, cache memory circuitry 905 may perform a hash on a specific address or a portion thereof, and the resulting hash value may be used to map the specific address to a corresponding cache line 920. Because cache memory circuitry 905 may be significantly smaller than system memory circuitry 910, two different system addresses may result in hash values ​​that map to the same cache line 920. In such a case, the second of the two addresses may fail to be assigned.

[0100] exist Figure 9 In the example shown in FIG. 1 , storage locations 935 b, 935 f, and 935 i are mapped to cache lines 920 h, 920 e, and 920 c, respectively. However, these three cache lines 920 have already been allocated to storage locations 935 a, 935 h, and 935 g, respectively. Therefore, storage locations 935 b, 935 f, and 935 i cannot be allocated. As shown in the italicized bold text in buffer 915, the unallocated storage locations are scattered throughout buffer 915. If the agent then traverses the contents of buffer 915 in logical order, starting at storage location 935 a, cache misses occur one at a time, separated by two or more cache hits before reaching the next cache miss.

[0101] However, if storage locations 935 were allocated in the same linear order as buffer 915, storage location 935b would be allocated instead of storage location 935g, and storage location 935f would be allocated instead of storage location 935h. This would result in storage locations 935g, 935h, and 935i all failing to be allocated. In this scenario, as the agent traverses buffer 915, three cache misses occur in the row at the end of buffer 915, with no cache hits between the misses. Three fetches from system memory circuit 910 in a row may result in delays because the second and third fetches may have to wait for the previous fetches to be processed. Therefore, allocating buffer 915 using a specific order rather than a linear order can reduce the overall time to traverse buffer 915.

[0102] After allocation of buffer 915 to cache memory circuitry 905 is complete, processing circuitry 901 or other agents in system 900 may access cache memory circuitry 905 as a low-latency path to the value stored in buffer 915. Location 935 that has been successfully cached may provide faster access to the contents of buffer 915 than directly accessing location 935 in system memory circuitry 910.

[0103] Please note that Figure 9 The embodiments are merely examples. Figure 9 Only elements used to describe the disclosed technology are included. In other embodiments, additional elements may be included. For example, one or more bus circuits, a memory management unit, etc. may be included in other embodiments. For clarity, the number of cache lines and storage locations is limited. In other embodiments, any suitable number of cache lines and storage locations may be included.

[0104] exist Figure 9 In the description of

[0014] , failures to successfully allocate a buffer location were briefly discussed. If a particular location in a buffer is mapped to a cache line that is already allocated to a different location in the buffer, the allocation fails. In some embodiments, a particular location in a buffer may be mapped to a cache line that is currently allocated to a different location in system memory that is not associated with the buffer. Techniques for handling this situation are now presented.

[0105] Now move to Figure 10 , again showing the Figure 9 As shown in the figure, the system 900 is a block diagram of an embodiment of the system 900. Figure 9 1, except that the cache memory circuit is shown with four additional cache lines, namely cache lines 920i-9201. As mentioned above, for clarity, the cache memory circuit 905 is shown in FIG. Figure 9Cache memory circuit 905 may include any suitable number of cache lines, including, for example, Figure 10 . Processing circuitry 901 is shown allocating storage locations 935b, 935e, and 935h of buffer 915 into cache memory circuitry 905. At time t0, processing circuitry 901 attempts to allocate storage location 935b into cache line 920k.

[0106] like Figure 9 As shown, storage location 935b is mapped to cache line 920h which has been previously allocated to storage location 935g of buffer 915. Figure 10 In an embodiment, storage location 935b may be further mapped to cache line 920k. For example, cache memory circuit 905 may be set associative and include multiple ways such that a given system memory address may be mapped to two or more cache lines 920. Thus, cache line 920k may be in a different way than cache line 920h, and thus an alternative cache line may be provided in which to allocate storage location 935b.

[0107] However, at time t0, cache line 920k is allocated to storage location 1035y, which may be a location in system memory circuitry 910 that is not associated with buffer 915. In response to a failure to cache storage location 935b to cache line 920k, processing circuitry 901 is configured to retry caching of storage location 935b before caching a different storage location. As shown, processing circuitry 901 generates a new allocation request for cached storage location 935b. In some embodiments, processing circuitry 901 may include a delay of a specified amount of time, or number of instruction cycles or bus cycles, between the initial attempt to allocate storage location 935b and the retry attempt.

[0108] At time t1, storage location 1035y may be evicted from cache line 920k, and therefore, storage location 935b may be successfully cached into cache line 920k. Subsequently, processing circuit 901 may further attempt to cache storage location 935e, followed by storage location 935h.

[0109] By retrying the cache allocation attempt for storage location 935b, processing circuit 901 can increase the number of successfully cached storage locations of buffer 915. The more storage locations that can be allocated to buffer 915 in cache memory circuit 905, the higher the probability that the QoS requirements of the application that will utilize buffer 915 will be met.

[0110] Please note that Figure 10 The system 900 shown in FIG. 1 is an example for illustrating the disclosed techniques. Only elements used to describe these techniques are shown. As previously described, other embodiments may include additional elements, such as additional cache lines and storage locations, as well as additional processing circuits and other bus and memory management circuits.

[0111] Figure 9 The system describes processing circuitry as performing many of the actions associated with caching storage locations in cache memory circuitry. Various types of processing circuitry may be utilized to perform such actions. One such processing circuitry includes direct memory access (DMA) circuitry, such as Figure 11 As shown in .

[0112] Now go to Figure 11 , depicts an embodiment of a system including a DMA circuit for caching a buffer of system memory in a cache memory. System 1100 includes a processor core 1190 coupled to a DMA circuit 1101, which is further coupled to cache memory circuit 905 and system memory circuit 910. In various embodiments, DMA circuit 1101, processor core 1190, or a combination of both may correspond to Figure 9 and Figure 10 processing circuit 901.

[0113] Processor core 1190 may be a general-purpose processor that performs computing operations. In some embodiments, processor core 1190 may be a specialized processing core, such as a graphics processor, an audio processor, or a neural processor. In some embodiments, processor core 1190 may include multiple general-purpose and / or specialized processor cores and support circuits for managing power signals, clock signals, memory requests, and the like. As depicted, DMA circuit 1101 is configured to issue memory transactions to copy or move values ​​between various memory addresses across the memory map of system 1100. DMA circuit 1101 may be implemented as a specialized circuit, a general-purpose circuit programmed to perform such tasks, or a combination thereof. DMA circuit 1101 may be programmed by at least processor core 1190 to execute multiple memory transactions in a desired order.

[0114] As previously described, processing circuitry 901 selects a particular order for caching the memory locations of buffer 915 in cache memory circuitry 905. As shown in system 1100, selecting the particular order is performed by processor core 1190, for example, based on the size of buffer 915 and / or the availability of cache lines in cache memory circuitry 905. Processor core 1190 is configured to program the particular order into DMA circuitry 1101 and to cache some of the memory locations 935 of buffer 915 in cache memory circuitry 905 using DMA circuitry 1101. For example, DMA circuitry 1101 may include various registers in which processor core 1190 may store source addresses for locations 935 and destination addresses for caching memory locations 935 in cache memory circuitry 905, including providing a particular order for issuing memory transactions corresponding to some of the memory locations 935.

[0115] As shown, processor core 1190 is further configured to track a cache miss rate in cache memory circuit 905 for memory transactions that include accesses to memory locations 935. After buffers 915 have been allocated to cache memory circuit 905, processor core 1190 or different agents in system 1100 may issue various memory transactions that access some of memory locations 935. Based on how many memory locations 935 are successfully allocated to cache memory circuit 905, a specific cache miss rate may be determined for these memory transactions targeting addresses in memory locations 935. For example, if ten percent of memory locations 935 fail to be allocated, and memory locations 935 are equally accessed by a particular agent using buffers 915, the cache miss rate will be close to or equal to ten percent. However, if a particular agent accesses a particular memory location in memory locations 935 more frequently than other memory locations, the cache miss rate may be higher or lower than ten percent depending on whether the more frequently accessed memory location is successfully allocated.

[0116] In response to determining that the tracked cache miss rate meets a threshold rate, processor core 1190 may be further configured to modify the specific order in DMA circuit 1101. For example, if the threshold miss rate is 15% and the tracked miss rate is 18%, processor core 1190 may identify memory locations 935 that are not cached but are frequently targeted in memory transactions, as well as identify successfully cached memory locations 935 that are not frequently targeted. The revised order may adjust the order in which these identified memory locations are allocated, such that more frequently accessed locations are allocated sooner in the revised order, and less frequently accessed locations are moved toward the end of the revised order. When subsequent buffers are to be allocated to cache memory circuit 905, the revised order may be selected relative to the original specific order. In some embodiments, various orders may be determined and associated with specific agents, tasks, processes, etc., such that the selected order for allocation takes into account past executions of similar tasks.

[0117] With respect to determining the allocation order, a technique is disclosed above in which a specific increment between consecutive locations is used to select subsequent storage locations. Figure 11 , a technique is shown that includes dividing the buffer 915 into a plurality of blocks 1130a-1130c (collectively, blocks 1130) having corresponding series of adjacent storage locations 935. The nine storage locations 935 shown are divided into three blocks 1130, each block 1130 including three consecutive storage locations 935. Although the blocks 1130 are shown as including an equal number of storage locations 935 per block, in other embodiments, the number of storage locations 935 included in each block 1130 may vary. For example, the usage of the buffer 915 may be known, and based on the known usage, particular storage locations 935 or groups of locations may be known to be accessed less frequently, while other storage locations are known to be accessed more frequently. Therefore, the number of storage locations 935 assigned to each block may be adjusted so that, for example, the initial storage locations 935 of each block are locations that are known to be accessed more frequently.

[0118] After dividing the storage locations 935 into respective blocks 1130, the processor core 1190 may select a particular order in which to allocate the first storage locations 935 of respective series of some of the blocks 1130 to the cache memory circuit 905, and then allocate the second storage locations 935 of some of the blocks 1130. As shown, block 1130a includes an initial storage location 935a, followed by storage locations 935c and 935c. Similarly, block 1130b includes an initial storage location 935d, followed by storage locations 935e and 935f, and block 1130c includes an initial storage location 935g, followed by storage locations 935h and 935i.

[0119] In a first pass, processor core 1190 causes DMA circuit 1101 to cache the initial storage location from each of chunks 1130, storage locations 935a, 935d, and 935g. In a second pass, DMA circuit 1101 then caches the second storage location from each chunk 1130 (storage locations 935b, 935e, and 935h), followed by a third pass in which the third location from each chunk 1130 (storage locations 935c, 935f, and 935i) is cached.

[0120] As described above, processor core 1190 may modify the specific order based on the monitored cache miss rate. This modification may include adjusting the number of locations included in each block, the number of locations stored at one time from each block, or the order used to allocate locations within each block. For example, in block 1130b, processor core 1190 may determine that storage location 935e is accessed more frequently than storage location 935d. In the modified order, the initial storage location allocated from block 1130b may be 935e instead of 935d.

[0121] Note that system 1100 is only an example. For clarity, it has been simplified. Figure 11 Although nine storage locations and three blocks are shown, buffer 915 may include any suitable number of storage locations, and these locations may be divided into any suitable number of blocks. The number of locations included in each block may vary between blocks. Additionally, the number of locations from each block allocated at a given time may vary between passes.

[0122] about Figures 1 to 8 Various types of QoS levels are discussed.The transactions for caching buffers from system memory into cache memory may also utilize different QoS levels for different tasks. Figure 12 The use of batch and real-time transactions with the disclosed technology is shown.

[0123] Now continue to Figure 12 , showing the Figure 9 and Figure 10 , namely during allocation of buffers to a cache and during use of the allocated buffers. The system 900 includes the embodiment of the system 900 as previously described in Figure 9 and Figure 10. Additionally, cache memory circuitry 905 and system memory circuitry 910 are configured to support a batch channel 1240 and a real-time channel 1245, respectively. In some embodiments, batch channel 1240 and real-time channel 1245 may utilize separate physical connections between various agents and the memory circuitry to complete respective transactions. In other embodiments, at least a portion of real-time channel 1245 and batch channel 1240 are shared, and in some embodiments, may be implemented as virtual batch and real-time channels as described above.

[0124] At time t0, buffer 915 is cached in cache memory circuit 905. In this embodiment, buffer 915 is a real-time buffer. As used herein, a "real-time buffer" refers to a memory buffer in which real-time transactions are primarily used to access the buffer's location. A real-time buffer can be used with agents and / or tasks where failure to meet certain QoS requirements can result in improper operation of the agent or task. For example, processing a video frame for playback needs to be completed within a specific amount of time, otherwise the video playback may produce noticeable pauses or glitches to the viewer.

[0125] Although buffer 915 is a real-time buffer, the initial allocation of buffer 915 into the cache may not be time-sensitive. Therefore, storage locations 935 of cache buffer 915 may be allocated to cache memory circuit 905 using batch transactions 1242 across batch channel 1240. As shown at time t0, batch transactions 1242a, 1242b, and 1242c are transmitted using batch channel 1240 to allocate storage locations 935a, 935d, and 935g, respectively, in cache memory circuit 905. During this buffer allocation task, the agent (e.g., processing circuit 901) that will be using buffer 915 may not have values ​​ready to read from or write to buffer 915. Therefore, batch transactions 1242 may be used to allocate buffer 915.

[0126] However, since the buffer 915 is intended for use with real-time transactions, the batch transaction 1242 may include an indication of successfully cached storage locations 935, indicating that these cached storage locations are associated with real-time transactions. For example, the cache tag associated with each successfully cached storage location 935 may have a particular bit or set of bits that indicates that the associated cache line 920 will be used with real-time transactions. When cache lines are identified for eviction, cache lines 920 with real-time indications in their corresponding cache tags may receive a higher priority. For example, if a particular number of cache lines 920 in the cache memory circuit 905 reaches a threshold level (e.g., approaching a certain percentage of the maximum storage capacity), particular cache lines 920 that are not frequently accessed may be selected for eviction. Cache lines 920 with the real-time indication set may be omitted from consideration for eviction or may be set very low in the order of selection, e.g., so that other cache lines have a higher probability of being selected for eviction.

[0127] Cache memory circuit 905 may also reserve a specific amount of bandwidth for fetching data from system memory circuit 910 in response to a cache miss associated with a real-time memory transaction. Cache memory circuit 905 may limit the number of batch transactions issued and active at a given point in time so that bandwidth is reserved for issuing real-time transactions. For example, the bus circuit between cache memory circuit 905 and system memory circuit 910 may include a credit-based arbiter circuit. In order for an issued transaction to be selected by the arbiter circuit, cache memory circuit 905 may need to maintain a specific number of bus credits. In such an embodiment, cache memory circuit 905 may delay issuing a batch transaction if the number of bus credits is at or near a specific number. A batch transaction may be sent after cache memory circuit 905 has accumulated a sufficient number of bus credits.

[0128] At time t1, buffer 915 has been assigned to cache memory circuit 905. As indicated by the bold italic text, locations 935f and 935i were not successfully cached. For example, storage locations 935f and 935i may have been mapped to cache lines 920i and 920l, which were previously assigned to storage locations 1235x and 1235y, respectively. Processing circuit 901 is further configured to use real-time transaction 1250a to access successfully cached storage location 935c. Cache memory circuit 905 may be configured to process real-time transaction 1250a using the value stored in cache line 920a.

[0129] Cache memory circuitry 905 is configured to generate a fetch request to system memory circuitry 910 in response to a cache miss associated with a corresponding memory transaction, the generated fetch request having a QoS level compatible with the corresponding memory transaction. For example, cache memory circuitry 905 may generate batch fetches 1265a and 1265b in response to a batch transaction from a given agent. Processing circuitry 901 may be further configured to use real-time transaction 1250b to access unsuccessfully cached memory location 935f. In response to a cache miss at memory location 935f, cache memory circuitry 905 is configured to complete real-time transaction 1250b using real-time fetch 1290. Because cache memory circuitry 905 is configured to reserve bandwidth for real-time fetches, real-time fetches may be processed before other batch fetches that have not yet been issued. For example, batch fetch 1265b may be queued to await completion of batch fetch 1265a. If the real-time extract 1290 is generated before the batch extract 1265b is published, the real-time extract 1290 may be processed before the batch extract 1265b.

[0130] Using such real-time and batch QoS levels can reduce the access time of the real-time buffers used by the agent to be allocated to the cache memory. In the case where a portion of the real-time buffer cannot be allocated to the buffer, the use of the real-time QoS level can also reduce the memory access time.

[0131] Please note that Figure 12 The embodiments are examples for demonstration purposes. For clarity, the Figure 12 Although the number of memory locations and cache lines is shown, any suitable number of memory locations and cache lines may be included in other embodiments. Although only real-time and batch transactions are shown, any suitable number of QoS levels may be used in other embodiments.

[0132] The above about Figures 9 to 12 The described circuits, processes, and techniques describe various techniques for allocating buffers in system memory to cache memory. These various techniques can be implemented using a variety of methods. Figures 13 to 15 Describe three such methods.

[0133] Now move to Figure 13 , a flow chart illustrating an embodiment of a method for caching a buffer in a system memory into a cache memory circuit. In various embodiments, method 1300 may be performed by Figure 9 、 Figure 10 and Figure 12The processing circuit 901 in FIG. 1 is executed as part of a process for caching the buffer 915 in the cache memory circuit 905. For example, the processing circuit 901 may include (or have access to) a non-transitory computer-readable medium having program instructions stored thereon, the program instructions being executable by the processing circuit to cause the reference to be made. Figure 13 Describes the operation. Common Reference Figure 9 and Figure 13 , method 1300 begins at box 1310.

[0134] At block 1310, method 1300 includes allocating, by processing circuit 901, a plurality of storage locations 935 in system memory circuit 910 to buffer 915. As shown, processing circuit 901 or various agents within system 900 may request allocation of buffer 915 within system memory circuit 910 for use with a particular process or task that the agent is preparing to perform. For example, the task may involve processing of images or audio files, encryption or decryption of files, analysis of input from sensors, and the like. In some embodiments, buffer 915 may be a real-time buffer that uses real-time transactions to access storage locations 935. As previously described, real-time transactions have a higher QoS level than other transactions, such as batch transactions.

[0135] At block 1320, method 1300 further includes determining a specific order for allocating storage locations 935 to cache memory circuitry 905. This specific order can be selected to increase the uniformity of cache miss rates compared to using a linear order. As previously discussed, allocating storage locations 935 using a linear order can result in storage locations 935 near the beginning of the linear order being successfully cached, while storage locations 935 at the end of the linear order are not successfully cached due to being mapped to the same cache line 920 as previously cached storage locations 935. If data in buffer 915 were accessed from storage locations 935 in the same order in which they were allocated, more cache misses would be expected as processing moves toward the end of the order. Therefore, selecting a specific order causes caching to occur in an order that attempts to evenly distribute cache misses during the use of buffer 915. As a result, cache misses may not be concentrated during any particular portion of buffer accesses during the use of buffer 915.

[0136] At block 1330, the method 1300 further includes using the particular order to cache the storage locations 935 of the buffer 915. After the particular order for allocating the storage locations 935 has been selected, the processing circuit 901 begins allocating some of the storage locations 935 to the cache memory circuit 905. In some embodiments, such as Figure 10As shown in , method 130 may include, in response to a failure to cache a particular storage location 935 (eg, storage location 935b), retrying caching of storage location 935b before caching a different storage location 935 (such as storage location 935e).

[0137] Method 1300 may end at block 1330. In some embodiments, at least a portion of method 1300 may be repeated. For example, method 1300 may be repeated in response to receiving a request to allocate a different buffer in system memory circuitry 910. In some cases, method 1300 may be executed concurrently with other instances of the method. For example, two or more instances of processing circuitry 901 or multiple process threads within a single instance of processing circuitry 901 may each execute method 1300 independently of one another.

[0138] Now go to Figure 14 , shows a flow chart of an embodiment of a method for using various QoS levels using buffers allocated to cache memory circuits. In a similar manner to method 1300, method 1400 may be performed by Figure 9 、 Figure 10 and Figure 12 As described above, the processing circuit 901 may include (or may have access to) a non-transitory computer-readable medium having program instructions stored thereon, the program instructions being executable by the processing circuit 901 to cause the reference Figure 14 Describes the operation. Common Reference Figure 12 and Figure 14 , method 1400 begins at box 1410.

[0139] At block 1410, method 1400 includes allocating a plurality of locations to a cache memory circuit using a batch transaction. As shown, the allocation process for buffer 915 may not have critical QoS requirements. Therefore, caching of storage locations 935 of buffer 915 may be performed using batch transactions 1242 to allocate storage locations 935 to cache memory circuit 905. Figure 12 As shown at time t0 in FIG. 1 , batch channel 1240 is used to transmit batch transactions 1242 a , 1242 b , and 1242 c to allocate storage locations 935 a , 935 d , and 935 g , respectively, into cache memory circuit 905 .

[0140] At block 1420, method 1400 further includes including an indication of a successfully cached storage location 935 that is used with a real-time transaction. Although the allocation process for buffer 915 may not have real-time requirements, it is anticipated that real-time transactions will be used to access buffer 915. Therefore, when a particular storage location 935 is successfully cached in a corresponding cache line 920, the corresponding cache tag for the cache line may include an indication that the cached contents are associated with a real-time transaction. As previously described, such an indication may help avoid eviction of a cache line 920 that has been allocated to buffer 915.

[0141] At block 1430, the method 1400 further includes accessing, by the agent (e.g., processing circuit 901), the successfully cached storage location 935 using a real-time transaction. Figure 12 As shown, processing circuit 901 can use real-time transactions 1250a and 1250b to access some of storage locations 935. Real-time transaction 1250a hits cache line 920a where storage location 935c is already cached. If real-time transaction 1250a comprises a read request, data corresponding to the requested address from cache line 920a can be sent from cache memory circuit 905 to processing circuit 901 using the real-time transaction.

[0142] At block 1440, the method 1400 further includes, in response to a cache miss at a particular location of the memory locations 935 that failed to be cached, accessing, by the cache memory circuit 905, the particular memory location 935 in the buffer 915 in the system memory circuit 910 using a real-time transaction. Figure 12 As shown, real-time transaction 1250b targets storage location 935f. However, storage location 935f was not successfully cached in cache memory circuit 905. Therefore, cache memory circuit 905 generates and issues real-time fetch 1290 to system memory circuit 910 to retrieve the value from storage location 935f. If either of bulk fetches 1265a and 1265b, also generated by cache memory circuit 905, has not been issued by the time real-time fetch 1290 is ready to be issued, real-time fetch 1290 may take precedence over the unissued bulk fetch.

[0143] Method 1400 may end at block 1440, or in some embodiments, may be repeated in whole or in part. For example, block 1430 may be repeated while processing circuit 901 is processing a value in buffer 915. Similarly, block 1440 may be repeated while processing circuit 901 accesses a memory location 935 that was not successfully cached. In a manner similar to method 1300, method 1400 may be executed concurrently with other instances of method 1400.

[0144] Now continue to Figure 15 , shows a flow chart of an embodiment of a method for selecting and adjusting a particular order for allocating buffers to cache memory circuits. As described with respect to methods 1300 and 1400, method 1400 may be performed by Figure 9 、 Figure 10 and Figure 12 As described, the processing circuit 901 may include (or may have access to) a non-transitory computer-readable medium having program instructions stored thereon, the program instructions being executable by the processing circuit 901 to cause the reference Figure 15 Describes the operation. Common Reference Figure 12 and Figure 15 , method 1500 begins at box 1510.

[0145] At block 1510, method 1500 includes determining a particular order using expected cache miss rates for a plurality of storage locations 935. As described above, the particular order for allocating buffers 915 can be selected with the goal of distributing cache misses across buffers 915. An agent (e.g., processing circuit 901) that will use buffer 915 can process data stored in buffer 915 using a linear order. Processing circuit 901 can begin at an initial storage location, such as 935a, and sequentially progress through storage locations 935, e.g., 935b, 935c, and so on, ending at storage location 935i. If storage locations 935 were allocated in this same linear order, multiple storage locations 935 might not be cached toward the end of buffer 915. Processing data in buffer 915 in the same order can result in a cache miss rate that increases as processing proceeds, potentially peaking toward the end of buffer 915. The particular order may be selected to distribute the failures of the storage locations 935 to be allocated across the buffers 915 so that as the buffers 915 are processed, the peak cache miss rate remains below a desired cache miss rate.

[0146] At block 1520, the method 1500 further includes accessing, by the processing circuit 901, the plurality of storage locations 935 using a linear order after caching. As described, the processing circuit 901 may access the buffer 915 using a linear order different from the specific order. In other embodiments, the processing circuit 901 may use an order different from the linear order. In such embodiments, the specific order may be selected to be different from the specific order, including, for example, allocating the storage locations 935 using a linear order.

[0147] At block 1530, the method further includes tracking a cache miss rate associated with using the particular order to cache the plurality of storage locations 935. As the processing circuit 901 uses the buffer 915, the observed cache miss rate can be tracked and further compared to an expected cache miss rate. If the particular order used to allocate the storage locations 935 is effective, the tracked cache miss rate should remain lower than the expected cache miss rate because cache misses can occur more consistently throughout the processing of all data in the buffer 915. By distributing the cache misses consistently, the peak cache miss rate should remain reasonably low and not exceed the expected cache miss rate.

[0148] At frame 1540, method 1500 also comprises in response to determining that the cache miss rate that is tracked meets threshold rate, and adjusting specific order for subsequent use.As shown in the figure, if the cache miss rate that is tracked reaches or exceeds the cache miss rate of expectation, then use selected specific order allocation buffer 915 and do not realize the result of expectation.The threshold rate can be equal to the cache miss rate of expectation, or can be adjusted higher or lower based on whole system operation target.In order to adjust specific order, can analyze the cache miss that occurs when cache miss rate meets threshold rate to identify the storage location 935 being accessed.One or more of these identified storage locations 935 can be selected to move closer to the beginning of the allocation order of adjustment.In addition, can also identify the storage location 935 that is accessed when the cache miss rate is low.One or more of these storage locations can be selected to move towards the end of the allocation order of adjustment.

[0149] In some embodiments, method 1500 may end at block 1540 or may be repeated in whole or in part. For example, blocks 1520 and 1530 may be repeated while processing circuit 901 is accessing storage location 935 in buffer 915. As described with respect to methods 1300 and 1400, method 1500 may also be performed concurrently with other instances of method 1500. Additionally, methods 1300, 1400, and 1500 may be performed concurrently with one another.

[0150] Figures 1 to 8 Circuits and methods are presented for a system that reallocates a portion of cache memory for use as a directly addressable address region. Figures 9 to 15 Circuits and techniques for caching a buffer in system memory into a cache memory circuit are described. Any embodiment of the disclosed system can be included in one or more of a variety of computer systems, such as desktop computers, laptop computers, smartphones, tablet computers, wearable devices, etc. In some embodiments, the circuits described above can be implemented on a system on a chip (SoC) or other type of integrated circuit. Figure 16 A block diagram illustrating an embodiment of a computer system 1600 is shown in FIG. In some embodiments, computer system 1600 may include any of the disclosed embodiments, such as system 100, 200, 500, 600, 900, or 1100.

[0151] In the illustrated embodiment, system 1600 includes at least one instance of a system-on-chip (SoC) 1606, which may include various types of processing circuitry such as a central processing unit (CPU), a graphics processing unit (GPU), or other communication structures, as well as interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 1606 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 1606 is coupled to external memory 1602, peripheral devices 1604, and a power source 1608.

[0152] A power source 1608 is also provided that supplies a supply voltage to the SoC 1606 and one or more supply voltages to the memory 1602 and / or peripherals 1604. In various embodiments, the power source 1608 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, or tablet computer, or other device). In some embodiments, more than one instance of the SoC 1606 is included (and more than one external memory 1602 is also included).

[0153] Memory 1602 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low-power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the device is mounted with an SoC or integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

[0154] Depending on the type of system 1600, peripherals 1604 include any desired circuitry. For example, in one embodiment, peripherals 1604 include devices for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, and the like. In some embodiments, peripherals 1604 also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripherals 1604 include user interface devices such as a display, including a touch display or a multi-touch display, a keyboard or other input device, a microphone, a speaker, and the like.

[0155] As shown, system 1600 is shown as having applications in a wide range of fields. For example, system 1600 can be used as part of a chip, circuit system, component, etc. of a desktop computer 1610, a laptop computer 1620, a tablet computer 1630, a cellular or mobile phone 1640, or a television 1650 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 1660 are also shown. In some embodiments, the smartwatch may include various general computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user's calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices 1660 are also contemplated, such as devices worn around the neck, devices attached to a hat or other helmet, devices implantable in the human body, glasses designed to provide augmented and / or virtual reality experiences, and the like.

[0156] System 1600 can also be used as part of a cloud-based service 1670. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Further, system 1600 can be used in one or more devices in a home 1680 other than those previously mentioned. For example, home appliances can monitor and detect noteworthy conditions. Various devices in a home (e.g., a refrigerator, a cooling system, etc.) can monitor the status of the devices and provide alerts to the homeowner (or, for example, a maintenance facility) if specific events are detected. Alternatively, a thermostat can monitor the temperature in a home and automatically adjust the heating / cooling system based on a history of responses by the homeowner to various conditions. Figure 16 Also shown are applications of system 1600 to various modes of transportation 1690. For example, system 1600 may be used in control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), and the like. In various cases, system 1600 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, and the like.

[0157] Note that various potential applications of system 1600 may include various performance, cost, and power consumption requirements. Therefore, it may be beneficial to enable a scalable solution that can use one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption. These and many other embodiments are possible and contemplated. Note that Figure 16 The devices and applications shown are illustrative only and are not intended to be limiting. Other devices are possible and contemplated.

[0158] As about Figure 16 As disclosed, the computer system 1600 may include one or more integrated circuits included in a personal computer, smart phone, tablet computer, or other type of computing device. Figure 17 A process for designing and producing an integrated circuit using design information is presented in .

[0159] Figure 17 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. Figure 17 Embodiments of the present invention may be used in the design and manufacture of integrated circuits (e.g., Figures 1 to 15 100 ). In the illustrated embodiment, semiconductor manufacturing system 1720 is configured to process design information 1715 stored on non-transitory computer-readable storage medium 1710 and to manufacture integrated circuits 1730 (e.g., system 100) based on the design information 1715.

[0160] The non-transitory computer-readable storage medium 1710 may include any of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1710 may be an installation medium, such as a CD-ROM, floppy disk, or tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, magnetic media, such as a hard drive or optical storage device; a register or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1710 may also include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 1710 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0161] Design information 1715 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. Design information 1715 can be used by semiconductor manufacturing system 1720 to manufacture at least a portion of integrated circuit 1730. The format of design information 1715 can be recognized by at least one semiconductor manufacturing system, such as, for example, semiconductor manufacturing system 1720. In some embodiments, design information 1715 can include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1730 can also be included in design information 1715. Such cell libraries can include information indicating device or transistor-level netlists, mask design data, characterization data, and the like indicating the cells included in the cell library.

[0162] In various embodiments, integrated circuit 1730 may include one or more custom macrocells, such as memory, analog or mixed-signal circuits, etc. In this case, design information 1715 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDS) or any other suitable format.

[0163] Semiconductor manufacturing system 1720 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet light treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1720 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0164] In various embodiments, integrated circuit 1730 is configured to operate according to the circuit design specified by design information 1715, which may include performing any of the functions described herein. For example, integrated circuit 1730 may include any of the various components shown or described herein. Additionally, integrated circuit 1730 may be configured to perform the various functions described herein in conjunction with other components.

[0165] As used herein, phrases of the form "design information specifying a design of a circuit configured to..." do not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0166] ***

[0167] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). An embodiment is different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," etc., do not necessarily refer to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of this disclosure.

[0168] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation falling within the scope of a claim may not exhibit some or all of the disclosed advantages. For example, a particular implementation may include additional circuitry outside the scope of this disclosure that, in combination with one of the disclosed embodiments, negates or mitigates one or more of the disclosed advantages. Furthermore, suboptimal design implementation of a particular implementation (e.g., a specific implementation technique or tool) may also negate or mitigate the disclosed advantages. Even assuming a specific implementation of the technique, the realization of an advantage may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring in a particular situation, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors external to this disclosure, any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate one or more types of improvements available to designers who benefit from this disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantages often depends on technical realities of additional factors.

[0169] Unless otherwise indicated, the embodiments are non-restrictive. That is, the disclosed embodiments are not intended to limit the scope of claims drafted based on this disclosure, even when only a single example is described for a particular feature. The embodiments disclosed herein are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art knowing the effective effects of this disclosure.

[0170] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be formulated during the prosecution of this patent application (or a patent application claiming priority thereto) directed to any such combination of features. In particular, with reference to the appended claims, features of dependent claims may, where appropriate, be combined with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may, where appropriate, be combined.

[0171] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0172] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0173] ***

[0174] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0175] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim, without accompanying context, does not exclude additional instances of that item. A "plurality" of an item refers to a collection of two or more items.

[0176] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0177] The terms "include" and "including" and their forms are open ended and mean "including, but not limited to."

[0178] When the term "or" is used in this disclosure with respect to a list of options, unless the context provides otherwise, it will generally be understood to be used in an inclusive sense. Thus, the expression "x or y" is equivalent to "x or y, or both," thus encompassing 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0179] The expression "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" is intended to encompass all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases encompass any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby encompassing all possible combinations in that list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0180] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Furthermore, unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0181] The phrase "based on" or "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover embodiments in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0182] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrases do not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with or independent of the specified factors. That is, the effect may be responsive only to these factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is the factor that triggers the performance of A or triggers a particular result of A. The phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. The phrase also does not exclude that the performance of A may be performed in response to B and C in conjunction. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0183] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0184] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0185] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA could be "configurable to" perform that function. After being appropriately programmed, the FPGA could then be considered "configured to" perform the particular function.

[0186] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing function]” construct to phrase the claim element.

[0187] ***

[0188] Different “circuits” may be described in this disclosure. These circuits or “circuitry” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits can be custom designed or taken from standard libraries. In various specific implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry.

[0189] Thus, the disclosed circuits / units / components and other elements shown in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an instruction's opcode and routing that instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible architectures for the circuit.

[0190] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to one another and the manner in which they interact form a microarchitecture definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Thus, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can, without undue experimentation and with the application of ordinary skill, implement the structure by coding a description of the circuits / units / components in a hardware description language (HDL) such as Verilog or VHDL. HDL descriptions are often expressed in a manner that can be rendered as functional. However, for those skilled in the art, the HDL description is a means for converting the structure of a circuit, unit, or component into the next level of implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and may be modified for timing, power, and other reasons to obtain a final design database that is transmitted to the factory to generate masks and ultimately produce the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in the schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to situations where the circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at a different stage in the circuit implementation process.

[0191] The fact that many different low-level combinations of circuit elements can be used to achieve the same specifications of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries available for a particular project, and so on. In many cases, the selection of these different implementations made by different design tools or methodologies can be arbitrary.

[0192] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Consequently, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device comprising: a cache memory circuit comprising a cache memory having a plurality of cache lines; as well as a cache controller circuit configured to: receiving a request to reallocate a currently in-use portion of the cache memory circuitry, wherein the request identifies an address region corresponding to one or more cache lines of the plurality of cache lines; as well as In response to the request: setting a corresponding real-time memory indicator for at least one cache line among the one or more cache lines, wherein a given real-time memory indicator indicates that the corresponding cache line is associated with a real-time transaction having a higher priority than a batch transaction; as well as Based on the live memory indicator, the one or more cache lines are converted to directly addressable random access memory RAM by excluding the one or more cache lines from cache operation.

2. The apparatus of claim 1 , wherein the cache controller circuit is further configured to: supporting a real-time virtual channel for memory transactions in the identified address region; and Memory transactions received via the real-time virtual channel are prioritized over memory transactions received via the bulk virtual channel.

3. The apparatus of claim 1 , wherein the cache controller circuit is further configured to: determining that the address region is included in a secure access region; and Responsive to the determination, memory transactions in the address region from agents not authorized to access the secure access region are ignored. 4 . The apparatus of claim 1 , wherein the cache controller circuit is further configured to flush the one or more cache lines before translating the one or more cache lines to the directly addressable RAM.

5. The apparatus of claim 1 , wherein the cache controller circuit is further configured to: issuing a write-back request for the valid cache line in response to data in the valid cache line being written; and The one or more cache lines are excluded from write-back requests.

6. The apparatus of claim 1 , wherein the cache controller circuit is further configured to: receiving a different request to deallocate the portion of the cache memory from the directly addressable RAM; and In response to the different request, the one or more cache lines are included in a cache operation without copying data stored in the directly addressable RAM while reallocating the one or more cache lines.

7. The apparatus of claim 6, wherein the cache controller circuit is further configured to generate an error in response to a memory transaction in the directly addressable RAM received after the portion of the cache memory is deallocated.

8. A method comprising: receiving, by cache controller circuitry, a request to reallocate a currently used portion of cache memory circuitry to a directly addressable address region, wherein the request identifies an inactive address region; selecting one or more cache lines of the cache memory circuit for translation based on the identified address region; and A corresponding indication is set, by the cache controller circuitry, for a cache line in the selected cache lines to exclude the selected cache line from further cache operations, wherein the corresponding indication includes a real-time memory indicator indicating that the associated selected cache line is associated with a real-time transaction having a higher priority than the batch transaction.

9. The method according to claim 8, further comprising: Based on the live memory indicator, the selected cache line is mapped for use in the identified address region.

10. The method of claim 8, further comprising ignoring, by the cache controller circuitry, memory transactions to the identified address region from agents not authorized to access the secure access region in response to determining that the identified address region is part of the secure access region.

11. The method of claim 8, further comprising flushing, by the cache controller circuitry, the selected cache line before setting the corresponding indication.

12. The method of claim 8, wherein data written to a specific address currently cached in the cache memory circuit is written back to the specific address in system memory; and Data written to a different address in the identified address area is not written back to the system memory.

13. The method according to claim 8, further comprising: receiving, by the cache controller circuitry, a different request to deallocate the portion of the cache memory circuitry from the directly addressable address region; as well as In response to the different request, the selected cache line is included in a cache operation, wherein data stored in the directly addressable address region is overwritten without being written back to system memory circuitry when the selected cache line is deallocated.

14. The method of claim 13, further comprising returning, by the cache controller circuitry, a default value in response to a read request for an address in the directly addressable address region received after the portion of the cache memory circuitry is deallocated.

15. A system comprising: a cache memory circuit comprising a cache memory having a plurality of ways; a processor configured to issue memory requests using an address map comprising an active address region and an inactive address region; as well as a cache controller circuit configured to: receiving a request from the processor to reallocate a portion of the cache memory as directly addressable memory, wherein the request identifies an inactive address region; selecting, based on the request, a portion of the plurality of lanes for conversion by setting one or more corresponding real-time memory indicators for the selected lanes, wherein a given real-time memory indicator indicates that the corresponding lane is associated with a real-time transaction having a higher priority than a batch transaction; as well as Based on the live memory indicator, a selected portion of a way is mapped for use in the identified address region.

16. The system of claim 15 , wherein to convert the selected portion of the way, the cache controller circuit is configured to set the corresponding live indicator in a cache tag corresponding to a particular cache line included in the selected portion of the way, wherein the corresponding live indicator causes the particular cache line to be removed from use as cache memory.

17. The system of claim 16, further comprising a system memory mapped to at least a portion of the active address region, and wherein the inactive address region is not mapped to the system memory.

18. The system of claim 15 , wherein the cache controller circuitry is further configured to include the selected portion of the way in cache operations in response to receiving a request to deallocate the directly addressable memory, wherein data stored in the directly addressable memory when the selected portion of the way is deallocated is not relocated in response to the request to deallocate the directly addressable memory.

19. The system of claim 15, wherein the cache controller circuit is further configured to flush cache lines in the selected portion of the way before mapping the selected portion of the way for use in the identified address region.

20. The system of claim 15, wherein the portion of the pathway is half of a particular pathway.

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