A chip pin hanging detection circuit based on load potential and detection method thereof

Abstract

The present invention provides a chip pin hanging detection circuit based on load potential and a detection method thereof. The chip pin hanging detection circuit includes a switch circuit, a pull-up circuit, a pull-down circuit, a first reference voltage circuit, a second reference voltage circuit, a comparator U1, a comparator U2, a trigger U3, a trigger U4, a logic AND gate U5, a reverse circuit U6, a reverse circuit U7, and a timing circuit. The outside of the PIN is regarded as a load of a circuit. The weight of the load equivalent to the PIN hanging and the PIN having an external circuit is different. The PIN hanging means an extremely light load, and the PIN having an external circuit means a relatively heavier load. Based on this characteristic, the present invention applies an extremely weak drive (pull-up or pull-down) to the PIN, and the lighter load potential will be higher (pull-up) or lower (pull-down). Whether the PIN is connected to an external circuit is inferred by the height of the load potential. The present invention can cover the detection of three situations and has good functional completeness.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical components, and in particular to a chip pin suspension detection circuit based on load potential and a detection method thereof. Background Art

[0002] In integrated circuit applications, in many cases, the circuit needs to be set according to the actual application scenario. For example, in power chip applications, different voltage protection and current protection need to be set. This setting can often be achieved through external circuits. In some practical applications, in addition to external settings, some chips also have reserved functional modules inside the chip, and usually only one of the two can be selected. Therefore, in actual use, the external circuit will be tested to determine whether there is an external setting circuit. These applications have put forward requirements for chip pin floating detection. In addition, there may be many situations for the external setting circuit, and the various possibilities of the external circuit put forward requirements for the completeness of the detection circuit function.

[0003] Figure 1a to 1c Three situations of the chip pin (PIN) external circuit are shown. In actual application, various possible situations need to be taken into account.

[0004] The prior art applies different detection methods to different situations. Therefore, a circuit and method capable of detecting pins of multiple PIN chips are needed. Summary of the invention

[0005] The present invention is to solve the problem of detecting whether the PIN chip pin is suspended, and provides a chip pin suspension detection circuit based on load potential and its detection method. The outside of the PIN is regarded as the load of a circuit. The load weight of the PIN suspended and the PIN with an external circuit is different. The PIN suspended means an extremely light load, and the PIN with an external circuit means a relatively heavier load. Based on this characteristic, the present invention applies an extremely weak drive (pull-up or pull-down) to the PIN. The lighter load potential will be higher (pull-up) or lower (pull-down). Whether the PIN is connected to an external circuit can be inferred by the height of the load potential. The present invention can cover Figure 1a to 1c It can detect all situations in the system and has good functional completeness.

[0006] The present invention provides a chip pin floating detection circuit based on load potential, comprising a switch circuit connected to a PIN to be tested, a pull-up circuit and a pull-down circuit respectively connected to the PIN to be tested through the switch circuit, a first reference voltage circuit and a second reference voltage circuit respectively connected to a power supply voltage, a comparator U1 whose positive-phase input is connected to the PIN to be tested and whose negative-phase input is connected to the first reference voltage circuit, a comparator U2 whose negative-phase input is connected to the PIN to be tested and whose positive-phase input is connected to the second reference voltage circuit, and a timing circuit connected to the pull-up circuit, the pull-down circuit, and the switch circuit;

[0007] The switch circuit includes NM0 connected to the pull-down circuit and a fourth PMOS transistor PM4, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6 connected between the pull-up circuit and the pull-down circuit;

[0008] The pull-up circuit includes a PMOS tube current mirror circuit connected to the power supply voltage Vdd, and the pull-down circuit includes an NMOS tube current mirror circuit connected to the power supply voltage Vdd. The PMOS tube current mirror circuit and the NMOS tube current mirror circuit copy the power supply voltage Vdd to the branch circuit in proportion.

[0009] The timing circuit controls the pull-up circuit, the pull-down circuit, and the switch circuit to work in time sequence. The EN signal is an enable signal. After the EN signal is delayed, the EN1 signal, the EN2 signal, the EN3 signal, and the EN4 signal are obtained in sequence. The EN_N signal is the inverted signal of the EN signal, and the EN4_N signal is the inverted signal of the EN signal.

[0010] The switch circuit controls the pull-up circuit and the pull-down circuit to drive the PIN to be tested respectively;

[0011] The positive input of comparator U1 is the voltage value when the PIN to be tested is driven by the pull-up circuit, and the negative input is the reference voltage Vdd-V R , the comparator U1 outputs a high level indicating that the PIN to be tested has no external pull-down circuit;

[0012] The non-inverting input of comparator U2 is the reference voltage V R , the inverting input is the voltage value when the PIN to be tested is pulled down and driven. The high level output of comparator U2 indicates that the PIN to be tested has no external pull-up circuit.

[0013] The present invention discloses a chip pin floating detection circuit based on load potential. As a preferred embodiment, the PMOS tube current mirror circuit includes a first PMOS tube PM1, a second PMOS tube PM2 and a third PMOS tube PM3 whose gates are connected. The sources of PM1, PM2 and PM3 are all connected to the power supply voltage Vdd. The gate and drain of PM1 are connected, and the drain is connected to the drain of NM2 in the NMOS tube current mirror circuit. The drain of PM2 is connected to the source of PM4.

[0014] The second reference voltage circuit includes a resistor R2, one end of which is connected to the drain of PM3 and the non-inverting input of the comparator U2, and the other end of which is connected to all sources of the pull-down circuit and then grounded.

[0015] The chip pin floating detection circuit based on load potential described in the present invention, as a preferred embodiment, the NMOS tube current mirror circuit includes a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3 and a fourth NMOS tube NM4, whose gates are all connected, whose sources are all connected and then grounded;

[0016] The drain of NM1 is connected to the drain of NM0, the source and the gate are both connected to the reference current CurrentSource, the drain of NM3 is connected to the source of NM6, and the drain of NM4 is connected to the first reference voltage circuit;

[0017] The first reference voltage circuit includes a resistor R1, one end of the resistor R1 is connected to all sources of the pull-up circuit and then connected to the power supply voltage Vdd, and the other end is connected to the drain of MM4 and the inverting input terminal of the comparator U1;

[0018] The gate of the NMOS tube NM0 inputs the EN_N signal, the source is grounded, and the drain is connected to the reference current CurrentSource. The gate and drain of an NMOS tube in the NMOS tube current mirror circuit are both connected to the reference current CurrentSource, the source is connected to the source of NM0 and then grounded, the source of NM6 is connected to the drain of an NMOS tube in the NMOS tube current mirror circuit, the drain is connected to the source of NM5, the gate inputs the EN2 signal, the drain of NM5 is connected to the drain of PM4, the gate inputs the EN4_N signal, the source of PM4 is connected to the drain of a PMOS tube in the PMOS tube current mirror circuit, the gate inputs the EN2 signal, and the PIN to be tested is connected to the drain of PM4 and the drain of NM5.

[0019] The chip pin floating detection circuit based on load potential described in the present invention is, as a preferred embodiment, the currents flowing through NM1, NM2, NM3, and NM4 are I1, I2, I3, and I4 respectively, and the output current of the reference current CurrentSource is I0;

[0020] The channel width and length of NM1, NM2, NM3, and NM4 are the same, I1=I2=I3=I4=I0;

[0021] The currents flowing through PM1, PM2, and PM3 are I2, I5, and I6 respectively. The channel width and length of PM1, PM2, and PM3 are the same, and I5=I6=I2=I0;

[0022] The chip pin floating detection circuit based on load potential described in the present invention is preferably configured such that the resistance values ​​of the resistors R1 and R2 are the same, both R, and the reference voltages provided by the first reference voltage circuit and the second reference voltage circuit are Vdd-V R and V R .

[0023] The chip pin floating detection circuit based on load potential described in the present invention, as a preferred mode, the signal timing of the timing circuit output is: at t0, the EN signal changes from low level to high level and then remains at high level, and EN1 to EN4 signals are all low level; at t1, the EN1 signal changes from low level to high level and then remains at high level, and EN2 to EN4 signals are still all low level; at t2, the EN2 signal changes from low level to high level and then remains at high level, and EN3 to EN4 signals are still all low level; at t3, the EN3 signal changes from low level to high level and then remains at high level, and the EN4 signal is still low level; at t4, the EN4 signal changes from low level to high level and then remains at high level;

[0024] From t0 to t1, it is determined whether there is an external pull-down circuit for the PIN to be tested, the result is latched at t1, the pull-up circuit is switched to the pull-down circuit at t2, and from t2 to t3, it is determined whether there is an external pull-up circuit for the PIN to be tested, the result is latched at t3, and the pull-down circuit is closed at t4.

[0025] The chip pin floating detection circuit based on load potential described in the present invention, as a preferred embodiment, also includes a trigger U3 connected to the output end of the comparator U1, a trigger U4 connected to the output end of the comparator U2, a logic AND gate U5 connected to the output end of the trigger U3 and the output end of the trigger U4, a reverse circuit U6 connected to the EN1 signal output end, and a reverse circuit U7 connected to the EN4 signal output end;

[0026] The CLK pin of the trigger U3 inputs the EN signal, and the trigger U3 saves the output result OUT1 of U1 at time t1; the CLK pin of the trigger U4 inputs the EN3 signal, and the trigger U4 saves the output result OUT2 of U2 at time t3;

[0027] The reverse circuit U6 outputs the EN_N signal, and the reverse circuit U7 outputs the EN4_N signal;

[0028] The logic AND gate U5 infers whether the PIN to be tested is connected to an external pull-up circuit and / or an external pull-down circuit according to the level of the load potential.

[0029] The present invention provides a detection method of a chip pin suspension detection circuit based on load potential, comprising the following steps:

[0030] S1, open the pull-up circuit connected to the PIN to be tested;

[0031] S2, comparator U1 determines whether the voltage of the PIN to be tested can be pulled up to close to the power supply voltage Vdd to obtain the pull-up result OUT1 and output it to the trigger U3;

[0032] S3, trigger U3 latches the pull-up result OUT1;

[0033] S4, close the pull-up circuit and open the pull-down circuit connected to the PIN to be tested;

[0034] S5, the comparator U2 determines whether the voltage of the PIN to be tested can be pulled down to close to the ground to obtain the pull-down result OUT2 and output it to the trigger U4;

[0035] S6, trigger U4 latches the pull-down result OUT2, and the circuit controls to proceed to step S7, and determines whether the pin is suspended and proceeds to step S8;

[0036] S7, close the pull-down circuit;

[0037] S8, the logic AND gate U5 determines whether the pins of the external pull-up circuit and / or the external pull-down circuit of the PIN to be tested are suspended according to the pull-up result OUT1 and the pull-down result OUT2; a detection method for a chip pin suspension detection circuit based on load potential is completed.

[0038] The detection method of the chip pin floating detection circuit based on load potential described in the present invention is, as a preferred embodiment, in step S1, when the EN signal is at a low level, NM0 is turned on, and the chip pin floating detection circuit does not work; at time t0, the EN signal changes from a low level to a high level, NM0 is turned off, and the chip pin floating detection circuit starts to work;

[0039] In step S2, at time t0-t1, the EN2 signal is at a low level, PM4 is turned on, NM6 is turned off, the pull-up circuit is turned on, and the comparator U1 confirms the pull-up upper limit of the PIN to be tested, and determines whether the voltage value of the PIN to be tested when driven by the pull-up circuit can be pulled up to close to Vdd. If not, the comparator U1 outputs a low level, the PIN to be tested has an external pull-down circuit, and the external pull-down circuit is connected normally; if yes, the comparator U1 outputs a high level, the PIN to be tested is not connected to the external pull-down circuit, and the pin of the external pull-down circuit is suspended or does not exist;

[0040] In step S3, at time t1, the EN1 signal is at a high level, and the trigger U3 latches the pull-up result OUT1;

[0041] In step S4, at time t2, the EN2 signal changes from low level to high level, the EN4 signal is low level, PM4 is turned off, NM6 is turned on, the pull-up circuit is turned off, NM5 is turned on, and the pull-down circuit is turned on;

[0042] In step S5, at time t2-t3, the comparator U2 confirms the pull-down lower limit of the PIN to be tested, and determines whether the voltage value of the PIN to be tested when driven by the pull-down circuit can be pulled down to near the ground. If not, the comparator U1 outputs a low level, the PIN to be tested has an external pull-up circuit, and the external pull-up circuit is connected normally; if yes, the comparator U1 outputs a high level, the PIN to be tested is not connected to the external pull-up circuit, and the pin of the external pull-up circuit is suspended or does not exist;

[0043] In step S6, at time t3, the EN3 signal is at a high level, and the trigger U4 latches the pull-down result OUT2;

[0044] In step S7, at time t4, the EN4 signal changes from low level to high level, NM5 is turned off, and the pull-down circuit is turned off;

[0045] In step S8, the logic AND gate U5 determines the output result Floating, and the output result Floating includes the pull-up result OUT1 and the pull-down result OUT2;

[0046] The detection method of a chip pin floating detection circuit based on load potential described in the present invention is, as a preferred mode, when the pull-up result OUT1 and the pull-down result OUT2 indicate that the comparator U1 and the comparator U2 are both high levels, the pin of the PIN to be tested is suspended; when the pull-up result OUT1 and the pull-down result OUT2 indicate that the comparator U1 and the comparator U2 are both low levels, the pin of the PIN to be tested is not suspended.

[0047] The present invention has the following advantages:

[0048] The present invention regards the outside of the PIN as a load of a circuit. The weight of the equivalent load when the PIN is suspended and when the PIN has an external circuit is different. The PIN is suspended, which means an extremely light load, and the PIN has an external circuit, which means a relatively heavier load. Based on this characteristic, the present invention applies an extremely weak drive (pull-up or pull-down) to the PIN. The lighter load potential will be higher (pull-up) or lower (pull-down). Whether the PIN is connected to an external circuit can be inferred by the load potential. The present invention can cover Figure 1a to 1c It can detect all situations in the system and has good functional completeness. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1a This is the circuit diagram of the first case of the chip pin external circuit;

[0050] Figure 1b This is the circuit diagram of the second case of the chip pin external circuit;

[0051] Figure 1c The third circuit diagram of the chip pin external circuit;

[0052] Figure 2 The schematic diagram is a chip pin floating detection circuit based on load potential;

[0053] Figure 3 It is a timing diagram of a detection method of a chip pin floating detection circuit based on load potential;

[0054] Figure 4 The present invention is a flow chart of a detection method of a chip pin floating detection circuit based on load potential. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0056] Example 1

[0057] like Figures 2 to 4 As shown, a chip pin floating detection circuit based on load potential and a detection method thereof, the chip pin floating detection circuit can cover Figure 1a to 1c It can detect all situations in the system and has good functional completeness.

[0058] The principle of this circuit: regard the outside of the PIN as the load of a circuit. The weight of the equivalent load when the PIN is suspended and when the PIN has an external circuit is different. A suspended PIN means an extremely light load, and a PIN with an external circuit means a relatively heavier load. Based on this characteristic, an extremely weak drive (pull-up or pull-down) is applied to the PIN, and the lighter load potential will be higher (pull-up) or lower (pull-down). Whether the PIN is connected to an external circuit can be inferred by the height of the load potential.

[0059] The circuit includes: a timing circuit, which is used to control each functional module to work in a certain time sequence; a current source, which provides a reference current; a current mirror circuit, which copies the reference current to other circuit branches in a certain proportion; a switch circuit, which is used to control the conduction of each branch; a reference voltage source circuit, which provides a reference voltage for comparison; a comparator, which is used to compare the voltage in the circuit; a trigger, which is used for latching the circuit; and a logic function module, which performs logic judgment.

[0060] PM1, PM2, PM3, and PM4 are all PMOS tubes, and NM1, NM2, NM3, NM4, NM5, and NM6 are all NMOS tubes.

[0061] The timing of the chip pin floating detection circuit is as follows Figure 3 As shown, the workflow is as follows:

[0062] 1. The working flow diagram of the detection circuit is shown in Figure 4 .

[0063] 2. PIN is the chip pin to be tested.

[0064] 3. In the timing circuit, delay is the delay module, EN is the input enable signal, EN1, EN2, EN3, and EN4 are the delayed signals respectively. See the circuit timing diagram for details. Figure 4 . t0~t1 determines whether there is an external pull-down circuit for PIN, the result is latched at t1, the internal pull-up channel is switched to the pull-down channel at t2, t2~t3 determines whether there is an external pull-up circuit for PIN, the result is latched at t3, and the internal pull-down channel is closed at t4.

[0065] 4. CurrentSource is the reference current source, and the current size of the current source is I0.

[0066] 5. NM1, NM2, NM3, and NM4 form a current mirror circuit, and the currents flowing through them are I1, I2, I3, I4, I5, and I6 respectively. The channel width and length of NM1, NM2, NM3, and NM4 are the same, that is:

[0067]

[0068] Then I1=I2=I3=I4=I0.

[0069] 6. PM1, PM2, and PM3 form a current mirror circuit. The channel width and length of PM1, PM2, and PM3 are the same, that is:

[0070]

[0071] Then I5=I6=I2=I0.

[0072] 7. NM0, NM5, NM6, and PM4 form a switch circuit. When the signal EN is at a low level, NM0 is turned on and the circuit does not work. When the signal EN changes from a low level to a high level, NM0 is turned off and the circuit starts to work. After the circuit starts to work, if EN2 is at a low level, PM4 is turned on, NM6 is turned off, and the pull-up circuit of the PIN is turned on. When the signal EN2 changes from a low level to a high level, PM4 is turned off, NM6 is turned on, and the pull-up circuit of the PIN is turned off; if EN4 is at a low level, NM5 is turned on, and the pull-down circuit of the PIN is turned on. When the signal EN4 changes from a low level to a high level, NM5 is turned off, and the pull-down circuit of the PIN is turned off.

[0073] 8. R1 and R2 are used in the reference voltage generation circuit, and the reference voltages provided are Vdd-V R and V R. Take R1=R2=R, the voltage across R1 and R2 is equal, and the voltage across the resistor is V R =I0*R, choose a reasonable value for R so that V R About 200mV.

[0074] 9. U1 and U2 are comparators. The positive input of U1 is the voltage value when PIN is pulled up, and the negative input is the reference voltage Vdd-V R , the output high level indicates that PIN has no external pull-down circuit (PIN can be pulled up to close to Vdd). The positive input of U2 is the reference voltage V R The inverting input is the voltage value when the PIN is pulled down and driven. The output high level indicates that the PIN has no external pull-up circuit (the PIN can be pulled down to near ground).

[0075] 10. U3 and U4 are triggers used to save the comparison results. U3 saves the output result OUT1 of U1 at time t1 (rising edge of EN1). U4 saves the output result OUT2 of U2 at time t3 (rising edge of EN3).

[0076] 11. U6 and U7 are inverting circuits, used to invert signals EN and EN4, and the output signals are EN_N and EN4_N respectively.

[0077] 12. U5 is a logic AND gate, and the output result is Floating, which is used to determine whether the two comparison results are both high level. Floating is high level, indicating that the pin of the chip to be tested is floating, and Floating is low level, indicating that the pin of the chip to be tested is not floating.

[0078] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A chip pin floating detection circuit based on load potential, characterized in that: It includes a switch circuit connected to the PIN to be tested, a pull-up circuit and a pull-down circuit respectively connected to the PIN to be tested through the switch circuit, a first reference voltage circuit and a second reference voltage circuit respectively connected to the power supply voltage, a comparator U1 whose positive input is connected to the PIN to be tested and whose negative input is connected to the first reference voltage circuit, a comparator U2 whose negative input is connected to the PIN to be tested and whose positive input is connected to the second reference voltage circuit, a timing circuit connected to the pull-up circuit, the pull-down circuit and the switch circuit, a trigger U3 connected to the output end of the comparator U1, a trigger U4 connected to the output end of the comparator U2, a logic AND gate U5 connected to the output ends of the trigger U3 and the trigger U4, an inverting circuit U6 connected to the output end of the EN signal, and an inverting circuit U7 connected to the output end of the EN4 signal; The switch circuit includes an NMOS tube NM0 connected to the pull-down circuit and a fourth PMOS tube PM4, a fifth NMOS tube NM5, and a sixth NMOS tube NM6 connected between the pull-up circuit and the pull-down circuit; The pull-up circuit includes a PMOS tube current mirror circuit connected to the power supply voltage Vdd, and the pull-down circuit includes an NMOS tube current mirror circuit connected to the power supply voltage Vdd, and the PMOS tube current mirror circuit and the NMOS tube current mirror circuit copy the power supply voltage Vdd to the branch circuit in proportion; The timing circuit controls the pull-up circuit, the pull-down circuit, and the switch circuit to work in time sequence, the EN signal is an enable signal, and the EN1 signal, the EN2 signal, the EN3 signal, and the EN4 signal are obtained in sequence after the EN signal is delayed, the EN_N signal is an inverted signal of the EN signal, and the EN4_N signal is an inverted signal of the EN4 signal; The switch circuit controls the pull-up circuit and the pull-down circuit to drive the PIN to be tested respectively; The reference voltages provided by the first reference voltage circuit and the second reference voltage circuit are Vdd-V R and V R ; The positive input of the comparator U1 is the voltage value of the PIN to be tested when it is driven by the pull-up circuit, and the negative input is the reference voltage Vdd-V R , when the comparator U1 outputs a high level, the PIN to be tested has no external pull-down circuit; The non-inverting input of comparator U2 is the reference voltage V R , the inverting input is the voltage value when the PIN to be tested is driven by the pull-down circuit. When the comparator U2 outputs a high level, the PIN to be tested has no external pull-up circuit; The CLK pin of the trigger U3 inputs the EN1 signal, and the trigger U3 saves the output result OUT1 of U1 at time t1; the CLK pin of the trigger U4 inputs the EN3 signal, and the trigger U4 saves the output result OUT2 of U2 at time t3; The reverse circuit U6 outputs the EN_N signal, and the reverse circuit U7 outputs the EN4_N signal; The logic AND gate U5 infers whether the PIN to be tested is connected to an external pull-up circuit and / or an external pull-down circuit according to the level of the load potential.

2. A chip pin floating detection circuit based on load potential according to claim 1, characterized in that: The PMOS tube current mirror circuit comprises a first PMOS tube PM1, a second PMOS tube PM2 and a third PMOS tube PM3 whose gates are connected, the sources of PM1, PM2 and PM3 are all connected to the power supply voltage Vdd, the gate and drain of PM1 are connected, the drain is connected to the drain of the second NMOS tube NM2 in the NMOS tube current mirror circuit, and the drain of PM2 is connected to the source of PM4; The second reference voltage circuit includes a resistor R2, one end of which is connected to the drain of PM3 and the non-inverting input of the comparator U2, and the other end of which is connected to all sources of the pull-down circuit and then grounded; The gate of the NMOS tube NM0 inputs an EN_N signal, the source is grounded, and the drain is connected to the reference current CurrentSource; the gate and drain of an NMOS tube in the NMOS tube current mirror circuit are both connected to the reference current CurrentSource, the source is connected to the source of NM0 and then grounded, the source of NM6 is connected to the drain of an NMOS tube in the NMOS tube current mirror circuit, the drain is connected to the source of NM5, the gate inputs an EN2 signal, the drain of NM5 is connected to the drain of PM4, the gate inputs an EN4_N signal, the source of PM4 is connected to the drain of a PMOS tube in the PMOS tube current mirror circuit, the gate inputs an EN2 signal, and the PIN to be tested is connected to the drain of PM4 and the drain of NM5.

3. A chip pin hanging detection circuit based on load potential according to claim 2, characterized in that: The NMOS transistor current mirror circuit includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3 and a fourth NMOS transistor NM4, all of which have their gates connected, their sources connected and then grounded; The drain of NM1 is connected to the drain of NM0, the source and the gate are both connected to the reference current CurrentSource, the drain of NM3 is connected to the source of NM6, and the drain of NM4 is connected to the first reference voltage circuit; The first reference voltage circuit includes a resistor R1, one end of which is connected to all sources of the pull-up circuit and then to a power supply voltage Vdd, and the other end of which is connected to the drain of MM4 and the inverting input terminal of the comparator U1.

4. The chip pin floating detection circuit based on load potential according to claim 3, characterized in that: The currents flowing through NM1, NM2, NM3, and NM4 are I1, I2, I3, and I4 respectively, and the output current of the reference current CurrentSource is I0; The channel width and length of NM1, NM2, NM3, and NM4 are the same, I1 = I2 = I3 = I4 = I0; The currents flowing through PM1, PM2, and PM3 are I2, I5, and I6 respectively. The channel width and length of PM1, PM2, and PM3 are the same, and I5=I6=I2=I 0。 5. The chip pin floating detection circuit based on load potential according to claim 3, characterized in that: The resistance values ​​of the resistor R1 and the resistor R2 are the same, both R.

6. The chip pin floating detection circuit based on load potential according to claim 1, characterized in that: The signal timing of the timing circuit output is: At t0, the EN signal changes from low level to high level and then remains high level, and the EN1~EN4 signals are all low level; At t1, the EN1 signal changes from low level to high level and then remains at high level, and the EN2~EN4 signals are still at low level; At t2, the EN2 signal changes from low level to high level and then remains at high level, and the EN3~EN4 signals are still at low level; At t3, the EN3 signal changes from low level to high level and then remains at high level, while the EN4 signal remains at low level; At t4, the EN4 signal changes from low level to high level and then remains high level; At t0-t1, it is determined whether there is an external pull-down circuit for the PIN to be tested, the result is latched at t1, the pull-up circuit is switched to the pull-down circuit at t2, and at t2-t3, it is determined whether there is an external pull-up circuit for the PIN to be tested, the result is latched at t3, and the pull-down circuit is closed at t4.

7. A detection method for a chip pin floating detection circuit based on load potential according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1, opening the pull-up circuit connected to the PIN to be tested; S2, the comparator U1 determines whether the voltage of the PIN to be tested can be pulled up to close to the power supply voltage Vdd to obtain the pull-up result OUT1 and output it to the trigger U3; S3, trigger U3 latches the pull-up result OUT1; S4, close the pull-up circuit, and open the pull-down circuit connected to the PIN to be tested; S5, the comparator U2 determines whether the voltage of the PIN to be tested can be pulled down to close to ground to obtain a pull-down result OUT2 and outputs it to the trigger U4; S6, the trigger U4 latches the pull-down result OUT2, the circuit controls to proceed to step S7, and determines whether the pin is suspended and proceeds to step S8; S7, closing the pull-down circuit; S8. The logic AND gate U5 determines whether the pins of the external pull-up circuit and / or the external pull-down circuit of the PIN to be tested are suspended according to the pull-up result OUT1 and the pull-down result OUT2. A detection method for a chip pin suspension detection circuit based on load potential is completed.

8. The detection method of a chip pin floating detection circuit based on load potential according to claim 7, characterized in that: In step S1, when the EN signal is at a low level, NM0 is turned on, and the chip pin floating detection circuit does not work; at time t0, the EN signal changes from a low level to a high level, NM0 is turned off, and the chip pin floating detection circuit starts to work; In step S2, at time t0-t1, the EN2 signal is at a low level, PM4 is turned on, NM6 is turned off, the pull-up circuit is turned on, and the comparator U1 confirms the pull-up upper limit of the PIN to be tested, and determines whether the voltage value of the PIN to be tested when driven by the pull-up circuit can be pulled up to close to Vdd. If not, the comparator U1 outputs a low level, the PIN to be tested has an external pull-down circuit, and the external pull-down circuit is connected normally; if yes, the comparator U1 outputs a high level, the PIN to be tested is not connected to the external pull-down circuit, and the pin of the external pull-down circuit is suspended or does not exist; In step S3, at time t1, the EN1 signal is at a high level, and the trigger U3 latches the pull-up result OUT1; In step S4, at time t2, the EN2 signal changes from a low level to a high level, the EN4 signal is a low level, PM4 is turned off, NM6 is turned on, the pull-up circuit is turned off, NM5 is turned on, and the pull-down circuit is turned on; In step S5, at time t2-t3, the comparator U2 confirms the pull-down lower limit of the PIN to be tested, and determines whether the voltage value of the PIN to be tested when driven by the pull-down circuit can be pulled down to near the ground. If not, the comparator U1 outputs a low level, and the PIN to be tested has an external pull-up circuit, and the external pull-up circuit is connected normally; if yes, the comparator U1 outputs a high level, and the PIN to be tested is not connected to the external pull-up circuit, and the pin of the external pull-up circuit is suspended or does not exist; In step S6, at time t3, the EN3 signal is at a high level, and the trigger U4 latches the pull-down result OUT2; In step S7, at time t4, the EN4 signal changes from a low level to a high level, NM5 is turned off, and the pull-down circuit is turned off; In step S8 , the logic AND gate U5 determines the output result Floating, and the output result Floating includes the pull-up result OUT1 and the pull-down result OUT2 .

9. The detection method of a chip pin floating detection circuit based on load potential according to claim 8, characterized in that: In step S8, when the pull-up result OUT1 and the pull-down result OUT2 indicate that the comparator U1 and the comparator U2 are both at high levels, the pin of the PIN to be tested is suspended; when the pull-up result OUT1 and the pull-down result OUT2 indicate that the comparator U1 and the comparator U2 are both at low levels, the pin of the PIN to be tested is not suspended.

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