Method of processing a semiconductor structure and semiconductor structure

Abstract

The embodiments of the present disclosure provide a semiconductor structure processing method, a semiconductor structure forming method, and a semiconductor structure. The semiconductor structure processing method comprises: providing a semiconductor structure to be processed, the semiconductor structure comprising a substrate and a plurality of sub-structures disposed on the substrate; wherein a depth-width ratio of the sub-structure is greater than a preset ratio; forming a support layer, the support layer bridging a region between the plurality of sub-structures, a critical dimension of the region being less than a dimension threshold, and the support layer having at least one opening; performing a cleaning process on the semiconductor structure by using the opening; and removing the support layer on top of the plurality of sub-structures.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of semiconductor technology, and in particular to a method for processing a semiconductor structure and a semiconductor structure. Background Technology

[0002] As semiconductor integration density increases, the use of high aspect ratio structures is becoming increasingly common. High aspect ratio structures can have aspect ratios greater than 5:1, 10:1, or 20:1. In semiconductor manufacturing processes involving high aspect ratio structures, especially those with aspect ratios of 10 or higher, the surface tension of the liquid (i.e., capillary force) during cleaning and drying can cause the high aspect ratio structure to tilt or even collapse, thereby damaging the semiconductor structure and affecting the electrical performance of the final semiconductor product, resulting in lower product yield. Summary of the Invention

[0003] In view of this, the present disclosure provides a method for processing a semiconductor structure and a semiconductor structure.

[0004] This disclosure provides a method for processing a semiconductor structure, including:

[0005] A semiconductor structure to be processed is provided, the semiconductor structure including a substrate and multiple substructures disposed on the substrate; wherein the aspect ratio of the substructures is greater than a preset ratio value;

[0006] A support layer is formed, which bridges areas between multiple substructures where the critical dimensions are less than a size threshold, and the support layer has at least one opening;

[0007] Using openings to clean semiconductor structures;

[0008] Remove the support layers at the top of multiple substructures.

[0009] In some embodiments, the support layer is open in regions between multiple substructures where the critical size is greater than or equal to a size threshold, to form at least one of the openings.

[0010] In some embodiments, forming a support layer includes: depositing a first material on top of a plurality of substructures using a preset deposition process to form a support layer; the preset deposition process includes at least one of the following: selective atomic layer deposition process, plasma-enhanced chemical vapor deposition process.

[0011] In some embodiments, a hard mask layer is provided on top of the substructure.

[0012] In some embodiments, cleaning the semiconductor structure using an opening includes: ashing the semiconductor structure; and cleaning the ashed semiconductor structure using the opening.

[0013] In some embodiments, removing the support layer on top of multiple substructures includes: filling the spaces between the multiple substructures after cleaning with a second material to form a first filler layer covering the multiple substructures and the support layer; planarizing the surface of the first filler layer until the top surface of the support layer is exposed; and etching the planarized first filler layer and the support layer until the support layer is removed.

[0014] In some embodiments, removing the support layer on top of the plurality of substructures further includes forming a first padding layer on the cleaned surfaces of the plurality of substructures before forming the first filling layer.

[0015] In some embodiments, forming a first liner layer on the surfaces of a plurality of substructures after cleaning includes: performing thermal oxidation on the plurality of substructures after cleaning to form a first liner layer covering the surfaces of the plurality of substructures; or, depositing a third material on the surfaces of the plurality of substructures after cleaning to form a first liner layer covering the surfaces of the plurality of substructures and the surface of the support layer.

[0016] In some embodiments, the method further includes: performing a second cleaning process on the multiple substructures after the support layer has been removed.

[0017] In some embodiments, the method further includes filling the spaces between the plurality of substructures after a second cleaning process with a fourth material to form a second filling layer covering the top of the plurality of substructures and the first filling layer.

[0018] In some embodiments, the method further includes forming a second liner layer on top of a plurality of substructures after a second cleaning process, prior to forming the second filler layer.

[0019] In some embodiments, forming a second liner layer on top of a plurality of substructures after a second cleaning process includes: performing a thermal oxidation process on the top of the plurality of substructures after a second cleaning process to form a second liner layer covering the surface of the top of the plurality of substructures; or, depositing a fifth material on the surface of the plurality of substructures after a second cleaning process to form a second liner layer covering the surface of the plurality of substructures and the surface of the first filler layer.

[0020] This disclosure provides a semiconductor structure, including:

[0021] Substrate;

[0022] Multiple substructures are disposed on the substrate, and the aspect ratio of the substructures is greater than a preset ratio value;

[0023] A support layer covering the top of multiple substructures, the support layer bridging areas between the multiple substructures with critical dimensions less than a size threshold, and the support layer having at least one opening.

[0024] In some embodiments, the support layer is open in regions between multiple substructures where the critical size is greater than or equal to a size threshold, to form at least one opening.

[0025] In some embodiments, a hard mask layer is provided on top of the substructure, and a support layer covers the hard mask layer.

[0026] This disclosure provides a semiconductor structure, which is obtained by processing using any of the above-described semiconductor structure processing methods.

[0027] In this embodiment, a semiconductor structure to be processed is provided. The semiconductor structure includes a substrate and a plurality of substructures disposed on the substrate. The aspect ratio of the substructures is greater than a preset ratio. A support layer is formed, bridging regions between the plurality of substructures whose critical dimensions are less than a size threshold, and the support layer has at least one opening. The semiconductor structure is cleaned using the opening. The support layer on top of the plurality of substructures is removed. Thus, on the one hand, since the support layer covers the top of the plurality of substructures with an aspect ratio greater than the preset ratio, and the support layer bridges regions between the plurality of substructures whose critical dimensions are less than a size threshold, the support layer can stabilize the substructures during the cleaning process, reducing the damage to the substructures caused by liquid surface tension, thereby reducing the deformation of the substructures and improving the electrical performance of the semiconductor product and increasing product yield. On the other hand, since the support layer has at least one opening, the cleaning fluid can enter the gap region between the lower parts of the substructures during the cleaning process, achieving a better cleaning effect on the substructures. Furthermore, in some embodiments, during the process of removing the support layer on top of multiple substructures, a second material can be filled between the multiple substructures after cleaning to form a first filling layer covering the multiple substructures and the support layer. After removing the support layer, the multiple substructures are cleaned again. In this way, since there is a first filling layer between the multiple substructures during the second cleaning process, the aspect ratio of the substructures can be reduced, thereby reducing the damage of liquid surface tension to the substructures and further improving the product yield. Attached Figure Description

[0028] Figure 1A This is a schematic diagram of the deformation of a high aspect ratio structure during the cleaning process;

[0029] Figure 1B This is a schematic diagram illustrating the principle of how liquid surface tension affects structures with high aspect ratios.

[0030] Figure 2A A schematic diagram illustrating the implementation flow of a semiconductor structure processing method provided in this embodiment of the disclosure;

[0031] Figure 2B and Figure 2CThese are a top view of a semiconductor structure after a support layer has been formed on it, and a cross-sectional view of the semiconductor structure along the AA' direction, respectively, provided in the embodiments of this disclosure.

[0032] Figure 2D This is a schematic diagram of a hard mask layer in a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Figure 2E and Figure 2F These are a top view of a semiconductor structure and a cross-sectional view of the semiconductor structure along the AA' direction, respectively, provided in an embodiment of this disclosure.

[0034] Figure 2G and Figure 2H These are a top view of the semiconductor structure after the formation of the first filling layer in a semiconductor structure processing method provided in this embodiment of the present disclosure, and a cross-sectional view of the semiconductor structure along the AA' direction, respectively.

[0035] Figure 2I and Figure 2J These are a top view of the semiconductor structure after planarization and a cross-sectional view of the semiconductor structure along the AA' direction, respectively, provided in an embodiment of this disclosure.

[0036] Figure 2K and Figure 2L These are a top view of the semiconductor structure after the support layer is removed, and a cross-sectional view of the semiconductor structure along the AA' direction, respectively, provided in an embodiment of this disclosure.

[0037] Figure 2M This is a schematic cross-sectional view of the semiconductor structure after forming a first pad layer and a first fill layer in a semiconductor structure processing method provided in an embodiment of the present disclosure.

[0038] Figure 3A This is a schematic diagram of the structure of the first pad layer formed in a semiconductor structure processing method provided in this embodiment of the present disclosure;

[0039] Figure 3B This is a schematic diagram of the structure of the first pad layer formed in a semiconductor structure processing method provided in this embodiment of the present disclosure;

[0040] Figure 3C and Figure 3D These are a top view of the semiconductor structure after the formation of the second filling layer in a semiconductor structure processing method provided in this embodiment of the present disclosure, and a cross-sectional view of the semiconductor structure along the AA' direction, respectively.

[0041] Figure 3EA schematic cross-sectional view of the semiconductor structure after forming the second pad layer and the second fill layer in a semiconductor structure processing method provided in this embodiment of the present disclosure;

[0042] Figure 3F This is a schematic diagram of the structure of the second pad layer formed in a semiconductor structure processing method provided in this disclosure embodiment;

[0043] Figure 3G This is a schematic diagram of the structure of the second pad layer formed in a semiconductor structure processing method provided in this disclosure embodiment;

[0044] Figure 4 This is a schematic diagram illustrating the implementation process of a method for forming a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0048] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] like Figure 1A As shown, during the cleaning process of the semiconductor structure 10 with a high aspect ratio structure 11, the liquid height between each aspect ratio structure 11 is not equal. Due to the surface tension of the liquid, the high aspect ratio structure 11 will deform, thereby damaging the semiconductor structure 10 and affecting the electrical performance of the final semiconductor product, resulting in a low product yield. The principle is referenced... Figure 1B ,like Figure 1B As shown, there is a gap S between two separate high aspect ratio structures 11. At this time, the surface tension of the liquid at the top of the high aspect ratio structure is γ, and the angle between γ and the side of the high aspect ratio structure 11 is θ. Then, the force F acting on both sides of the high aspect ratio structure 11 is F=((2γcosθ) / S)*H*D, where H and D are the height of the liquid and the height of the high aspect ratio structure 11, respectively.

[0052] In some related technologies, surface modifiers (such as hexamethyloxydisilane, alkoxysilane, alkylsilane, fluorinated or long-chain hydrocarbons based on trichlorosilane, dichlorosilane, monochlorosilane, methoxysilane, and ethoxysilane) can be added to the surface of high aspect ratio structures. These modifiers alter the surface properties of the high aspect ratio structure, reducing static friction between two adjacent surfaces or increasing the hydrophobicity of the high aspect ratio structure surface, thereby helping to reduce the destructive effect of liquid surface tension γ on the high aspect ratio structure. However, the surface modifiers used in this approach are expensive, and the carbon, fluorine, or chlorine in the surface modifiers may remain on the high aspect ratio structure, requiring an additional dry plasma reaction asher process to remove the residues, thus increasing the process cost.

[0053] In some related technologies, after cleaning high aspect ratio structures, supercritical drying is used. This method utilizes supercritical fluid to dry the cleaned semiconductor structure. By directly transforming the supercritical fluid from its supercritical state to the gas phase, a gas-liquid interface is eliminated, thus eliminating surface tension that affects the high aspect ratio structure. This allows for the drying of the high aspect ratio structure without damaging it. However, this approach requires additional high-cost high-pressure supercritical dryers, as well as additional plant costs for high pressure and large quantities of supercritical fluid, resulting in high process costs.

[0054] In some related technologies, during the drying of high aspect ratio structures, stimulus-responsive materials, such as polymer-based materials, are used as sacrificial support materials to prevent structural collapse. The sacrificial support material solidifies on and around the high aspect ratio structure to provide mechanical support and prevent collapse during drying. After drying, the mechanical support can be removed using stimuli (such as ultraviolet light, heat, and / or non-plasma-based stimuli like chemicals). However, this approach involves costly stimulus-responsive materials, and the chemicals used for stimuli may remain on the high aspect ratio structure, requiring an additional dry plasma ashing process to remove residues, thus increasing process costs.

[0055] In view of this, embodiments of the present disclosure provide a method for processing a semiconductor structure, such as... Figure 2A As shown, the method includes steps S101 to S104, wherein:

[0056] Step S101: Provide a semiconductor structure to be processed. The semiconductor structure includes a substrate and a plurality of substructures disposed on the substrate. The aspect ratio of the substructures is greater than a preset ratio.

[0057] Here, the substrate can be a silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, etc. In some embodiments, the substrate can be a single-layer substrate or a multi-layer substrate, such as a single-crystal silicon single-layer substrate, a polycrystalline silicon single-layer substrate, a polycrystalline silicon and metal multilayer substrate, etc. In some embodiments, the substrate may also include other semiconductor elements or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.

[0058] Multiple substructures are formed on a substrate, each with an aspect ratio greater than a preset value. The substructures may be made of the same material as the substrate or a different material. In practice, the preset aspect ratio can be determined in advance by those skilled in the art based on actual conditions, and this disclosure does not limit this. In some embodiments, the substructures are high aspect ratio structures, and the preset aspect ratio may include, but is not limited to, 5:1, 10:1, or 20:1. In some embodiments, the substructures are high aspect ratio nanostructures.

[0059] In implementation, the substructure on the substrate can be formed by any suitable process, including but not limited to at least one of etching processes (such as wet etching process, dry etching process) and deposition processes (such as selective deposition process), and the embodiments disclosed herein are not limited in this respect.

[0060] In some implementations, a substrate may be provided first, and then multiple substructures with aspect ratios greater than a preset ratio may be selectively deposited on the substrate.

[0061] In some embodiments, a substrate and a capping layer disposed on the substrate can be provided first. A hard mask layer and a photoresist mask layer for defining substructures are patterned on the surface of the capping layer using a photolithography process. The capping layer is then etched based on the photoresist mask layer and the hard mask layer to form multiple substructures disposed on the substrate. Here, the capping layer can be made of the same material as the substrate, or it can be made of a different material.

[0062] Step S102: A support layer is formed, which bridges regions between multiple substructures whose critical dimensions are less than a size threshold, and the support layer has at least one opening.

[0063] Here, the support layer can cover the top of multiple substructures and bridge areas where the critical dimensions between the substructures are smaller than a size threshold. There are gaps between the multiple substructures; the critical dimension refers to the width of the gap between the substructures, which can be determined based on the actual design layout of the semiconductor structure. Areas where the critical dimension is smaller than the size threshold can be any gap between two substructures where the width is less than the size threshold. The size threshold can be determined based on the semiconductor structure's process requirements and / or the substructure's aspect ratio, etc. For example, when the semiconductor structure has high process requirements, a larger size threshold can be set to stabilize the corresponding substructures even with large critical dimensions between them, thereby improving the electrical performance of the semiconductor structure; when the semiconductor structure has lower process requirements, a smaller size threshold can be set, reducing the area of ​​the support layer and thus reducing process costs. For example, when the depth-to-width ratio of a substructure is large, the tilting caused by the surface tension of the liquid becomes more severe. Therefore, a larger size threshold can be set to stabilize the corresponding substructure even when the critical dimensions between substructures are large. When the depth-to-width ratio of a substructure is small, a smaller size threshold can be set to reduce the area of ​​the support layer and thus reduce the process cost.

[0064] In practice, the material forming the support layer can be any suitable material with a high etching selectivity ratio to the material forming the substructure, and this disclosure does not limit this. For example, the material forming the substructure can be silicon, silicon germanium, etc., and the material forming the support layer can be a nitride, etc.

[0065] Figure 2B and Figure 2C These are, respectively, a top view of a semiconductor structure after a support layer has been formed on it, and a cross-sectional view of the semiconductor structure along the AA' direction, according to embodiments of this disclosure. Figure 2B and Figure 2C As shown, the semiconductor structure 100 includes a substrate 110 and a plurality of substructures 120 disposed on the substrate 110; a formed support layer 130 covers the top of the plurality of substructures 120; the support layer 130 bridges regions 131 between the plurality of substructures 120 where the critical dimension CD1 is less than a size threshold, and the support layer has at least one opening 132.

[0066] Step S103: Clean the semiconductor structure using the opening.

[0067] Here, any suitable cleaning process can be used to clean the semiconductor structure in order to clean the surface of the substructure and the surface of the substrate.

[0068] Cleaning processes can remove etching byproducts and other substances that adhere to the surface of the substructure beneath the support layer during substructure formation. These etching byproducts may include, but are not limited to, at least one of carbon, silicon oxide, fluorides, and chlorides. In practice, a wet cleaning process can be used to clean the semiconductor structure. Since the support layer has at least one opening, the cleaning solution can enter the gaps between the substructures beneath the support layer to clean them. The cleaning liquid used may include, but is not limited to, at least one of hydrofluoric acid (e.g., 49% hydrofluoric acid, diluted hydrofluoric acid), a mixture of sulfuric acid and hydrogen peroxide in a molar ratio of 1:6 to 1:4 (i.e., SPM mixed solution), a mixture of ammonia, hydrogen peroxide, and water (i.e., SC1 mixed solution), and a mixture of hydrochloric acid, hydrogen peroxide, and water (i.e., SC2 mixed solution).

[0069] In some embodiments, the cleaned semiconductor structure may also be dried, thereby drying the substructure surface and the substrate surface. In practice, any suitable drying process can be used to dry the cleaned semiconductor structure, and this disclosure is not limited in this regard. The drying process may include, but is not limited to, at least one of liquid-phase drying, gas-phase drying, etc.

[0070] Step S104: Remove the support layer on top of multiple substructures.

[0071] Here, after cleaning, any suitable etching process can be used to remove the support layer, and the embodiments disclosed herein are not limited in this regard.

[0072] In some embodiments, the support layer can be etched using an etching gas or etchant with a high selectivity for both the material of the support layer and the material of the substructure, thereby removing the support layer and retaining the substructure. For example, the etching selectivity ratio of the etching gas or etchant for the material of the support layer and the material of the substructure can be 500:1.

[0073] In some implementations, to reduce recontamination of the substructure surface and substrate surface during the removal of the support layer, a gap filling layer can be formed by pre-filling material between the substructures based on subsequent process requirements. This protects the cleaned substructure surface and substrate surface and provides support for the substructure in subsequent processes.

[0074] In this embodiment, a semiconductor structure to be processed is provided. The semiconductor structure includes a substrate and a plurality of substructures disposed on the substrate. The aspect ratio of the substructures is greater than a preset ratio. A support layer is formed, bridging regions between the plurality of substructures whose critical dimensions are less than a size threshold, and the support layer has at least one opening. The semiconductor structure is cleaned using the opening. The support layer on top of the plurality of substructures is removed. Thus, on the one hand, since the support layer covers the top of the plurality of substructures with an aspect ratio greater than the preset ratio, and the support layer bridges regions between the plurality of substructures whose critical dimensions are less than a size threshold, the support layer can stabilize the substructures during the cleaning process, reducing the damage to the substructures caused by liquid surface tension, thereby reducing the deformation of the substructures and improving the electrical performance of the semiconductor product and increasing product yield. On the other hand, since the support layer has at least one opening, the cleaning fluid can enter the gap region between the lower parts of the substructures during the cleaning process, achieving a better cleaning effect on the substructures. Furthermore, in the semiconductor structure processing method provided in this disclosure embodiment, there is no need to use high-cost surface modifiers, supercritical fluids, and stimulus-responsive materials, thereby reducing process costs. Moreover, by removing the support layer after the cleaning process, the impact of the support layer on the electrical performance of the semiconductor product can be further reduced.

[0075] In some embodiments, see continue to see Figure 2B and Figure 2C The support layer 130 is open in areas where the critical dimension CD2 is greater than or equal to a size threshold between the multiple substructures 120, forming at least one opening 132. Here, the area where the critical dimension is greater than or equal to the size threshold can be a gap area where the width of the gap between any two substructures is greater than or equal to the size threshold. In this way, since the support layer is open in areas where the critical dimension is greater than or equal to the size threshold between the multiple substructures, the formed openings can be larger, facilitating the inflow and outflow of cleaning fluid in subsequent cleaning processes, and further reducing the area of ​​the support layer, thereby reducing process costs.

[0076] In some embodiments, step S102 may include the following step S111:

[0077] Step S111: A first material is deposited on top of multiple substructures using a preset deposition process to form a support layer; the preset deposition process includes at least one of the following: selective atomic layer deposition process, and plasma-enhanced chemical vapor deposition process.

[0078] Here, the first material can be a suitable material selected according to the actual situation, and may include, but is not limited to, nitrides.

[0079] Since selective atomic layer deposition (SALD) and ion-enhanced chemical vapor deposition (ICVD) both have poor step coverage, SALD and / or ICVD can be used to deposit the first material only on top of multiple substructures, forming a support layer covering the top of multiple substructures.

[0080] In some embodiments, see Figure 2D A hard mask layer 140 is provided on the top of the substructure 120.

[0081] In some embodiments, step S111 above may include the following step S121:

[0082] Step S121: Using a preset deposition process, a first material is deposited on the surface of the hard mask layer to form a support layer.

[0083] Here, in some embodiments, a photoresist mask layer and a hard mask layer can be patterned during the etching of the substructure; then, after the substructure is etched, the patterned photoresist mask layer can be removed, leaving the hard mask layer on top of the substructure.

[0084] In some implementations, instead of patterning a hard mask layer during the etching of the substructure, a hard mask layer can be deposited on the surface of the substructure after etching to form the substructure.

[0085] In practice, the materials used to deposit the hard mask layer may include, but are not limited to, silicon oxide, thermal oxide, tetraethyl orthosilicate (TEOS) oxide, high-density plasma oxide, atomic layer deposition oxide, or spin dielectric oxide.

[0086] In the above embodiments, by first setting a hard mask layer on top of the substructure before depositing and forming the support layer, the hard mask layer can act as a protective layer to protect the top of the substructure.

[0087] In some embodiments, the cleaning process of the semiconductor structure using the opening described in step S103 above may include the following steps S131 to S132:

[0088] Step S131: Ashing treatment is performed on the semiconductor structure;

[0089] Step S132: Clean the ashing semiconductor structure using the opening.

[0090] Here, ashing can be used to ashing the remaining etching gas or etching liquid, preventing the residual etching gas or etching liquid from continuing to etch the substructure or substrate.

[0091] See Figure 2E and Figure 2FDuring the formation of substructure 120, some etching byproducts 21 may adhere to the surface of the substructure and the substrate under the support layer 130. By performing ashing treatment on the semiconductor structure and cleaning the multiple substructures 120 and the substrate 110 in the ashing semiconductor structure using the opening 132, the etching byproducts 21 can be removed.

[0092] In some embodiments, an oxygen-free ashing process can be used to ashing the semiconductor structure. This involves using a first mixed gas containing at least hydrogen and nitrogen to ashing the semiconductor structure, thereby removing corrosive gases and polymeric materials remaining on the surface after etching. For oxygen-free ashing, since the mixed gas does not contain oxygen, it does not damage the surface of the semiconductor structure (it does not oxidize the surfaces of the substrate, substructures, and support layers). Furthermore, the use of hydrogen effectively removes corrosive gases and polymeric materials remaining on the surface of the semiconductor structure.

[0093] In some embodiments, an oxygen-based ashing process can be used to ashing the semiconductor structure. This involves using a second oxygen-containing gas mixture, which includes at least hydrogen, nitrogen, and oxygen. Oxygen-based ashing offers higher ashing efficiency due to the presence of oxygen in the gas mixture, allowing for faster removal of corrosive gases and polymers remaining on the semiconductor structure surface after etching.

[0094] In the above embodiments, by performing ashing treatment on the semiconductor structure and using the openings of the support layer to clean the ashing semiconductor structure, the surface of the substructure under the support layer and the substrate surface can be cleaned better.

[0095] In some embodiments, step S104 may include steps S141 to S143 as follows:

[0096] Step S141: Fill the spaces between the multiple substructures after cleaning with a second material to form a first filling layer covering the multiple substructures and the support layer.

[0097] Here, the second material includes at least one of the following: oxides and nitrides. In practice, the second material may include oxides (such as silicon oxide, germanium oxide, etc.), nitrides (such as silicon nitride, germanium nitride, etc.), or oxide-nitride compositions; this disclosure is not limiting in this regard. In some embodiments, the first filling layer may serve as a dielectric layer for isolation between conductive layers.

[0098] Figure 2G and Figure 2HThese are, respectively, a top view of the semiconductor structure after the formation of the first filling layer and a cross-sectional view of the semiconductor structure along the AA' direction, as provided in the semiconductor structure processing method of this disclosure. Figure 2G and Figure 2H As shown, filling the spaces between the multiple substructures 120 after cleaning with a second material can form a first filling layer 150 covering the multiple substructures 120 and the support layer 130.

[0099] Step S142: Planarize the surface of the first filling layer until the top surface of the support layer is exposed.

[0100] Here, planarization can include, but is not limited to, etching and / or polishing. Etching can include, for example, wet etching or dry etching. Polishing can include, for example, chemical mechanical polishing (CMP).

[0101] In some embodiments, the surface of the first filler layer can be chemically reacted with oxidants, catalysts, etc. used in the polishing process to generate a relatively easy-to-remove soft layer; then the soft layer is removed under the mechanical action of abrasives and polishing pads used in the polishing process; repeating the aforementioned steps of generating and removing the soft layer, the surface of the first filler layer can be planarized under the combined action of chemical reaction and mechanical grinding until the top surface of the support layer is exposed.

[0102] In some embodiments, the surface of the first filler layer can be etched to remove the surface layer of the first filler layer; then, the residue after etching can be removed by cleaning; repeating the etching and cleaning processes can make the surface of the first filler layer achieve a suitable flatness, thereby achieving the planarization of the surface of the first filler layer until the top surface of the support layer is exposed.

[0103] Figure 2I and Figure 2J These are, respectively, a top view of the semiconductor structure after planarization and a cross-sectional view of the semiconductor structure along the AA' direction, as provided in the semiconductor structure processing method of this disclosure. Figure 2I and Figure 2J As shown, after planarizing the surface of the first filling layer 150, the top surface of the support layer 130 can be exposed.

[0104] Step S143: Etch the first filler layer and support layer after planarization until the support layer is removed.

[0105] Here, the first filler layer and the support layer can be etched simultaneously until the support layer is removed; alternatively, the first filler layer can be etched first to expose the entire support layer, and then the support layer can be etched to remove it. In practice, any suitable etching process can be used to etch the first filler layer and the support layer, such as wet etching or dry etching, etc., and this disclosure is not limited in this regard.

[0106] Figure 2K and Figure 2L These are, respectively, a top view of the semiconductor structure after removing the support layer in a semiconductor structure processing method provided in this disclosure, and a cross-sectional view of the semiconductor structure along the AA' direction. Figure 2K and Figure 2L As shown, the upper part of the first filling layer 150 and the support layer 130 can be etched to remove the support layer 130 and expose the top of each substructure 120.

[0107] In the above embodiments, a second material is filled between the multiple substructures after cleaning to form a first filling layer covering the multiple substructures and the support layer; the surface of the first filling layer is planarized until the top surface of the support layer is exposed; the planarized first filling layer and the support layer are etched until the support layer is removed. In this way, since the first filling layer can stabilize the multiple substructures, damage to the substructures during the removal of the support layer can be reduced, and contamination of the substructures and substrate beneath the support layer can be minimized.

[0108] In some embodiments, step S104 may further include the following step S151:

[0109] Step S151: Before forming the first filling layer, a first padding layer is formed on the surfaces of multiple substructures after cleaning.

[0110] Here, before filling the first filling layer with the second material, a first padding layer can be formed on the surfaces of multiple substructures after cleaning. Then, the second material is filled between the multiple substructures after the first padding layer is formed to form a first filling layer covering the substructures, the support layer, and the first padding layer.

[0111] In practice, the material of the first liner layer formed may include, but is not limited to, at least one of thermal oxides (such as silicon dioxide), silicon, oxides, nitrides, etc., and the embodiments disclosed herein are not limited in this regard.

[0112] Figure 2M This is a schematic cross-sectional view of the semiconductor structure after forming the first pad layer and the first fill layer in a semiconductor structure processing method provided in this embodiment of the present disclosure, as shown in the figure. Figure 2MAs shown, a first padding layer 160 is formed on the surface of multiple substructures 120 after cleaning, and a first filling layer 150 covers the substructures 120, the support layer 130 and the first padding layer 160.

[0113] In this way, on the one hand, the first pad layer can repair the damage caused to the surface of the substructure during the etching process; on the other hand, the first pad layer can protect the substructure and reduce the damage to the substructure caused by device stress or etching operations in subsequent processes.

[0114] In some embodiments, step S151 may include step S161 or step S162:

[0115] Step S161: Perform thermal oxidation on the multiple substructures after cleaning to form a first liner layer covering the surfaces of the multiple substructures.

[0116] In some embodiments, the material of the first liner layer may include thermal oxides (such as silicon dioxide). See also Figure 3A Thermal oxides can be generated on the surface of substructure 120 and substrate 110 through thermal oxidation treatment to form a first pad layer 160 covering the surface of each substructure 120.

[0117] Step S162: Deposit a third material on the multiple substructure surfaces after cleaning to form a first liner layer covering the multiple substructure surfaces and the support layer surface.

[0118] In some embodiments, the third material may include at least one of the following: silicon, oxide, or nitride. Silicon may include, but is not limited to, at least one of amorphous silicon, polycrystalline silicon, and crystalline silicon. The oxide may include, but is not limited to, at least one of ethyl silicate oxide and atomic layer deposited oxide. See also... Figure 3B A third material can be deposited on the surface of the substructure 120 and the surface of the support layer 130 to form a first liner layer 160 covering the surface of each substructure 120 and the surface of the support layer 130.

[0119] In some embodiments, the above method may further include the following step S171:

[0120] Step S171: Clean the multiple substructures after removing the support layer again;

[0121] Here, see continue. Figure 2E and Figure 2FDuring the formation of substructure 120, some etching byproducts 22 may adhere to the top of substructure 120. After the support layer 130 is formed, the etching byproducts 22 are covered under the support layer 130. Therefore, multiple substructures after the support layer 130 is removed can be cleaned again to remove the etching byproducts 22 adhering to the top of substructure 120.

[0122] When implementing the process, the cleaning solution used for the second cleaning treatment may include, but is not limited to, at least one of diluted hydrofluoric acid, buffered oxide etching solution (made of 49% concentration hydrofluoric acid and water, or ammonium fluoride and water), phosphoric acid, SPM mixed solution, or SC1 mixed solution.

[0123] In some embodiments, after step S171, the above method may further include the following step S172:

[0124] Step S172: Fill the spaces between the multiple substructures after the second cleaning process with a fourth material to form a second filling layer covering the top of the multiple substructures and the first filling layer.

[0125] Here, the fourth material includes at least one of the following: oxides and nitrides. In practice, the fourth material may include oxides (such as silicon oxide, germanium oxide, etc.), nitrides (such as silicon nitride, germanium nitride, etc.), or oxide-nitride compositions; this disclosure is not limiting in this regard. In some embodiments, the second filling layer may serve as a dielectric layer for isolation between conductive layers.

[0126] Figure 3C and Figure 3D These are, respectively, a top view of the semiconductor structure after the formation of the second filling layer in a semiconductor structure processing method provided in this disclosure, and a cross-sectional view of the semiconductor structure along the AA' direction. Figure 3C and Figure 3D As shown, filling the spaces between the multiple substructures 120 after the second cleaning process with a fourth material can form a second filling layer 170 covering the top of the multiple substructures 120 and the first filling layer 150.

[0127] In the above embodiments, the support layer is removed after the first filling layer is formed. During the process of cleaning multiple substructures after the support layer is removed, the first filling layer can stabilize the substructure and reduce the aspect ratio of the substructure to reduce the damage of liquid surface tension to the substructure, thereby reducing the deformation of the substructure, and thus improving the electrical performance of the semiconductor product and increasing the product yield.

[0128] In some embodiments, prior to step S172, the method may further include step S181:

[0129] Step S181: Before forming the second filling layer, a second liner layer is formed on top of the multiple substructures after the second cleaning treatment.

[0130] Here, before filling the fourth material to form the second filling layer, a first padding layer can be formed on the surfaces of multiple substructures after the second cleaning process. Then, the fourth material is filled between the multiple substructures after the first padding layer is formed to form a second filling layer covering the top of the multiple substructures, the first filling layer, and the second padding layer.

[0131] In practice, the material of the second liner layer formed may include, but is not limited to, at least one of thermal oxides (such as silicon dioxide), silicon, oxides, nitrides, etc., and the embodiments disclosed herein are not limited in this regard.

[0132] It should be noted that the material of the second liner layer can be the same as or different from that of the first liner layer; the process of forming the second liner layer can be the same as or different from that of forming the first liner layer.

[0133] here, Figure 3E This is a schematic cross-sectional view of the semiconductor structure after forming the second pad layer and the second fill layer in a semiconductor structure processing method provided in this embodiment of the present disclosure, as shown in the figure. Figure 3E As shown, a second liner layer 180 is formed on top of multiple substructures 120 after a second cleaning process, and a second filler layer 170 covers the top of the substructures 120, the first filler layer 150, and the second liner layer 180.

[0134] In this way, on the one hand, the second pad layer can repair the damage caused to the surface of the substructure during the removal of the support layer and / or the hard mask layer set on top of the substructure; on the other hand, the second pad layer can protect the substructure and reduce the damage to the substructure caused by device stress or etching operations in subsequent processes; furthermore, the second pad layer can compensate for the critical dimensions of the upper part of the substructure, so that the critical dimensions of the upper part of the substructure after the formation of the second pad layer are consistent with the critical dimensions of the lower part of the substructure after the formation of the first pad layer.

[0135] In some embodiments, step S181 may include step S191 or step S192:

[0136] Step S191: Perform thermal oxidation on the top of the multiple substructures after the second cleaning process to form a second liner layer covering the top surface of the multiple substructures.

[0137] In some embodiments, the material of the second liner layer may include thermal oxides (such as silicon dioxide). See also Figure 3FThermal oxides can be generated on the surface of substructure 120 through thermal oxidation treatment to form a second liner layer 180 covering the top surface of each substructure 120.

[0138] Step S192: Deposit a fifth material on the multiple substructure surfaces after the second cleaning process to form a second liner layer covering the multiple substructure surfaces and the surface of the first filler layer.

[0139] In some embodiments, the fifth material may include at least one of the following: silicon, oxide, or nitride. Silicon may include, but is not limited to, at least one of amorphous silicon, polycrystalline silicon, and crystalline silicon. The oxide may include, but is not limited to, at least one of ethyl silicate oxide and atomic layer deposited oxide. See also Figure 3G A fifth material can be deposited on the surface of the substructure 120 and the surface of the first filler layer 150 to form a second liner layer 180 covering the top surface of each substructure 120 and the surface of the first filler layer 150.

[0140] This disclosure provides a semiconductor structure, see [link to relevant documentation] Figure 2B and Figure 2C The semiconductor structure 100 includes:

[0141] Substrate 110;

[0142] Multiple substructures 120 are disposed on the substrate 110, and the aspect ratio of the substructures 120 is greater than a preset ratio value;

[0143] A support layer 130 covers the top of multiple substructures 120, the support layer 130 bridges regions 131 between the multiple substructures 120 where the critical dimension CD1 is less than a size threshold, and the support layer 130 has at least one opening.

[0144] In some embodiments, see continue to see Figure 2B and Figure 2C The support layer 130 is open in areas where the critical dimension CD2 is greater than or equal to a size threshold among the multiple substructures 120, to form at least one opening 132.

[0145] In some embodiments, see Figure 2D A hard mask layer 140 is provided on the top of the substructure 120, and a support layer 130 covers the hard mask layer 140.

[0146] In some embodiments, the support layer is made of a nitride material; the hard mask layer is made of an oxide material.

[0147] This disclosure provides a method for forming a semiconductor structure. Figure 4 This is a schematic diagram illustrating the implementation flow of a method for forming a semiconductor structure according to an embodiment of this disclosure. Figure 4As shown, the method includes the following steps S401 to S403:

[0148] Step S401, provide a substrate;

[0149] Step S402: A plurality of substructures are formed on the substrate, wherein the aspect ratio of the substructures is greater than a preset ratio.

[0150] Step S403: Form a support layer covering the top of the plurality of substructures, the support layer bridging areas between the plurality of substructures with critical dimensions less than a size threshold, and the support layer having at least one opening.

[0151] This disclosure provides a semiconductor structure obtained by processing the semiconductor structure using the processing method described in any of the above processing method embodiments.

[0152] The above-described semiconductor structure embodiments have similar beneficial effects to the semiconductor structure processing method embodiments. For technical details not disclosed in the semiconductor structure embodiments of this disclosure, please refer to the description of the semiconductor structure processing method embodiments of this disclosure for understanding.

[0153] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0154] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0155] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0156] The above description is only some implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present disclosure should be included within the protection scope of the present disclosure.

Claims

1. A method for processing a semiconductor structure, characterized in that, The method includes: A semiconductor structure to be processed is provided, the semiconductor structure including a substrate and a plurality of substructures disposed on the substrate; wherein the aspect ratio of the substructures is greater than a preset ratio value; A support layer is formed, which bridges regions between the plurality of substructures where the critical dimension is less than a size threshold, and the support layer has at least one opening; the critical dimension is the width of the gap between the substructures; The semiconductor structure is cleaned using the opening; Remove the support layer at the top of the plurality of substructures.

2. The method according to claim 1, characterized in that, The support layer is open in areas where the critical dimensions between the plurality of substructures are greater than or equal to the size threshold, to form at least one of the openings.

3. The method according to claim 1, characterized in that, The formation of the support layer includes: A first material is deposited on top of the plurality of substructures using a preset deposition process to form the support layer; the preset deposition process includes at least one of the following: selective atomic layer deposition process, and plasma-enhanced chemical vapor deposition process.

4. The method according to claim 3, characterized in that, A hard mask layer is provided on the top of the substructure.

5. The method according to any one of claims 1 to 4, characterized in that, The cleaning process of the semiconductor structure using the opening includes: The semiconductor structure is subjected to ashing treatment; The ashing process is performed on the semiconductor structure through the opening.

6. The method according to claim 1, characterized in that, The removal of the support layer at the top of the plurality of substructures includes: A second material is filled between the plurality of substructures after cleaning to form a first filling layer covering the plurality of substructures and the support layer; The surface of the first filling layer is planarized until the top surface of the support layer is exposed; The first filling layer and the support layer after planarization are etched until the support layer is removed.

7. The method according to claim 6, characterized in that, The removal of the support layer at the top of the plurality of substructures further includes: Before the first filling layer is formed, a first padding layer is formed on the surfaces of the plurality of substructures after the cleaning process.

8. The method according to claim 7, characterized in that, The formation of a first liner layer on the surfaces of the plurality of substructures after cleaning includes: The multiple substructures after cleaning are subjected to thermal oxidation to form a first liner layer covering the surface of the multiple substructures. or, A third material is deposited on the surfaces of the plurality of substructures after cleaning to form a first liner layer covering the surfaces of the plurality of substructures and the surface of the support layer.

9. The method according to any one of claims 6 to 8, characterized in that, The method further includes: The multiple substructures after the support layer has been removed are then cleaned again.

10. The method according to claim 9, characterized in that, The method further includes: A fourth material is filled between the plurality of substructures after the second cleaning process to form a second filling layer covering the top of the plurality of substructures and the first filling layer.

11. The method according to claim 10, characterized in that, The method further includes: Before the second filling layer is formed, a second liner layer is formed on top of the plurality of substructures after a second cleaning process.

12. The method according to claim 11, characterized in that, The process of forming a second liner layer on top of the plurality of substructures after a second cleaning process includes: After the secondary cleaning process, the top of the multiple substructures is subjected to thermal oxidation to form a second liner layer covering the top surface of the multiple substructures. or, A fifth material is deposited on the surfaces of the plurality of substructures after a second cleaning process to form a second liner layer covering the surfaces of the plurality of substructures and the surface of the first filler layer.

13. A semiconductor structure, characterized in that, include: Substrate; Multiple substructures are disposed on the substrate, wherein the aspect ratio of the substructures is greater than a preset ratio value; A support layer covering the top of the plurality of substructures, the support layer bridging areas between the plurality of substructures with a critical dimension less than a size threshold, and the support layer having at least one opening; the critical dimension being the width of the gap between the substructures.

14. The semiconductor structure according to claim 13, characterized in that, The support layer is open in areas where the critical dimensions between the plurality of substructures are greater than or equal to the size threshold, to form at least one of the openings.

15. The semiconductor structure according to claim 13, characterized in that, A hard mask layer is provided on the top of the substructure, and the support layer covers the hard mask layer.

16. A semiconductor structure, characterized in that, The semiconductor structure is obtained by processing according to any one of claims 1-12.

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