Display panel and display device

Abstract

A display panel and a display device, a display area of the display panel includes a sub-display area and a main display area, the sub-display area includes a light-transmitting area and a circuit area. The driving backboard includes pixel circuits and first reset signal lines, the pixel circuits include first pixel circuits and second pixel circuits, part of the first pixel circuits are located in the main display area and the circuit area, and the second pixel circuits are located in the circuit area; part of the first reset signal lines include first reset segments and second reset segments arranged intermittently along a first direction; the first reset segments are located in the main display area, and the second reset segments are located in the circuit area; the light-emitting devices include first light-emitting devices located in the main display area and the circuit area and second light-emitting devices located in the light-transmitting area; the first light-emitting devices in the main display area are connected with part of the first reset signal lines located in the main display area through the first pixel circuits in the main display area; and the light-emitting devices in the sub-display area are connected with the second reset segments through the pixel circuits in the circuit area.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] With the development of display technology, full display with camera (FDC) has been gradually applied to display products due to its advantage of a large screen-to-body ratio. Full-screen display devices typically place optical components such as cameras under the display panel, greatly improving the screen-to-body ratio.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a display panel and a display device.

[0005] According to one aspect of this disclosure, a display panel is provided having a display area and a peripheral area at least partially surrounding the display area; the display area includes a sub-display area and a main display area located on at least one side of the sub-display area, the sub-display area including a light-transmitting area and a circuit area located on at least one side of the light-transmitting area; The driving backplane includes multiple arrayed pixel circuits and multiple first reset signal lines. Each pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuits are located in the main display area and the circuit area, and the second pixel circuits are located in the circuit area. The multiple first reset signal lines extend along a first direction, and some of these first reset signal lines are first-type first reset signal lines, while others are second-type first reset signal lines. The second-type first reset signal lines include first reset segments and second reset segments intermittently arranged along the first direction. The first reset segments are located in the main display area, and the second reset segments are located in the circuit area. Multiple light-emitting devices are located on one side of the driving backplate, including a first light-emitting device located in the main display area and the circuit area, and a second light-emitting device located in the light-transmitting area; the first light-emitting device is connected to the first pixel circuit, and the second light-emitting device is connected to the second pixel circuit via an adapter cable; The first reset segment is connected to a portion of the first pixel circuit within the main display area, and the first reset segment is configured to provide a first type of reset signal to the first pixel circuit within the main display area; the second reset segment is connected to the first pixel circuit and the second pixel circuit of the circuit area, and the second reset segment is configured to provide a second type of reset signal to the first pixel circuit and the second pixel circuit of the circuit area.

[0006] In one exemplary embodiment of this disclosure, the drive backplane further includes: The first reset bus is located in the peripheral area; The second reset bus is located in the peripheral area and is spaced apart from the first reset bus. The second reset bus is connected to the first reset segment of the main display area. A first reset connection line extends from the peripheral area into the display area along a second direction, and the first reset connection line connects the first reset bus and the second reset segment; The first direction and the second direction intersect.

[0007] In one exemplary embodiment of this disclosure, in the first direction, there is a gap region extending along the second direction between the main display area and the circuit area, and the first reset connection line is located within the gap region.

[0008] In one exemplary embodiment of this disclosure, the number of circuit areas in the sub-display area is two, and they are respectively located on both sides of the light-transmitting area along the first direction; the two circuit areas are separated from the main display area; The number of the first reset connection lines is two, and the first reset connection lines are provided in both of the two interval areas. Both of the first reset connection lines are connected to the first reset bus.

[0009] In one exemplary embodiment of this disclosure, there are two sub-display areas and four first reset connection lines; each of the interval areas is provided with a first reset connection line, and all four first reset connection lines are connected to the first reset bus.

[0010] In one exemplary embodiment of this disclosure, among the two first reset connection lines located on both sides of a sub-display area, the first end of the two first reset connection lines is connected to the first reset bus, and the second end of the two first reset connection lines is connected by a connection trace extending along the first direction.

[0011] In one exemplary embodiment of this disclosure, the peripheral area includes a fan-out area extending in a direction away from the display area; The first reset bus includes a first bus segment, a second bus segment, and a third bus segment. The first bus segment and the second bus segment are located on both sides of the display area and extend to the fan-out area. The third bus segment is located on the side of the display area away from the fan-out area and connects the first bus segment and the second bus segment. The first reset connection line is connected to the third bus segment. The second reset bus is located on both sides of the display area and extends to the fan-out area. The second reset bus is disconnected on the side of the display area away from the fan-out area, and the first reset connection line passes through the location where the second reset bus is disconnected.

[0012] In one exemplary embodiment of this disclosure, the number of sub-display areas is multiple, and they are spaced apart along the first direction; The main display area between two adjacent sub-display areas is provided with a second reset connection line extending along the second direction; at least one first type of first reset signal line is connected to the first reset segment between two adjacent sub-display areas through the second reset connection line.

[0013] In one exemplary embodiment of this disclosure, there are two second reset connection lines between the two sub-display areas, and they are spaced apart along the first direction; the first reset segment between two adjacent sub-display areas is connected by the two second reset connection lines.

[0014] In one exemplary embodiment of this disclosure, two first reset segments of the same first reset signal line separated by a sub-display area in the first direction are connected by a lead; at least a portion of the lead is located on the side of the first reset segment to which it is connected that is closer to the fan-out area, or at least a portion of the lead is located on the side of the first reset segment to which it is connected that is farther away from the fan-out area.

[0015] In one exemplary embodiment of this disclosure, the first reset signal line includes a plurality of routing units distributed along the first direction and a connection unit connected to two adjacent routing units, wherein the connection unit and the routing units are located on different layers. Both the first reset segment and the second reset segment include multiple wiring units and connection units; In a first reset signal line having a first reset segment and a second reset segment, a connection unit is intermittently disposed in the interval area, with one end connected to a routing unit of the first reset segment and the other end connected to a routing unit of the second reset segment; The first reset connection line intersects with the intermittently arranged connection unit.

[0016] In one exemplary embodiment of this disclosure, the wiring unit, the first reset connection line, and the second reset connection line are disposed on the same layer and located on the side of the connection unit closer to the light-emitting device.

[0017] In one exemplary embodiment of this disclosure, the first reset connection line and the second reset connection line are disposed on the same layer and located on the side of the wiring unit away from the connection unit.

[0018] In one exemplary embodiment of this disclosure, the second reset connection line is intersected and connected to a portion of the connection units.

[0019] In one exemplary embodiment of this disclosure, each pixel circuit is divided into multiple array-distributed circuit groups; one circuit group includes multiple circuit units distributed along the first direction; one circuit unit includes two pixel circuits distributed along the first direction. In the first direction, the distance between two adjacent circuit groups is greater than the distance between two adjacent pixel circuits; the two pixel circuits of the same circuit unit are symmetrically arranged about a straight line extending along the second direction; The interval region is a portion of the area between two adjacent circuit groups.

[0020] In one exemplary embodiment of this disclosure, the pixel circuit includes a first reset transistor; In the circuit area, the second reset segment is connected to the light-emitting device through the first reset transistor; In the main display area, the first reset segment is connected to the light-emitting device through the first reset transistor.

[0021] In one exemplary embodiment of this disclosure, the display panel further includes: An adapter layer is disposed between the driving backplate and the light-emitting device, and includes the adapter wire, which extends from the circuit area to the light-transmitting area. At least one second light-emitting device is connected to at least one second pixel circuit through at least one of the adapter wires.

[0022] According to one aspect of this disclosure, a display device is provided, comprising: The display panel described in any of the above items; A photosensitive element is located on the side of the driving backplate away from the plurality of light-emitting devices, and the orthographic projection of the photosensitive element on the driving backplate at least partially overlaps with the orthographic projection of the light-transmitting area on the driving backplate.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 This is a top view of one embodiment of the display panel of this disclosure.

[0026] Figure 2 This is a partial schematic diagram of the pixel circuit and light-emitting device of one embodiment of the display panel of this disclosure.

[0027] Figure 3 This is a schematic diagram of the pixel circuit in one embodiment of the display panel of this disclosure.

[0028] Figure 4 This is a cross-sectional schematic diagram of one embodiment of the display panel of this disclosure.

[0029] Figure 5 for Figure 1 A partial view of section A in the middle.

[0030] Figure 6 for Figure 5 A schematic diagram of the first semiconductor layer and the first gate layer.

[0031] Figure 7 for Figure 5 A schematic diagram of the first semiconductor layer to the second gate layer.

[0032] Figure 8 for Figure 5 A schematic diagram of the first semiconductor layer to the third gate layer.

[0033] Figure 9 for Figure 5 A schematic diagram of the first semiconductor layer to the first source / drain layer.

[0034] Figures 10-16 They are respectively Figure 5 A partial schematic diagram of some of the membrane layers.

[0035] Figure 17 for Figure 5 A partial view of section B in the middle.

[0036] Figures 18-20 for Figure 17 A partial schematic diagram of some of the membrane layers.

[0037] Figure 21This is a top view of another embodiment of the display panel of this disclosure.

[0038] Figure 22 This is a top view of another embodiment of the display panel of this disclosure.

[0039] Figure 23 This is a top view of another embodiment of the display panel of this disclosure.

[0040] Figure 24 This is a top view of one embodiment of the display device of this disclosure. Detailed Implementation

[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0042] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0043] In this document, the first direction can be represented by the row direction X, and the second direction can be represented by the column direction Y. The row direction X and the column direction Y are only two intersecting directions, for example, they can be perpendicular to each other. In the accompanying drawings of this disclosure, the row direction X can be horizontal and the column direction Y can be vertical, but it is not limited to these. If the display panel is rotated, the actual orientation of the row direction X and the column direction Y may change.

[0044] In this paper, the "overlap" of features A and B means that the orthographic projections of features A and B on the substrate at least partially coincide.

[0045] In this paper, "same layer" for features A and B means that features A and B can be formed simultaneously, and they are discontinuous or continuous different regions in the same film layer, and they are not separated by other film layers in the direction perpendicular to the substrate. "Different layers" means that features A and B are distributed at intervals along the direction perpendicular to the substrate, and they are separated by other film layers.

[0046] This disclosure provides a display panel, such as... Figure 1 and Figure 2 As shown, the display panel may have a display area AA and an outer peripheral area WA located outside the display area AA. The outer peripheral area WA may be a continuous or discontinuous annular area surrounding the display area AA, that is, the outer peripheral area WA is set around the display area AA at least in part. The shape of the outer peripheral area WA is not specifically limited here.

[0047] The peripheral area WA may include a fan-out area FA extending in a direction away from the display area AA. The display area AA and the fan-out area FA may be distributed along the column direction Y. The fan-out area FA has a bonding portion PA, which may have multiple pads. Each pad can be bonded to a flexible circuit board, thereby controlling the illumination of the display area AA of the display panel to display an image via a control circuit board bonded to the flexible circuit board.

[0048] The display area AA may include a main display area MA and a secondary display area SA. The main display area MA is located outside the secondary display area SA. In the row direction X, the main display area MA may be located on at least one side of the secondary display area SA. For example, the main display area MA may surround the secondary display area SA, or the boundary of the main display area MA may partially coincide with the boundary of the secondary display area SA.

[0049] The sub-display area SA may include a light-transmitting area SA1 and a circuit area SA2 outside the light-transmitting area SA1. In the row direction X, the circuit area SA2 is located on at least one side of the light-transmitting area SA1. Both the light-transmitting area SA1 and the circuit area SA2 can emit light, but the light transmittance of the light-transmitting area SA1 is greater than that of the circuit area SA2, so as to realize under-display imaging. The shape of the light-transmitting area SA1 can be circular, elliptical, rectangular or other polygonal shapes, or other regular or irregular shapes, without special limitation. At least a portion of the circuit area SA2 and the light-transmitting area SA1 can be distributed along the row direction X. For example, a sub-display area SA may have one light-transmitting area SA1 and two circuit areas SA2, and the two circuit areas SA2 are located on both sides of the light-transmitting area SA1 along the row direction X, and can be symmetrically arranged about a straight line passing through the center of the light-transmitting area SA1 along the column direction Y.

[0050] like Figure 2 and Figure 4 As shown, the display panel may include a driving backplate BP and a plurality of light-emitting devices (LDs) disposed on one side of the driving backplate BP. The driving backplate BP has a driving circuit for driving the light-emitting devices LDs to emit light. The driving circuit may include pixel circuits PC located in the display area AA and peripheral circuits located in the peripheral area WA, wherein: There are multiple pixel circuits (PCs), and they are arranged in multiple rows and columns along the X and Y directions. One pixel circuit PC can connect to one light-emitting device (LD). Of course, it is also possible for one pixel circuit PC to connect to multiple light-emitting devices (LDs). This article only uses the one-to-one correspondence between pixel circuit PCs and light-emitting devices (LDs) as an example. The pixel circuit PCs can be distributed in the circuit area SA2 of the main display area and the sub-display area SA, while the light-transmitting area SA1 does not have pixel circuit PCs to improve the light transmittance of the light-transmitting area SA1. Specifically, each pixel circuit PC can be divided into a first pixel circuit PC1 and a second pixel circuit PC2. The first pixel circuit PC1 is distributed in the main display area MA and the circuit area SA2, while the second pixel circuit PC2 is located in the circuit area SA2. That is to say, the circuit area SA2 contains both the first pixel circuit PC1 and the second pixel circuit PC2, while the main display area MA only contains the first pixel circuit PC1.

[0051] A pixel circuit PC may include multiple transistors and capacitors, and it may be a pixel circuit such as 3T1C, 7T1C, 8T1C, etc. nTmC indicates that a pixel circuit PC includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0052] The peripheral circuit can be connected to the pixel circuit PC and the light-emitting device LD, and the current through the light-emitting device LD can be controlled by the pixel circuit PC, thereby controlling the brightness of the light-emitting device LD. The peripheral circuit may include gate driving circuit and light-emitting control circuit, and of course, it may also include other circuits. The specific structure of the peripheral circuit is not specifically limited here.

[0053] Each light-emitting device (LD) can be located on one side of the driving backplate BP and within the display area AA. The main display area MA and the light-transmitting area SA1 and circuit area SA2 of the sub-display area SA are each equipped with a light-emitting device LD, allowing the entire display area AA to emit light. Simultaneously, the light-emitting device LD may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked along a direction away from the driving backplate BP. The light-emitting device LD can be an OLED (Organic Light-Emitting Diode), or of course, a Micro LED (Micron Light-Emitting Diode), a Mini LED (Sub-Millimeter Light-Emitting Diode), or a QLED (Quantum Dot Diode), etc.

[0054] like Figure 4As shown, the first electrode ANO can be disposed on one side of the driving backplane BP and arranged in an array. The light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked along a direction away from the driving backplane BP. Each light-emitting device LD can share a second electrode CAT, that is, the second electrode CAT can be a continuous solid layer structure, and the second electrode CAT can extend to the peripheral area and receive the second power signal VSS. The first electrodes ANO are arranged in an array and connected to the pixel circuit PC to ensure that each light-emitting device LD can emit light independently. In addition, in order to limit the light emission range of the light-emitting device LD and prevent crosstalk, a pixel definition layer PDL can be disposed on the surface where the first electrode ANO is disposed. It may have openings that expose each first electrode ANO, and the light-emitting layer EL is stacked with the first electrode ANO in the openings.

[0055] Each light-emitting device (LD) can share at least one light-emitting material layer, ensuring that all LDs emit the same color. To achieve color display, a color filter layer can be placed on the side of the LD furthest from the driving backplane (BP). Color display is achieved through the filter elements in the color filter layer corresponding to each LD. Alternatively, each LD can have an independent light-emitting material layer, allowing it to emit monochromatic light directly, and different LDs can emit different colors, thus achieving color display.

[0056] like Figure 2 As shown, based on the division of the pixel circuit PC above, the light-emitting devices can be correspondingly divided into a first light-emitting device LD1 and a second light-emitting device LD2. The first light-emitting device LD1 is distributed in the main display area MA and the circuit area SA2, while the second light-emitting device LD2 is distributed in the light-transmitting area SA1. Simultaneously, to drive each light-emitting device LD, in the main display area MA and the circuit area SA2, the first light-emitting device LD1 can be connected to the first pixel circuit PC1, thereby emitting light under the drive of the first pixel circuit PC1. The second light-emitting device LD2 can be connected to the second pixel circuit PC2 through an adapter cable CL, which extends from the light-transmitting area SA1 to the circuit area SA2. For example: like Figure 2 and Figure 4As shown, in some embodiments of this disclosure, the display panel may include an adapter layer BL, which may be disposed between the driving backplane BP and the light-emitting device LD, and includes a plurality of adapter lines CL extending from the circuit area SA2 to the light-transmitting area SA1. At least one second light-emitting device LD2 is connected to at least one second pixel circuit PC2 through at least one adapter line CL. For example, a second light-emitting device LD2 is connected to a second pixel circuit PC2 through an adapter line CL, such that one second pixel circuit PC2 drives only one second light-emitting device LD2; or, a second light-emitting device LD2 is connected to a plurality of second pixel circuit PC2s through a plurality of adapter lines CL, such that a plurality of second pixel circuit PC2s can drive the same second light-emitting device LD2; or, a plurality of second light-emitting devices LD2 are connected to the same second pixel circuit PC2 through a plurality of adapter lines CL, such that one second pixel circuit PC2 can drive a plurality of second light-emitting devices LD2.

[0057] The adapter cable CL can be made of a transparent conductive material, such as indium tin oxide (ITO), to reduce the impact on the light transmittance of the light-transmitting area SA1. Furthermore, the adapter cables CL connected to each of the second light-emitting devices LD2 can be located on the same layer or distributed across multiple layers. For example, the adapter layer BL can include multiple routing layers and planarization layers alternately distributed along a direction away from the driving backplane BP. The specific number is not specifically limited here, ensuring that each routing layer is covered by a planarization layer. Each routing layer can have some adapter cables CL installed to increase wiring space.

[0058] In addition, the display panel may also include an encapsulation layer covering each light-emitting device (LD), which may be encapsulated in a thin-film manner. For example, the encapsulation layer includes a first inorganic layer, an organic layer, and a second inorganic layer, wherein: the first inorganic layer can cover each light-emitting device, that is, the first inorganic layer can cover the surface of the second electrode CAT away from the driving backplane BP. The material of the first inorganic layer may include inorganic insulating materials such as silicon nitride and silicon oxide. The organic layer may be disposed on the surface of the first inorganic layer away from the driving backplane BP, and the boundary of the organic layer may be defined inside the boundary of the first inorganic layer by a barrier dam located in the peripheral area WA. The material of the organic layer may be an organic material such as resin.

[0059] The second inorganic layer can cover both the organic layer and the first inorganic layer that is not covered by the organic layer. The second inorganic layer can block the intrusion of water and oxygen, while the organic layer, which has fluidity (during the manufacturing process), can achieve planarization. The material of the second inorganic layer can include inorganic insulating materials such as silicon nitride and silicon oxide.

[0060] In addition, the display panel may also include other film layers such as a touch layer and a transparent cover plate disposed on the side of the encapsulation layer away from the driving backplane BP. The transparent cover plate may be located on the side of the touch layer away from the driving backplane BP.

[0061] Taking a mutual capacitance touch structure as an example, the touch layer may include multiple first touch electrodes and multiple second touch electrodes. Each first touch electrode may be spaced apart along the row direction X. A first touch electrode may include multiple first electrode blocks spaced apart along the column direction Y and a bridge connecting adjacent first electrode blocks. Each second touch electrode may be spaced apart along the column direction Y. A second touch electrode includes multiple second electrode blocks connected in series along the row direction X. A bridge intersects with and is insulated from a second touch electrode. One of the first and second touch electrodes may serve as a transmitting electrode, and the other as a receiving electrode, both connected to a peripheral touch driving circuit.

[0062] The following explanation uses a pixel circuit PC with a 7T1C structure as an example: like Figures 3-9 As shown, the transistors in the pixel circuit PC may include a first reset transistor T1, a compensation transistor T2, a drive transistor T3, a write transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a storage capacitor Cst. Each transistor includes a gate, a first electrode, and a second electrode. By applying a control signal to the gate, the first electrode and the second electrode can be turned on or off. The storage capacitor Cst may include overlapping first and second electrodes.

[0063] like Figure 3 As shown, the gate of the first light-emitting control transistor T5 is used to input the light-emitting control signal EM, its first electrode is used to input the first power supply signal VDD, and its second electrode is connected to the first electrode of the driving transistor T3. The gate of the driving transistor T3 is connected to the first node N1, and its second electrode is connected to the first electrode of the second light-emitting control transistor T6 at the second node N2. The second electrode of the second light-emitting control transistor T6 is connected to the first electrode ANO of a light-emitting device LD, and its gate is used to input the light-emitting control signal EM.

[0064] The gate of the first reset transistor T1 is used to input the first reset control signal RE1, and the first electrode is used to input the first reset signal VI1, i.e., the first type of reset signal. The second electrode and the first electrode ANO of the second light-emitting control transistor T6 are connected to the fourth node N4.

[0065] The gate of the write transistor T4 is used to input the first scan signal Gate1, the first terminal is used to input the data signal DA, and the second terminal is connected to the third node N3 along with the first terminal of the drive transistor T3 and the second terminal of the first light-emitting control transistor T5.

[0066] The gate of the compensation transistor T2 is used to input the second scan signal Gate2. The first terminal is connected to the second node N2 via the driving transistor T3, and the second terminal is connected to the first node N1.

[0067] The gate of the second reset transistor T7 is used to input the second reset control signal RE2, the first terminal is used to input the second reset signal VI2, and the second terminal is connected to the first node N1.

[0068] The first plate of the storage capacitor Cst is used to input the first power supply signal VDD, and the second plate is connected to the first node N1.

[0069] The working principle of the pixel circuit PC described above is explained below: During the reset phase t1: the second reset transistor T7 is turned on by the second reset control signal RE2, writing the first reset signal VI2 to the first node N1. Simultaneously, the first reset transistor T1 is turned on by the first reset control signal RE1, writing the first reset signal VI1 to the fourth node N4. This resets the gate of the driving transistor T3 and the light-emitting device LD.

[0070] During the write phase t2: the write transistor T4 and the compensation transistor T2 are turned on by the first scan signal Gate1 and the second scan signal Gate2. Data signal DA is written to the first node N1 through the third node N3 and the second node N2 until the potential reaches Vdata + vth, where Vdata is the voltage of data signal DA and Vth is the threshold voltage of the driving transistor T3. The first scan signal Gate1 and the second scan signal Gate2 can be the same signal or two synchronized signals. Furthermore, the first scan signal Gate1 and the second scan signal Gate2 can be high-frequency signals, which helps to reduce the load on the source signal of the driving transistor T3.

[0071] During the light-emitting stage t3: the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on by the light-emitting control signal EM. Drive transistor T3 is then turned on under the influence of the voltage Vdata+Vth stored in the storage capacitor Cst and the first power supply signal VDD. Under the influence of the first power supply signal VDD and the second power supply signal VSS, the light-emitting device LD emits light. In this process, the first terminal of drive transistor T3 acts as the source, and the second terminal acts as the drain.

[0072] The output current of driving transistor T3 satisfies the following formula: I = (μWCox / 2L)(Vgs-Vth) 2 Where I is the output current of driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the channel width of driving transistor T3; L is the channel length of driving transistor T3; Vgs is the gate-source voltage difference of driving transistor T3 (the voltage difference between the gate and the source); and Vth is the threshold voltage of driving transistor T3.

[0073] Based on the formula for the output current of the driving transistor T3, substituting the gate voltage Vdata+Vth and source voltage VDD of the driving transistor T3 in the pixel circuit PC of this disclosure into the formula, we can obtain: the output current of the driving transistor T3 I=(μWCox / 2L)(Vdata+Vth-VDD-Vth) 2 It can be seen that the output current of the pixel circuit PC is independent of the threshold voltage Vth of the driving transistor T3, but only related to Vdata. This eliminates the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled solely by the voltage Vdata of the data signal DA, so as to control the brightness of the light-emitting device LD.

[0074] All transistors in the aforementioned pixel circuit PC can be polysilicon transistors, meaning the transistor channel is polysilicon, such as P-type or N-type low-temperature polysilicon transistors. Alternatively, metal-oxide transistors (MOS transistors) can be used, meaning the transistor channel is made of metal oxides such as indium gallium zinc oxide (IGNOW). Specifically, P-type MOS transistors are turned off when a high-level signal is input to their gate and turned on when a low-level signal is input; N-type MOS transistors are turned off when a low-level signal is input to their gate and turned on when a high-level signal is input. The MOS transistors can be N-type MOS transistors, which are turned on when a high-level signal is input to their gate and turned off when a low-level signal is input.

[0075] In some embodiments of this disclosure, the 7T1C pixel circuit described above can employ LTPO (LTPS+Oxide) technology. Specifically, the driving transistor T3, writing transistor T4, first reset transistor T1, first light-emitting control transistor T5, and second light-emitting control transistor T6 can be P-type low-temperature polysilicon transistors; the second reset transistor T7 and compensation transistor T2 can be N-type metal-oxide transistors. Since P-type low-temperature polysilicon transistors have higher carrier mobility, this is beneficial for achieving display panels with high resolution, high response speed, high pixel density, and high aperture ratio, thereby obtaining higher carrier mobility and improving response speed. Simultaneously, N-type metal-oxide transistors can reduce leakage current.

[0076] like Figure 6As shown, based on the pixel circuit PC using LTPO technology described above, in some embodiments of this disclosure, each pixel circuit PC can be divided into multiple array-distributed circuit groups CM. A circuit group CM may include multiple circuit units CU distributed along the row direction X, and a circuit unit CU may include two pixel circuit PCs distributed along the row direction X. Simultaneously, in the row direction X, the spacing between two adjacent circuit groups CM is greater than the spacing between two adjacent pixel circuit PCs. Two pixel circuit PCs in the same circuit unit CU can be symmetrically arranged about a straight line extending along the column direction Y. Here, symmetrical arrangement means that the two pixel circuit PCs are completely symmetrical or the transistors of the two pixel circuit PCs are symmetrical.

[0077] All the signals input to the pixel circuit PC mentioned above can be transmitted through traces. The traces for transmitting each of the above signals are described below: like Figures 5-9 As shown, the driving backplane BP may include multiple travel lines that extend at least partially along the row direction X. Any travel line may be connected to a row pixel circuit PC. These travel lines may include a first reset control line REL1, a first reset signal line VIL1, a second reset control line REL2, a second reset signal line VIL2, a first scan line GAL1, a second scan line GAL2, and a light emission control line EML, wherein: For a pixel circuit PC: The first reset control line REL1 can be connected to the gate of the first reset transistor T1 and is used to transmit the first reset control signal RE1. The first reset signal line VIL1 can be connected to the first electrode of the first reset transistor T1 and is used to transmit the first reset signal VI1 to the first electrode ANO of the light-emitting device LD.

[0078] In some embodiments of this disclosure, the first reset signal line VIL1 may include multiple routing units VB distributed along the row direction X and connection units VL connected to two adjacent routing units VB. The connection units VL and the routing units VB are located on different layers, allowing other traces on the same layer as the routing units VB to pass through between two adjacent routing units VB. Furthermore, the routing units VB may be located within the aforementioned circuit group CM, while the connection units VL are located between two adjacent circuit groups CM. That is, two adjacent routing units VB cross the area between two adjacent circuit groups CM through the connection units VL.

[0079] The second reset control line REL2 can be connected to the gate of the second reset transistor T7 to transmit the second reset control signal RE2. The second reset signal line VIL2 is connected to the first terminal of the second reset transistor T7 to transmit the second reset signal VI2.

[0080] The first scan line GAL1 can be connected to the gate of the write transistor T4 to transmit the first scan signal Gate1. The second scan line GAL2 can be connected to the gate of the compensation transistor T2 to transmit the second scan signal Gate2.

[0081] The light-emitting control line EML can be connected to the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 to transmit light-emitting control signals.

[0082] In addition to the aforementioned routing lines, the drive backplane BP also includes column routing lines extending along the column direction Y, including a data line DAL and a power line VDL. The data line DAL is connected to the first terminal of the write transistor T4 of each pixel circuit PC in a column of pixel circuits (PCs) to transmit the data signal DA. The power line VDL can be connected to the second electrode plate Cst2 of each pixel circuit PC in a column of pixel circuits (PCs) and the first terminal of the first light-emitting control transistor T5 to transmit the first power signal VDD.

[0083] Based on the 7T1C pixel circuit described above, the following is a detailed explanation of each film layer driving the backplane BP: like Figure 4 As shown, in some embodiments of this disclosure, the driving backplane BP may include a substrate SU, a first semiconductor layer POL, a first gate insulating layer GI1, a first gate layer GA1, a first insulating layer ILD0, a second gate layer GA2, a second insulating layer ILD1, a second semiconductor layer IGL, a second gate insulating layer GI2, a third gate layer GA3, a third insulating layer ILD2, a first source / drain layer SD1, a first planarization layer PLN1, a second source / drain layer SD2, and a second planarization layer PLN2, wherein: The substrate SU can be a flexible transparent material such as polyimide (PI) or a rigid transparent material such as glass, and the substrate SU can be a multilayer or single-layer structure.

[0084] like Figure 10 As shown, the first semiconductor layer POL can be disposed on one side of the substrate SU, and includes the channel of the driving transistor T3, the writing transistor T4, the first reset transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 in the pixel circuit PC. The material of the first semiconductor layer POL can be polycrystalline silicon.

[0085] The first gate insulating layer GI1 can cover the first semiconductor layer POL, and the material of the first gate insulating layer GI1 can be insulating materials such as silicon nitride and silicon oxide.

[0086] like Figure 11As shown, the first gate layer GA1 can be disposed on the surface of the first gate insulating layer GI1 away from the substrate SU, and includes a first reset control line REL1, a light emission control line EML, a first scan line GAL1, and a first electrode Cst1 of the storage capacitor Cst, wherein: The first electrode plate Cst1 overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel of the driving transistor T3, and the first electrode plate Cst1 is reused as the gate of the driving transistor T3. The first reset control line REL1 overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel of the first reset transistor T1, and the overlapping portion of the first reset control line REL1 forms the gate of the first reset transistor T1. The first scan line GAL1 overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel of the writing transistor T4, and the overlapping portion of the first scan line GAL1 forms the gate of the writing transistor T4. The light emission control line EML overlaps with a portion of the first semiconductor layer POL. The overlapping portion of the first semiconductor layer POL forms the channel of the first light emission control transistor T5 and the second light emission control transistor T6, and the overlapping portion of the light emission control line EML forms the gate of the first light emission control transistor T5 and the second light emission control transistor T6.

[0087] In addition, the connection unit VL of the first reset signal line VIL1 mentioned above can also be located in the first gate layer GA1.

[0088] The first insulating layer ILD0 can cover the first gate layer GA1, and its material can be insulating materials such as silicon nitride and silicon oxide.

[0089] like Figure 12 As shown, the second gate layer GA2 can be disposed on the surface of the first insulating layer ILD0 away from the substrate SU, and includes a second reset signal line VIL2 and a second electrode Cst2. The second electrode Cst2 overlaps with the first electrode Cst1 to form a storage capacitor Cst.

[0090] The second insulating layer ILD1 may cover the second gate layer GA2, and it may be a single-layer or multi-layer structure, and the material may include insulating materials such as silicon nitride and silicon oxide. For example, the second insulating layer ILD1 may include a dielectric layer and a buffer layer stacked sequentially in a direction away from the substrate SU.

[0091] like Figure 13 As shown, the second semiconductor layer IGL may be disposed on the surface of the second insulating layer ILD1 away from the substrate SU, and includes the channel of the second reset transistor T7 and the compensation transistor T2.

[0092] The second gate insulating layer GI2 can cover the second semiconductor layer IGL, and its material can be insulating materials such as silicon nitride and silicon oxide.

[0093] like Figure 14 As shown, the third gate layer GA3 may be disposed on the surface of the second gate insulating layer GI2 away from the substrate SU, and includes the second reset control line REL2 and the second scan line GAL2, and overlaps with at least a portion of the second semiconductor layer IGL.

[0094] The third insulating layer ILD2 can cover the third gate layer GA3. It can be a single layer or a multi-layer structure, and the material can include inorganic insulating materials such as silicon nitride and silicon oxide, or organic insulating materials such as insulating resin.

[0095] like Figure 15 As shown, the first source / drain layer SD1 may be disposed on the surface of the third insulating layer ILD2 away from the substrate SU, and includes a wiring unit VB.

[0096] The first planarization layer PLN1 may cover the first source / drain layer SD1, and its material may be an insulating material such as resin. In addition, it may also include a passivation layer that covers the first source / drain layer SD1, and the first planarization layer PLN1 covers the first source / drain layer SD1.

[0097] like Figure 16 As shown, the second source / drain layer SD2 can be disposed on the surface of the first planarization layer PLN1 away from the substrate SU, and includes the data line DAL and the power line VDL.

[0098] The second planarization layer PLN2 may cover the second source / drain layer SD2, and its material may be an insulating material such as resin. The transition layer BL may be disposed on the surface of the second planarization layer PLN2 away from the substrate SU.

[0099] Furthermore, such as Figure 5 and Figure 12 As shown, the second gate layer GA2 may further include an auxiliary reset line REL2s and an auxiliary scan line GAL2s extending along the row direction X. The auxiliary reset line REL2s may overlap with the second reset control line REL2, and the auxiliary reset line REL2s may also overlap with the second semiconductor layer IGL. The second semiconductor layer IGL corresponding to the overlap is still the channel of the second reset transistor T7, and the auxiliary reset line REL2s at the overlap is also the gate of the second reset transistor T7. At the same time, the auxiliary reset line REL2s may be connected to the second reset control line REL2 through a contact hole in the display area AA, or they may be connected after extending them to the peripheral area WA, thereby increasing the gate area of ​​the second reset transistor T7.

[0100] The auxiliary scan line GAL2s can overlap with the second scan line GAL2, and it also overlaps with the second semiconductor layer IGL. The second semiconductor layer IGL at the overlap point still serves as the channel of the compensation transistor T2, and the auxiliary scan line GAL2s at the overlap point also serves as the gate of the compensation transistor T2. Simultaneously, the auxiliary scan line GAL2s can be connected to the second scan line GAL2 within the display area AA via a contact hole, or they can be extended to the peripheral area WA before being connected, thereby increasing the gate area of ​​the compensation transistor T2.

[0101] In addition, such as Figure 4 As shown, a light-shielding layer BSM can be disposed between the substrate SU and the first semiconductor layer POL. This layer can be made of a light-shielding metal or other materials and can be a single-layer or multi-layer structure. At least a portion of the light-shielding layer BSM can overlap with at least a portion of the channel region of the transistor to block light illuminating the transistor, thereby stabilizing the electrical characteristics of the transistor. For example, the light-shielding layer BSM can include multiple arrayed light-shielding units, one of which can block the channel of a driving transistor T3. Simultaneously, the light-shielding units can be connected by light-shielding lines to form a single structure, and a second power signal VSS or a second power signal VDD can be input to the light-shielding layer BSM to achieve electrostatic shielding.

[0102] Furthermore, such as Figure 4 As shown, the light-shielding layer BSM can be covered by an insulating buffer layer, and the first semiconductor layer can be disposed on the surface of the buffer layer facing away from the substrate SU. The buffer layer can be a single-layer or multi-layer structure, and its material can include insulating materials such as silicon nitride and silicon oxide.

[0103] To save space, such as Figure 5 and Figure 8 As shown, some traces of adjacent rows of pixel circuits PC can be reused. For example, the first reset control line REL1 connected to the nth row of pixel circuit PC can be reused as the first scan line GAL1 connected to the (n+1)th row of pixel circuit PC, where n is a positive integer. That is, the first reset control line REL1 connected to the nth row of pixel circuit PC is also the first scan line GAL1 connected to the (n+1)th row of pixel circuit PC.

[0104] The inventor discovered that, such as Figure 2As shown, since the second pixel circuit PC2 is connected to the second light-emitting device LD2 through the adapter cable CL, compared with the first pixel circuit PC1 which is directly connected to the first light-emitting device LD1, the presence of the adapter cable CL will increase the load between the second pixel circuit PC2 and the connected second light-emitting device LD2. If the same reset signal is used to reset the first light-emitting device LD1 and the second light-emitting device LD2, the reset of the second light-emitting device LD2 will lag behind the reset of the first light-emitting device, causing the light-transmitting area SA1 to be asynchronous with the main display area MA and the circuit area SA2. Especially at low gray levels, there is an abnormality in the lighting.

[0105] To resolve the aforementioned startup anomaly, such as... Figure 3 As shown, the inventors provide a new solution. By designing the first reset signal line, the first light-emitting device LD1 and the second light-emitting device LD2 are reset separately. Specifically, the first reset signal VI1 is used to reset the first light-emitting device LD1, and the third reset signal VI3 is used to reset the second light-emitting device LD2. By controlling the timing of the third reset signal VI3 and the first reset signal VI1, abnormal start-up can be compensated for, and the difference between the start-up time of the light-transmitting area SA1 and the start-up time of the main display area MA and the circuit area SA2 can be reduced or eliminated. The third reset signal VI3 is the second type of reset signal. The solution is described in detail below: like Figure 1 and Figure 2 As shown, for all pixel circuits PC in the display area AA, each row of pixel circuits PC can be connected to a reset signal line VIL1, which can be divided into two types. The first type of first reset signal line VIL1 is located outside the sub-display area SA in the column direction Y, that is, the first type of first reset signal line VIL11 and the sub-display area SA are distributed along the column direction Y. The second type of first reset signal line VIL12 extends in a direction that intersects with the sub-display area SA, and a part of the second type of first reset signal line VIL12 is located in the circuit area SA2 within the sub-display area SA.

[0106] The second type of first reset signal line VIL12 can be divided along the horizontal direction X into a discontinuous first reset segment LV1 and a second reset segment LV2. The first reset segment LV1 is located in the main display area MA, and the second reset segment LV2 is located in the circuit area SA2, as shown below. Figure 5 , Figure 6 Figure 11 Figure 15 As shown, both the first reset segment LV1 and the second reset segment LV2 include multiple routing units VB and connection units VL; wherein: For the first light-emitting device LD1 in the main display area MA, its connected first pixel circuit PC1 can be connected to the first reset segment LV1 of the first type of first reset signal line VIL11 and the second type of first reset signal line VIL12. That is, in the main display area MA, the first pixel circuit PC1 distributed along the row direction X with the pixel circuit PC in the sub-display area SA can be connected to the first reset segment LV1 of the second type of first reset signal line VIL12, while other first pixel circuits PC1 are connected to the first type of first reset signal line VIL11. Thus, the first reset signal VI1 can be transmitted through the first type of first reset signal line VIL11 and the first reset segment LV1 to reset the first light-emitting device LD1 in the main display area AA.

[0107] For the light-emitting devices LD (second light-emitting device LD2 and part of the first light-emitting device LD1) in the sub-display area SA, the connected pixel circuit PC (second pixel circuit PC2 and part of the first pixel circuit PC1) can be connected to the second reset segment LV2 of the second type of first reset signal line VIL12, so that the third reset signal VI3 can be transmitted through the second reset segment LV2, thereby resetting the first electrode ANO of the light-emitting device LD in the sub-display area SA through the third reset signal VI3.

[0108] like Figure 1 As shown, in some embodiments of this disclosure, the driver backplane may further include a first reset bus BV1, a second reset bus BV2, and a first reset connection line LV3, wherein: The first reset bus BV1 can be located in the peripheral area WA. The first reset bus BV1 extends to the fan-out area FA and is connected to the bonding part PA so as to transmit the third reset signal VI3.

[0109] The second reset bus BV2 can be located in the peripheral area and can be arranged on the same layer as the first reset bus BV1, with intervals between them. The second reset bus BV2 is connected to a portion of the first reset segment LV1 of the first type first reset signal line VIL11 and the second type first reset signal line VIL12, that is, connected to the portion of each first reset signal line VIL1 located within the main display area MA. The second reset bus BV2 extends to the fan-out area FA and is connected to the bonding part PA to transmit the first reset signal VI1.

[0110] The first reset connection line LV3 can extend from the peripheral area WA to the display area AA along the column direction Y, and connect the first reset bus BV1 and the second reset segment LV2, so that the third reset signal VI3 can be transmitted to the second reset segment LV2, and avoids short circuit with the first reset segment LV1.

[0111] like Figure 1As shown, in some embodiments of this disclosure, the first reset bus BV1 may include a first bus segment BV11, a second bus segment BV12, and a third bus segment BV13. The first bus segment BV11 and the second bus segment BV12 are located on both sides of the display area AA and extend to the fan-out area FA, and are connected to the bonding part PA. The third bus segment BV13 is located on the side of the display area AA away from the fan-out area FA, and connects to the first bus segment BV11 and the second bus segment BV12, thereby forming a "U"-shaped structure around the display area AA. The first reset connection line LV3 may extend along the column direction Y to the peripheral area WA and connect to the third bus segment BV13.

[0112] The second reset bus BV2 is located on both sides of the display area AA, and is disconnected on the side of the display area AA away from the fan-out area FA. The first reset connection line LV3 can pass through the disconnection point of the second reset bus BV2, thus avoiding overlap with the second reset bus BV2. If the first reset bus BV1 and the first reset connection line LV3 are set on the same layer and adopt an integrated structure, a short circuit can be avoided at the disconnection point of the second reset bus BV2. Of course, if the second reset bus BV2 and the first reset connection line LV3 are located on different layers, the first reset connection line LV3 can cross the second reset bus BV2.

[0113] Furthermore, such as Figure 5 and Figure 9 As shown, in some embodiments of this disclosure, in the row direction X, the main display area MA and the circuit area SA2 may have a gap extending in the column direction Y. The gap may be one of the regions between two adjacent circuit groups CM, specifically the region between the circuit group CM closest to the main display area MA in the circuit area SA2 and the circuit group CM closest to the circuit area SA2 in the main display area MA. The first reset connection line LV3 may be located within the gap, thereby connecting the end of the second reset segment LV2 to the first reset connection line LV3. The first reset connection line LV3 may be disposed on the same layer as each routing unit VB. For example, the first reset connection line LV3 and the routing unit VB are both located on the first source / drain layer SD1 and are connected to the second reset segment LV2 by integral molding.

[0114] At the same time, such as Figure 5 and Figure 9As shown, the first reset connection line LV3 can be intersected with the connection unit VL within the gap area Gap, and this connection unit VL is intermittently arranged, that is, divided into at least two disconnected parts in the horizontal direction X, thereby realizing the disconnection of the first reset segment LV1 and the second reset segment LV2, and preventing the first reset connection line LV3 from connecting with the first reset segment LV1. Specifically, in a first reset signal line VIL1 having a first reset segment LV1 and a second reset segment LV2, a connection unit VL is intermittently arranged in the gap area, and one end is connected to a routing unit VB of the first reset segment LV1 through a contact hole, and the other end is connected to a routing unit VB of the second reset segment LV2 through a contact hole. The intermittent connection unit VL here can also be completely omitted, as long as it can prevent the first reset connection line LV3 from connecting with the first reset segment LV1. The reason for setting the intermittent connection unit VL and connecting it to the first reset segment LV1 and the second reset segment LV2 through contact holes is to make the contact holes in the display area AA evenly distributed, ensuring the uniformity of the shape.

[0115] Of course, the first reset connection line LV3 can also be located between two adjacent circuit groups CM in the circuit area SA2, or between two adjacent circuit units CU, and can be connected to the routing units VB of the second reset section LV2 on both sides by means of integral molding, etc., but the connection unit VL connected to the two routing units VB connected by the first reset connection line LV3 does not need to be disconnected.

[0116] In some embodiments of this disclosure, as described above, the number of circuit areas SA2 in the sub-display area SA is two, and they are separated on both sides of the light-transmitting area SA1 along the row direction X; each of the two circuit areas SA2 has a gap between it and the main display area MA. Correspondingly, the number of first reset connection lines LV3 can also be two, and each of the two gaps can be provided with a first reset connection line LV3, and both first reset connection lines LV3 are connected to the first reset bus BV1.

[0117] In some embodiments of this disclosure, such as Figure 1 As shown, there are two sub-display areas SA, and two circuit areas SA2 within each sub-display area SA. Each circuit area SA2 is separated from the main display area MA by a gap, resulting in four circuit areas SA2 and four gap areas. Correspondingly, there are four first reset connection lines LV3. Each gap area contains a first reset connection line LV3, and all four first reset connection lines LV3 are electrically connected to the first reset bus BV1.

[0118] like Figure 23As shown, the first reset connection line LV3 has a first end and a second end distributed along the column direction Y. Among the two first reset connection lines LV3 located on both sides of a display area SA, the first ends of the two first reset connection lines LV3 are connected to the first reset bus BV1, and the second ends of the two first reset connection lines LV3 are connected through a connection trace LV6 extending along the row direction X.

[0119] like Figure 21 As shown, for a display panel with only one sub-display area SA, the first reset segment LV1 on both sides of the sub-display area SA is disconnected at the sub-display area SA, but can extend in the opposite direction to the peripheral area WA and connect with the second reset bus BV2 to receive the first reset signal VI1. However, if there are multiple sub-display areas SA distributed linearly along the row direction X, the first reset segment LV1 between two adjacent sub-display areas SA can receive the first reset signal VI1 in the following manner: like Figure 1 , Figures 17-20 as well as Figure 22 As shown, in some embodiments of this disclosure, a second reset connection line LV4 extending along the column direction Y can be provided in the main display area MA between two adjacent sub-display areas SA, and the second reset connection line LV4 is connected to at least one first reset signal line VIL1 (first type of first reset signal line VIL11) located outside the sub-display area SA in the column direction Y. At the same time, the second reset connection line LV4 is connected to a first reset segment LV1 between two adjacent sub-display areas SA, so that the second reset connection line LV4 can bypass the sub-display area SA and transmit the first reset signal VI1 to a reset segment LV1 between two adjacent sub-display areas SA.

[0120] like Figures 17-20 As shown, the second reset connection line LV4 can be located in the same gap area Gap as the first reset connection line LV3, but the gap is set on the side of the first reset connection line LV3 away from the light-transmitting area SA1. At this time, the first reset segment LV1 between two adjacent sub-display areas SA is located on the same side of the second reset connection line LV4. Of course, at least one circuit group CM can be separated between the second reset connection line LV4 and the first reset connection line LV3. The second reset connection line LV4 has a first reset segment LV1 on both sides. At this time, the connection unit VL of the second reset connection line LV4 and the first reset segment LV1 crosses, and the cross connection unit VL of the second reset connection line LV4 is continuous in the horizontal direction X without being broken, so as to ensure that the second reset connection line LV4 can transmit the first reset signal VI1 to both sides.

[0121] Furthermore, the second reset connection line LV4 can be disposed on the same layer as the first reset connection line LV3. For example, both can be disposed on the first source / drain layer SD1, and can be disposed on the same layer as the routing unit VB. The second reset connection line LV4 can be located between two adjacent circuit groups CM in the main display area MA, or between two adjacent circuit units CU.

[0122] like Figure 1 As shown, there can be multiple second reset connection lines LV4, distributed along the row direction X. For example, there can be two second reset connection lines LV4, both connected to the first reset segment LV1 between two adjacent sub-display areas SA. Furthermore, the two second reset connection lines LV4 can be symmetrically arranged about the central axis along the column direction Y of the area between two adjacent sub-display areas SA.

[0123] In some other embodiments of this disclosure, the second reset connection line LV4 may also be located on the side of the routing unit VB away from the connection unit VL. In this case, the second reset connection line LV4 may overlap with the pixel circuit PC, as long as the first reset signal VI1 can be transmitted to the first reset segment LV1 in the main display area MA between the two adjacent sub-display areas SA.

[0124] like Figure 22 As shown, in other embodiments of this disclosure, for the first reset segment LV1 separated by the sub-display area SA and located on the same first reset signal line VIL1, the first reset segments LV1 on both sides of the sub-display area SA can be connected by a lead LV5 that bypasses the sub-display area SA. This lead LV5 can be located in any film layer of the driving backplane BP, or in any film layer between the driving backplane BP and the light-emitting device LD. Furthermore, the lead LV5 can be located in the same film layer, or it can include different segments located in multiple film layers, as long as it can achieve the aforementioned connection function.

[0125] Furthermore, such as Figure 22 As shown, two first reset segments LV1 of the same first reset signal line VIL1, separated by a display area SA in the horizontal direction X, are connected by a lead LV5; at least a portion of the lead LV5 is located on the side of the first reset segment LV1 to which it is connected, closer to the fan-out area FA, or at least a portion of the lead LV5 is located on the side of the first reset segment LV1 to which it is connected, further away from the fan-out area FA. For example: In some embodiments of this disclosure, each lead LV5 can be divided into two parts, and the number of lead LV5 in the two parts can be the same or different; wherein, one part of the lead LV5 is located on the side of the first reset segment LV1 to which it is connected that is close to the fan-out area FA, and the other part of the lead LV5 is located on the side of the first reset segment LV1 to which it is connected that is far away from the fan-out area FA, which can avoid the lead LV5 being too concentrated and make full use of the space for routing.

[0126] In some embodiments of this disclosure, each lead LV5 is located on the side of the first reset segment LV1 to which it is connected, near the fan-out region FA.

[0127] In some embodiments of this disclosure, each lead LV5 is located on the side of the first reset segment LV1 to which it is connected, away from the fan-out region FA.

[0128] This disclosure also provides a display device, which may be a mobile phone, tablet computer, television, or other electronic device with under-display camera functionality, and will not be listed here. Figure 23 As shown, the display device disclosed herein may include a display panel PNL and a photosensitive element CAU, wherein: The display panel PNL can be any of the above-described embodiments of the display panel PNL, and its structure can be referred to the above-described embodiments of the display panel PNL, which will not be described in detail here.

[0129] The photosensitive element CAU can be located on the side of the driving backplate BP away from the light-emitting device LD, and the orthographic projection of the photosensitive element CAU on the driving backplate BP and the orthographic projection of the light-transmitting area SA1 on the driving backplate BP at least partially overlap.

[0130] In some embodiments of this disclosure, there are multiple sub-display areas SA, the number of photosensitive elements CAU is the same as the number of sub-display areas SA, and each photosensitive element CAU is overlapped with the light-transmitting area SA1 of each sub-display area SA in a one-to-one correspondence.

[0131] External light can pass through the light-transmitting area SA1 and illuminate the corresponding photosensitive element CAU. The photosensitive element CAU can generate an electrical signal based on the light transmitted through the corresponding light-transmitting area SA1, thereby generating an image. The photosensitive element CAU may include an image sensor, such as a CCD image sensor or a CMOS image sensor.

[0132] A photosensitive element (CAU) can generate images based on visible light, or on infrared or other light sources. For example, a photosensitive element (CAU) may include an infrared sensor that receives ambient infrared light to form an infrared image, facilitating the recognition of fingerprint patterns, iris patterns, facial patterns, etc., based on the infrared image. Alternatively, a photosensitive element (CAU) may include an illuminance sensor that measures the illuminance around the display device, and the display panel (PNL) can adjust its brightness based on the measured illuminance. Furthermore, a photosensitive element (CAU) may also employ a LiDAR (Light Detection and Ranging) sensor.

[0133] The photosensitive element CAU can be used not only in cameras that capture images, but also in small lamps that measure distance by outputting and detecting light.

[0134] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel having a display area and a peripheral area at least partially surrounding the display area; the display area includes a sub-display area and a main display area located on at least one side of the sub-display area, the sub-display area including a light-transmitting area and a circuit area located on at least one side of the light-transmitting area; The driving backplane includes multiple arrayed pixel circuits and multiple first reset signal lines. Each pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuits are located in the main display area and the circuit area, and the second pixel circuits are located in the circuit area. The multiple first reset signal lines extend along a first direction, and some of these first reset signal lines are first-type first reset signal lines, while others are second-type first reset signal lines. The second-type first reset signal lines include first reset segments and second reset segments intermittently arranged along the first direction. The first reset segments are located in the main display area, and the second reset segments are located in the circuit area. Multiple light-emitting devices are located on one side of the driving backplate, including a first light-emitting device located in the main display area and the circuit area, and a second light-emitting device located in the light-transmitting area; The first light-emitting device is connected to the first pixel circuit, and the second light-emitting device is connected to the second pixel circuit via an adapter cable; The first reset segment is connected to a portion of the first pixel circuit within the main display area, and the first reset segment is configured to provide a first type of reset signal to the first pixel circuit within the main display area; the second reset segment is connected to the first pixel circuit and the second pixel circuit of the circuit area, and the second reset segment is configured to provide a second type of reset signal to the first pixel circuit and the second pixel circuit of the circuit area. The drive backplate also includes: A first reset bus is located in the peripheral area; the first reset bus is used to transmit a third reset signal, the third reset signal being the second type of reset signal. A second reset bus is located in the peripheral area and is spaced apart from the first reset bus. The second reset bus is connected to the first type of first reset signal line and the first reset segment of the main display area. The second reset bus is used to transmit a first reset signal. The first reset signal is the first type of reset signal. A first reset connection line extends from the peripheral area into the display area along a second direction, and the first reset connection line connects the first reset bus and the second reset segment; The first direction and the second direction intersect.

2. The display panel according to claim 1, wherein, In the first direction, there is a gap between the main display area and the circuit area extending in the second direction, and the first reset connection line is located within the gap.

3. The display panel according to claim 2, wherein, The secondary display area has two circuit areas, which are located on both sides of the light-transmitting area along the first direction; each of the two circuit areas has a spacing area between it and the main display area; The number of the first reset connection lines is two, and the first reset connection lines are provided in both of the two interval areas. Both of the first reset connection lines are connected to the first reset bus.

4. The display panel according to claim 3, wherein, There are two sub-display areas and four first reset connection lines; each of the interval areas is provided with a first reset connection line, and all four first reset connection lines are connected to the first reset bus.

5. The display panel according to claim 4, wherein, In the two first reset connection lines located on both sides of the sub-display area, the first ends of the two first reset connection lines are connected to the first reset bus, and the second ends of the two first reset connection lines are connected by a connection trace extending along the first direction.

6. The display panel according to claim 3, wherein, The peripheral area includes a fan-out area extending away from the display area; The first reset bus includes a first bus segment, a second bus segment, and a third bus segment. The first bus segment and the second bus segment are located on both sides of the display area and extend to the fan-out area. The third bus segment is located on the side of the display area away from the fan-out area and connects the first bus segment and the second bus segment. The first reset connection line is connected to the third bus segment. The second reset bus is located on both sides of the display area and extends to the fan-out area. The second reset bus is disconnected on the side of the display area away from the fan-out area, and the first reset connection line passes through the location where the second reset bus is disconnected.

7. The display panel according to claim 6, wherein, The number of sub-display areas is multiple, and they are distributed at intervals along the first direction; The main display area between two adjacent sub-display areas is provided with a second reset connection line extending along the second direction; at least one first type of first reset signal line is connected to the first reset segment between two adjacent sub-display areas through the second reset connection line.

8. The display panel according to claim 7, wherein, There are two second reset connection lines between the two sub-display areas, and they are spaced apart along the first direction; the first reset segment between two adjacent sub-display areas is connected by the two second reset connection lines.

9. The display panel according to claim 6, wherein, Two first reset segments of the same first reset signal line, separated by a sub-display area in the first direction, are connected by leads; at least a portion of the leads are located on the side of the first reset segment to which they are connected that is closer to the fan-out area, or at least a portion of the leads are located on the side of the first reset segment to which they are connected that is farther away from the fan-out area.

10. The display panel according to claim 7, wherein, The first reset signal line includes a plurality of routing units distributed along the first direction and a connection unit connected to two adjacent routing units, wherein the connection unit and the routing units are located on different layers; Both the first reset segment and the second reset segment include multiple wiring units and connection units; In a first reset signal line having a first reset segment and a second reset segment, a connection unit is intermittently disposed in the interval area, with one end connected to a routing unit of the first reset segment and the other end connected to a routing unit of the second reset segment; The first reset connection line intersects with the intermittently arranged connection unit.

11. The display panel according to claim 10, wherein, The wiring unit, the first reset connection line, and the second reset connection line are arranged on the same layer and are located on the side of the connection unit closer to the light-emitting device.

12. The display panel according to claim 10, wherein, The first reset connection line and the second reset connection line are arranged on the same layer and are located on the side of the wiring unit away from the connection unit.

13. The display panel according to claim 10, wherein, The second reset connection line is intersected and connected to a portion of the connection units.

14. The display panel according to claim 2, wherein, Each pixel circuit is divided into multiple array-distributed circuit groups; one circuit group includes multiple circuit units distributed along the first direction; one circuit unit includes two pixel circuits distributed along the first direction. In the first direction, the distance between two adjacent circuit groups is greater than the distance between two adjacent pixel circuits; the two pixel circuits of the same circuit unit are symmetrically arranged about a straight line extending along the second direction; The interval region is a portion of the area between two adjacent circuit groups.

15. The display panel according to claim 11, wherein, The pixel circuit includes a first reset transistor; In the circuit area, the second reset segment is connected to the light-emitting device through the first reset transistor; In the main display area, the first reset segment is connected to the light-emitting device through the first reset transistor.

16. The display panel according to any one of claims 1-15, wherein, The display panel also includes: An adapter layer is disposed between the driving backplate and the light-emitting device, and includes the adapter wire, which extends from the circuit area to the light-transmitting area. At least one second light-emitting device is connected to at least one second pixel circuit through at least one of the adapter wires.

17. A display device, comprising: The display panel according to any one of claims 1-16; A photosensitive element is located on the side of the driving backplate away from the plurality of light-emitting devices, and the orthographic projection of the photosensitive element on the driving backplate at least partially overlaps with the orthographic projection of the light-transmitting area on the driving backplate.

Images