LCD panel

Abstract

The present application discloses an embodiment of a liquid crystal display panel. In the liquid crystal display panel of the present application, in an orthographic projection pattern of the liquid crystal display panel, a first shielding portion of a black matrix layer completely covers two adjacent scan lines, the thin-film transistors connected thereto, and a spacer. The present application arranges a spacer, two scan lines, and the thin-film transistors connected thereto in an area covered by a first shielding portion, so that the first shielding portion simultaneously covers the spacer, the two scan lines, and the thin-film transistors connected thereto. Compared to a design with a single row of scan lines, this avoids the area where the spacer is located exceeding the width of the area adjacent to the single row of scan lines, thereby avoiding additional waste of aperture ratio. This improves the aperture ratio of the liquid crystal display panel without sacrificing product performance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a liquid crystal display panel. Background Art

[0002] In related technologies, the aperture ratio of a liquid crystal display panel is usually affected by three aspects: first, the base of the black matrix layer under the pad (PS). The size of the base is limited by the mechanical testing capability of the product. In order to ensure the mechanical testing capability, the base of the black matrix layer is usually required to block the pad at a certain safety distance; second, the width of the black matrix layer in the scanning line direction, which is mainly limited by the design of the thin film transistor (TFT) and the control of the safety distance. The black matrix layer needs to block the metal traces in the scanning line direction; third, the width of the black matrix layer in the data line direction. Generally speaking, the width of the black matrix layer in the data line direction is affected by factors such as the product charging rate and touch performance.

[0003] Since the upper limit of the aperture ratio improvement is limited, a new architecture is needed to improve the aperture ratio. Summary of the Invention

[0004] The embodiments of the present application provide a liquid crystal display panel that can improve the aperture ratio of a product without sacrificing product performance.

[0005] An embodiment of the present application provides a liquid crystal display panel, comprising:

[0006] A black matrix layer, wherein the black matrix layer is provided with a plurality of pixel openings, the black matrix layer includes a plurality of first shielding portions arranged along a first direction, the first shielding portions being located between two adjacent rows of the pixel openings;

[0007] an array substrate comprising a plurality of pixel electrodes, a plurality of scan lines arranged along the first direction, and a plurality of thin film transistors; the pixel electrodes are arranged corresponding to the pixel openings, and in an orthographic projection pattern of the liquid crystal display panel, two adjacent scan lines are correspondingly arranged between two adjacent rows of pixel openings, and the first shielding portion covers the scan lines and the thin film transistors; the scan lines are connected to the gates of the thin film transistors;

[0008] A spacer is provided on the array substrate, and in the orthographic projection pattern of the liquid crystal display panel, the first shielding portion covers the spacer.

[0009] Optionally, in some embodiments of the present application, two rows of pixel openings are provided between two adjacent first blocking portions, and the array substrate further includes a common electrode line extending along the first direction, the common electrode line being provided between the two rows of pixel openings and located between the two first blocking portions;

[0010] The black matrix layer includes a third shielding portion, and the third shielding portion covers the common electrode line.

[0011] Optionally, in some embodiments of the present application, the array substrate further includes a plurality of data lines arranged along a second direction intersecting with the first direction;

[0012] In an orthographic projection pattern of the liquid crystal display panel, the data lines are respectively arranged to intersect with the scan lines and the common electrode lines, the pixel electrodes include a first pixel electrode and a second pixel electrode; the first pixel electrode corresponds to a pixel opening, the second pixel electrode corresponds to a pixel opening, the scan lines include a first scan line and a second scan line, the thin film transistors include a first thin film transistor and a second thin film transistor, the gate of the first thin film transistor is connected to the first scan line, the gate of the second thin film transistor is connected to the second scan line, the output electrode of the first thin film transistor is connected to the first pixel electrode, the output electrode of the second thin film transistor is connected to the second pixel electrode, a side of the first pixel electrode away from the first thin film transistor and a side of the second pixel electrode away from the second thin film transistor are separated by the common electrode line, and a side of the first pixel electrode close to the first thin film transistor and a side of the second pixel electrode close to the second thin film transistor are separated by the first scan line and the second scan line;

[0013] The black matrix layer includes a second shielding portion; the first shielding portion and the second shielding portion are cross-connected, and in the orthographic projection pattern of the liquid crystal display panel, in a direction perpendicular to the first direction, the first shielding portion, the pixel opening, the third shielding portion and the pixel opening are alternately arranged, and the second shielding portion covers the data line.

[0014] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the liquid crystal display panel, a plurality of the spacers are arranged in rows along the first direction, and in a direction perpendicular to the first direction, a row of the first pixel electrodes and a row of the second pixel electrodes are arranged between two adjacent rows of the spacers.

[0015] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the liquid crystal display panel, the padding is provided at the intersection of the first shielding portion and the second shielding portion;

[0016] The spacer partially overlaps the first scan line, the second scan line, and the data line simultaneously.

[0017] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the liquid crystal display panel, in a direction perpendicular to the first direction, the area where the pad is located has a first width, the area where the first scan line and the first thin film transistor connected thereto are located has a second width, the area where the second scan line and the second thin film transistor connected thereto are located has a third width, the first width is greater than the second width and the third width, and the first width is less than or equal to the sum of the second width and the third width.

[0018] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the liquid crystal display panel, the first thin film transistor is arranged on a side of the first scan line away from the second scan line, and the second thin film transistor is arranged on a side of the second scan line away from the first scan line, and is aligned with the first thin film transistor.

[0019] Optionally, in some embodiments of the present application, the first scan line includes a first main line and at least one first extension portion, the first extension portion is connected to a side of the first main line away from the second scan line, and the first extension portion is connected to the gate of the first thin film transistor;

[0020] The first thin film transistor includes a first active layer. In an orthographic projection pattern of the liquid crystal display panel, the first active layer is overlapped with a gate of the first thin film transistor.

[0021] Optionally, in some embodiments of the present application, the first active layer is extended along the extension direction of the first main line, the extension direction of the first extension portion intersects with the extension direction of the first main line, and the first active layer is overlapped with the two first extension portions.

[0022] Optionally, in some embodiments of the present application, the second scan line includes a second main line and at least one second extension portion, the second extension portion is connected to a side of the second main line away from the first scan line, and the second extension portion is multiplexed as a gate of the second thin film transistor;

[0023] The second thin film transistor includes a second active layer. In an orthographic projection pattern of the liquid crystal display panel, the second active layer is overlapped with the second extension portion.

[0024] Optionally, in some embodiments of the present application, the second active layer is extended along the extension direction of the second main line, the extension direction of the second extension portion intersects with the extension direction of the second main line, and the second active layer is overlapped with the two second extension portions.

[0025] Optionally, in some embodiments of the present application, in the orthographic projection pattern of the liquid crystal display panel, along the first direction, the first thin film transistor and the second thin film transistor are partially overlapped;

[0026] The first shielding portion includes a base and a row shielding portion connected to the base, wherein in an orthographic projection pattern of the liquid crystal display panel, the base completely covers the backing material, the base covers a portion of the scan lines and the thin film transistors, and the row shielding portion covers another portion of the scan lines and the thin film transistors;

[0027] Wherein, in a direction perpendicular to the first direction, the width of the base is greater than the width of the row shielding portion. Optionally, in some embodiments of the present application, the first thin film transistor includes a first active layer, the first active layer includes a first portion and a second portion connected to the first portion, and an extension direction of the first portion intersects an extension direction of the second portion;

[0028] The first scan line overlaps with the first portion and the second portion simultaneously, and a portion of the first scan line that overlaps with the first portion and the second portion simultaneously is multiplexed as a gate of the first thin film transistor.

[0029] Optionally, in some embodiments of the present application, the first scanning line includes a first turning portion and a first connecting portion connected between two adjacent first turning portions, the first turning portion includes a first segment, a second segment, and a third segment connected in sequence, an extension direction of the first segment intersects with an extension direction of the second segment, an extension direction of the second segment intersects with an extension direction of the third segment, the first segment and the third segment are both connected to a side of the second segment close to the second scanning line, one end of the first connecting portion is connected to the first segment of one first turning portion, and the other end of the first connecting portion is connected to the third segment of another first turning portion;

[0030] The first connecting portion is overlapped with the first portion, and the first section is overlapped with the second portion.

[0031] Optionally, in some embodiments of the present application, the second thin film transistor includes a second active layer, the second active layer includes a third portion and a fourth portion connected to the third portion, and an extension direction of the third portion intersects an extension direction of the fourth portion;

[0032] The second scan line overlaps with the third portion and the fourth portion simultaneously, and a portion of the second scan line that overlaps with the third portion and the fourth portion simultaneously is multiplexed as a gate of the second thin film transistor.

[0033] Optionally, in some embodiments of the present application, the second scanning line includes a second turning portion and a second connecting portion connected between two adjacent second turning portions, the second turning portion includes a fourth segment, a fifth segment, and a sixth segment connected in sequence, an extension direction of the fourth segment intersects with an extension direction of the fifth segment, an extension direction of the fifth segment intersects with an extension direction of the sixth segment, the fourth segment and the sixth segment are both connected to a side of the fifth segment away from the first scanning line, one end of the second connecting portion is connected to the fourth segment of one second turning portion, and the other end of the second connecting portion is connected to the sixth segment of another second turning portion;

[0034] The fourth section is overlapped with the third section, and the fifth section is overlapped with the fourth section.

[0035] Optionally, in some embodiments of the present application, in a direction perpendicular to the first direction, the first turning portion and the second turning portion are aligned, and the first connecting portion and the second connecting portion are aligned;

[0036] Along the first direction, the fifth section and the first connecting portion extend in the same direction, and the fifth section and the first connecting portion are alternately arranged and aligned.

[0037] Optionally, in some embodiments of the present application, the first part and the third part are cross-connected, the first thin film transistor and the second thin film transistor share a common input electrode, and the common input electrode is connected to the data line and connected to the intersection of the first part and the third part.

[0038] Optionally, in some embodiments of the present application, the data line is connected to the common input electrode through a first via hole, and in the orthographic projection pattern of the liquid crystal display panel, the data line, the first via hole and the common input electrode are correspondingly overlapped.

[0039] Optionally, in some embodiments of the present application, the output electrode of the first thin film transistor and the output electrode of the second thin film transistor are adjacently arranged in the area defined by the first bend portion and the fifth segment, and the common input electrode is arranged between the first connecting portion and the second connecting portion.

[0040] Optionally, in some embodiments of the present application, the liquid crystal display panel includes an opposing substrate arranged opposite to the array substrate, the black matrix layer is integrated with the opposing substrate or the array substrate, and the pad is integrated with the opposing substrate or the array substrate.

[0041] In the liquid crystal display panel of an embodiment of the present application, in the orthographic projection pattern of the liquid crystal display panel, a first shielding portion of the black matrix layer completely covers two adjacent scan lines, the thin-film transistors connected thereto, and the spacer. In the present application, the spacer, two scan lines, and the thin-film transistors connected thereto are disposed in the area covered by the first shielding portion, so that the first shielding portion simultaneously covers the spacer, the two scan lines, and the thin-film transistors connected thereto. Compared to a design with a single row of scan lines, this avoids the area where the spacer is located extending beyond the width of the area adjacent to the single row of scan lines, which would otherwise waste additional aperture ratio. This improves the aperture ratio of the liquid crystal display panel without sacrificing product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic diagram of an orthographic projection of a liquid crystal display panel in the related art;

[0043] Figure 2 is a schematic cross-sectional structural diagram of a liquid crystal display panel provided in an embodiment of the present application;

[0044] Figure 3 1 is a schematic diagram of the orthographic projection structure of a liquid crystal display panel provided in an embodiment of the present application;

[0045] Figure 4 yes Figure 3 Enlarged view of part A;

[0046] Figure 5 yes Figure 4 Schematic diagram of removing the spacer and pixel electrode;

[0047] Figure 6 yes Figure 3 Schematic diagram of the black matrix layer;

[0048] Figure 7 is another schematic diagram of the orthographic projection structure of the liquid crystal display panel provided in an embodiment of the present application;

[0049] Figure 8 yes Figure 7 Enlarged view of part A;

[0050] Figure 9 yes Figure 7 Schematic diagram of removing the spacer and pixel electrode. DETAILED DESCRIPTION

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as labels and do not impose numerical requirements or establish an order.

[0052] The embodiments of the present application provide a liquid crystal display panel, which is described in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0053] In the related art of liquid crystal panels, please refer to Figure 1 The area where a single row of scan lines scan, the thin film transistor mos connected thereto, and a common electrode line com are located is referred to as a row area, and the area where the pixel electrodes are located is referred to as a pixel area xs. In the extension direction of the data line data, a row area and a row of pixel electrodes are alternately arranged. The pad jg is correspondingly arranged in the row area, wherein the portion of the black matrix layer hs corresponding to the pad jg is the base fg, and the portion of the black matrix layer hs corresponding to the row area is the row shielding portion h1. Since the base fg needs to shield the pad jg, it requires a certain safety distance, so the width of the base fg is usually more than 20 microns, and the width of the row shielding portion h1 is less than 20 microns, which results in part of the base in each row area exceeding the row shielding portion, thereby causing waste of the opening.

[0054] In the liquid crystal display panel of the embodiment of the present application, in the orthographic projection pattern of the liquid crystal display panel, two rows of pixel electrodes are disposed between two adjacent row line groups, a spacer is stacked on the row line group, and the first shielding portion of the black matrix layer fully covers the row line group and the spacer. In the present application, the spacer, two scan lines, and thin-film transistors connected thereto are disposed in the region where the row line group is located, so that the first shielding portion simultaneously covers the spacer, the two scan lines, and the thin-film transistors connected thereto. Compared to a design with a single row of scan lines, this avoids the region where each row of spacers is located extending beyond the width of the region adjacent to the single row of scan lines, thereby avoiding additional waste of aperture ratio. Thus, the aperture ratio of the liquid crystal display panel can be increased without reducing the size of the scan lines and thin-film transistors, and thus without sacrificing product performance.

[0055] Please refer to Figures 2 to 4 An embodiment of the present application provides a liquid crystal display panel 100, which includes an array substrate 10a, a spacer ps and a black matrix layer BM.

[0056] The black matrix layer BM is provided with a plurality of pixel openings b1 and a plurality of first blocking portions m1 arranged along a first direction x, wherein the first blocking portions m1 are located between two adjacent rows of the pixel openings b1.

[0057] The array substrate 10a includes a plurality of pixel electrodes p, a plurality of scan lines arranged along a first direction x, and a plurality of thin-film transistors. Pixel openings b1 are provided corresponding to the pixel electrodes p. In the orthographic projection pattern of the liquid crystal display panel 100, two adjacent scan lines are provided between two adjacent rows of pixel openings b1, and the first shielding portion m1 covers the scan lines and thin-film transistors. The scan lines are connected to the gates of the thin-film transistors.

[0058] The spacer ps is disposed on the array substrate 10 a . In the orthographic projection pattern of the liquid crystal display panel 100 , the first shielding portion m1 covers the spacer ps.

[0059] In the liquid crystal display panel 100 of the embodiment of the present application, in the orthographic projection pattern of the liquid crystal display panel 100, the first blocking portion m1 of the black matrix layer BM completely covers two adjacent scan lines, the thin film transistors connected thereto, and the spacer ps. In the present application, the spacer ps, the two scan lines, and the thin film transistors connected thereto are disposed in the area covered by the first blocking portion, so that the first blocking portion m1 simultaneously covers the spacer ps, the two scan lines, and the thin film transistors connected thereto. Compared to a design with a single row of scan lines, this avoids the area where the spacer ps is located in each row exceeding the width of the area adjacent to the single row of scan lines, thereby avoiding additional waste of aperture ratio. Thus, the aperture ratio of the liquid crystal display panel 100 can be improved without reducing the size of the scan lines and thin film transistors, and thus without sacrificing product performance.

[0060] Optionally, two adjacent scan lines and the thin film transistors connected thereto form a row line group z1. The scan lines include a first scan line 111 and a second scan line 112. The thin film transistors include a first thin film transistor t1 and a second thin film transistor t2. The gate of the first thin film transistor t1 is connected to the first scan line 111. The gate of the second thin film transistor t2 is connected to the second scan line 112.

[0061] The padding ps is stacked and arranged on the row line group z1.

[0062] In one embodiment, in the orthographic projection pattern of the liquid crystal display panel 100 , the first shielding portion m1 completely covers the row line group z1 and the spacer ps.

[0063] In one embodiment, the liquid crystal display panel 100 includes an opposing substrate 10b disposed opposite to the array substrate 10a, a black matrix layer BM integrated on the opposing substrate 10b or the array substrate 10a, and a spacer ps integrated on the opposing substrate 10b or the array substrate 10a.

[0064] For example, the black matrix layer BM is integrated on the opposite substrate 10 b , and the spacer ps is integrated on the array substrate 10 a , wherein the spacer ps is arranged on the side of the thin film transistor layer close to the opposite substrate 10 b .

[0065] For example, the black matrix layer BM is integrated with the array substrate 10a, and the spacer ps is integrated with the array substrate 10a. The black matrix layer BM is arranged on the side of the thin film transistor layer close to the opposite substrate 10b, and the spacer ps is arranged on the side of the black matrix layer BM close to the opposite substrate 10b.

[0066] For example, the black matrix layer BM is integrated on the array substrate 10a, and the spacer ps is integrated on the counter substrate 10b. The black matrix layer BM is disposed on the side of the thin film transistor layer close to the counter substrate 10b.

[0067] For another example, the black matrix layer BM and the padding ps are integrated into the opposing substrate 10b. Taking this embodiment as an example, the opposing substrate 10b includes a first substrate 101, a black matrix layer BM and a padding ps. The black matrix layer BM is arranged on the side of the first substrate 101 close to the array substrate 10a, and the padding ps is arranged on the side of the black matrix layer BM close to the array substrate 10a.

[0068] In one embodiment, the array substrate 10a includes a second substrate 102 and a thin film transistor layer 103 disposed on a side of the second substrate 102 close to the opposite substrate 10b. The thin film transistor layer 103 includes a first scan line 111, a second scan line 112, a first thin film transistor t1, and a second thin film transistor t2.

[0069] Optionally, the first scan line 111 , the second scan line 112 , the gate of the first thin film transistor t1 and the gate of the second thin film transistor t2 are provided in the same layer and are formed using the same photomask process.

[0070] In one embodiment, two rows of pixel openings b1 are disposed between two adjacent first shielding portions m1. The array substrate 10a further includes common electrode lines 13 extending along the first direction x. The common electrode lines 13 are disposed between the two rows of pixel openings b1 and between the two first shielding portions m1.

[0071] The black matrix layer BM includes a third blocking portion m3 , and the third blocking portion m3 covers the common electrode line 13 .

[0072] In panels with a single-row scan line architecture, to ensure common electrode uniformity, common electrode lines are typically located alongside the single scan line, meaning each row region is provided with a common electrode line. However, in this embodiment, common electrode lines 13 are located between two adjacent row line groups z1, rather than being integrated within row line group z1. Therefore, compared to a single-row scan line architecture, this embodiment reduces the number of common electrode lines 13 by half while ensuring common electrode uniformity, further improving the aperture ratio.

[0073] The array substrate 10a further includes data lines 12 arranged along a second direction intersecting with the first direction x. The first direction x is the first direction, and the second direction is the extending direction of the data lines 12.

[0074] In the orthographic projection pattern of the liquid crystal display panel 100, the data line 12 is arranged to intersect with the scan line and the common electrode line 13 respectively. The pixel electrode p includes a first pixel electrode p1 and a second pixel electrode p2. The first pixel electrode p1 corresponds to a pixel opening b1, and the second pixel electrode p2 corresponds to another pixel opening b1. The output electrode of the first thin-film transistor t1 is connected to the first pixel electrode p1, and the output electrode of the second thin-film transistor t2 is connected to the second pixel electrode p2. A common electrode line 13 is separated between the side of the first pixel electrode p1 away from the first thin-film transistor t1 and the side of the second pixel electrode p2 away from the second thin-film transistor t2. A line group z1 is separated between the side of the first pixel electrode p1 close to the first thin-film transistor t1 and the side of the second pixel electrode p2 close to the second thin-film transistor t2.

[0075] The black matrix layer BM further includes a second blocking portion m2 , which is cross-connected with the third blocking portion m3 , and the first blocking portion m1 and the second blocking portion m2 are cross-connected with each other.

[0076] In the orthographic projection pattern of the liquid crystal display panel 100, the first shielding portion m1, the pixel opening b1, the third shielding portion m3, and the pixel opening b1 are alternately arranged in a direction perpendicular to the first direction x. The second shielding portion m2 covers the data line 12. The third shielding portion m3 covers the common electrode line 13.

[0077] Optionally, the second shielding portion m2 completely covers the data line 12 , and the third shielding portion m3 completely covers the common electrode line 13 .

[0078] In the black matrix layer BM, first shielding portions m1 and third shielding portions m3 are alternately arranged in a direction perpendicular to the first direction. Second shielding portions m2 intersect and connect with the first shielding portions m1 and the third shielding portions m3, respectively. Two adjacent second shielding portions, a first shielding portion m1, and a third shielding portion m3 are connected to form a pixel opening b1.

[0079] Optionally, a width v1 of the third blocking portion m3 is smaller than a width v2 of the first blocking portion m1.

[0080] Optionally, the data line 12 , the input electrode and the output electrode of the first thin film transistor t1 , and the input electrode and the output electrode of the second thin film transistor t2 are arranged in the same layer and formed in the same photomask process.

[0081] It is understood that if one of the input and output electrodes of a thin film transistor is a source electrode, the other is a drain electrode. This application uses the input electrode of a thin film transistor as a source electrode and the output electrode as a drain electrode as an example for explanation, but is not limited thereto.

[0082] Optionally, the data line 12 is connected to the input electrode of the first thin film transistor t1 and the input electrode of the second thin film transistor.

[0083] In one embodiment, in the orthographic projection pattern of the liquid crystal display panel 100, a plurality of spacers ps are arranged in rows along a first direction x. In a direction perpendicular to the first direction x, a row of first pixel electrodes p1 and a row of second pixel electrodes p2 are disposed between two adjacent rows of spacers ps.

[0084] That is, two rows of pixel electrodes p are arranged between two adjacent rows of spacers ps. In the embodiment of the present application, the number of spacers ps is reduced by arranging the spacers ps in an intermittent manner, thereby improving the aperture ratio.

[0085] In one embodiment, in the orthographic projection pattern of the liquid crystal display panel 100 , the spacer ps is disposed at the intersection of the first shielding portion m1 and the second shielding portion m2 .

[0086] The spacer ps partially overlaps the first scan line 111 , the second scan line 112 , and the data line 12 at the same time.

[0087] Among them, the padding ps is arranged at the intersection of the first shielding part m1 and the second shielding part m2. On the one hand, it is convenient to position the padding ps so that the padding ps is evenly arranged; on the other hand, when the padding ps is offset due to error, the second shielding part m2 can compensate for the offset of the padding ps.

[0088] Optionally, the intersection of the first shielding portion m1 and the second shielding portion m2 is set as a base dz of the padding ps, and the base dz is used to support and shield the padding ps.

[0089] That is, in the orthographic projection pattern of the liquid crystal display panel 100 , the chassis dz completely blocks the spacer ps.

[0090] The first shielding portion m1 includes a base dz and a row shielding portion m11 connected between two adjacent bases dz.

[0091] The second shielding portion m2 includes a base dz and a column shielding portion m21 connected between two adjacent bases dz.

[0092] In the first direction x, the width of the base dz is greater than the width of the column shielding portion m21; in a direction perpendicular to the first direction x, the width of the base dz is greater than the width of the row shielding portion m11. This arrangement ensures that the base dz fully shields the padding ps.

[0093] In one embodiment, in the orthographic projection pattern of the liquid crystal display panel 100, in a direction perpendicular to the first direction x, the area where the spacer ps is located has a first width k1, the area where the first scan line 111 and the first thin film transistor t1 connected thereto are located has a second width k2, and the area where the second scan line 112 and the second thin film transistor t2 connected thereto are located has a third width k3. The first width k1 is greater than the second width k2 and the third width k3, and is less than or equal to the sum of the second width k2 and the third width k3.

[0094] The area of ​​a single thin film transistor is reduced by changing the structure of the thin film transistor, thereby increasing the aperture ratio.

[0095] In one embodiment, in the same row line group z1 , the first thin film transistor t1 and the second thin film transistor t2 are disposed back-to-back with the first scan line 111 and the second scan line 112 separated therefrom.

[0096] That is, in the orthographic projection pattern of the liquid crystal display panel 100, in the same row line group z1, the first thin film transistor t1 is arranged on the side of the first scan line 111 away from the second scan line 112, and the second thin film transistor t2 is arranged on the side of the second scan line 112 away from the first scan line 111, and is aligned with the first thin film transistor t1.

[0097] The first thin film transistor t1 and the second thin film transistor t2 are arranged back to back, which can save space in the row direction and thus improve the resolution.

[0098] In one embodiment, the first scan line 111 includes a first main line 11a and at least one first extension portion 11b connected to a side of the first main line 11a away from the second scan line 112 and connected to the gate of the first thin film transistor t1.

[0099] The first thin film transistor t1 includes a first active layer 141. In the orthographic projection pattern of the liquid crystal display panel 100, the first active layer 141 is overlapped with the gate electrode of the first thin film transistor t1.

[0100] Optionally, the first active layer 141 and the first main line 11 a are both extended along the first direction x to reduce the width of the region where the first thin film transistor t1 is located, thereby increasing the aperture ratio.

[0101] In one embodiment, the first active layer 141 extends along the extension direction of the first main line 11a, and the extension direction of the first extension portion 11b intersects the extension direction of the first main line 11a. The first active layer 141 overlaps the gates of the two first thin film transistors t1.

[0102] That is, the first thin film transistor t1 is a dual-gate thin film transistor, which improves the turn-on speed of the first thin film transistor t1.

[0103] In one embodiment, the second scan line 112 includes a second main line 11c and at least one second extension 11d. The second extension 11d is connected to a side of the second main line 11c away from the first scan line 111. The second extension 11d is connected to the gate of the second thin film transistor t2.

[0104] The second thin film transistor t2 includes a second active layer 142. In the orthographic projection pattern of the liquid crystal display panel 100, the second active layer 142 is overlapped with the gate electrode of the second thin film transistor t2.

[0105] Optionally, the second active layer 142 and the second main line 11 c are both extended along the first direction x to reduce the width of the region where the second thin film transistor t2 is located, thereby increasing the aperture ratio.

[0106] In one embodiment, the second active layer 142 extends along the extension direction of the second main line 11c, and the extension direction of the second extension portion 11d intersects the extension direction of the second main line 11c. The second active layer 142 overlaps the gates of the two second thin film transistors t2.

[0107] That is, the second thin film transistor t2 is a dual-gate thin film transistor, which improves the turn-on speed of the second thin film transistor t2.

[0108] In one embodiment, the output electrode d1 of the first thin film transistor t1 and the output electrode d2 of the second thin film transistor t2 are arranged back to back, and the input electrode of the first thin film transistor t1 and the input electrode of the second thin film transistor t2 are arranged back to back.

[0109] An output electrode d1 of the first thin film transistor t1 is connected to the first pixel electrode p1 , and an output electrode d2 of the second thin film transistor t2 is connected to the second pixel electrode p2 .

[0110] Optionally, the input electrode of the first thin film transistor t1 is connected to the first active layer 141 through the first via hole h1, and the output electrode d1 of the first thin film transistor t1 is connected to the first active layer 141 through the first via hole h1. The output electrode d1 of the first thin film transistor t1 is connected to the first pixel electrode p1 through the second via hole h2.

[0111] The input electrode of the second thin film transistor t2 is connected to the second active layer 142 through the third via hole h3, and the output electrode d2 of the second thin film transistor t2 is connected to the second active layer 142 through the third via hole h3. The output electrode d2 of the second thin film transistor t2 is connected to the second pixel electrode p2 through the fourth via hole h4.

[0112] Optionally, the first thin film transistor t1 and the second thin film transistor t2 may also be of a single-gate structure.

[0113] When the first active layer 141 of the dual-gate first thin film transistor t1 and the second active layer 142 of the dual-gate second thin film transistor t2 are both in a straight line, the embodiment of the present application is superior to the liquid crystal panel with a single scan line structure ( Figure 1 As shown), the opening rate can be increased by 6.1% to 10.2%.

[0114] Please refer to Figure 5 and Figure 6 In one embodiment, different from the above embodiment, in the orthographic projection pattern of the liquid crystal display panel 100 , the first thin film transistor t1 and the second thin film transistor t2 are partially overlapped along the first direction x.

[0115] Correspondingly, the first shielding portion m1 includes a base dz and a row shielding portion m11 connected between two adjacent bases dz. The second shielding portion m2 includes a base dz and a column shielding portion m21 connected between two adjacent bases dz. That is, the first shielding portion m1 and the second shielding portion m2 share the base dz.

[0116] In the first direction x, along which the first shielding portion m1 extends, the width of the base dz is greater than that of the column shielding portion m21. In a direction perpendicular to the first direction x, along which the first shielding portion m1 extends, the width of the base dz is greater than that of the row shielding portion m11. This arrangement ensures that the base dz fully shields the padding ps. By partially overlapping the first and second thin-film transistors t1 and t2 in the first direction x, the size of the row circuit group z1 along the first direction x is reduced, thereby improving the aperture ratio.

[0117] In one embodiment, the first thin film transistor t1 includes a first active layer 141. The first active layer 141 includes a first portion 14a and a second portion 14b connected to the first portion 14a. An extension direction of the first portion 14a intersects an extension direction of the second portion 14b.

[0118] In the same row line group z1, the first scan line 111 overlaps the first portion 14a and the second portion 14b. The portion of the first scan line 111 that overlaps the first portion 14a and the second portion 14b is reused as the gate of the first thin film transistor t1.

[0119] The first active layer 141 is arranged in a bent manner. Compared with a straight arrangement, the space of the first shielding portion m1 in the extending direction x can be shortened, thereby saving the layout space of the first thin film transistor t1.

[0120] In one embodiment, the first scanning line 111 includes a first bend portion 1a and a first connecting portion 1b connecting two adjacent first bend portions 1a. The first bend portion 1a includes a first segment 1a1, a second segment 1a2, and a third segment 1a3, which are sequentially connected. The extension direction of the first segment 1a1 intersects with the extension direction of the second segment 1a2, and the extension direction of the second segment 1a2 intersects with the extension direction of the third segment 1a3. The first segment 1a1 and the third segment 1a3 are both connected to the side of the second segment 1a2 close to the second scanning line 112. One end of the first connecting portion 1b is connected to the first segment 1a1 of one first bend portion 1a, and the other end of the first connecting portion 1b is connected to the third segment 1a3 of another first bend portion 1a.

[0121] The first connecting portion 1b is overlapped with the first portion 14a, and the first section 1a1 is overlapped with the second portion 14b.

[0122] Optionally, the first portion 14a and the second portion 14b are orthogonally connected, and the first connecting portion 1b is orthogonally intersecting with the first portion 14a at different layers. The extending direction of the first segment 1a1 and the extending direction of the third segment 1a3 are both perpendicular to the extending direction of the second segment 1a2, and the extending direction of the first connecting portion 1b is parallel to the extending direction of the second segment 1a2.

[0123] Optionally, the first portion 14 a is overlapped with the data line 12 to save space.

[0124] In one embodiment, the second thin film transistor t2 includes a second active layer 142. The second active layer 142 includes a third portion 14c and a fourth portion 14d connected to the third portion 14c. An extension direction of the third portion 14c intersects an extension direction of the fourth portion 14d.

[0125] In the same row line group z1 , the second scan line 112 overlaps with both the third portion 14c and the fourth portion 14d . The portion of the second scan line 112 overlapping with both the third portion 14c and the fourth portion 14d is reused as the gate of the second thin film transistor t2 .

[0126] The second active layer 142 is arranged in a bent manner. Compared with a straight arrangement, the space in the extension direction x of the first blocking portion m1 can be shortened, thereby saving the layout space of the second thin film transistor t2 .

[0127] Optionally, the third portion 14c and the fourth portion 14d are connected in an orthogonal manner.

[0128] In one embodiment, the second scan line 112 includes a second bend portion 1c and a second connecting portion 1d connecting two adjacent second bend portions 1c. The second bend portion 1c includes a fourth segment 1c1, a fifth segment 1c2, and a sixth segment 1c3, which are sequentially connected. The extension direction of the fourth segment 1c1 intersects with the extension direction of the fifth segment 1c2, and the extension direction of the fifth segment 1c2 intersects with the extension direction of the sixth segment 1c3. The fourth segment 1c1 and the sixth segment 1c3 are both connected to the side of the fifth segment 1c2 away from the first scan line 111. One end of the second connecting portion 1d is connected to the fourth segment 1c1 of one second bend portion 1c, and the other end of the second connecting portion 1d is connected to the sixth segment 1c3 of another second bend portion 1c.

[0129] The fourth section 1c1 is overlapped with the third portion 14c, and the fifth section 1c2 is overlapped with the fourth portion 14d.

[0130] Optionally, the fourth section 1c1 and the third portion 14c are perpendicular to each other. The extension direction of the fourth section 1c1 and the extension direction of the sixth section 1c3 are both perpendicular to the extension direction of the fifth section 1c2, and the extension direction of the second connecting portion 1d is parallel to the extension direction of the fifth section 1c2.

[0131] Optionally, in a direction perpendicular to the first direction x, the first turning portion 1a and the second turning portion 1c are aligned, and the first connecting portion 1b and the second connecting portion 1d are aligned, so as to save space in the first direction x.

[0132] Along the first direction x, the fifth segment 1c2 extends in the same direction as the first connecting portion 1b. The fifth segment 1c2 and the first connecting portion 1b are alternately arranged and aligned to save space perpendicular to the first direction x.

[0133] In one embodiment, the first portion 14a and the third portion 14c are cross-connected. The first thin film transistor t1 and the second thin film transistor t2 share a common input electrode 151. The common input electrode 151 is connected to the data line 12 and to the intersection of the first portion 14a and the third portion 14c.

[0134] Optionally, the first portion 14a and the third portion 14c are connected in an orthogonal manner. The first thin film transistor t1 and the second thin film transistor t2 share an input electrode, which can save one input electrode and thus save space.

[0135] In one embodiment, the output electrode d1 of the first thin film transistor t1 and the output electrode d2 of the second thin film transistor t2 are adjacently disposed in the region defined by the first bend portion 1a and the fifth segment 1c2. The common input electrode 151 is disposed between the first connecting portion 1b and the second connecting portion 1d.

[0136] That is, the output electrodes d1 and d2 are arranged in the space formed by the first bend portion 1a, and the common input electrode 151 is arranged in the space formed by the sixth segment 1c3, the second connecting portion 1d, and the fourth segment 1c1, so as to save space and avoid the output electrodes d1 and d2 from forming parasitic capacitances with the first scan line 111 and the second scan line 112 respectively.

[0137] Optionally, the common input electrode 151 is connected to the intersection of the first active layer 141 and the second active layer 142 through a first via hole h1, and the output electrode d1 of the first thin film transistor t1 is connected to the first active layer 141 through another first via hole h1. The output electrode d1 of the first thin film transistor t1 is connected to the first pixel electrode p1 through a second via hole h2.

[0138] Optionally, the data line 12 is connected to the common input electrode 151 through a first via hole h1. In the orthographic projection pattern of the liquid crystal display panel 100, the data line 12, the first via hole h1 and the common input electrode 151 are overlapped to save space for the first via hole h1 and improve the aperture ratio.

[0139] The output electrode d2 of the second thin film transistor t2 is connected to the second active layer 142 through the third via hole h3. The output electrode d2 of the second thin film transistor t2 is connected to the second pixel electrode p2 through the fourth via hole h4.

[0140] Optionally, in the first direction, the length of the second connecting portion 1d is greater than that of the first connecting portion 1b, and the length of the first turning portion 1a is greater than that of the second turning portion 1c.

[0141] When the first active layer 141 of the dual-gate first thin film transistor t1 and the second active layer 142 of the dual-gate second thin film transistor t2 are both in an L-shape, the embodiment of the present application is superior to the liquid crystal panel with a single scan line structure (such as Figure 1 As shown), the opening rate can be increased by 5.8% to 9.9%.

[0142] In the liquid crystal display panel of an embodiment of the present application, in an orthographic projection pattern of the liquid crystal display panel, two rows of pixel electrodes are disposed between two adjacent row line groups, a spacer is stacked on the row line group, and a first shielding portion of the black matrix layer fully covers the row line group and the spacer. In the present application, the spacer, two scan lines, and thin-film transistors connected thereto are disposed in the region where the row line group is located, so that the first shielding portion simultaneously covers the spacer, the two scan lines, and the thin-film transistors connected thereto. Compared to a design with a single row of scan lines, this avoids the region where each row of spacers is located extending beyond the width of the region adjacent to the single row of scan lines, thereby wasting additional aperture ratio. Thus, the aperture ratio of the liquid crystal display panel can be increased without limiting the size of the scan lines and thin-film transistors, and thus without sacrificing product performance.

[0143] The above is a detailed introduction to a liquid crystal display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A liquid crystal display panel, characterized in that: include: A black matrix layer, wherein the black matrix layer is provided with a plurality of pixel openings, the black matrix layer includes a plurality of first shielding portions arranged along a first direction, the first shielding portions being located between two adjacent rows of the pixel openings; An array substrate comprising a plurality of pixel electrodes, a plurality of scan lines arranged along the first direction, and a plurality of thin film transistors; the pixel electrodes are arranged corresponding to the pixel openings, the scan lines include a first scan line and a second scan line, and the thin film transistors include a first thin film transistor and a second thin film transistor, a gate of the first thin film transistor is connected to the first scan line, and a gate of the second thin film transistor is connected to the second scan line; in an orthographic projection pattern of the liquid crystal display panel, adjacent first scan lines and second scan lines are correspondingly arranged between two adjacent rows of pixel openings, and the first shielding portion covers the first scan line, the second scan line, the first thin film transistor, and the second thin film transistor; A padding material is provided on the array substrate, wherein the first shielding portion covers the padding material in the orthographic projection pattern of the liquid crystal display panel; The array substrate further includes a plurality of data lines arranged along a second direction intersecting the first direction; in an orthographic projection pattern of the liquid crystal display panel, the data lines are arranged to intersect the first scan line and the second scan line respectively; The first scanning line includes a first bend portion and a first connecting portion connecting two adjacent first bend portions, the first bend portion includes a first segment, a second segment, and a third segment connected in sequence, an extension direction of the first segment intersects with an extension direction of the second segment, an extension direction of the second segment intersects with an extension direction of the third segment, the first segment and the third segment are both connected to a side of the second segment close to the second scanning line, one end of the first connecting portion is connected to the first segment of one first bend portion, and the other end of the first connecting portion is connected to the third segment of another first bend portion; The second scanning line includes a second turning portion and a second connecting portion connected between two adjacent second turning portions, the second turning portion includes a fourth segment, a fifth segment, and a sixth segment connected in sequence, the extension direction of the fourth segment intersects with the extension direction of the fifth segment, the extension direction of the fifth segment intersects with the extension direction of the sixth segment, the fourth segment and the sixth segment are both connected to a side of the fifth segment away from the first scanning line, one end of the second connecting portion is connected to the fourth segment of one second turning portion, and the other end of the second connecting portion is connected to the sixth segment of another second turning portion; In a direction perpendicular to the first direction, the first turning portion and the second turning portion are aligned, and the first connecting portion and the second connecting portion are aligned; Along the first direction, the fifth section and the first connecting portion extend in the same direction, and the fifth section and the first connecting portion are alternately arranged and aligned.

2. The liquid crystal display panel according to claim 1, wherein Two rows of pixel openings are provided between two adjacent first shielding portions, and the array substrate further includes a common electrode line extending along the first direction, the common electrode line being provided between the two rows of pixel openings and between the two first shielding portions; The black matrix layer includes a third shielding portion, and the third shielding portion covers the common electrode line.

3. The liquid crystal display panel according to claim 2, wherein: In an orthographic projection pattern of the liquid crystal display panel, the data line and the common electrode line are arranged to intersect each other, the pixel electrodes include a first pixel electrode and a second pixel electrode; the first pixel electrode corresponds to a pixel opening, the second pixel electrode corresponds to a pixel opening, the output electrode of the first thin film transistor is connected to the first pixel electrode, the output electrode of the second thin film transistor is connected to the second pixel electrode, a side of the first pixel electrode away from the first thin film transistor and a side of the second pixel electrode away from the second thin film transistor are separated by the common electrode line, and a side of the first pixel electrode close to the first thin film transistor and a side of the second pixel electrode close to the second thin film transistor are separated by the first scan line and the second scan line; The black matrix layer includes a second shielding portion; the first shielding portion and the second shielding portion are cross-connected, and in the orthographic projection pattern of the liquid crystal display panel, in a direction perpendicular to the first direction, the first shielding portion, the pixel opening, the third shielding portion and the pixel opening are alternately arranged, and the second shielding portion covers the data line.

4. The liquid crystal display panel according to claim 3, wherein: In the orthographic projection pattern of the liquid crystal display panel, a plurality of the spacers are arranged in rows along the first direction, and in a direction perpendicular to the first direction, a row of the first pixel electrodes and a row of the second pixel electrodes are provided between two adjacent rows of the spacers.

5. The liquid crystal display panel according to claim 3, wherein: In the orthographic projection pattern of the liquid crystal display panel, the spacer is provided at the intersection of the first shielding portion and the second shielding portion; The spacer partially overlaps the first scan line, the second scan line, and the data line simultaneously.

6. The liquid crystal display panel according to any one of claims 3 to 5, wherein: in, In the orthographic projection pattern of the liquid crystal display panel, in a direction perpendicular to the first direction, an area where the spacer is located has a first width, an area where the first scan line and the first thin film transistor connected thereto are located has a second width, and an area where the second scan line and the second thin film transistor connected thereto are located has a third width, the first width is greater than the second width and the third width, and the first width is less than or equal to the sum of the second width and the third width.

7. The liquid crystal display panel according to any one of claims 3 to 5, wherein: In the orthographic projection pattern of the liquid crystal display panel, along the first direction, the first thin film transistor and the second thin film transistor are partially overlapped; The first shielding portion includes a base and a row shielding portion connected to the base, wherein in an orthographic projection pattern of the liquid crystal display panel, the base completely covers the backing material, the base covers a portion of the scan lines and the thin film transistors, and the row shielding portion covers another portion of the scan lines and the thin film transistors; Wherein, in a direction perpendicular to the first direction, the width of the base is greater than the width of the row shielding portion.

8. The liquid crystal display panel according to claim 7, wherein: The first thin film transistor includes a first active layer, the first active layer includes a first portion and a second portion connected to the first portion, and an extension direction of the first portion intersects an extension direction of the second portion; The first scan line overlaps with the first portion and the second portion simultaneously, and a portion of the first scan line that overlaps with the first portion and the second portion simultaneously is multiplexed as a gate of the first thin film transistor.

9. The liquid crystal display panel according to claim 8, wherein: The first connecting portion is overlapped with the first portion, and the first section is overlapped with the second portion.

10. The liquid crystal display panel according to claim 9, wherein The second thin film transistor includes a second active layer, the second active layer includes a third portion and a fourth portion connected to the third portion, and an extension direction of the third portion intersects an extension direction of the fourth portion; The second scan line overlaps with the third portion and the fourth portion simultaneously, and a portion of the second scan line that overlaps with the third portion and the fourth portion simultaneously is multiplexed as a gate of the second thin film transistor.

11. The liquid crystal display panel according to claim 10, wherein: The fourth section is overlapped with the third section, and the fifth section is overlapped with the fourth section.

12. The liquid crystal display panel according to claim 11, wherein The first portion and the third portion are cross-connected, the first thin film transistor and the second thin film transistor share a common input electrode, and the common input electrode is connected to the data line and to the intersection of the first portion and the third portion.

13. The liquid crystal display panel according to claim 12, wherein: The data line is connected to the common input electrode through a first via hole. In the orthographic projection pattern of the liquid crystal display panel, the data line, the first via hole and the common input electrode are correspondingly overlapped.

14. The liquid crystal display panel according to claim 12, wherein: The output electrode of the first thin film transistor and the output electrode of the second thin film transistor are adjacently arranged in the area defined by the first turning portion and the fifth section, and the common input electrode is arranged between the first connecting portion and the second connecting portion.

15. The liquid crystal display panel according to any one of claims 1 to 5, characterized in that: The liquid crystal display panel includes an opposite substrate arranged opposite to the array substrate, the black matrix layer is integrated with the opposite substrate or the array substrate, and the spacer is integrated with the opposite substrate or the array substrate.

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