Gate driving circuit, display panel and display device

Abstract

This application provides a gate driving circuit, a display panel, and a display device, which can improve the waveform of the output signal of the gate driving circuit. The gate driving circuit includes: an input circuit for charging the pull-up node of the gate driving circuit according to a cascaded signal; a pull-down circuit for pulling down the voltage of the pull-down node of the gate driving circuit according to a low gate voltage under the control of the voltage of the pull-up node; an output circuit including at least two drive output transistors respectively connected to at least two gate lines, and a bootstrap capacitor, wherein the at least two drive output transistors are respectively used to receive corresponding clock signals and output the corresponding clock signals as drive signals under the control of the voltage of the pull-up node; and a boost circuit including a boost capacitor for continuously charging the pull-up node under the control of the output signal of the output circuit, so that the voltage of the pull-up node is maintained at an effective voltage, wherein the ratio between the bootstrap capacitor and the boost capacitor is set within a predetermined range.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] Gate drive on array (GOA) technology integrates the gate drive circuit onto the array substrate, thereby replacing the gate drive chip and reducing power consumption and cost. To shorten the bezel of the display panel, multiple GOA drive circuits can share a pull-up node. However, the gate voltage of the last stage drive output transistor in the same pull-up node may drop too much, causing the falling edge of the clock signal output by the last stage drive output transistor to be too flat, i.e., the fall time is too long. This results in poor waveform consistency of the output signals from each stage drive output transistor, affecting the display effect. Summary of the Invention

[0003] This application provides a gate driving circuit, a display panel, and a display device that can improve the waveform of the output signal of the gate driving circuit.

[0004] In a first aspect, a gate driving circuit is provided, the gate driving circuit comprising: an input circuit for receiving a cascaded signal sent by a previous gate driving circuit cascaded with the gate driving circuit, and charging a pull-up node of the gate driving circuit according to the cascaded signal; a pull-down circuit connected to a gate low voltage for pulling down the voltage of the pull-down node of the gate driving circuit according to the gate low voltage under the control of the voltage of the pull-up node; an output circuit comprising at least two drive output transistors and a bootstrap capacitor, the at least two drive output transistors being respectively connected to at least two gate lines in a display panel, the at least two drive output transistors being respectively used to receive corresponding clock signals, and outputting the corresponding clock signals as drive signals under the control of the voltage of the pull-up node; and a boost circuit comprising a boost capacitor for continuously charging the pull-up node under the control of the output signal of the output circuit, so as to maintain the voltage of the pull-up node at an effective voltage, wherein the ratio between the bootstrap capacitor and the boost capacitor is set within a predetermined range.

[0005] The gate driving circuit provided in this application includes an input circuit, a pull-down circuit, an output circuit, and a boost circuit. The boost circuit includes a boost capacitor to maintain the voltage of the pull-up node at a high level, thereby reducing the falling time of the output signal of the driving output transistor in the output circuit. The output circuit also includes a bootstrap capacitor, which improves the driving range. By setting the ratio between the bootstrap capacitor and the boost capacitor in the boost circuit within a predetermined range, the amplitude of the output signals of each stage of the driving output transistor is made consistent, and the falling time of the output signal of the last stage driving output transistor is reduced. This effectively improves the waveform consistency of the output signals of each stage of the driving output transistor in the output circuit, thus improving the display effect of the display panel.

[0006] For example, the ratio between the bootstrap capacitor and the boost capacitor is set between 0.5 and 1. This ensures that the amplitude difference of the output signals of each stage of the drive output transistor is less than 5%, and that the fall time difference between the output signals of the first-stage drive output transistor and the last-stage drive output transistor is less than 0.13 microseconds, thereby effectively improving the waveform consistency of the output signals of each stage of the drive output transistor in the output circuit.

[0007] In some possible implementations, the bootstrap capacitor is connected between the control terminal and the first current terminal of any one of the at least two drive output transistors, the first current terminal of the drive output transistor is connected to the corresponding output terminal, and the second current terminal of the drive output transistor is connected to the corresponding clock signal.

[0008] In this implementation, the bootstrap capacitor can be connected between the control terminal and the power supply terminal of any drive output transistor, without the need for additional transistors, thereby reducing the number of components and facilitating the achievement of a narrow bezel effect for the display panel.

[0009] In some possible implementations, the output circuit further includes a cascaded output transistor, which receives a corresponding clock signal and outputs the corresponding clock signal as a cascaded signal under the control of the voltage of the pull-up node. The bootstrap capacitor is connected to the control terminal and the first current terminal of the cascaded output transistor, the first current terminal of the cascaded output transistor is connected to the corresponding output terminal, and the second current terminal of the cascaded output transistor is connected to the corresponding clock signal.

[0010] In this implementation, additional cascaded output transistors can be added, and a bootstrap capacitor can be connected between the control terminal and the current terminal of the cascaded output transistors. This ensures that the circuit structure of each stage of the drive output transistors is consistent, without affecting the overall circuit structure, resulting in more balanced and stable functionality. This also helps improve the waveform consistency of the output signals from each stage of the drive output transistors.

[0011] In some possible implementations, the input circuit includes a first transistor, which may be one or two, with the control terminal of the first transistor connected to the input terminal of the input circuit, and the two current terminals of the first transistor connected in series between the input terminal of the input circuit and the pull-up node.

[0012] In some possible implementations, the first transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage used to adjust the threshold voltage of the first transistor.

[0013] In some possible implementations, the gate drive circuit further includes a first voltage regulator circuit for charging the short-circuited current terminals of the two first transistors under the control of the voltage of the pull-up node, so as to maintain the voltage of the pull-up node at an effective voltage. The first voltage regulator circuit includes a second transistor, the control terminal of which is connected to the pull-up node, the first current terminal of which is connected to the corresponding power supply voltage, and the second current terminal of which is connected to the short-circuited current terminals of the two first transistors.

[0014] In this implementation, both transistors connected in series in the input circuit are connected to the pull-up node. When the pull-up node is at a high level, both transistors are in an off state. The leakage current generated by the two off-state transistors is less than the leakage current generated by a single transistor in an off state. This design can maintain the high-level state of the pull-up node more stably. Since the gate drive circuit also includes a first voltage regulator circuit, which is connected to the pull-up node and to the short-circuited current terminals of the two series transistors, it can suppress current leakage along the series transistors when the pull-up node is at a high level, further stabilizing the voltage of the pull-up node.

[0015] In some possible implementations, the gate drive circuit further includes a second voltage regulator circuit connected between the corresponding power supply voltage and the pull-down node. The number of the second voltage regulator circuits is one or two. When there are two second voltage regulator circuits, the two second voltage regulator circuits are used to alternately control the voltage of their respective connected pull-down nodes according to the power supply voltage they are connected to.

[0016] Optionally, the second voltage regulator circuit includes a third transistor, the control terminal and the first current terminal of the third transistor are connected to the corresponding power supply voltage, and the second current terminal of the third transistor is connected to the corresponding pull-down node.

[0017] In some possible implementations, the gate drive circuit further includes an auxiliary control circuit connected to the second voltage regulator circuit, for pulling down the voltage of the pull-up node according to the low gate voltage under the control of the voltage of the pull-down node of the second voltage regulator circuit.

[0018] Optionally, the auxiliary control circuit includes one or two groups of transistors, each group of transistors including one or two fourth transistors, the control terminal of the fourth transistor is connected to the pull-down node corresponding to the second voltage regulator circuit, and the two current terminals of the fourth transistor are connected in series between the gate low voltage and the pull-up node.

[0019] In some possible implementations, the fourth transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage used to adjust the threshold voltage of the fourth transistor.

[0020] In some possible implementations, the gate drive circuit further includes a first voltage regulator circuit for charging the short-circuited current terminals of the one or two fourth transistors under the control of the voltage of the pull-up node, so as to maintain the voltage of the pull-up node at an effective voltage. The first voltage regulator circuit includes a second transistor, the control terminal of which is connected to the pull-up node, the first current terminal of which is connected to the corresponding power supply voltage, and the second current terminal of which is connected to the short-circuited current terminals of the one or two fourth transistors.

[0021] In this implementation, both transistors connected in series in the auxiliary control circuit are connected to the pull-up node. When the pull-up node is at a high level, both transistors are in an off state. The leakage current generated by the two off-state transistors is less than the leakage current generated by a single transistor in an off state. This design can maintain the high-level state of the pull-up node more stably. Since the gate drive circuit also includes a first voltage regulator circuit, which is connected to the pull-up node and to the short-circuited current terminals of the two on-state transistors, it can suppress current leakage along the on-state transistors when the pull-up node is at a high level, further stabilizing the voltage of the pull-up node.

[0022] In some possible implementations, the gate drive circuit further includes an auxiliary pull-down circuit connected to the second voltage regulator circuit, used to set the voltage of the pull-down node corresponding to the second voltage regulator circuit to a gate low voltage according to the cascaded signal.

[0023] Optionally, the auxiliary pull-down circuit includes a fifth transistor, the first current terminal of the fifth transistor is connected to the pull-down node corresponding to the second voltage regulator circuit, the second current terminal of the fifth transistor is connected to the gate low voltage, and the control terminal of the fifth transistor is connected to the input terminal of the input circuit.

[0024] In some possible implementations, the gate drive circuit further includes an output pull-down circuit connected to the cascaded output transistors and each drive output transistor, wherein the output pull-down circuit includes one or two sixth transistors, and in the case where the pull-down circuit includes two sixth transistors, the control terminals of the two sixth transistors are respectively connected to the corresponding pull-down nodes, the first current terminal of the sixth transistor is connected to the corresponding output terminal, and the second current terminal of the sixth transistor is connected to the gate turn-off voltage.

[0025] In some possible implementations, the pull-down circuit includes a seventh transistor, the number of which is one or two. The control terminal of the seventh transistor is connected to the pull-up node, the first current terminal of the seventh transistor is connected to the pull-down node, and the second current terminal of the seventh transistor is connected to the gate low voltage.

[0026] In some possible implementations, the gate drive circuit further includes a first reset circuit and a second reset circuit. The first reset circuit includes an eighth transistor, which may be one or two. The control terminal of the eighth transistor is connected to a first reset signal, and the two current terminals of the eighth transistor are connected in series between the gate low voltage and the pull-up node. The second reset circuit includes a ninth transistor, which may be one or two. The control terminal of the ninth transistor is connected to a second reset signal, and the two current terminals of the ninth transistor are connected in series between the gate low voltage and the pull-up node.

[0027] In some possible implementations, the eighth transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage used to adjust the threshold voltage of the eighth transistor; and / or, the ninth transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage used to adjust the threshold voltage of the ninth transistor.

[0028] In some possible implementations, the gate drive circuit further includes a first voltage regulator circuit for charging the short-circuited current terminals of the two eighth transistors and / or the short-circuited current terminals of the two ninth transistors under the control of the voltage of the pull-up node, so as to maintain the voltage of the pull-up node at an effective voltage. The first voltage regulator circuit includes a second transistor, the control terminal of which is connected to the pull-up node, the first current terminal of which is connected to the corresponding power supply voltage, and the second current terminal of which is connected to the short-circuited current terminals of the two eighth transistors and / or the short-circuited current terminals of the two ninth transistors.

[0029] In this implementation, both transistors connected in series in the first and second reset circuits are connected to the pull-up node. When the pull-up node is at a high level, both transistors are in an off state. The leakage current generated by the two off-state transistors is less than the leakage current generated by a single transistor in an off state. This design can maintain the high-level state of the pull-up node more stably. Since the gate drive circuit also includes a first voltage regulator circuit, which is connected to the pull-up node and to the short-circuited current terminals of the two series transistors, it can suppress current leakage along the series transistors when the pull-up node is at a high level, further stabilizing the voltage of the pull-up node.

[0030] In a second aspect, a display panel is provided, including the gate driving circuit described in the first aspect or any possible implementation thereof.

[0031] Thirdly, a display device is provided, comprising the display panel described in the second aspect or any possible implementation thereof. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a gate driving circuit according to an embodiment of this application.

[0034] Figure 2 This is a schematic diagram of another gate driving circuit according to an embodiment of this application.

[0035] Figure 3 This is a schematic diagram of another gate driving circuit according to an embodiment of this application.

[0036] Figure 4 This is a schematic diagram of another gate driving circuit according to an embodiment of this application.

[0037] Figure 5 This is a schematic diagram of the cascaded gate drive circuit according to an embodiment of this application.

[0038] Figure 6 This is a schematic diagram of the signal timing and waveform of a gate driving circuit according to an embodiment of this application.

[0039] Figure 7 This is another signal timing and waveform diagram of the gate drive circuit according to an embodiment of this application.

[0040] Figure 8 This is a comparative schematic diagram of the signal timing and waveforms of the gate drive circuit in an embodiment of this application. Detailed Implementation

[0041] The embodiments of this application will be described in further detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of this application by way of example, but should not be used to limit the scope of this application, that is, this application is not limited to the described embodiments.

[0042] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and other forms such as the third-person singular "comprises" and the present participle "comprising" are interpreted as open and inclusive, meaning "including, but not limited to." In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the foregoing terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be included in any suitable manner in any of the embodiments or examples.

[0043] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0044] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structures in the embodiments of this application. It should also be noted in the description of the embodiments of this application that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] In this application, the term "embodiment" is used to mean that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. Those skilled in the art will explicitly and implicitly understand that the embodiments described in this application can be combined with other embodiments.

[0046] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0047] In addition, the use of “based on” implies openness and inclusivity, because a process, step, calculation or other action “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0048] The terms “about,” “approximately,” or “approximately” used in this application embodiment include the stated value and the average value within an acceptable deviation range of a particular value, wherein the acceptable deviation range is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity, i.e., the limitations of the measurement system.

[0049] GOA circuits can typically use a 1-to-N scheme, meaning one GOA circuit supports the signals required for N gate rows. The output circuit in the GOA circuit includes N levels of drive output transistors. The differences in the waveforms of the output signals of the N levels of drive output transistors may affect the display effect of the display panel.

[0050] Therefore, this application provides a GOA circuit, hereinafter also referred to as a gate drive circuit or shift register, which improves the consistency of the output signal waveform of each stage of the output transistor in the output circuit and improves the display effect of the display panel by setting a bootstrap capacitor in the output circuit and adjusting the ratio between the bootstrap capacitor and the boost capacitor in the boost circuit.

[0051] Figure 1 A gate drive circuit 100 provided in an embodiment of this application is shown. The gate drive circuit 100 is, for example, a GOA circuit. Figure 1 As shown, the gate drive circuit 100 includes an input circuit 110, a pull-down circuit 120, an output circuit 130, and a boost circuit 140. The input circuit 110 receives a cascaded signal from the previous gate drive circuit 100 cascaded with it, and charges the pull-up node (PU) of the gate drive circuit 100 according to the cascaded signal.

[0052] Pull-down circuit 120 is connected to the gate low voltage and is used to pull down the voltage of the pull-down node (PD) of gate drive circuit 100 according to the gate low voltage under the control of the voltage of pull-up node PU. Hereinafter, gate low voltage is the low level of gate low voltage (VGL), which can be set to be equal to VGL voltage.

[0053] The output circuit 130 includes at least two drive output transistors and a bootstrap capacitor Cz. The at least two drive output transistors are respectively connected to at least two gate lines in the display panel. The at least two drive output transistors are respectively used to receive corresponding clock signals and, under the control of the voltage of the pull-up node PU, output the corresponding clock signals as drive signals based on the corresponding clock signals.

[0054] in, Figure 1 Taking four drive output transistors as an example, i.e., a 1-to-4 gate drive circuit 100, it is also applicable to other 1-to-N architectures such as 1-to-2, 1-to-3, 1-to-5, etc. Figure 1The at least two drive output transistors shown include transistors M3A, M3B, M3C, and M3D, which are used to receive clock signals CLK1, CLK3, CLK5, and CLK7, respectively, and output corresponding drive signals OUT1, OUT2, OUT3, and OUT4. Transistors M3A, M3B, M3C, and M3D can be connected to the gate line G in the display panel. n Gate line G n+3 Gate line G n+5 and gate line G n+7 For the final stage gate drive circuit, the output terminal of the drive output transistor can be floating.

[0055] The boost circuit 140 includes a boost capacitor Cb, which is used to continuously charge the pull-up node PU under the control of the output signal of the output circuit 130, so that the voltage of the pull-up node PU is maintained at an effective voltage.

[0056] In other words, the boost capacitor Cb is a capacitor that compensates for the voltage of the pull-up node PU, making the voltage of the pull-up node PU more stable and with less fluctuation. For example, as... Figure 1 As shown, one end of the boost capacitor Cb can be connected to a high level (boost), and the other end can be connected to the pull-up node PU. This allows the pull-up node PU to be charged directly based on the high level, making the voltage of the pull-up node PU stably close to or equal to the high level.

[0057] Alternatively, a compensation transistor may be provided in the boost circuit 140, or a compensation transistor may be provided with an anti-reverse current diode added between the compensation transistor and the pull-up node. The control terminal and the first power supply terminal of the compensation transistor may be connected to the second power supply terminal of the cascaded output transistor, and the second power supply terminal of the compensation transistor may be connected to the pull-up node PU; alternatively, the control terminal of the compensation transistor may be connected to the clock signal output by the cascaded output transistor, the first power supply terminal may be connected to a high level, and the second power supply terminal may be connected to the pull-up node PU.

[0058] In the gate drive circuit 100 provided in this embodiment, a boost capacitor Cb is provided in the boost circuit 140 to maintain the voltage of the pull-up node PU at a high level, thereby reducing the falling time T of the output signal driving the output transistor in the output circuit 130. f The output circuit 130 also includes a bootstrap capacitor Cz, which improves the driving range of the gate drive circuit 100.

[0059] Furthermore, in this embodiment, the ratio between the bootstrap capacitor Cz and the boost capacitor Cb, i.e., Cz / Cb, is set within a predetermined range, thereby ensuring that the amplitudes of the output signals of each stage of the drive output transistors are consistent and reducing the fall time T of the output signal of the last stage drive output transistor. f This effectively improves the waveform consistency of the output signals of each stage of the drive output transistors in the output circuit 130, and improves the display effect of the display panel.

[0060] For example, the ratio between the bootstrap capacitor Cz and the boost capacitor Cb can be set between 0.5 and 1. This ensures that the amplitude difference of the output signals of each stage of the drive output transistor is small, for example, less than 5%, and that the fall time T of the output signals of the first stage drive output transistor and the last stage drive output transistor is similar. f The phase difference is small, for example, less than 0.13 microseconds, thereby effectively improving the consistency of the waveform of the output signal of each stage of the drive output transistor in the output circuit 130.

[0061] The bootstrap capacitor Cz can have the following two connection methods. In one implementation, for example, as shown... Figure 1 As shown, the output circuit 130 also includes a cascaded output transistor M11. The cascaded output transistor M11 receives the corresponding clock signal CLK_C and, under the control of the voltage of the pull-up node PU, outputs the corresponding clock signal CLK_C as a cascaded signal OUT_C, thereby transmitting it to the input circuit of the next-stage gate drive circuit. If there is no next-stage gate drive circuit, the output terminal of the cascaded output transistor M11 can be floating. In this case, a bootstrap capacitor Cz can be connected between the control terminal and the first current terminal of the cascaded output transistor M11. The first current terminal of the cascaded output transistor M11 is connected to the corresponding output terminal, and the second current terminal of the cascaded output transistor M11 is connected to the corresponding clock signal.

[0062] By adding an additional cascaded output transistor M11 and connecting the bootstrap capacitor Cz between the control and current terminals of M11, the circuit structure of each stage of the drive output transistors remains consistent, resulting in a more balanced and stable function. This improves the waveform consistency of the output signals from each stage. Furthermore, since the bootstrap capacitor Cz is only connected to the cascaded output transistor M11 and does not need to be connected to each individual drive output transistor, it is more conducive to achieving a narrow bezel effect.

[0063] In another implementation, for example, such as Figure 2As shown, in some cases, such as when the cascaded output transistor M11 is not set, the bootstrap capacitor Cz can be connected between the control terminal and the first current terminal of any one of the at least two drive output transistors, such as the first-stage drive transistor. The first current terminal of the drive output transistor is connected to the corresponding output terminal, and the second current terminal of the drive output transistor is connected to the corresponding clock signal. In this way, since it is not necessary to set up additional transistors, the number of components is reduced, which is beneficial to achieving the effect of a narrow bezel on the display panel.

[0064] Optionally, the clock signal CLK_C can be the same as or different from the clock signal CLK_1.

[0065] Since it is no longer necessary to provide a bootstrap capacitor at each of the driving output transistors in each stage of the output circuit 130, but only one bootstrap capacitor Cz is provided in the output circuit 130, this bootstrap capacitor Cz can be connected to any driving output transistor, such as transistor M13A, or connected to the cascaded output transistor M11, thereby reducing the number of capacitors and facilitating the achievement of a narrow bezel effect. Furthermore, by setting the ratio between the bootstrap capacitor Cz and the boost capacitor Cb within an appropriate range, the waveform consistency of the output driving signals at each stage can be improved.

[0066] It is understood that the transistors described in the embodiments of this application can be either P-type or N-type, and include a gate (G), a source (S), and a drain (D). The gate is referred to as the control terminal, and the source and drain are referred to as current terminals. For example, the first current terminal is the source, and the second current terminal is the drain; or, the first current terminal is the drain, and the second current terminal is the source. The transistors in the embodiments of this application include, but are not limited to, thin-film transistors (TFTs).

[0067] In some embodiments, such as Figure 1 As shown, the input circuit 110 includes a first transistor, and the number of the first transistors is one or two. Figure 1 Taking the input circuit 110, which includes two first transistors, namely transistor M1A and transistor M1B, as an example, Figure 3 Taking the input circuit 110 as an example, which includes a first transistor, namely transistor M1A. The control terminal of the first transistor is connected to the input terminal Input of the input circuit 110, and the two current terminals of the first transistor are connected in series between the input terminal Input of the input circuit 110 and the pull-up node PU.

[0068] In some embodiments, the gate drive circuit 100 further includes a second voltage regulator circuit 160, which is connected between the corresponding power supply voltage and the pull-down node PD. The number of second voltage regulator circuits 160 is one or two. When there are two second voltage regulator circuits 160, the two second voltage regulator circuits 160 are used to alternately control the voltage of their respective connected pull-down nodes PD according to their respective connected power supply voltages. Figure 1 Taking the gate drive circuit 100 including two second voltage regulator circuits 160 as an example, one of the two second voltage regulator circuits 160 is connected between the power supply voltage VDD_A and the pull-down node PD_A, and the other is connected between the power supply voltage VDD_B and the pull-down node PD_B. The power supply voltages VDD_A and VDD_B are the input voltages of the pull-down node PD, and they can be input alternately based on a set period. VDD_A and VDD_B can, for example, be equal to the voltage of gate high (VGH).

[0069] Optionally, the second voltage regulator circuit 160 includes a third transistor, the control terminal and the first current terminal of the third transistor are connected to the corresponding power supply voltage, and the second current terminal of the third transistor is connected to the corresponding pull-down node PD.

[0070] For example, such as Figure 1 As shown, the second voltage regulator circuit 160 includes two third transistors, namely transistor M5A and transistor M5B. The control terminals and first current terminals of transistors M5A and M5B are respectively connected to the power supply voltage VDD_A and the power supply voltage VDD_B. The second current terminals of transistors M5A and M5B are respectively connected to the pull-down node PD_A and the pull-down node PDB.

[0071] In some embodiments, the pull-down circuit 120 includes a seventh transistor, the number of which is one or two. The control terminal of the seventh transistor is connected to the pull-up node PU, the first current terminal of the seventh transistor is connected to the pull-down node PD, and the second current terminal of the seventh transistor is connected to the gate low voltage LVGL. For example, as Figure 1 As shown, the pull-down circuit 120 includes two seventh transistors, namely transistor M6A and transistor M6B.

[0072] In some embodiments, the gate drive circuit 100 further includes an auxiliary control circuit 180 connected to the second voltage regulator circuit 160, for pulling down the voltage of the pull-up node PU according to the gate low voltage LVGL under the control of the voltage of the pull-down node PD corresponding to the second voltage regulator circuit 160.

[0073] Optionally, the auxiliary control circuit 180 includes one or two groups of transistors, each group of transistors including one or two fourth transistors. The control terminal of the fourth transistor is connected to the pull-down node PD corresponding to the second voltage regulator circuit 160, and the two current terminals of the fourth transistor are connected in series between the gate low voltage LVGL and the pull-up node PU.

[0074] When there is one second voltage regulator circuit 160, one auxiliary control circuit 180 can be set; when there are two second voltage regulator circuits 160, two corresponding auxiliary control circuits 180 can be set.

[0075] like Figure 1 As shown, each auxiliary control circuit 180 includes a set of transistors. One auxiliary control circuit 180 includes two fourth transistors, namely transistors M8A1 and M8A2. The control terminals of transistors M8A1 and M8A2 are connected to the pull-down node PD_A. Transistors M8A1 and M8A2 are connected in series between the pull-up node PU and the gate low voltage LVGL. Another auxiliary control circuit 180 includes two fourth transistors, namely transistors M8B1 and M8B2. The control terminals of transistors M8B1 and M8B2 are connected to the pull-down node PD_B. Transistors M8B1 and M8B2 are connected in series between the pull-up node PU and the gate low voltage LVGL. Of course, as... Figure 3 As shown, each of the two auxiliary control circuits 180 may include only one fourth transistor, namely transistor M8A1 and transistor M8B1 respectively.

[0076] In some embodiments, the gate drive circuit 100 further includes an auxiliary pull-down circuit 190 connected to the second voltage regulator circuit 160, for setting the voltage of the pull-down node PD corresponding to the second voltage regulator circuit 160 to the gate low voltage LVGL according to the cascade signal.

[0077] Optionally, the auxiliary pull-down circuit 190 includes a fifth transistor. The first current terminal of the fifth transistor is connected to the pull-down node PD corresponding to the second voltage regulator circuit 160, the second current terminal of the fifth transistor is connected to the gate low voltage LVGL, and the control terminal of the fifth transistor is connected to the input terminal Input of the input circuit 110.

[0078] When there is only one second voltage regulator circuit 160, one auxiliary pull-down circuit 190 can be set; when there are two second voltage regulator circuits 160, two corresponding auxiliary pull-down circuits 190 can be set.

[0079] like Figure 1As shown, each of the two auxiliary pull-down circuits 190 includes a fifth transistor, namely transistor M7A and transistor M7B. The first current terminals of transistors M7A and M7B are connected to pull-down nodes PD_A and PD_B, respectively. The second current terminals of transistors M7A and M7B are connected to the gate low voltage LVGL. The control terminals of transistors M7A and M7B are connected to the input terminal Input of input circuit 110.

[0080] In some embodiments, the gate drive circuit 100 further includes a first reset circuit 171 and a second reset circuit 172. The first reset circuit 171 includes an eighth transistor, which may be one or two. The control terminal of the eighth transistor is connected to the first reset signal Reset, and the two current terminals of the eighth transistor are connected in series between the gate low voltage LVGL and the pull-up node PU.

[0081] The second reset circuit 172 includes a ninth transistor, which can be one or two. The control terminal of the ninth transistor is connected to the second reset signal, and the two current terminals of the ninth transistor are connected in series between the gate low voltage LVGL and the pull-up node PU. The second reset signal can be, for example, the discharge signal of all pull-up nodes of the gate drive circuit, i.e., the total reset signal total reset(T_Reset).

[0082] For example, such as Figure 1 As shown, the first reset circuit 171 includes two fifth transistors, namely transistor M2A and transistor M2B, and the second reset circuit 172 includes two fifth transistors, namely transistor M15A and transistor M15B. The control terminals of transistors M2A and M2B are connected to the first reset signal Reset, and transistors M2A and M2B are connected in series between the gate low voltage LVGL and the pull-up node PU. The control terminals of transistors M15A and M15B are connected to the second reset signal T_Reset, and transistors M15A and M15B are connected in series between the gate low voltage LVGL and the pull-up node PU. Of course, as... Figure 3 As shown, the first reset circuit 171 and the second reset circuit 172 may each include only one fifth transistor, namely transistor M2A and transistor M15A, respectively.

[0083] In the aforementioned input circuit 110, auxiliary control circuit 180, first reset circuit 171, and second reset circuit 172, when a single transistor is used, it is necessary to ensure that the transistor's threshold voltage Vth is greater than 0, and optionally, as shown... Figure 3As shown, the first voltage regulator circuit 150 can be omitted because the leakage current generated by a single transistor in the off state is small. When two transistors are used, the active layers of both transistors are connected in series. For example, when two transistors are used, the first power supply terminal of transistor M1A in the input circuit 110 is connected in series with the second power supply terminal of transistor M1B; the first power supply terminal of transistor M8A1 in the auxiliary control circuit 180 is connected in series with the second power supply terminal of transistor M8A2, and the first power supply terminal of transistor M8B1 is connected in series with the second power supply terminal of transistor M8B2; the first power supply terminal of transistor M2A in the first reset circuit 171 is connected in series with the second power supply terminal of transistor M2B; and the first power supply terminal of transistor M15A in the second reset circuit 172 is connected in series with the second power supply terminal of transistor M15B.

[0084] These series-connected transistors are all connected to the pull-up node PU. When the pull-up node PU is in a high-level state, both series-connected transistors are in an open state. The leakage current generated by the two series-connected transistors in an open state is less than the leakage current generated by a single transistor in an open state. This design can keep the high-level state of the pull-up node PU more stable.

[0085] Furthermore, the gate drive circuit 100 is further provided with a first voltage regulator circuit 150, which is used to charge the phase-short-circuited current terminals of the series-connected transistors under the control of the voltage of the pull-up node PU, so as to maintain the voltage of the pull-up node PU at an effective voltage. The first voltage regulator circuit 150 includes a second transistor, the control terminal of which is connected to the pull-up node PU, the first current terminal of which is connected to the corresponding power supply voltage, and the second current terminal of which is connected to the phase-short-circuited current terminals of the series-connected transistors.

[0086] Since the gate drive circuit 100 is provided with a first voltage regulator circuit 150, which is connected to the pull-up node PU and to the short-circuited current terminal of the two series transistors mentioned above, it can suppress the current leakage of the pull-up node PU along the series transistors when the pull-up node PU is in a high-level state, and further stabilize the voltage of the pull-up node PU.

[0087] like Figure 1As shown, the first voltage regulator circuit 150 includes a second transistor, namely transistor M0. The control terminal of transistor M0 is connected to the pull-up node PU, and the first current terminal of transistor M0 is connected to the power supply voltage VDDi, where the power supply voltage VDDi is the input signal for the leakage current, and can be equal to the gate high voltage VGH, for example. The second current terminal of transistor M0 is connected to the short-circuited current terminals of the aforementioned series-connected transistors, for example, the short-circuited current terminals of transistors M1A and M1B in the input circuit 110; the short-circuited current terminals of transistors M8A1 and M8A2, and transistors M8B1 and M8B2 in the auxiliary control circuit 180; the short-circuited current terminals of transistors M2A and M2B in the first reset circuit 171; and the short-circuited current terminals of transistors M15A and M15B in the second reset circuit 172.

[0088] When the pull-up node PU is in a high-level state, transistor M0 is turned on. The voltage at the short-circuited current terminals of the two series-connected transistors is set to the power supply voltage VDDi. This prevents the pull-up node PU from discharging positive charge along the short-circuited current terminals of these series-connected transistors, maintaining the stability of the pull-up node PU's level and improving the display effect. It is understandable that even when these series-connected transistors are in the off state, there may still be a slight current leakage.

[0089] In some embodiments, the input circuit 110, auxiliary control circuit 180, first reset circuit 171, and second reset circuit 172 described above may employ transistors with dual-gate structures. For example, the first transistor in the input circuit 110 may be a dual-gate structure, i.e., the first transistor includes two control terminals, namely a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal Input of the input circuit 110, and the second control terminal is connected to a specific power supply voltage VDDN, which is used to adjust the threshold voltage Vth of the first transistor; as another example, the fourth transistor in the auxiliary control circuit 180 may be a dual-gate structure, i.e., the fourth transistor includes two control terminals, namely a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal Input of the input circuit 110, and the second control terminal is connected to a specific power supply voltage VDDN, which is used to adjust the threshold voltage Vth of the fourth transistor; For example, the eighth transistor in the first reset circuit 171 can be a dual-gate structure, that is, the eighth transistor includes two control terminals, namely a first control terminal and a second control terminal. The first control terminal is connected to the input terminal Input of the input circuit 110, and the second control terminal is connected to a specific power supply voltage VDDN. The specific power supply voltage is used to adjust the threshold voltage Vth of the eighth transistor. For example, the ninth transistor in the second reset circuit 172 can be a dual-gate structure, that is, the ninth transistor includes two control terminals, namely a first control terminal and a second control terminal. The first control terminal is connected to the input terminal Input of the input circuit 110, and the second control terminal is connected to a specific power supply voltage VDDN. The specific power supply voltage is used to adjust the threshold voltage Vth of the ninth transistor.

[0090] Figure 4 This illustrates a case where only one transistor is used in the input circuit 110, auxiliary control circuit 180, first reset circuit 171, and second reset circuit 172, and that transistor has a dual-gate structure. Figure 4 As shown, transistor M1A in input circuit 110, transistors M8A and M8B in two auxiliary control circuits 180, transistor M2A in first reset circuit 171, and transistor M15A in second reset circuit 172 all have two gates. The bottom gate can be connected to the power supply voltage VDDN, thereby adjusting the threshold voltage Vth of these transistors and ensuring the threshold voltage variation margin (Vth margin) of these transistors.

[0091] In some embodiments, the gate drive circuit 100 further includes an output pull-down circuit 131 connected to the cascaded output transistor M11 and each output transistor, wherein the output pull-down circuit 131 includes one or two sixth transistors, and when the pull-down circuit 120 includes two sixth transistors, the control terminals of the two sixth transistors are respectively connected to the corresponding pull-down nodes PD, the first current terminal of the sixth transistor is connected to the corresponding output terminal, and the second current terminal of the sixth transistor is connected to the gate turn-off voltage VGL.

[0092] For example, such as Figures 1 to 4 As shown, the output terminals of the cascaded output transistors M11, M3A, M3B, M3C, and M3D—that is, the power supply terminals corresponding to the drive signals OUT_C, OUT1, OUT2, OUT3, and OUT4—are each connected to two sixth transistors. Specifically, the control terminals of the two sixth transistors corresponding to the cascaded output transistor M11—transistors M12A and M12B—are connected to the pull-down nodes PD_A and PD_B, respectively. Their first current terminals are connected to the output terminal of the corresponding drive signal OUT_C, and their second current terminals are connected to the gate turn-off voltage VGL. Similarly, the control terminals of the two sixth transistors corresponding to the drive output transistor M3A—transistors M13A1 and M13B1—are connected to the pull-down nodes PD_A and PD_B, respectively. Their first current terminals are connected to the output terminal of the corresponding drive signal OUT_1, and their second current terminals are connected to the gate turn-off voltage VGL. Finally, the control terminals of the two sixth transistors corresponding to the drive output transistor M3B—transistors M13A2 and M13B2—are connected to the pull-down nodes... For PD_A and pull-down nodes PD_B, the first current terminal is connected to the output terminal of the corresponding drive signal OUT_2, and the second current terminal is connected to the gate turn-off voltage VGL. The control terminals of the two sixth transistors corresponding to the drive output transistor M3C, namely transistors M13A3 and M13B3, are connected to the pull-down nodes PD_A and PD_B, respectively. The first current terminal is connected to the output terminal of the corresponding drive signal OUT_3, and the second current terminal is connected to the gate turn-off voltage VGL. The control terminals of the two sixth transistors corresponding to the drive output transistor M3D, namely transistors M13A4 and M13B4, are connected to the pull-down nodes PD_A and PD_B, respectively. The first current terminal is connected to the output terminal of the corresponding drive signal OUT_4, and the second current terminal is connected to the gate turn-off voltage VGL.

[0093] In this embodiment, for the gate drive circuit composed of N-type transistors, both the gate low voltage LVGL and the gate turn-off voltage VGL are low-level signals, for example, less than or equal to 0V. The power supply voltages VDD_A, VDD_B, and VDDi are all high-level signals.

[0094] The power supply voltages VDD_A, VDD_B, and VDDi are all optional settings. For example, VDD_B can be left unset, meaning only a second voltage regulator circuit 160 is configured, and VDD_A is set to be equal to VDDi. Alternatively, only VDD_A can be set, meaning VDDi is not set, i.e., the first voltage regulator circuit 150 is not configured, and VDD_B is also not set, i.e., only a second voltage regulator circuit 160 is configured.

[0095] Figures 1 to 4 A gate drive circuit 100 in a multi-stage gate drive circuit is shown. Figure 5 The cascading relationship of multiple gate drives is shown. In Figure 5 In this configuration, odd and even rows are driven independently, and two cascaded gate drive circuits are used to provide drive signals for the odd and even gate lines, respectively. Figure 5 The diagram shows a 24-clock (24CLK) architecture, where each gate drive circuit consists of four cascaded gate drive circuits forming a loop. These four cascaded gate drive circuits can be simultaneously reset using a second reset signal T_Reset. Each of the four gate drive circuits is a 1-to-4 structure. The cascaded signal OUT_C ​​output by the cascaded output transistor in the output circuit of the previous stage gate drive circuit is transmitted to the input terminal Input of the input circuit 110 of the next stage gate drive circuit.

[0096] The above combination Figures 1 to 5 The possible circuit structure of the gate drive circuit 100 according to an embodiment of this application is described below. Hereinafter, in conjunction with... Figures 6 to 8 The application describes in detail the signal timing and signal waveforms of the gate drive circuit 100 in the embodiments of this application.

[0097] based on Figure 1 In the gate drive circuit 100 shown, in step S1, before the input terminal receives the cascaded signal, transistors M5A, M8A1, M8A2, M12A, M13A1, M13A2, M13A3, and M13A4 are turned on, while other transistors are turned off.

[0098] In step S2, a start voltage (STV) signal is input. At this time, transistors M1A, M1B, M0, M5A, M6A, M6B, M7A, and M7B are turned on, while the other transistors are turned off.

[0099] In step S3, the input clock signal CLK1 is applied. At this time, the STV signal, the cascaded signal at the input terminal, and the gate turn-off signal VGL are equal. Transistors M0, M5A, M6A, M6B, M11, and M3A are turned on, while the other transistors are turned off.

[0100] In step S4, clock signal CLK3 is input. At this time, clock signal CLK1 is continuously input and equal to the gate high voltage VGH. Transistors M0, M5A, M6A, M6B, M11, M3A, and M3B are turned on, while other transistors are turned off.

[0101] In step S5, clock signal CLK5 is input. At this time, clock signals CLK1 and CLK3 are continuously input and are equal to the gate high voltage VGH. Transistors M0, M5A, M6A, M6B, M11, M3A, M3B, and M3C are turned on, while other transistors are turned off.

[0102] In step S6, clock signal CLK7 is input. At this time, clock signals CLK1, CLK3, and CLK5 are continuously input and are equal to the gate high voltage VGH. Transistors M0, M5A, M6A, M6B, M11, M3A, M3B, M3C, and M3D are turned on, while other transistors are turned off.

[0103] In step S7, clock signal CLK1 is the gate turn-off voltage VGL, and clock signals CLK3, CLK5, and CLK7 are continuously input and equal to the gate high voltage VGH. Transistors M0, M5A, M6A, M6B, M3B, M3C, and M3D are turned on, while other transistors are turned off.

[0104] In step S8, clock signal CLK3 is the gate turn-off voltage VGL, and clock signals CLK5 and CLK7 are continuously input and equal to the gate high voltage VGH. Transistors M0, M5A, M6A, M6B, M3C, and M3D are turned on, while other transistors are turned off.

[0105] In step S9, clock signal CLK5 is the gate turn-off voltage VGL, clock signal CLK7 is continuously input and equal to the gate high voltage VGH. Transistors M0, M5A, M6A, M6B, and M3D are turned on, and the other transistors are turned off.

[0106] In step S10, the clock signal CLK7 is the gate turn-off voltage VGL. Transistors M0, M5A, M6A, and M6B are turned on, while the other transistors are turned off.

[0107] In step S11, a reset is performed. Transistors M5A, M8A1, M8A2, M12A, M2A, M2B, M12A, M13A1, M13A2, M13A3, and M13A4 are turned on, while the other transistors are turned off.

[0108] Based on this control logic, the following can be obtained: Figure 6 The timing and waveform changes of each signal in the gate drive circuit 100 shown.

[0109] Figure 7 The voltage changes of the pull-up node PU, drive signals OUT1, OUT2, OUT3, and OUT4 are shown. Calculations show that the amplitude voltage Vgout of drive signals OUT1, OUT2, OUT3, and OUT4 is equal, all equal to 14V. Here, amplitude voltage Vgout refers to the difference between the minimum and maximum values ​​of the signal. The maximum difference ΔVgmax between the amplitude voltages Vgout1, Vgout2, Vgout3, and Vgout4 of each drive signal OUT1, OUT2, OUT3, and OUT4 is always approximately 0V. Furthermore, the fall time Tf1 of drive signal OUT1 is 0.521 microseconds, the fall time Tf4 of drive signal OUT4 is 0.597 microseconds, and the difference ΔTf = |Tf1 - Tf4| = |0.521 - 0.597| = 0.078 microseconds. This ensures that the output signals of each stage of the drive output transistors have consistent amplitudes, and reduces the fall time T of the output signal of the last stage drive output transistor. f This effectively improves the waveform consistency of the output signals of each stage of the drive output transistors in the output circuit 130, and improves the display effect of the display panel.

[0110] Further reference Figure 8 , Figure 8Curve 1 in the diagram represents the voltage change of the pull-up node PU when both the bootstrap capacitor Cz and the boost capacitor Cb are 0. The corresponding drive signals OUT1 and OUT4 are curves a and b, respectively. Curve 2 represents the voltage change of the pull-up node PU when both the bootstrap capacitor Cz and the boost capacitor Cb are 0.2pF. The corresponding drive signals OUT1 and OUT4 are curves a' and b', respectively. It can be seen that when the clock signal changes, the voltage signal of the pull-up node PU also changes. When Cz = Cb = 0, the rising voltage Vpu1 of the pull-up node PU is close to VGH, and Vpu2 is equal to VGH, causing the rise time Tr of the drive signal OUT1 to increase and the fall time Tf of the drive signal OUT4 to increase. The voltage of the pull-up node PU during reset is VGH. Since Vpu2 equals VGH, the change in the threshold voltage ΔVth of the transistor required in the gate drive circuit 100 is close to 0V. This change in threshold voltage Vth increases the fall time Tf of the drive signal OUT4. For example, if ΔVth increases by 1V, the fall time Tf of the drive signal OUT4 increases by 0.3 microseconds. Alternatively, the bootstrap capacitor Cz and boost capacitor Cb can be omitted from the gate drive circuit 100, meaning both Cz and Cb are zero. However, this requires strict control over the TFT device's characteristic range and threshold voltage variation.

[0111] When Cz = Cb = 0.2, the rising voltages Vpu1 and Vpu2 of the pull-up node PU are both more than 4V higher than VGH. The rising waveform and rise time Tr of the drive signal OUT1 are improved, while the fall time Tf of the drive signal OUT4 is reduced, and the threshold voltage change margin of the transistor is increased by more than 4V. Therefore, preferably, in this embodiment, both the bootstrap capacitor Cz and the boost capacitor Cb are provided, and the ratio of the bootstrap capacitor Cz to the boost capacitor Cb is adjusted within a predetermined range.

[0112] Simulation results show that when the ratio of bootstrap capacitor Cz to boost capacitor Cb satisfies 0 ≤ Cz / Cb ≤ 1, the amplitude difference of the output signals of each stage of the driving output transistor is less than 5%, or even close to 0. Furthermore, the fall time T between the output signals of the first and last stage driving output transistors can be reduced. f The phase difference is less than 0.13 microseconds, or even less than 0.8 microseconds, which effectively improves the waveform consistency of the output signals of each stage of the drive output transistor in the output circuit 130.

[0113] This application also provides a display panel, including the gate driving circuit 100 described in any of the above embodiments. The display panel is, for example, a liquid crystal display panel or a light-emitting diode display panel.

[0114] This application also provides a display device, including the display panel described in any of the above embodiments. This display device can be, for example, any device with display functionality such as a monitor, mobile phone, tablet computer, or billboard.

[0115] In the embodiments of this application, the order of the steps does not imply the order of execution. The execution order of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0116] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: An input circuit is used to receive a cascaded signal sent by the previous gate driving circuit cascaded with the gate driving circuit, and to charge the pull-up node of the gate driving circuit according to the cascaded signal. A pull-down circuit, connected to the gate low voltage, is used to pull down the voltage of the pull-down node of the gate drive circuit according to the gate low voltage under the control of the voltage of the pull-up node; The output circuit includes at least two drive output transistors and a bootstrap capacitor. The at least two drive output transistors are respectively connected to at least two gate lines in the display panel. Each of the at least two drive output transistors is used to receive a corresponding clock signal and, under the control of the voltage of the pull-up node, outputs the corresponding clock signal as a drive signal. A boost circuit, including a boost capacitor, is used to continuously charge the pull-up node under the control of the output signal of the output circuit, so as to maintain the voltage of the pull-up node at an effective voltage, wherein the ratio between the bootstrap capacitor and the boost capacitor is set between 0.5 and 1.

2. The gate driving circuit according to claim 1, characterized in that, The bootstrap capacitor is connected between the control terminal and the first current terminal of any one of the at least two drive output transistors. The first current terminal of the drive output transistor is connected to the corresponding output terminal, and the second current terminal of the drive output transistor is connected to the corresponding clock signal.

3. The gate driving circuit according to claim 1, characterized in that, The output circuit further includes a cascaded output transistor, which is used to receive the corresponding clock signal and output the corresponding clock signal as a cascaded signal under the control of the voltage of the pull-up node. The bootstrap capacitor is connected to the control terminal and the first current terminal of the cascaded output transistor. The first current terminal of the cascaded output transistor is connected to the corresponding output terminal, and the second current terminal of the cascaded output transistor is connected to the corresponding clock signal.

4. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The input circuit includes a first transistor, which may be one or two. The control terminal of the first transistor is connected to the input terminal of the input circuit, and the two current terminals of the first transistor are connected in series between the input terminal of the input circuit and the pull-up node.

5. The gate driving circuit according to claim 4, characterized in that, The first transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage, the specific power supply voltage being used to adjust the threshold voltage of the first transistor.

6. The gate driving circuit according to claim 4, characterized in that, The gate drive circuit further includes a first voltage regulator circuit, used to charge the short-circuited current terminals of the two first transistors under the control of the voltage of the pull-up node, so as to maintain the voltage of the pull-up node at an effective voltage. The first voltage regulator circuit includes a second transistor, the control terminal of the second transistor is connected to the pull-up node, the first current terminal of the second transistor is connected to the corresponding power supply voltage, and the second current terminal of the second transistor is connected to the current terminals of the two first transistors that are shorted together.

7. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The gate drive circuit further includes a second voltage regulator circuit, which is connected between the corresponding power supply voltage and the pull-down node. The number of second voltage regulator circuits can be one or two. When there are two second voltage regulator circuits, they are used to alternately control the voltage of their respective connected pull-down nodes according to the power supply voltage they are connected to. The second voltage regulator circuit includes a third transistor, the control terminal and the first current terminal of the third transistor are connected to the corresponding power supply voltage, and the second current terminal of the third transistor is connected to the corresponding pull-down node.

8. The gate driving circuit according to claim 7, characterized in that, The gate drive circuit further includes an auxiliary control circuit connected to the second voltage regulator circuit, used to pull down the voltage of the pull-up node according to the low gate voltage under the control of the voltage of the pull-down node of the second voltage regulator circuit. The auxiliary control circuit includes one or two groups of transistors, each group of transistors including one or two fourth transistors. The control terminal of the fourth transistor is connected to the pull-down node corresponding to the second voltage regulator circuit, and the two current terminals of the fourth transistor are connected in series between the gate low voltage and the pull-up node.

9. The gate driving circuit according to claim 8, characterized in that, The fourth transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage, the specific power supply voltage being used to adjust the threshold voltage of the fourth transistor.

10. The gate driving circuit according to claim 8, characterized in that, The gate drive circuit further includes a first voltage regulator circuit, used to charge the short-circuited current terminals of the one or two fourth transistors under the control of the voltage of the pull-up node, so as to maintain the voltage of the pull-up node at an effective voltage. The first voltage regulator circuit includes a second transistor, the control terminal of the second transistor is connected to the pull-up node, the first current terminal of the second transistor is connected to the corresponding power supply voltage, and the second current terminal of the second transistor is connected to the current terminals of the one or two fourth transistors that are shorted together.

11. The gate driving circuit according to claim 7, characterized in that, The gate drive circuit further includes an auxiliary pull-down circuit connected to the second voltage regulator circuit, used to set the voltage of the pull-down node corresponding to the second voltage regulator circuit to a low gate voltage according to the cascaded signal. The auxiliary pull-down circuit includes a fifth transistor. The first current terminal of the fifth transistor is connected to the pull-down node corresponding to the second voltage regulator circuit. The second current terminal of the fifth transistor is connected to the gate low voltage. The control terminal of the fifth transistor is connected to the input terminal of the input circuit.

12. The gate driving circuit according to claim 7, characterized in that, The gate drive circuit further includes an output pull-down circuit connected to the cascaded output drive signal and each drive output transistor. The output pull-down circuit includes one or two sixth transistors. When the pull-down circuit includes two sixth transistors, the control terminals of the two sixth transistors are respectively connected to the corresponding pull-down nodes, the first current terminal of the sixth transistor is connected to the corresponding output terminal, and the second current terminal of the sixth transistor is connected to the gate turn-off voltage.

13. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The pull-down circuit includes a seventh transistor, which may be one or two. The control terminal of the seventh transistor is connected to the pull-up node, the first current terminal of the seventh transistor is connected to the pull-down node, and the second current terminal of the seventh transistor is connected to the gate low voltage.

14. The gate driving circuit according to any one of claims 1 to 3, characterized in that, The gate drive circuit further includes a first reset circuit and a second reset circuit. The first reset circuit includes an eighth transistor, which may be one or two. The control terminal of the eighth transistor is connected to the first reset signal, and the two current terminals of the eighth transistor are connected in series between the gate low voltage and the pull-up node. The second reset circuit includes a ninth transistor, which may be one or two. The control terminal of the ninth transistor is connected to a second reset signal, and the two current terminals of the ninth transistor are connected in series between the gate low voltage and the pull-up node.

15. The gate driving circuit according to claim 14, characterized in that, The eighth transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage, the specific power supply voltage being used to adjust the threshold voltage of the eighth transistor; and / or, The ninth transistor includes a first control terminal and a second control terminal, wherein the first control terminal is connected to the input terminal of the input circuit, and the second control terminal is connected to a specific power supply voltage, the specific power supply voltage being used to adjust the threshold voltage of the ninth transistor.

16. The gate driving circuit according to claim 14, characterized in that, The gate drive circuit further includes a first voltage regulator circuit, used to charge the current terminals of the two eighth transistors shorted together and / or the two ninth transistors shorted together under the control of the voltage of the pull-up node, so as to maintain the voltage of the pull-up node at an effective voltage. The first voltage regulator circuit includes a second transistor, the control terminal of the second transistor is connected to the pull-up node, the first current terminal of the second transistor is connected to the corresponding power supply voltage, and the second current terminal of the second transistor is connected to the current terminals of the two eighth transistors that are shorted together and / or the current terminals of the two ninth transistors that are shorted together.

17. A display panel, characterized in that, Includes the gate drive circuit according to any one of claims 1 to 16.

18. A display device, characterized in that, Includes the display panel according to claim 17.

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