Display panel and display device

Abstract

The embodiments of the present disclosure provide a display panel and a display device, which relate to the field of display technology and are used to achieve a narrow frame. The display panel includes a plurality of initialization signal lines, a plurality of pixel driving circuits, a plurality of initialization signal buses, a plurality of auxiliary signal lines and a plurality of adapter lines. Along the column direction, among the same type of initialization signal lines, all initialization signal lines are divided into a plurality of initialization signal line groups, and an initialization signal line group includes a plurality of initialization signal lines. Any auxiliary signal line includes at least one auxiliary signal line, and an auxiliary signal line is connected to all initialization signal lines of the same type of initialization signal line. The plurality of adapter lines are located on a base substrate in a peripheral area, and any adapter line includes a plurality of adapter lines, one end of a adapter line is connected to an initialization signal bus, and the other end of the adapter line is connected to at least one initialization signal line group of the same type of initialization signal line. The above-mentioned display panel is used to display images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) has been widely used in the display field due to its advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed and flexible display. Summary of the Invention

[0003] An object of the embodiments of the present disclosure is to provide a display panel and a display device for achieving a narrow frame.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a display panel is provided. The display panel includes a display area and a peripheral area surrounding the display area, the peripheral area includes a first frame area, and along the row direction, the first frame area is located on at least one side of the display area. The display panel includes a base substrate, and a plurality of initialization signal lines, a plurality of pixel driving circuits, a plurality of initialization signal buses, a plurality of auxiliary signal lines and a plurality of adapter lines located on the base substrate. The plurality of initialization signal lines are located on the base substrate of the display area, and any one of the initialization signal lines includes a plurality of initialization signal lines, and the plurality of initialization signal lines extend along the row direction and are arranged along the column direction. Wherein, along the column direction, in the same type of initialization signal lines, all the initialization signal lines are divided into a plurality of initialization signal line groups, and one of the initialization signal line groups includes a plurality of the initialization signal lines. A plurality of pixel driving circuits are located on the base substrate of the display area, and the plurality of pixel driving circuits are arranged in multiple rows and columns. A row of pixel driving circuits is electrically connected to the plurality of initialization signal lines. A plurality of initialization signal buses are located on the base substrate of the first border area, and any one of the initialization signal buses includes at least one initialization signal bus, and the initialization signal bus extends along the first border area, and the extension direction of the initialization signal bus intersects with the extension direction of the initialization signal line. A plurality of auxiliary signal lines are located on the substrate, and any one of the auxiliary signal lines includes at least one auxiliary signal line, and the extension direction of the auxiliary signal line intersects with the extension direction of the initialization signal line, and one auxiliary signal line is connected to all the initialization signal lines of the same type. A plurality of adapter lines are located on the base substrate of the peripheral area, and any one of the adapter lines includes a plurality of adapter lines, one end of one of the adapter lines is connected to one of the initialization signal buses, and the other end of the adapter line is connected to at least one initialization signal line group of the same type of initialization signal line.

[0006] In the above-mentioned display panel, an auxiliary signal line is used to connect to all the initialization signal lines of the same type of initialization signal line. That is, at this time, all the initialization signal lines of the same type of initialization signal line are connected in series. Thus, in the same type of adapter line, one end of a adapter line is connected to an initialization signal bus, and the other end of the adapter line is connected to at least one initialization signal line group of the same type of initialization signal line. That is, one adapter line in the same type of adapter line can correspond to at least one initialization signal line group of the same type of initialization signal line. That is, one adapter line in a type of adapter line can correspond to multiple initialization signal lines in the same type of initialization signal line. Compared with the above-mentioned implementable manner, in which one adapter line in a type of adapter line can correspond to one initialization signal line in the same type of initialization signal line, the number of adapter lines can be effectively reduced. Furthermore, the space occupied by the adapter line in the peripheral area can be reduced, so as to achieve a narrow frame of the display panel.

[0007] In some embodiments, the auxiliary signal line includes a first auxiliary portion, the first auxiliary portion is located in the display area, and an orthographic projection of the first auxiliary portion on the base substrate does not overlap with an orthographic projection of the pixel driving circuit on the base substrate.

[0008] In some embodiments, an orthographic projection of one of the first auxiliary parts on the base substrate is located between orthographic projections of two adjacent columns of the pixel driving circuits on the base substrate.

[0009] In some embodiments, the first auxiliary portion is connected to all of the initialization signal lines of the same type.

[0010] In some embodiments, the other end of one of the adapter wires is connected to one of the initialization signal line groups of the same type of initialization signal line, and the number of initialization signal lines in each of the initialization signal line groups of the same type of initialization signal line is equal.

[0011] In some embodiments, the auxiliary signal line includes a second auxiliary portion, and an orthographic projection of the second auxiliary portion on the substrate is located on a side of the orthographic projections of all the transfer lines on the substrate close to the display area.

[0012] In some embodiments, the second auxiliary portion is connected to all of the initialization signal line groups of the same type of initialization signal line.

[0013] In some embodiments, one end of the adapter wire is connected to the initialization signal bus, and the other end of the adapter wire is connected to an initialization signal line group of the same type of initialization signal line through the second auxiliary part, and among the same type of initialization signal lines, the number of initialization signal lines in each initialization signal line group is equal.

[0014] In some embodiments, the first border area includes a first area and a corner area, and along the column direction, the corner area is located on at least one side of the first area. The display area includes a first display area and a second display area, and along the row direction, the corner area overlaps with the first display area, and the first area overlaps with the second display area. A plurality of adapter lines are located in the first area, and the adapter lines are connected to the initialization signal line group located in the second display area.

[0015] In some embodiments, the first border area includes a first area and a corner area, and the corner area is located on at least one side of the first area along the column direction. The display area includes a first display area and a second display area, and the corner area overlaps with the first display area, and the first area overlaps with the second display area along the row direction. The auxiliary signal line includes a first auxiliary portion and a second auxiliary portion. The first auxiliary portion is located in the display area, and the orthographic projection of one of the first auxiliary portions on the substrate does not overlap with the orthographic projection of the pixel driving circuit on the substrate. The first auxiliary portion is connected to at least all initialization signal lines of the same type located in the second display area. The orthographic projection of the second auxiliary portion on the substrate is located on a side of the orthographic projection of all the adapter lines on the substrate that is closer to the display area, and the second auxiliary portion is connected to at least all initialization signal lines of the same type located in the first display area. Multiple adapter lines are located in the first area, and among the multiple adapter lines, the adapter lines adjacent to the corner area are first target adapter lines, and the remaining are second target adapter lines. The first target patch cord is connected to the second auxiliary portion, and one of the second target patch cords is connected to at least one of the initialization signal line groups located in the second display area.

[0016] In some embodiments, the first auxiliary portion is located in the second display area and is connected to all initialization signal lines of the same type located in the second display area. The second auxiliary portion is located at least in the corner area and is connected to all initialization signal lines of the same type located in the first display area.

[0017] In some embodiments, the plurality of initialization signal lines include two types of initialization signal lines, and the two types of initialization signal lines include a first type of initialization signal line and a second type of initialization signal line. The display panel further includes: two types of initialization signal buses, two auxiliary signal lines, and two adapter lines. The two types of initialization signal buses are respectively a first type of initialization signal bus and a second type of initialization signal bus. The two auxiliary signal lines are respectively a first type of auxiliary signal line and a second type of auxiliary signal line. The first type of auxiliary signal line is connected to all the initialization signal lines included in the first type of initialization signal line, and the second type of auxiliary signal line is connected to all the initialization signal lines included in the second type of initialization signal line. The two adapter lines are respectively a first type of adapter line and a second type of adapter line, one end of a first type of adapter line is connected to the first type of initialization signal bus, and the other end of the first type of adapter line is connected to at least one group of initialization signal lines in the first type of initialization signal line. One end of a second type of adapter line is connected to a second type of initialization signal bus, and the other end of the second type of adapter line is connected to at least one group of initialization signal lines in the second type of initialization signal line.

[0018] In another aspect, a display device is provided, comprising: a cover plate and a display panel according to any one of the above embodiments, wherein the cover plate is located on a light-emitting side of the display panel.

[0019] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0021] Figure 1 is a structural diagram of a display panel according to some embodiments;

[0022] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0023] Figure 3 is a partial structural diagram of a display panel according to some possible implementations;

[0024] Figure 4is a partial structural diagram of a display panel according to some embodiments;

[0025] Figure 5 for Figure 4 A partial enlarged view of C1 in the middle;

[0026] Figure 6 is a partial layout structure diagram of a display panel according to some embodiments;

[0027] Figure 7 is a partial structural diagram of a display panel according to some other embodiments;

[0028] Figure 8 is a partial layout structure diagram of a display panel according to some embodiments;

[0029] Figure 9 is a partial structural diagram of a display panel according to some further embodiments;

[0030] Figure 10 is a partial structural diagram of a display panel according to some further embodiments;

[0031] Figure 11 is a partial structural diagram of a display panel according to some further embodiments;

[0032] Figure 12 for Figure 11 A partial enlarged view of C2 in the middle;

[0033] Figure 13 is a partial layout structure diagram of a display panel according to some embodiments;

[0034] Figure 14 is a partial structural diagram of a display panel according to some further embodiments;

[0035] Figure 15 is a partial structural diagram of a display panel according to some further embodiments;

[0036] Figure 16 is a partial structural diagram of a display panel according to some further embodiments. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0042] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0043] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0044] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0045] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0048] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] Figure 1 FIG is a structural diagram of a display device according to some embodiments. Figure 1 As shown, some embodiments of the present disclosure provide a display device 200, which includes a cover plate and a display panel 100, wherein the cover plate is located on the light-emitting side of the display panel 100. The cover plate can protect the display panel 100 and improve the overall impact resistance of the display device 200.

[0051] In some examples, the material of the cover includes at least one of transparent polyimide and ultra-thin glass.

[0052] It should be noted that the light-emitting side of the display panel 100 may be the side of the display panel 100 used for displaying light. The backlight side of the display panel 100 may be the side of the display panel 100 facing away from the light-emitting side. That is, if the light-emitting side of the display panel 100 is located on the front side of the display panel 100, then the backlight side of the display panel 100 is located on the back side of the display panel 100.

[0053] In some examples, the display device 200 may further include a frame, a display driver integrated circuit (IC), and other electronic components. The display driver integrated circuit is configured to provide a data drive signal (also referred to as a data signal) to the display panel 100 so that the display panel 100 can display an image.

[0054] Exemplarily, the display device 200 may be a liquid crystal display (LCD). Alternatively, the display device 200 may be an electroluminescent display or a photoluminescent display. If the display device 200 is an electroluminescent display, the electroluminescent display may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device 200 is a photoluminescent display, the photoluminescent display may be a quantum dot photoluminescent display.

[0055] Exemplarily, the display device 200 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0056] Figure 2 is a structural diagram of a display panel according to some embodiments.

[0057] In some embodiments, as Figure 2 As shown, the display panel 100 includes a display area (active area, AA area for short; also referred to as the effective display area) AA and a peripheral area SA surrounding the display area AA. The peripheral area SA includes a first border area SA1. The first border area SA1 is located on at least one side of the display area AA along the row direction X.

[0058] Wherein, along the row direction X, the first border area SA1 is located on at least one side of the display area AA, which may include the following situations.

[0059] The first type: the first frame area SA1 is located on one side of the display area AA along the row direction X. That is, the first frame area SA1 can be located on the left side of the display area AA, or the first frame area SA1 can also be located on the right side of the display area AA.

[0060] The second type: the first frame area SA1 includes a first sub-frame area SA11 and a second sub-frame area SA12. Along the row direction X, the display area AA is located between the first sub-frame area SA11 and the second sub-frame area SA12. Figure 2 As shown, the first sub-frame area SA11 is located on the left side of the display area AA. That is, the first sub-frame area SA11 can be the left frame area. The second sub-frame area SA12 is located on the right side of the display area AA. That is, the second sub-frame area SA12 can be the right frame area.

[0061] The peripheral area SA may further include a second border area SA2 . Along the column direction Y, the second border area SA2 is located on at least one side of the display area AA.

[0062] Wherein, along the column direction Y, the first border area SA1 is located on at least one side of the display area AA, which may include the following situations.

[0063] The first type: the second frame area SA2 is located on one side of the display area AA along the column direction Y. That is, the second frame area SA2 can be located on the upper side of the display area AA, or the second frame area SA2 can also be located on the lower side of the display area AA.

[0064] The second type: the second frame area SA2 includes the third sub-frame area SA21 and the fourth sub-frame area SA22. Along the column direction Y, the display area AA is located between the third sub-frame area SA21 and the fourth sub-frame area SA22. Figure 2 As shown, the third sub-frame area SA21 is located on the left side of the display area AA. That is, the third sub-frame area SA21 can be a left frame area. The fourth sub-frame area SA22 is located on the upper side of the display area AA. That is, the fourth sub-frame area SA22 can be a bottom frame area.

[0065] When the first border area SA1 includes the first sub-border area SA11 and the second sub-border area SA12, and the second border area SA2 includes the third sub-border area SA21 and the fourth sub-border area SA22, the first sub-border area SA11, the third sub-border area SA21, the second sub-border area SA12 and the fourth sub-border area SA22 are connected in sequence to form a peripheral area SA surrounding the display area AA.

[0066] In addition, if Figure 3 As shown, the display panel 100 may further include a binding area BB, and the binding area BB is located on a side of the fourth sub-bezel area SA22 away from the display area AA.

[0067] like Figure 2 As shown, the display panel 100 includes a base substrate 10 and a plurality of sub-pixels P located on the base substrate 10. The plurality of sub-pixels P are disposed in a display area AA, wherein all the sub-pixels P are arranged in multiple rows and columns in the display area AA.

[0068] Sub-pixel P is the smallest unit for displaying images on the display panel 100. Multiple sub-pixels P may include red sub-pixels, blue sub-pixels, and green sub-pixels. By adjusting the brightness (grayscale) of sub-pixels of different colors, multiple colors can be displayed through color combination and superposition, thereby realizing full-color display of the display panel 100.

[0069] In some other examples, the display panel 100 may further include a white sub-pixel.

[0070] The display panel 100 may further include a plurality of scan signal lines and a plurality of data signal lines. The plurality of scan signal lines may extend along a row direction X and be arranged along a column direction Y. The plurality of data signal lines may extend along a column direction Y and be arranged along a row direction X. The plurality of scan signal lines and the plurality of data signal lines intersect to define a plurality of sub-pixels P.

[0071] like Figure 2 As shown, each sub-pixel P may include a light-emitting device O and a pixel driving circuit Q for driving the light-emitting device O. When all sub-pixels P are arranged in multiple rows and columns within the display area AA, the corresponding multiple pixel driving circuits Q are also arranged in multiple rows and columns within the display area AA.

[0072] In some examples, the method includes an anode layer, a light-emitting layer, and a cathode layer stacked in sequence. In some examples, an electron transport layer is disposed between the cathode layer and the light-emitting layer, and a hole transport layer is disposed between the anode layer and the light-emitting layer.

[0073] In some examples, the pixel driving circuit Q includes multiple transistors. In some embodiments, the structure of the pixel driving circuit Q in the present disclosure includes multiple structures, which can be selected according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C" or "8T1C", etc. Here, "T" represents a thin film transistor, and the number before "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number before "C" represents the number of storage capacitors C.

[0074] In addition, the display panel 100 may further include a variety of signal lines. The aforementioned various signal lines may be electrically connected to the pixel driving circuit to provide the pixel driving circuit with the signals it needs.

[0075] Figure 3 FIG. 1 is a partial structural diagram of a display panel according to some possible implementation methods. Figure 3 To clearly illustrate the relationship between the initialization signal line 20, the initialization signal bus 30 and the adapter line 40, Figure 3 Only the lower half of the display panel 100 is shown for illustration.

[0076] In some examples, such as Figure 3 As shown, the display panel 100 further includes a plurality of initialization signal lines 20, which are located on the base substrate 10 in the display area AA. Each type of initialization signal line 20 includes a plurality of initialization signal lines 20, which extend along the row direction X and are arranged along the column direction Y.

[0077] The display panel 100 includes multiple initialization signal lines 20 , which may include the following situations.

[0078] Type 1: The display panel 100 includes two types of initialization signal lines 20, including a first type initialization signal line 20A and a second type initialization signal line 20B. The first type initialization signal line 20A includes multiple initialization signal lines 20, each of which is defined as a first initialization signal line Vinit1. Furthermore, the second type initialization signal line 20B also includes multiple initialization signal lines 20, each of which is defined as a second initialization signal line Vinit2.

[0079] Let's take the "7T1C" pixel driving circuit Q as an example. Here, the pixel driving circuit Q includes a first reset transistor and a second reset transistor. A first initialization signal line Vinit1 can be connected to the source of the first reset transistor, and a second initialization signal line Vinit2 can be connected to the source of the second reset transistor.

[0080] Exemplarily, multiple first initialization signal lines Vinit1, multiple second initialization signal lines Vinit2 and multiple rows of pixel driving circuits Q may correspond one to one, so that the pixel driving circuits Q in one row are simultaneously connected to one first initialization signal line Vinit1 and one second initialization signal line Vinit2.

[0081] Type 2: Display panel 100 includes three types of initialization signal lines, including a first type of initialization signal line, a second type of initialization signal line, and a third type of initialization signal line. This differs from Type 1 in that the plurality of initialization signal lines 20 also includes a third type of initialization signal line. Similarly, the third type of initialization signal line includes a plurality of initialization signal lines 20, and these initialization signal lines 20 are defined as third initialization signal lines.

[0082] The pixel driving circuit Q of "8T1C" is used as an example for description. In this case, the pixel driving circuit Q includes a third reset transistor in addition to the first reset transistor and the second reset transistor, and the third initialization signal line can be connected to the source of the third reset transistor.

[0083] Regardless of how many types of initialization signal lines 20 the display panel 100 includes, each initialization signal line 20 must correspond to one initialization signal bus 30 , so that the initialization signal bus 30 can be used to transmit the initialization signal to the initialization signal line.

[0084] That is, if Figure 3As shown, the display panel 100 further includes multiple initialization signal buses 30. The multiple initialization signal buses 30 are located on the base substrate 10 in the first border area SA1, and each initialization signal bus 30 corresponds to each initialization signal line 20. Each initialization signal bus 30 includes at least one initialization signal bus 30. The initialization signal bus 30 extends along the first border area SA1, and the extension direction of the initialization signal bus 30 intersects the extension direction of the initialization signal line 20.

[0085] The display panel 100 may further include an initialization signal bus extension portion, which is located within the bonding area BB. In other words, the initialization signal bus 30 may extend into the bonding area BB to facilitate electrical connection with devices within the bonding area and to facilitate reception of initialization signals. In other words, the portion of the initialization signal bus 30 extending into the bonding area is the initialization signal bus extension portion.

[0086] It should be noted that the initialization signal bus 30 extends along the first border area SA1. It can be understood that when the initialization signal bus 30 is located in the first sub-border area SA11, the initialization signal bus 30 extends from the side of the first sub-border area SA11 close to the third sub-border area SA21 to the side of the first sub-border area SA11 close to the fourth sub-border area SA22. Of course, when the initialization signal bus 30 is located in the second sub-border area SA12, the initialization signal bus 30 extends from the side of the first sub-border area SA11 close to the third sub-border area SA21 to the side of the first sub-border area SA11 close to the fourth sub-border area SA22.

[0087] In some achievable ways, such as Figure 3 As shown, the display panel 100 further includes a plurality of adapter lines 40 . The plurality of adapter lines 40 are located on the base substrate 10 in the peripheral area SA. One adapter line 40 is used to connect an initialization signal line 20 to an initialization signal bus 30 .

[0088] Specifically, any type of adapter line 40 includes multiple adapter lines 40, and the multiple adapter lines 40 are arranged along the column direction Y. One end of each adapter line 40 is connected to an initialization signal bus 30, and the other end of the adapter line 40 is connected to an initialization signal line 20. That is, the multiple adapter lines 40 included in one type of adapter line 40 correspond one-to-one to the multiple initialization signal lines 20 included in one type of initialization signal line 20.

[0089] In some examples, the display panel 100 includes two types of initialization signal lines. In this case, the display panel 100 includes two types of initialization signal buses 30 and two types of adapter lines 40. The two types of initialization signal buses 30 are respectively a first type of initialization signal bus 30A and a second type of initialization signal bus 30B, and the two types of adapter lines 40 are respectively a first type of adapter line 40A and a second type of adapter line 40B.

[0090] Two types of initialization signal bus lines 30 may be located within the first sub-peripheral area SA11 of the first peripheral area SA1. The first type of initialization signal bus line 30A may include one initialization signal bus line 30, which is defined as a first initialization signal bus line 31. The second type of initialization signal bus line 30B may also include one initialization signal bus line 30, which is defined as a second initialization signal bus line 32. The second initialization signal bus line 32 may be located on a side of the first initialization signal bus line 31 away from the display area AA.

[0091] The two adapter lines 40 correspond to the two initialization signal buses 30. The two adapter lines 40 are located in the first sub-peripheral area SA1 of the first peripheral area SA1, and the orthographic projections of the two adapter lines 40 on the base substrate 10 are located on the side of the orthographic projections of the two initialization signal buses 30 on the base substrate 10 close to the display area AA, so that the adapter lines 40 are used to connect the initialization signal buses 30 and the initialization signal lines 20.

[0092] The first type of adapter line 40A includes multiple adapter lines 40, each of which is defined as a first adapter line 41. In this case, the multiple first adapter lines 41 correspond one-to-one with the multiple first initialization signal lines Vinit1. That is, one end of a first adapter line 41 is connected to the first initialization signal bus 31, and the other end of the first adapter line 41 is connected to a first initialization signal line Vinit1. This allows each first initialization signal line Vinit1 in the display area AA to be connected to the first initialization signal bus 31 in the peripheral area SA via the corresponding first adapter line 41.

[0093] Similarly, multiple second adapter lines 42 correspond one-to-one with multiple second initialization signal lines Vinit2. That is, one end of a second adapter line 42 is connected to the second initialization signal bus 32, and the other end of the second adapter line 42 is connected to a second initialization signal line Vinit2. This allows each second initialization signal line Vinit2 in the display area AA to be connected to the second initialization signal bus 32 in the peripheral area SA via the corresponding second adapter line 42.

[0094] The inventors have discovered that, since the number of adapter wires 40 contained in any type of adapter wire 40 must correspond one-to-one to the number of initialization signal lines 20 contained in a type of initialization signal line 20 to which it is connected, the number of adapter wires 40 will be large, and the adapter wires 40 will occupy a larger area of ​​the peripheral area SA, making it difficult to achieve a narrow bezel design.

[0095] Figure 4 FIG is a partial structural diagram of a display panel according to some embodiments. Figure 4 To clearly illustrate the relationship between the initialization signal line 20, the initialization signal bus 30 and the adapter line 40, Figure 4 Only the lower half of the display panel 100 is shown for illustration.

[0096] Based on this, the embodiment of the present disclosure provides a display panel 100, such as Figure 4 As shown, the display panel 100 further includes a plurality of auxiliary signal lines 50, which are located on the base substrate 10. Each type of auxiliary signal lines 50 includes at least one auxiliary signal line 50, and the extending direction of the auxiliary signal lines 50 intersects with the extending direction of the initialization signal lines 20. In addition, one auxiliary signal line 50 is connected to all initialization signal lines 20 of the same type.

[0097] At this time, along the column direction Y, all the initialization signal lines 20 of the same type are divided into a plurality of initialization signal line groups W, and one initialization signal line group W includes a plurality of initialization signal lines 20 .

[0098] Since one auxiliary signal line 50 can be used in the display panel 100 to connect to all the initialization signal lines 20 of the same type, that is, all the initialization signal lines 20 of the same type are connected in series.

[0099] Thus, among the same type of adapter wires 40, one end of one adapter wire 40 is connected to one initialization signal bus 30, and the other end of the adapter wire 40 is connected to at least one initialization signal line group W among the same type of initialization signal lines 20. That is, one adapter wire 40 among the same type of adapter wires 40 can correspond to at least one initialization signal line group W among the same type of initialization signal lines 20. That is, one adapter wire 40 among the same type of adapter wires 40 can correspond to multiple initialization signal lines 20 among the same type of initialization signal lines 20. Compared to the above-mentioned implementation method, in which one adapter wire 40 among the same type of adapter wires 40 can correspond to one initialization signal line 20 among the same type of initialization signal lines 20, the number of adapter wires 40 can be effectively reduced. Furthermore, the space occupied by the adapter wires 40 in the peripheral area SA can be reduced, thereby facilitating the realization of a narrow bezel for the display panel 100.

[0100] It should be noted that one patch cable 40 can be connected to at least one initialization signal line group W in the same type of initialization signal line 20. That is, one patch cable 40 can be connected to one initialization signal line group W, multiple initialization signal line groups W, or all initialization signal line groups W in the same type of initialization signal line 20. Different connection scenarios will be described below.

[0101] In some embodiments, as Figure 4 As shown, the display panel 100 includes two types of initialization signal lines as an example. The two types of initialization signal lines 20 include a first type of initialization signal line 20A and a second type of initialization signal line 20B. All first initialization signal lines Vinit1 included in the first type of initialization signal line 20A are divided into a plurality of initialization signal line groups W, which are defined as a first initialization signal line group W1. Similarly, all first initialization signal lines Vinit1 included in the second type of initialization signal line 20B are divided into a plurality of initialization signal line groups W, which are defined as a second initialization signal line group W2.

[0102] In this case, the display panel 100 includes two types of auxiliary signal lines 50: a first type of auxiliary signal line 50A and a second type of auxiliary signal line 50B. The first type of auxiliary signal line 50A includes at least one auxiliary signal line 50, which is defined as a first auxiliary signal line 51. The first auxiliary signal line 51 is connected to all first initialization signal lines Vinit1. Similarly, the second type of auxiliary signal line 50B includes at least one auxiliary signal line 50, which is defined as a second auxiliary signal line 52. The second auxiliary signal line 52 is connected to all second initialization signal lines Vinit2.

[0103] Furthermore, the display panel 100 further includes two types of adapter cables 40, namely a first adapter cable 40A and a second adapter cable 40B. The first adapter cable 40A includes multiple adapter cables 40, each of which is defined as a first adapter cable 41. One end of each first adapter cable 41 is connected to the first initialization signal bus 31, and the other end of each first adapter cable 41 is connected to at least one first initialization signal line group W1.

[0104] As configured above, one first adapter line 41 corresponds to at least one first initialization signal line group W1. That is, one first adapter line 41 corresponds to multiple first initialization signal lines Vinit1. Compared to the case where one first adapter line 41 corresponds to one first initialization signal line Vinit1, this can effectively reduce the number of first adapter lines 41, thereby reducing the space occupied by the first adapter lines 41 in the peripheral area SA, thereby facilitating a narrow bezel of the display panel 100.

[0105] Similarly, the second adapter line 40B includes multiple adapter lines 40, which are defined as second adapter lines 42. One end of a second adapter line 42 is connected to the second initialization signal bus 32, and the other end of the second adapter line 42 is connected to at least one second initialization signal line group W2.

[0106] As configured above, one second adapter line 42 corresponds to at least one second initialization signal line group W2. That is, one second adapter line 42 corresponds to multiple second initialization signal lines Vinit2. Compared to the case where one second adapter line 42 corresponds to one second initialization signal line Vinit2, this can effectively reduce the number of second adapter lines 42, thereby reducing the space occupied by the second adapter lines 42 in the peripheral area SA, thereby facilitating a narrow bezel of the display panel 100.

[0107] Figure 5 for Figure 4 A partial enlarged view of C1 in the figure.

[0108] In some embodiments, combined Figure 4 and Figure 5 As shown, the display panel 100 further includes a gate drive circuit G, which is located in the first border area SA1. The gate drive circuit G is configured to provide a scanning signal to the pixel drive circuit Q of the sub-pixel P. The orthographic projection of the initialization signal bus 30 on the base substrate 10 is located on a side of the orthographic projection of the gate drive circuit G on the base substrate 10 that is closer to the display area AA. This arrangement facilitates the connection of the initialization signal bus 30 to the initialization signal line 20 located in the display area AA.

[0109] Figure 6 FIG. 4 is a partial layout structure diagram of a display panel according to some embodiments.

[0110] In some embodiments, as Figure 6 As shown, along the direction away from the base substrate 10 , the display panel 100 further includes: an active layer, a first gate metal layer Gate1 , a second gate metal layer Gate2 , a first source / drain metal layer SD1 , and a second source / drain metal layer SD2 .

[0111] The active layer may include the channel portion of each transistor in the pixel driving circuit Q, the first gate metal layer Gate1 may include the gate of each transistor in the pixel driving circuit Q, and the second gate metal layer Gtae2 may include the source and drain of each transistor in the pixel driving circuit Q. The first source-drain metal layer SD1 may include a conductive portion for connecting each transistor in the pixel driving circuit Q, and the second source-drain metal layer SD2 may include a data signal line Data, etc.

[0112] As described above with reference to the accompanying drawings, the display panel 100 can connect all initialization signal lines 20 of the same type in series by adding auxiliary signal lines 50. This allows a single patch cable 40 to simultaneously transmit signals to multiple initialization signal lines 20, thereby reducing the number of patch cables 40. The following describes in detail the layout design of the patch cables 40 in the display panel 100 with reference to the accompanying drawings.

[0113] In some embodiments, as Figure 4 As shown, the auxiliary signal line 50 includes a first auxiliary portion 50 a , which is located in the display area AA. The orthographic projection of the first auxiliary portion 50 a on the base substrate 10 does not overlap with the orthographic projection of the pixel driving circuit Q on the base substrate 10 .

[0114] For the purposes of this description, the auxiliary signal line 50 is described as the first auxiliary signal line 51 in the first type of auxiliary signal line 50A. In this case, a first auxiliary portion 50a is provided within the display area AA of the display panel 100. The extension direction of the first auxiliary portion 50a intersects with the extension direction of the initialization signal line 20, and one first auxiliary portion 50a is connected to all initialization signal lines 20 of the same type. Therefore, the first auxiliary portion 50a connects all first initialization signal lines Vinit1 in the first type of initialization signal lines 20A in series. In other words, any first initialization signal line Vinit1 in the first type of initialization signal lines 20A receives the first initialization signal transmitted from the first initialization signal bus 31 and can transmit the first initialization signal to the remaining first initialization signal lines Vinit1 in the first type of initialization signal lines 20A.

[0115] Therefore, when the first adapter line 41 is connected to any one of the first initialization signal lines Vinit1 in at least one first initialization signal line group W1, the first initialization signal from the first initialization signal bus 31 can be transmitted to all of the first initialization signal lines Vinit1 in at least one first initialization signal line group W1. The same applies to the second adapter line 42.

[0116] Thus, the number of adapter lines 40 in the display panel 100 can be effectively reduced. Furthermore, the space occupied by the adapter lines 40 in the peripheral area SA can be reduced, so as to realize a narrow frame of the display panel 100.

[0117] In some embodiments, as Figure 4 As shown, the orthographic projection of the first auxiliary portion 50 a on the base substrate 10 does not overlap with the orthographic projection of the pixel driving circuit Q on the base substrate 10 .

[0118] Based on this, it is possible to prevent the various transistors, various connection nodes or other conductive parts in the pixel driving circuit Q from receiving the jump signal, which may cause the potential of the initialization signal transmitted by the first auxiliary part 50a to change, thereby affecting the initialization signal received by the initialization signal line 20, which is beneficial to improving the display uniformity of the display panel 100.

[0119] In some embodiments, as Figure 4 As shown, the orthographic projection of a first auxiliary portion 50 a on the base substrate 10 is located between the orthographic projections of two adjacent columns of pixel driving circuits Q on the base substrate 10 .

[0120] Based on this, the orthographic projection of the first auxiliary portion 50a on the base substrate 10 can be ensured to not overlap with the orthographic projection of the pixel driving circuit Q on the base substrate 10, thereby preventing the potential of the initialization signal transmitted by the first auxiliary portion 50a from changing and affecting the initialization signal received by the initialization signal line 20, thereby facilitating improved display uniformity of the display panel 100. Furthermore, disposing the first auxiliary portion 50a between the orthographic projections of the pixel driving circuits Q of two adjacent columns on the base substrate 10 can also prevent the first auxiliary portion 50a from affecting the aperture ratio of the display panel 100.

[0121] In some examples, the first auxiliary portion 50a of the first auxiliary signal line 51 in the first type of auxiliary signal line 50A and the first auxiliary portion 50a of the second auxiliary signal line 52 in the second type of auxiliary signal line 50B can be respectively located between the orthographic projections of two different adjacent columns of pixel driving circuits Q on the base substrate 10. That is, the first auxiliary portion 50a of the first auxiliary signal line 51 in the first type of auxiliary signal line 50A is located between the orthographic projections of two adjacent columns of pixel driving circuits Q on the base substrate 10, while the first auxiliary portion 50a of the second auxiliary signal line 52 in the second type of auxiliary signal line 50B is located between the orthographic projections of two adjacent columns of pixel driving circuits Q on the base substrate 10.

[0122] In this way, the two first auxiliary parts 50a can be prevented from being arranged between the orthographic projections of the two adjacent columns of pixel driving circuits Q on the base substrate 10, which would cause a large distance between the two adjacent columns of pixel driving circuits Q. In addition, the two first auxiliary parts 50a can be prevented from being too close to each other, which would cause a short circuit between the two.

[0123] In some examples, combined Figure 4 and Figure 6 As shown, the first auxiliary portion 50a may be located in the second source / drain metal layer SD2, or may be located in other film layers within the display panel 100. When the first auxiliary portion 50a is disposed in the second source / drain metal layer SD2, the layout of the first auxiliary portion 50a may be facilitated.

[0124] In addition, when the first auxiliary portion 50 a and the initialization signal line 20 are provided in different layers, the first auxiliary portion 50 a and the initialization signal line 20 may be connected through a via hole or a conductive portion.

[0125] In some embodiments, as Figure 4 As shown, since one auxiliary signal line 50 is connected to all initialization signal lines 20 of the same type, the first auxiliary portion 50 a included in one auxiliary signal line 50 can be connected to at least one initialization signal group W of the same type of initialization signal line 20 .

[0126] The first auxiliary portion 50 a may be connected to at least one initialization signal group W in the same initialization signal line 20 , which may include the following situations.

[0127] First: The first auxiliary portion 50a can be connected to some initialization signal groups W in the same initialization signal line 20. In this case, the first auxiliary portion 50a can be connected to one initialization signal group W in the same initialization signal line 20. Alternatively, the first auxiliary portion 50a can be connected to multiple initialization signal groups W in the same initialization signal line 20.

[0128] In this case, the auxiliary signal line 50 can be connected to a portion of the initialization signal line group W in the same type of initialization signal line 20 using the first auxiliary portion 50a. The remaining initialization signal line groups W in the same type of initialization signal line 20 in the display panel 100 can be connected using other auxiliary portions. This method will be described below.

[0129] Second, the first auxiliary portion 50a can be connected to all initialization signal groups W in the same type of initialization signal line 20. In this case, the auxiliary signal line 50 is the first auxiliary portion 50a. One first auxiliary portion 50a can be connected to all initialization signal lines 20 in the same type of initialization signal line 20.

[0130] The above arrangement simplifies the structure of the auxiliary signal lines 50, making it easier to connect all initialization signal lines 20 of the same type in series using a single first auxiliary portion 50a. This eliminates the need for a one-to-one correspondence between the number of adapter lines 40 and the number of initialization signal lines 20, thereby reducing the number of adapter lines 40 in the display panel 100. Furthermore, the space occupied by the adapter lines 40 in the peripheral area SA can be reduced, thereby achieving a narrow bezel on the display panel 100.

[0131] In some embodiments, as Figure 4 As shown, the other end of a patch cord 40 is connected to an initialization signal line group W in the same type of initialization signal line 20 .

[0132] Since all initialization signal lines 20 of the same type have been connected in series using the auxiliary signal line 50, a patch cable 40 can be connected to any initialization signal line 20 to indirectly connect to the remaining initialization signal lines of the same type. Therefore, the other end of the patch cable 40 is connected to an initialization signal line group W of the same type of initialization signal line 20. It can be understood that the other end of the patch cable 40 is directly connected to any initialization signal line 20 of the initialization signal line group W of the same type of initialization signal line 20, rather than being indirectly connected via other initialization signal lines.

[0133] In other words, the number of adapter lines 40 in the same type of adapter line 40 is equal to the number of initialization signal line groups W in the same type of initialization signal line 20, so that multiple adapter lines 40 in the same type of adapter line 40 correspond one-to-one to multiple initialization signal line groups W in the same type of initialization signal line 20.

[0134] Based on this, each initialization signal line group W in the same type of initialization signal line 20 can be directly connected to the adapter line 40, rather than only being indirectly connected to other initialization signal line groups W. This can reduce the loss of the initialization signal transmitted from the adapter line 40 indirectly through other initialization signal line groups W, thereby improving the uniformity of the display panel 100.

[0135] In some embodiments, as Figure 4 As shown, when the other end of the adapter line 40 is connected to an initialization signal line group W of the same type of initialization signal lines 20 , the number of initialization signal lines 20 in each initialization signal line group W of the same type of initialization signal lines 20 is equal.

[0136] The number of initialization signal lines 20 corresponding to each adapter line 40 can be made equal to prevent the number of initialization signal lines 20 in the initialization signal line group W connected to a certain adapter line 40 from being greater than the number of initialization signal lines 20 in the initialization signal line group W connected to other adapter lines 40, which would result in excessive loss of the initialization signal received by the initialization signal line 20 farthest from the adapter line 40 in the initialization signal line group W with a larger number of initialization signal lines 20, thereby causing the problem of poor display uniformity of the display panel 100.

[0137] That is, when the other end of the adapter line 40 is connected to an initialization signal line group W in the same type of initialization signal line 20, the number of initialization signal lines 20 in each initialization signal line group W in the same type of initialization signal line 20 is equal, which is beneficial to further improve the display uniformity of the display panel 100.

[0138] Figure 7is a partial structural diagram of a display panel according to some other embodiments, Figure 8 is a partial layout structure diagram of a display panel according to some embodiments, Figure 9 is a partial structural diagram of a display panel according to some further embodiments.

[0139] In some embodiments, combined Figure 4 、 Figures 6 to 9 As shown, the number of the initialization signal lines 20 in each initialization signal line group W can be any one of 2, 3, 4, 5 or 6. However, the embodiments of the present disclosure are not limited thereto.

[0140] In addition, when the number of initialization signal lines 20 in each initialization signal line group W is within the above-mentioned range of 2 to 6, not only can the number of adapter lines 40 be effectively reduced, but also the problem of poor display uniformity of the display panel 100 can be prevented from occurring due to excessive loss of the initialization signal received by the initialization signal line 20 farthest from the adapter line 40 in the initialization signal line group W connected to the adapter line 40.

[0141] like Figure 4 and Figure 6 As shown, taking the example of two initialization signal lines 20 in each initialization signal line group W, this corresponds to connecting one adapter line 40 to every two initialization signal lines 20 along the column direction Y. In other words, when each initialization signal line group W includes two initialization signal lines 20, the number of adapter lines 40 can be reduced by 50% compared to the case where one adapter line 40 is connected to one initialization signal line 20.

[0142] like Figure 7 and Figure 8 As shown, taking the example of four initialization signal lines 20 in each initialization signal line group W, this corresponds to connecting one adapter line 40 to every four initialization signal lines 20 along the column direction Y. In other words, when each initialization signal line group W includes four initialization signal lines 20, the number of adapter lines 40 can be reduced by 75% compared to the case where one adapter line 40 is connected to one initialization signal line 20.

[0143] like Figure 9 As shown, taking the example of six initialization signal lines 20 in each initialization signal line group W, this corresponds to connecting one adapter line 40 to every six initialization signal lines 20 along the column direction Y. In other words, when each initialization signal line group W includes six initialization signal lines 20, the number of adapter lines 40 can be reduced by 83.3% compared to the case where one adapter line 40 is connected to one initialization signal line 20.

[0144] Figure 10 is a partial structural diagram of a display panel according to some further embodiments.

[0145] In some embodiments, as Figure 10 As shown, with the development of display panel technology, display panels with diverse shapes are becoming more and more common. Based on this, the display panel 100 in the above-mentioned display device can be a special-shaped display panel. In this case, the first border area SA1 includes the first area E and the corner area R. Along the column direction Y, the corner area R is located on at least one side of the first area E. That is, along the column direction Y, the corner area R can be located on one side of the first area E, or the corner area R can be located on both sides of the first area E.

[0146] For example, the corner regions R of the first sub-border region SA11 of the first border region SA1 may be located on both sides of the first region E thereof. That is, the corner regions R of the first sub-border region SA11 may include a first sub-region R1 and a second sub-region R2. The first sub-region R1 of the first sub-border region SA11 is adjacent to the third sub-border region SA21, and the second sub-region R2 of the first sub-border region SA12 is adjacent to the fourth sub-border region SA22. The same applies to the second sub-border region SA12 of the first border region SA1.

[0147] The display area AA includes a first display area AA1 and a second display area AA2. Along the row direction X, the corner area R overlaps with the first display area AA1, and the first area E overlaps with the second display area AA2. Multiple patch cables 40 are located in the first area E, and the patch cables 40 are connected to the initialization signal line group W located in the second display area AA2.

[0148] Based on this, the adapter lines 40 in the first frame area SA1 can be concentrated in the first area E, and the adapter lines 40 in the first area E can be connected to the initialization signal line group W in the second display area AA2 to transmit the initialization signal from the initialization signal bus 30 to the initialization signal line group W in the second display area AA2. In addition, since all initialization signal lines 20 of the same type of initialization signal line 20 have been connected in series using the auxiliary signal line 50 (first auxiliary portion 50a), the adapter lines 40 in the first area E can use the initialization signal line group W in the second display area AA2 and the first auxiliary portion 50a to transmit the initialization signal from the initialization signal bus 30 to the first auxiliary portion 50a located in the first display area AA1, and then use the first auxiliary portion 50a located in the first display area AA1 to transmit the initialization signal to the initialization signal line group W in the first display area AA1.

[0149] Therefore, no additional adapter line 40 is required at the corner area R to connect the initialization signal line group W in the second display area AA2 . Therefore, the space of the corner area R can be saved, so as to realize a narrow frame of the display panel 100 .

[0150] It should be noted that if Figure 10 As shown, the number of initialization signal lines 20 in at least two initialization signal line groups W is different. It can be understood that the number of initialization signal lines 20 in the initialization signal line W closest to the corner area R can be greater than the number of initialization signal lines 20 in other initialization signal line groups W. In other words, relative Figure 4 The display panel 100 shown can merge the initialization signal line group W corresponding to the corner area R and the initialization signal line W adjacent to it and corresponding to the first area E into one initialization signal line group W, so as to eliminate the adapter line 40 connected to the initialization signal line group W corresponding to the corner area R, thereby eliminating the need to set the adapter line 40 at the position of the corner area R, saving space in the corner area R, and facilitating the realization of a narrow frame of the display panel 100.

[0151] The above, combined with the relevant drawings, primarily describes the design of the first auxiliary portion 50a (auxiliary signal line 50) when disposed in the display area AA of the display panel 100. The following, combined with the relevant drawings, describes the design of the second auxiliary portion 50b (auxiliary signal line) disposed in the peripheral area SA of the display panel 100.

[0152] Figure 11 is a partial structural diagram of a display panel according to some further embodiments, Figure 12 for Figure 11 A partial enlarged view of C2 in the middle.

[0153] in, Figure 11 To clearly illustrate the relationship between the initialization signal line 20, the initialization signal bus 30 and the adapter line 40, Figure 11 Only the lower half of the display panel 100 is shown for illustration.

[0154] In some embodiments, combined Figure 11 and Figure 12 As shown, the auxiliary signal line 50 includes a second auxiliary portion 50b. The second auxiliary portion 50b is located in the peripheral area SA. The orthographic projection of the second auxiliary portion 50b on the base substrate 10 is located on the side of the orthographic projections of all the patch lines 40 on the base substrate 10 that is closer to the display area AA. In other words, the orthographic projection of the second auxiliary portion 50b on the base substrate 10 is located between the orthographic projections of all the patch lines 40 on the base substrate 10 and the orthographic projections of all the initialization signal lines 20 on the base substrate 10, thereby connecting the patch lines 40 and the initialization signal lines 20 using the second auxiliary portion 50b.

[0155] The following description uses the auxiliary signal line 50 as the first auxiliary signal line 51 in the first type of auxiliary signal line 50A. In this case, a second auxiliary portion 50b is provided in the peripheral area SA of the display panel 100. The second auxiliary portion 50b can be disposed adjacent to the display area AA and connected to the end of each initialization signal line 20 in at least one first initialization signal line group W1.

[0156] Based on this, the second auxiliary part 50b located in the peripheral area SA can be connected to the first adapter line 41 also located in the peripheral area SA to receive the first initialization signal transmitted from the first initialization signal bus 31, and the first initialization signal can be transmitted to each first initialization signal line Vinit1 connected to the second auxiliary part 50b.

[0157] Therefore, the first adapter line 41 does not need to correspond to each first initialization signal line Vinit1 one by one. By connecting the first adapter line 41 to the second auxiliary portion 50b, it can be connected to each initialization signal line 20 in at least one first initialization signal line group W1. The same applies to the second adapter line 42.

[0158] Thus, the number of adapter lines 40 in the display panel 100 can be effectively reduced. Furthermore, the space occupied by the adapter lines 40 in the peripheral area SA can be reduced, so as to realize a narrow frame of the display panel 100.

[0159] In addition, since the second auxiliary portion 50b is connected in series between the adapter line 40 and the initialization signal line 20, the initialization signal line 20 only needs to receive the initialization signal transmitted via the second auxiliary portion 50b. Compared with the method of using the first auxiliary portion 50a, in which part of the initialization signal line 20 needs to receive the initialization signal transmitted via the first auxiliary portion 50a and other initialization signal lines 20, the loss of the initialization signal can be reduced, which is beneficial to improving the brightness uniformity of the display panel 100.

[0160] Furthermore, the second auxiliary portion 50 b is disposed in the peripheral area SA, which can better prevent the auxiliary signal line 50 from affecting the aperture ratio of the display panel 100 compared to the case where the first auxiliary portion 50 a is disposed in the display area AA.

[0161] Figure 13 FIG. 4 is a partial layout structure diagram of a display panel according to some embodiments.

[0162] In some examples, such as Figure 13 As shown, the second auxiliary portion 50b may be located in the second source / drain metal layer SD2, or may be located in other film layers within the display panel 100. When the second auxiliary portion 50b is disposed in the second source / drain metal layer SD2, the layout of the second auxiliary portion 50b may be facilitated.

[0163] In addition, when the second auxiliary portion 50 b and the initialization signal line 20 are provided in different layers, the second auxiliary portion 50 b and the initialization signal line 20 may be connected through a via hole or a conductive portion.

[0164] In some embodiments, combined Figure 11 and Figure 12 As shown, since one auxiliary signal line 50 is connected to all initialization signal lines 20 of the same type, the second auxiliary portion 50 b included in one auxiliary signal line 50 can be connected to at least one initialization signal group W of the same type of initialization signal line 20 .

[0165] The second auxiliary portion 50 b may be connected to at least one initialization signal group W in the same initialization signal line 20 , which may include the following situations.

[0166] First, the second auxiliary portion 50b can be connected to some of the initialization signal groups W in the same initialization signal line 20. In this case, the second auxiliary portion 50b can be connected to one initialization signal group W in the same initialization signal line 20. Alternatively, the second auxiliary portion 50b can be connected to multiple initialization signal groups W in the same initialization signal line 20.

[0167] In this case, the auxiliary signal line 50 can be connected to a portion of the initialization signal line group W in the same type of initialization signal line 20 using the second auxiliary portion 50b. The remaining initialization signal line group W in the same type of initialization signal line 20 in the display panel 100 can be connected using another auxiliary portion (the first auxiliary portion). This method will be described below.

[0168] Second: The second auxiliary portion 50b can be connected to all initialization signal groups W in the same type of initialization signal line 20. In this case, the auxiliary signal line 50 is the second auxiliary portion 50b. One second auxiliary portion 50b can be connected to all initialization signal lines 20 in the same type of initialization signal line 20.

[0169] The above arrangement simplifies the structure of the auxiliary signal lines 50, making it easier to connect all initialization signal lines 20 of the same type in series using a single second auxiliary portion 50b. This eliminates the need for a one-to-one correspondence between the number of adapter lines 40 and the number of initialization signal lines 20, thereby reducing the number of adapter lines 40 in the display panel 100. Furthermore, the space occupied by the adapter lines 40 in the peripheral area SA can be reduced, thereby achieving a narrow bezel on the display panel 100.

[0170] In some embodiments, combined Figure 11 and Figure 12As shown, one end of a patch cord 40 is connected to an initialization signal bus 30 , and the other end of the patch cord 40 is connected to an initialization signal line group W in the same type of initialization signal line 20 through the second auxiliary portion 50 b .

[0171] Since the second auxiliary portion 50b of the auxiliary signal line 50 has been used to connect multiple initialization signal lines 20 in at least one initialization signal line group W in series, a patch cord 40 can be connected to the second auxiliary portion 50b to achieve connection with the multiple initialization signal line groups W connected to the second auxiliary portion 50b.

[0172] Therefore, the other end of the so-called patch cable 40 is connected to an initialization signal line group W in the same type of initialization signal line 20. It can be understood that, along the row direction X, the patch cable 40 overlaps with any initialization signal line 20 in the same type of initialization signal line 20 in the same type of initialization signal line group W. In other words, the number of patch cables 40 in the same type of patch cable 40 is equal to the number of initialization signal line groups W in the same type of initialization signal line 20, so that multiple patch cables 40 in the same type of patch cable 40 correspond one-to-one to multiple initialization signal line groups W in the same type of initialization signal line 20.

[0173] Based on this, each initialization signal line group W in the same type of initialization signal lines 20 can correspond to one adapter line 40 , which can reduce the loss of the initialization signal and thus improve the uniformity of the display panel 100 .

[0174] In some embodiments, combined Figure 11 and Figure 12 As shown, one end of an adapter line 40 is connected to an initialization signal bus 30, and the other end of the adapter line 40 is connected to an initialization signal line group W in the same type of initialization signal line 20 through the second auxiliary part 50b. In the same type of initialization signal line 20, the number of initialization signal lines 20 in each initialization signal line group W is equal.

[0175] The number of initialization signal lines 20 corresponding to each adapter line 40 can be made equal to prevent the number of initialization signal lines 20 in the initialization signal line group W connected to a certain adapter line 40 from being greater than the number of initialization signal lines 20 in the initialization signal line group W connected to other adapter lines 40, which would result in excessive loss of the initialization signal received by the initialization signal line 20 farthest from the adapter line 40 in the initialization signal line group W with a larger number of initialization signal lines 20, thereby causing the problem of poor display uniformity of the display panel 100.

[0176] That is, when the other end of the adapter line 40 is connected to an initialization signal line group W in the same type of initialization signal line 20, the number of initialization signal lines 20 in each initialization signal line group W in the same type of initialization signal line 20 is equal, which is beneficial to further improve the display uniformity of the display panel 100.

[0177] In some embodiments, combined Figure 11 and Figure 12 As shown, the number of the initialization signal lines 20 in each initialization signal line group W can be any one of 2, 3, 4, 5 or 6. However, the embodiments of the present disclosure are not limited thereto.

[0178] In addition, when the number of initialization signal lines 20 in each initialization signal line group W is within the above-mentioned range of 2 to 6, not only can the number of adapter lines 40 be effectively reduced, but also the problem of poor display uniformity of the display panel 100 can be prevented from occurring due to excessive loss of the initialization signal received by the initialization signal line 20 farthest from the adapter line 40 in the initialization signal line group W connected to the adapter line 40.

[0179] For example, if each initialization signal line group W includes two initialization signal lines 20, this means that every two initialization signal lines 20 are connected to one adapter line 40. In other words, when each initialization signal line group W includes two initialization signal lines 20, the number of adapter lines 40 can be reduced by 50% compared to when one adapter line 40 is connected to one initialization signal line 20.

[0180] Figure 14 is a partial structural diagram of a display panel according to some further embodiments.

[0181] In some embodiments, as Figure 14 As shown, the display panel 100 in the display device can be a special-shaped display panel. In this case, a plurality of adapter lines 40 are located in the first area E, and the adapter lines 40 are connected to the initialization signal line group W located in the second display area AA2.

[0182] Based on this, the adapter lines 40 in the first frame area SA1 can be concentrated in the first area E, and the adapter lines 40 in the first area E can use the second auxiliary portion 50b located in the first area E to connect to the initialization signal line group W in the second display area AA2, and transmit the initialization signal from the initialization signal bus 30 to the initialization signal line group W in the second display area AA2. In addition, since all initialization signal lines 20 of the same type of initialization signal line 20 have been connected in series using the auxiliary signal line 50 (the second auxiliary portion 50b), the adapter lines 40 in the first area E can use the second auxiliary portion 50b located in the first area E to transmit the initialization signal from the initialization signal bus 30 to the second auxiliary portion 50b located in the corner area R, and then use the second auxiliary portion 50b located in the corner area R to transmit the initialization signal to the initialization signal line group W in the first display area AA1.

[0183] Therefore, no additional adapter line 40 is required at the corner area R to connect the initialization signal line group W in the first display area AA1 . Therefore, the space of the corner area R can be saved, so as to realize a narrow frame of the display panel 100 .

[0184] Figure 15 is a partial structural diagram of a display panel according to some further embodiments, Figure 16 FIG is a partial structural diagram of a display panel according to some other embodiments. Figure 15 and Figure 16 To clearly illustrate the relationship between the initialization signal line 20, the initialization signal bus 30 and the adapter line 40, Figure 15 and Figure 16 Only the lower half of the display panel 100 is shown for illustration.

[0185] In other embodiments, Figure 15 and Figure 16 As shown, the display panel 100 in the above-mentioned display device can be a special-shaped display panel. When the first auxiliary portion 50a is configured to connect to at least all of the initialization signal lines 20 of the same type located in the second display area AA2 and the second auxiliary portion 50b is configured to connect to at least all of the initialization signal lines 20 of the same type located in the first display area AA1, the auxiliary signal line 50 can be configured to include a first auxiliary portion 50a and a second auxiliary portion 50b. In this case, multiple patch cords 40 are located in the first area E, and among the multiple patch cords 40, the patch cords 40 adjacent to the corner area R are the first target patch cords 40a, and the remaining are the second target patch cords 40b.

[0186] Based on this, the first target adapter line 40a near the corner area R in the first area E is connected to the second auxiliary part 50b, and the second target adapter line 40b other than the first target adapter line 40a in the first area E is connected to at least one initialization signal line group W of the same type of initialization signal line 20 located in the second display area AA2.

[0187] Because the second auxiliary portion 50b has been connected to at least all of the initialization signal lines 20 of the same type located in the first display area AA1, that is, the second auxiliary portion 50b has been used to connect at least all of the initialization signal lines 20 of the same type located in the first display area AA1 in the display area AA in series, the first target patch cable 40a can be used to transmit the initialization signal to at least one initialization signal line group W of the same type of initialization signal lines 20 located in the first display area AA1, so that all of the initialization signal line groups W of the same type of initialization signal lines 20 located in the first display area AA1 receive the initialization signal. Furthermore, because the first auxiliary portion 50a has been connected to at least all of the initialization signal lines 20 of the same type located in the second display area AA2, That is, the first auxiliary part 50a is used to connect in series at least all the initialization signal lines 20 of the same type in the second display area AA2 in the display area AA, and then the second target adapter line 40b can be used to transmit the initialization signal to at least one initialization signal line group W of the same type of initialization signal line 20 located in the second display area AA2, so that all the initialization signal line groups W of the same type of initialization signal line 20 located in the second display area AA2 receive the initialization signal.

[0188] Therefore, no additional adapter line 40 is required at the corner area R to connect the initialization signal line group W in the first display area AA1 . Therefore, the space of the corner area R can be saved, so as to realize a narrow frame of the display panel 100 .

[0189] The first auxiliary portion 50a is connected to at least all the initialization signal lines 20 of the same type in the second display area AA2, which may include the following two situations:

[0190] The first type: the first auxiliary portion 50 a is connected to all the initialization signal lines 20 of the same type located in the second display area AA2 .

[0191] The second type: the first auxiliary portion 50 a is connected to at least all of the initialization signal lines 20 of the same type located in the display area AA (the first display area AA1 and the second display area AA2 ).

[0192] The second auxiliary portion 50b is connected to at least all the initialization signal lines 20 of the same type of initialization signal lines 20 located in the first display area AA1, which may include the following two situations:

[0193] The first type: the second auxiliary portion 50 b is connected to all the initialization signal lines 20 of the same type located in the first display area AA1 .

[0194] The second type: the second auxiliary portion 50 b is connected to all the initialization signal lines 20 of the same type located in the display area AA (the first display area AA1 and the second display area AA2 ).

[0195] As described above, any of the two configurations of the first auxiliary portion 50a can be combined with any of the two configurations of the second auxiliary portion 50b to form the auxiliary signal line 50. That is, the auxiliary signal line 50 can include the following three configurations:

[0196] The first one: Figure 15 As shown, the first auxiliary portion 50a is connected to all the initialization signal lines 20 of the same type located in the second display area AA2, and the second auxiliary portion 50b is connected to all the initialization signal lines 20 of the same type located in the first display area AA1.

[0197] At this time, the first auxiliary portion 50a can be located in the second display area AA2, and the second auxiliary portion 50b can be located at least in the corner area R. That is, the second auxiliary portion 50b can extend to connect with the first target patch cord 40a, or the second auxiliary portion 50b can extend into the first area E and connect with the initialization signal bus 30, so that the second auxiliary portion 50b can receive the initialization signal transmitted from the initialization signal bus 30. Alternatively, the first auxiliary portion 50a can be located in the second display area AA2, and the second auxiliary portion 50b can be located in the corner area R, and then a patch cord is provided extending from the corner area R to the first area E to connect the second auxiliary portion 50b with the first target patch cord 40a located in the first area E. Alternatively, the second auxiliary portion 50b can be connected to the initialization signal bus 30 in the first area E.

[0198] The second type: the first auxiliary portion 50a is connected to all the initialization signal lines 20 of the same type located in the second display area AA2, and the second auxiliary portion 50b is connected to all the initialization signal lines 20 of the same type located in the display area AA (the first display area AA1 and the second display area AA2).

[0199] At this time, the first auxiliary portion 50 a may be located in the first area E, and the second auxiliary portion 50 b may be located in the first bezel area SA1 .

[0200] The third type: the first auxiliary portion 50a is connected to all the initialization signal lines 20 of the same type located in the display area AA (the first display area AA1 and the second display area AA2), and the second auxiliary portion 50b is connected to all the initialization signal lines 20 of the same type located in the first display area AA1.

[0201] At this time, the first auxiliary part 50a is located in the display area AA, and the second auxiliary part 50b can extend to connect with the first target adapter line 40a, or, the second auxiliary part 50b can extend into the first area E and connect with the initialization signal bus 30, so that the second auxiliary part 50b can receive the initialization signal transmitted from the initialization signal bus 30.

[0202] The fourth type: Figure 16 As shown, the first auxiliary portion 50a is connected to all initialization signal lines 20 of the same type of initialization signal lines 20 located in the display area AA (the first display area AA1 and the second display area AA2), and the second auxiliary portion 50b is connected to all initialization signal lines 20 of the same type of initialization signal lines 20 located in the display area AA (the first display area AA1 and the second display area AA2).

[0203] At this time, the first auxiliary portion 50 a is located in the display area AA, and the second auxiliary portion 50 b is located in the first frame area SA1 .

[0204] Regardless of any of the aforementioned arrangements for the auxiliary signal lines 50, the first target adapter line 40a located in the first area E can be connected to the second auxiliary portion 50b to achieve connection with at least all of the initialization signal lines 20 within the first display area AA1. Therefore, no additional adapter line 40 is required at the corner area R to connect the initialization signal line group W within the first display area AA1. This saves space in the corner area R, facilitating a narrow bezel for the display panel 100.

[0205] However, in the above-mentioned second and third settings of the auxiliary signal lines 50, a part of the initialization signal lines 20 is connected to one auxiliary part, and the other part of the initialization signal lines 20 is connected to both auxiliary connection parts, which will cause the initialization signals received by the two parts of the initialization signal lines to be different, which is likely to affect the brightness uniformity of the display panel 100.

[0206] The fourth arrangement of the auxiliary signal lines 50 allows each initialization signal line to be connected to both auxiliary connection portions. That is, the initialization signal lines 20 located in the first display area AA1 are all connected to the first auxiliary portion 50a and the second auxiliary portion 50b, and the initialization signal lines 20 located in the second display area AA2 are also all connected to the first auxiliary portion 50a and the second auxiliary portion 50b. Compared to the second and third arrangements of the auxiliary signal lines 50, this arrangement can also reduce the differences in the initialization signals received by each initialization signal line 20, thereby improving the brightness uniformity of the display panel 100.

[0207] The first arrangement of the auxiliary signal lines 50 allows each initialization signal line to be connected to only one type of auxiliary connection portion. That is, the initialization signal line 20 located in the first display area AA1 is connected only to the first auxiliary portion 50a, while the initialization signal line 20 located in the second display area AA2 is connected only to the second auxiliary portion 50b. Compared to the second and third arrangements of the auxiliary signal lines 50, this arrangement can reduce the differences in the initialization signals received by each initialization signal line 20, thereby improving the brightness uniformity of the display panel 100. Furthermore, compared to the fourth arrangement of the auxiliary signal lines 50, the first arrangement of the auxiliary signal lines 50 can simplify the structure of the auxiliary signal lines 50.

[0208] In other embodiments, the display panel 100 is a display panel that can realize split-screen control. At this time, along the row direction X, the display area AA of the display panel 100 includes a first sub-area and a second sub-area, and the initialization signal line 20 in the display panel 100 needs to be disconnected at the boundary between the first sub-area and the second sub-area, so as to realize separate control of the pixel driving circuit Q in the two sub-areas. Since the initialization signal line 20 in the display panel 100 needs to be disconnected at the boundary between the first sub-area and the second sub-area, it is necessary to provide a switching line 40 and an initialization signal bus 30 in the first sub-frame area SA11 and the second sub-frame area SA12 of the first frame area SA1, so as to transmit the initialization signal for the initialization signal line in different sub-areas of the display area AA. At this time, the specific setting of the first sub-frame area SA11 can be combined with the description of any of the above embodiments, and the structure of the second sub-frame area SA12 can be symmetrical with the structure of the first sub-frame area SA11, which will not be repeated here.

[0209] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: It has a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a first frame area. Along the row direction, the first frame area is located on at least one side of the display area; The display panel includes: substrate; A plurality of initialization signal lines are located on the base substrate of the display area, wherein any one of the initialization signal lines includes a plurality of initialization signal lines, and the plurality of initialization signal lines extend in a row direction and are arranged in a column direction; Wherein, along the column direction, among the same type of initialization signal lines, all the initialization signal lines are divided into a plurality of initialization signal line groups, and one of the initialization signal line groups includes a plurality of the initialization signal lines; A plurality of pixel driving circuits are located on the base substrate of the display area, and the plurality of pixel driving circuits are arranged in multiple rows and columns; a row of the pixel driving circuits is electrically connected to the plurality of initialization signal lines; a plurality of initialization signal buses located on the base substrate in the first border region, wherein each of the initialization signal buses includes at least one initialization signal bus extending along the first border region, and an extension direction of the initialization signal bus intersecting with an extension direction of the initialization signal line; A plurality of auxiliary signal lines are located on the base substrate, wherein each type of auxiliary signal line includes at least one auxiliary signal line, wherein an extension direction of the auxiliary signal line intersects an extension direction of the initialization signal line, and one auxiliary signal line is connected to all the initialization signal lines of the same type; a plurality of patch cords located on the base substrate in the peripheral area, wherein any patch cord comprises a plurality of patch cords, one end of each patch cord being connected to one of the initialization signal buses, and the other end of each patch cord being connected to at least one initialization signal line group of the same type of initialization signal line; The auxiliary signal line includes a first auxiliary portion, the first auxiliary portion is located in the display area, and an orthographic projection of the first auxiliary portion on the base substrate does not overlap with an orthographic projection of the pixel driving circuit on the base substrate; The auxiliary signal line includes a second auxiliary portion, and the orthographic projection of the second auxiliary portion on the base substrate is located on a side of the orthographic projection of all the adapter lines on the base substrate close to the display area.

2. The display panel according to claim 1, wherein: An orthographic projection of one of the first auxiliary parts on the base substrate is located between orthographic projections of two adjacent columns of the pixel driving circuits on the base substrate.

3. The display panel according to claim 1, wherein: The first auxiliary portion is connected to all of the initialization signal lines of the same type.

4. The display panel according to claim 1, wherein: The other end of one of the adapter wires is connected to one of the initialization signal line groups of the same type of initialization signal line; and among the same type of initialization signal line, the number of the initialization signal lines in each of the initialization signal line groups is equal.

5. The display panel according to any one of claims 1 to 4, wherein: The second auxiliary portion is connected to all of the initialization signal line groups of the same type of initialization signal lines.

6. The display panel according to any one of claims 1 to 4, wherein: One end of the adapter line is connected to one of the initialization signal buses, and the other end of the adapter line is connected to an initialization signal line group of the same type of initialization signal line through the second auxiliary part, and among the same type of initialization signal lines, the number of the initialization signal lines in each initialization signal line group is equal.

7. The display panel according to any one of claims 1 to 4, wherein: The first border area includes a first area and a corner area, and along the column direction, the corner area is located on at least one side of the first area; The display area includes a first display area and a second display area, and along the row direction, the corner area overlaps with the first display area, and the first area overlaps with the second display area; A plurality of the adapter lines are located in the first area, and the adapter lines are connected to the initialization signal line group located in the second display area.

8. The display panel according to claim 1, wherein: The first border area includes a first area and a corner area, and along the column direction, the corner area is located on at least one side of the first area; The display area includes a first display area and a second display area, and along the row direction, the corner area overlaps with the first display area, and the first area overlaps with the second display area; The auxiliary signal line includes: a first auxiliary portion located in the display area, an orthographic projection of the first auxiliary portion on the base substrate having no overlap with an orthographic projection of the pixel driving circuit on the base substrate, and the first auxiliary portion being connected to at least all of the same type of initialization signal lines located in the second display area; a second auxiliary portion, wherein an orthographic projection of the second auxiliary portion on the base substrate is located on a side of the orthographic projections of all the adapter lines on the base substrate close to the display area, and the second auxiliary portion is connected to at least all of the same type of initialization signal lines located in the first display area; The plurality of patch cords are located in the first area, and among the plurality of patch cords, the patch cords adjacent to the corner area are first target patch cords, and the remaining patch cords are second target patch cords; The first target patch cord is connected to the second auxiliary portion, and one of the second target patch cords is connected to at least one of the initialization signal line groups located in the second display area.

9. The display panel according to claim 8, wherein: The first auxiliary portion is at least located in the second display area, and the first auxiliary portion is connected to all the initialization signal lines of the same type located in the second display area; The second auxiliary portion is located in the corner area and is connected to all the initialization signal lines of the same type located in the first display area.

10. The display panel according to claim 1, wherein The plurality of initialization signal lines include two types of initialization signal lines, and the two types of initialization signal lines include a first type of initialization signal line and a second type of initialization signal line; The display panel further includes: The two initialization signal buses are respectively a first initialization signal bus and a second initialization signal bus; Two types of auxiliary signal lines are a first type of auxiliary signal line and a second type of auxiliary signal line; the first type of auxiliary signal line is connected to all the initialization signal lines included in the first type of initialization signal lines, and the second type of auxiliary signal line is connected to all the initialization signal lines included in the second type of initialization signal lines, Two types of adapter cables are respectively a first type of adapter cable and a second type of adapter cable, one end of one of the first type of adapter cables is connected to the first type of initialization signal bus, and the other end of the first type of adapter cable is connected to at least one of the initialization signal line groups in the first type of initialization signal line; one end of one of the second type of adapter cables is connected to a second type of initialization signal bus, and the other end of the second type of adapter cable is connected to at least one of the initialization signal line groups in the second type of initialization signal line.

11. A display device, characterized in that: include: cover; The display panel according to any one of claims 1 to 10, wherein the cover plate is located on a light-emitting side of the display panel.

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