Shift register, gate driving circuit and display panel

Abstract

The present disclosure provides a shift register, a gate driving circuit, and a display panel, relating to the field of display technologies. The shift register includes an input circuit, a cascaded output circuit, a control circuit, and a scan output circuit; the input circuit is configured to control the levels of a first node and a control node under the control of a first clock signal and a cascaded output signal of a previous-level cascaded output circuit; the cascaded output circuit is configured to output a cascaded output signal under the control of the first node, the control node, and a second clock signal; the control circuit is configured to control the level of a fourth node under the control of the first node, the control node, and the first clock signal; the scan output circuit is configured to output a scan signal under the control of the control node, the fourth node, and an output clock signal; the effective duration of the high level of the cascaded output signal output by the cascaded output circuit is less than the effective duration of the high level of the scan signal output by the scan output circuit. The present disclosure can improve the display quality of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more particularly, to a shift register, a gate driving circuit, and a display panel. Background Art

[0002] In the display field, such as in OLED (organic light emitting diode) displays, the application of LTPO (low temperature polycrystalline oxide) is becoming more and more widespread.

[0003] For narrow bezel considerations, a gate driving circuit GOA (gate driving circuit) generally requires P-type LTPS (low temperature polycrystalline silicon). The gates of some TFTs (thin film transistors) in a pixel driving circuit PDC (pixel driving circuit) need to input a high-level pulse waveform to effectively output. Therefore, it is very crucial to use a P-type TFT to output a high-level pulse waveform. At the same time, due to the requirements of high ppi (pixel density) and high refresh rate, the waveform to be output should be as wide as possible.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a shift register, a gate driving circuit, and a display panel to improve the display quality of the display panel.

[0006] According to one aspect of the present disclosure, a shift register is provided. The shift register includes an input circuit, a cascaded output circuit, a control circuit, and a scan output circuit;

[0007] The input circuit is configured to control the levels of a first node and a control node under the control of a first clock signal and a cascaded output signal of a previous-stage cascaded output circuit;

[0008] The cascaded output circuit is configured to output a cascaded output signal under the control of the first node, the control node, and a second clock signal;

[0009] The control circuit is configured to control the level of a fourth node under the control of the first node, the control node, and the first clock signal;

[0010] The scan output circuit is configured to output a scan signal under the control of the control node, the fourth node, and an output clock signal;

[0011] The effective duration of the cascaded output signal output by the cascaded output circuit is less than the effective duration of the scan signal output by the scan output circuit.

[0012] In an embodiment of the present disclosure, the cascaded output circuit includes a first cascaded output sub - circuit and a second cascaded output sub - circuit;

[0013] A first pole of the first cascaded output sub - circuit is electrically connected to a first power supply voltage terminal, a second pole is electrically connected to a cascaded output signal terminal, and a control terminal is electrically connected to the control node. The first cascaded output sub - circuit is configured to load the first power supply voltage to the cascaded output signal terminal in response to the selected - on electrical level of the control node;

[0014] A first pole of the second cascaded output sub - circuit is electrically connected to a second clock signal terminal, a second pole of the second cascaded output sub - circuit is electrically connected to the cascaded output signal terminal, and a control terminal of the second cascaded output sub - circuit is electrically connected to the first node. The second cascaded output sub - circuit is configured to load the voltage of the second clock signal to the cascaded output signal terminal in response to the selected - on electrical level of the first node.

[0015] In an embodiment of the present disclosure, the scan output circuit includes a first scan output sub - circuit and a second scan output sub - circuit;

[0016] A first pole of the first scan output sub - circuit is electrically connected to a second power supply voltage terminal, a second pole is electrically connected to a scan output signal terminal, and a control terminal is electrically connected to a control node. The first scan output sub - circuit is configured to output the second power supply voltage to the scan output signal terminal in response to the selected - on electrical level of the control node;

[0017] A first pole of the second scan output sub - circuit is electrically connected to an output clock signal terminal, a second pole is electrically connected to the scan output signal terminal, and a control terminal is electrically connected to a fourth node. The second scan output sub - circuit is configured to output the voltage of the output clock signal to the scan output signal terminal in response to the selected - on electrical level of the fourth node.

[0018] In an embodiment of the present disclosure, the input circuit includes a cascaded input sub - circuit, a first sub - circuit, and a second sub - circuit;

[0019] A first pole of the cascaded input sub - circuit is electrically connected to a cascaded input signal terminal, a second pole of the cascaded input sub - circuit is electrically connected to the first node, and a control terminal of the cascaded input sub - circuit is electrically connected to a first clock signal terminal. The cascaded input sub - circuit is configured to load the voltage of the cascaded input signal to the first node in response to the selected - on electrical level of the first clock signal;

[0020] The first pole of the first sub - circuit is electrically connected to the second power - supply voltage terminal, the second pole is electrically connected to the control node, and the control terminal is electrically connected to the first clock - signal terminal. The first sub - circuit is configured to load the second power - supply voltage to the control node in response to the selected - on level of the first clock signal;

[0021] The first pole of the second sub - circuit is electrically connected to the first clock - signal terminal, the second pole is electrically connected to the control node, and the control terminal is electrically connected to the first node. The second sub - circuit is configured to load the voltage of the first clock signal to the control node in response to the selected - on level of the first node.

[0022] In an embodiment of the present disclosure, the control circuit includes a third sub - circuit, a fourth sub - circuit, and a fifth sub - circuit;

[0023] The first pole of the third sub - circuit is electrically connected to the first clock - signal terminal, the second pole is electrically connected to the third node, and the control terminal is electrically connected to the control node. The third sub - circuit is configured to load the voltage of the first clock signal to the third node in response to the selected - on level of the control node;

[0024] The first pole of the fourth sub - circuit is electrically connected to the second power - supply voltage terminal, the second pole is electrically connected to the third node, and the control terminal is electrically connected to the first node. The fourth sub - circuit is configured to load the second power - supply voltage to the third node in response to the selected - on level of the first node;

[0025] The first pole of the fifth sub - circuit is electrically connected to the third node, the second pole is electrically connected to the fourth node, and the control terminal is electrically connected to either the second clock - signal terminal or the second power - supply voltage terminal. The fifth sub - circuit is configured to load the voltage of the third node to the fourth node in response to the selected - on level of the second clock signal or the second power - supply voltage.

[0026] In an embodiment of the present disclosure, the first cascaded - output sub - circuit includes a third transistor and a first capacitor;

[0027] The first pole of the third transistor, the first electrode plate of the first capacitor, and the first power - supply voltage terminal are electrically connected. The second pole of the third transistor is electrically connected to the cascaded - output signal terminal. The control terminal of the third transistor, the second electrode plate of the first capacitor, and the control node are electrically connected. The third transistor is configured to load the first power - supply voltage to the cascaded - output signal terminal in response to the selected - on level of the control node;

[0028] The second cascaded - output sub - circuit includes an eighth transistor and a second capacitor;

[0029] A first pole of the eighth transistor is electrically connected to the second clock signal terminal. A second pole of the eighth transistor, a second electrode plate of the second capacitor, and a cascaded output signal terminal are electrically connected to each other. A control terminal of the eighth transistor, a first electrode plate of the second capacitor, and a second node are electrically connected to each other. The eighth transistor is configured to load a voltage of the second clock signal to the cascaded output signal terminal in response to an electrified level of the second node.

[0030] In an embodiment of the present disclosure, the first scan output sub - circuit includes a fifteenth transistor and a fourth capacitor;

[0031] A first pole of the fifteenth transistor is electrically connected to the second power supply voltage terminal, a second pole is electrically connected to the scan output signal terminal. A control terminal of the fifteenth transistor, a first electrode plate of the fourth capacitor, and the control node are electrically connected to each other. The fifteenth transistor is configured to output the second power supply voltage to the scan output signal terminal in response to an electrified level of the control node; A second electrode plate of the fourth capacitor is electrically connected to the first clock signal terminal;

[0032] The second scan output sub - circuit includes a fourteenth transistor and a third capacitor;

[0033] A first pole of the fourteenth transistor is electrically connected to the output clock signal terminal, a second pole is electrically connected to the scan output signal terminal. A control terminal of the fourteenth transistor, a first electrode plate of the third capacitor, and the fourth node are electrically connected to each other. The fourteenth transistor is configured to output a voltage of the output clock signal to the scan output signal terminal in response to an electrified level of the fourth node.

[0034] In an embodiment of the present disclosure, the cascaded input sub - circuit includes a second transistor;

[0035] A first pole of the second transistor is electrically connected to the cascaded input signal terminal, a second pole is electrically connected to the first node, and a control terminal is electrically connected to the first clock signal terminal. The second transistor is configured to load a voltage of the cascaded input signal to the first node in response to an electrified level of the first clock signal;

[0036] The first sub - circuit includes a first transistor;

[0037] A first pole of the first transistor is electrically connected to the second power supply voltage terminal, a second pole is electrically connected to the control node, and a control terminal is electrically connected to the first clock signal terminal. The first transistor is configured to load the second power supply voltage to the control node in response to an electrified level of the first clock signal;

[0038] The second sub-circuit includes a fourth transistor;

[0039] A first pole of the fourth transistor is electrically connected to the first clock signal terminal, a second pole is electrically connected to the control node, and a control end is electrically connected to the first node. The fourth transistor is configured to load the voltage of the first clock signal to the control node in response to an electrified level of the first node.

[0040] In an embodiment of the present disclosure, the third sub-circuit includes a tenth transistor;

[0041] A first pole of the tenth transistor is electrically connected to the first clock signal terminal, a second pole is electrically connected to the third node, and a control end is electrically connected to the control node. The tenth transistor is configured to load the voltage of the first clock signal to the third node in response to an electrified level of the control node;

[0042] The fourth sub-circuit includes a ninth transistor;

[0043] A first pole of the ninth transistor is electrically connected to the second power supply voltage terminal, a second pole is electrically connected to the third node, and a control end is electrically connected to the first node. The ninth transistor is configured to load the second power supply voltage to the third node in response to an electrified level of the first node;

[0044] The fifth sub-circuit includes a twelfth transistor;

[0045] A first pole of the twelfth transistor is electrically connected to the third node, a second pole of the twelfth transistor is electrically connected to the fourth node, and a control end of the twelfth transistor is electrically connected to any one of the second clock signal terminal and the second power supply voltage terminal. The twelfth transistor is configured to load the voltage of the third node to the fourth node in response to an electrified level of the second clock signal or the second power supply voltage.

[0046] In an embodiment of the present disclosure, the shift register further includes a sixteenth transistor;

[0047] A first pole of the sixteenth transistor, a control end of the sixteenth transistor and the first clock signal terminal are electrically connected to each other, a second pole of the sixteenth transistor is electrically connected to a first electrode plate of the fourth capacitor, and the sixteenth transistor is configured to load the voltage of the first clock signal to the first electrode plate of the fourth capacitor in response to an electrified level of the first clock signal.

[0048] In an embodiment of the present disclosure, the control circuit further includes a thirteenth transistor;

[0049] The first pole of the thirteenth transistor is electrically connected to the third node, the second pole of the thirteenth transistor is electrically connected to the fourth node, and the control terminal of the thirteenth transistor is electrically connected to any one of the first node, the second node, and the cascaded input signal terminal. The thirteenth transistor is configured to load the voltage of the third node to the fourth node in response to the selected electrical level of the first node or the second node or the cascaded input signal.

[0050] In an embodiment of the present disclosure, the shift register further includes a seventeenth transistor;

[0051] The first pole of the seventeenth transistor is electrically connected to the second pole of the tenth transistor, the second pole of the seventeenth transistor is electrically connected to the third node, and the control terminal of the seventeenth transistor is electrically connected to the second clock signal terminal. The seventeenth transistor is configured to load the voltage of the second pole of the tenth transistor to the third node in response to the selected electrical level of the second clock signal.

[0052] In an embodiment of the present disclosure, the shift register further includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0053] The first pole of the fifth transistor is electrically connected to the first power supply voltage terminal, the second pole of the fifth transistor is electrically connected to the first pole of the sixth transistor, and the control terminal of the fifth transistor is electrically connected to the control node. The fifth transistor is configured to load the first power supply voltage to the first pole of the sixth transistor in response to the selected electrical level of the control node;

[0054] The second pole of the sixth transistor, the first pole of the seventh transistor, and the first node are electrically connected to each other. The control terminal of the sixth transistor is electrically connected to the second clock signal terminal. The sixth transistor is configured to load the voltage of the first pole of the sixth transistor to the first node in response to the selected electrical level of the second clock signal;

[0055] The second pole of the seventh transistor is electrically connected to the second node, and the control terminal of the seventh transistor is electrically connected to the second power supply voltage terminal. The seventh transistor is configured to load the voltage of the first node to the second node in response to the second power supply voltage;

[0056] The clock period of the first clock signal, the clock period of the second clock signal, and the clock period of the output clock signal are all the same;

[0057] The time length of the selected electrical level of the first clock signal does not exceed 1 / 4 of a clock period;

[0058] The time length of the selected conduction level of the second clock signal does not exceed 1 / 4 of a clock cycle;

[0059] The time length of the effective level of the output clock signal is greater than 1 / 2 of a clock cycle;

[0060] The selected conduction level of the first clock signal is 1 / 2 of a clock cycle earlier than the selected conduction level of the second clock signal;

[0061] The effective level of the output clock signal is 1 / 4 of a clock cycle earlier than the selected conduction level of the second clock signal.

[0062] According to another aspect of the present disclosure, there is provided a gate driving circuit, including a plurality of the above-mentioned shift registers cascaded in sequence; wherein, the cascaded output signal terminal of the upper-level shift register is electrically connected to the cascaded input signal terminal of the lower-level shift register.

[0063] According to the first aspect of the present disclosure, there is provided a display panel, including a gate driving circuit and a first control trace, a second control trace, and a third control trace for driving the gate driving circuit;

[0064] The gate driving circuit includes a plurality of shift registers as described in any one of claims 1 to 13 cascaded in sequence; the cascaded output signal terminal of the upper-level shift register is electrically connected to the cascaded input signal terminal of the lower-level shift register;

[0065] The first control trace is electrically connected to the first clock signal terminal of the odd-numbered shift registers and is also electrically connected to the second clock signal terminal of the even-numbered shift registers;

[0066] The second control trace is electrically connected to the second clock signal terminal of the odd-numbered shift registers and is also electrically connected to the first clock signal terminal of the even-numbered shift registers;

[0067] The third control trace is electrically connected to the output clock signal terminal of the shift register.

[0068] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0070] Figure 1 In one embodiment of the present disclosure, a schematic diagram of a display panel.

[0071] Figure 2 In one embodiment of the present disclosure, a schematic diagram of a film layer of a display panel.

[0072] Figure 3 In one embodiment of the present disclosure, a schematic diagram of a display panel.

[0073] Figure 4 In one embodiment of the present disclosure, a schematic diagram of a pixel driving circuit.

[0074] Figure 5 In one embodiment of the present disclosure, a driving timing diagram of a pixel driving circuit.

[0075] Figure 6 In one embodiment of the present disclosure, a schematic diagram of a pixel driving circuit.

[0076] Figure 7 In one embodiment of the present disclosure, a schematic diagram of a display panel.

[0077] Figure 8 In one embodiment of the present disclosure, a circuit schematic diagram of a shift register.

[0078] Figure 9 In one embodiment of the present disclosure, a circuit schematic diagram of a shift register.

[0079] Figure 10 In one embodiment of the present disclosure, a driving timing diagram corresponding to the shift register.

[0080] Figure 11 In one embodiment of the present disclosure, a circuit schematic diagram of a shift register.

[0081] Figure 12 In one embodiment of the present disclosure, a circuit schematic diagram of a shift register.

[0082] Figure 13 In one embodiment of the present disclosure, a driving timing diagram corresponding to the shift register.

[0083] Figure 14 In one embodiment of the present disclosure, a circuit schematic diagram of a shift register.

[0084] Figure 15 In one embodiment of the present disclosure, a circuit schematic diagram of a shift register. Detailed implementation manners

[0085] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures and thus their detailed description will be omitted. Further, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0086] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0087] The terms "a", "an", "the", "said" and "at least one" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0088] In the embodiments of the present disclosure, a transistor refers to an element including at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region where current mainly flows. In the embodiments of the present disclosure, in the case of using transistors with opposite polarities or when the current direction changes during the operation of a circuit, etc., the functions of the "source" and "drain" sometimes swap with each other, that is, the "source" and "drain" can swap with each other. In the embodiments of the present disclosure, for any transistor, one of the "source" and "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control terminal of the transistor. In the embodiments of the present disclosure, at least some signals have a high level and a low level; one of the high level and the low level can be used as the selected conduction level of the signal, and the selected conduction level of the signal can make the controlled transistor conduct; the other of the high level and the low level can be used as the cut-off level of the signal, and the cut-off level of the signal can make the controlled transistor cut off. For example, for a signal that controls a P-type transistor (the signal can be loaded to the control terminal of the P-type transistor), its selected conduction level is the low level, and its cut-off level is the high level. For another example, for a signal that controls an N-type transistor (the signal can be loaded to the control terminal of the N-type transistor), its selected conduction level is the high level, and its cut-off level is the low level.

[0089] The structural layer A is located on the side of the structural layer B away from the substrate. It can be understood that the structural layer A is formed on the side of the structural layer B away from the substrate. When the structural layer B is a patterned structure, some structures of the structural layer A can also be located at the same physical height as the structural layer B or lower than the physical height of the structural layer B, where the substrate is the height reference.

[0090] The embodiments of the present disclosure provide a display panel PNL. Refer to Figure 1 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with display units UU arranged in an array, and the display units UU include sub-pixels PIX and pixel driving circuits PDC for driving the sub-pixels PIX. The display panel PNL does not provide display units in the peripheral area BB, or the provided display units are not used for displaying images. Refer to Figure 1, the display panel PNL is provided with a plurality of scan lines GL extending in the row direction DH in the display area AA, and each scan line GL is correspondingly arranged with each display unit row. The pixel driving circuits PDC of each display unit in the display unit row are all electrically connected to the corresponding scan line GL. The display panel PNL is further provided with a plurality of data lines DL extending in the column direction DV in the display area AA, and each data line DL is correspondingly arranged with each display unit column. The pixel driving circuits PDC of each display unit in the display unit column are all electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to the scan line GL and the data line DL. A scan signal is loaded on the scan line GL to control the state of the pixel driving circuit PDC. It can be understood that, in Figure 1 the example of, only one kind of scan line GL corresponding to the display unit row is exemplified; according to needs, the display panel PNL can be provided with multiple different scan lines GL corresponding to the display unit row. A data voltage Vdata for driving the pixel driving circuit PDC can be loaded on the data line DL, and the pixel driving circuit PDC can drive the sub-pixel PIX according to the written data voltage Vdata, thereby controlling the brightness of the sub-pixel PIX. It can be understood that the pixel driving circuit PDC can also control the brightness of the sub-pixel PIX according to other signals.

[0091] Optionally, the pixel driving circuit PDC at least includes a data writing transistor, a driving transistor and a storage capacitor, and the gate of the driving transistor can be electrically connected to one electrode plate of the storage capacitor. The source of the data writing transistor can be electrically connected to the data line DL, and the gate of the data writing transistor can be electrically connected to a writing control trace for loading a data writing signal (a kind of scan signal). The pixel driving circuit PDC is configured such that when the selected conduction level of the data writing signal is loaded on the writing control trace, the data writing transistor is turned on, and thus the driving voltage on the data line DL is written into the gate of the driving transistor and the storage capacitor. After the data writing transistor is turned off, the driving voltage can be held by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It can be understood that the pixel driving circuit PDC of the embodiment of the present disclosure can also include other transistors or capacitors to enable the pixel driving circuit PDC to have better driving performance. For example, the pixel driving circuit PDC can be a 7T1C (7 thin film transistors and one storage capacitor), an 8T1C (8 thin film transistors and one storage capacitor) or a pixel driving circuit of other architectures.

[0092] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, it can be any one of light-emitting elements such as OLED, PLED, QLED, Micro LED, and MiNi LED. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, a red sub-pixel for emitting red light, a blue sub-pixel for emitting green light, and a green sub-pixel for emitting green light. It can be understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA can also have sub-pixels PIX of other colors (such as a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0093] In one embodiment of the present disclosure, referring to Figure 2 , the display panel PNL may include a substrate SBT, a driving layer DRL, and a pixel layer PIXL that are sequentially stacked. Sub-pixels PIX are provided in the pixel layer PIXL, and a pixel driving circuit PDC for driving the sub-pixels PIX is provided in the driving layer DRL; each sub-pixel PIX can emit light under the drive of the pixel driving circuit PDC to display an image. Further, the display panel PNL further includes a thin film encapsulation layer TFE on the side of the pixel layer PIXL away from the driving backplane DBP, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0094] Optionally, the substrate SBT can be a substrate made of inorganic materials, or a substrate made of organic materials; of course, it can also be a composite substrate formed by laminating an inorganic material substrate and an organic material substrate. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polysulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In still other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0095] Optionally, in the driving layer DRL, any pixel driving circuit PDC may include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a double-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0096] It can be understood that, among the various transistors in the pixel driving circuit, the types of any two transistors may be the same or different. Exemplarily, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again exemplarily, in some other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polycrystalline silicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low-temperature polycrystalline silicon transistor. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polycrystalline silicon transistors and some thin film transistors are metal oxide transistors.

[0097] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, a planarization layer PLN, etc., which are stacked between the substrate SBT and the pixel layer PIXL. Each thin film transistor and storage capacitor may be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, and the source-drain metal layer SD. Among them, the positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL may be used to form the channel region of the transistor, and may also be used to form part of the traces or conductive structures by conductorization when necessary. The gate layer may be used to form one or more scanning traces, such as forming one or more of the gate layer traces such as the write control trace, the reset control trace, and the light emission control trace, and may also be used to form the gate of the transistor, and may also be used to form part or all of the electrode plates of the storage capacitor. The source-drain metal layer may be used to form source-drain metal layer traces such as the data line DL and the driving power supply voltage trace, and may also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may also include other film layers according to needs, such as a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. According to needs, any one of the above film layers such as the semiconductor layer SCL, the gate layer GT, and the source-drain metal layer SD may also be a multi-layer. For example, the driving layer DRL may include two different semiconductor layers SCL, or include two or three source-drain metal layers SD, or include two or three gate layers GT; correspondingly, the insulating film layers (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) in the driving layer DRL may be increased or decreased adaptively, or new insulating film layers may be added according to needs.

[0098] Optionally, the driving layer DRL may further include a passivation layer, and the passivation layer may be disposed on the surface of the source-drain metal layer SD away from the substrate SBT to protect the source-drain metal layer SD.

[0099] As an example, referring to Figure 2 , the driving layer DRL may include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, and a planarization layer PLN that are sequentially stacked, and the thin film transistor formed in this way is a top-gate thin film transistor.

[0100] In an embodiment of the present disclosure, referring to Figure 2 , the sub-pixel PIX in the pixel layer PIXL is a thin film light-emitting element, which may include two electrodes stacked and a light-emitting functional layer sandwiched between the two electrodes. For example, referring to Figure 2, the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML that are sequentially stacked. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of the display panel; the part of the light-emitting functional layer EFL connected to the pixel electrode PE serves as the light-emitting functional unit of the sub-pixel PIX, and the common electrode layer COML serves as a common electrode and is electrically connected to the light-emitting functional units of each sub-pixel PIX.

[0101] Furthermore, the pixel layer PIXL may further include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings corresponding one-to-one to the plurality of pixel electrodes PE, and any one pixel opening exposes at least a partial area of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a partial internal area of the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode PE (the area directly connected to the light-emitting functional layer EFL), and further define the light-emitting area and light-emitting area of the sub-pixel PIX. The light-emitting functional layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The part of the light-emitting functional layer EFL located between the pixel electrode PE and the common electrode layer COML may serve as a light-emitting functional unit. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element LD serving as a sub-pixel. Among them, one of the pixel electrode PE and the common electrode layer COML serves as the anode of the sub-pixel PIX, and the other serves as the cathode of the sub-pixel PIX.

[0102] In one example, the pixel electrode PE serves as the anode of the sub-pixel PIX, and the common electrode layer COML serves as the cathode of the sub-pixel PIX.

[0103] It can be understood that for different types of light-emitting elements, the materials and film layers of the light-emitting functional layer EFL are different.

[0104] For example, when the light-emitting element is an OLED, the light-emitting functional layer EFL may include an organic light-emitting layer EML, and may include one or more of a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the organic light-emitting layer EML may include a light-emitting layer host material and a light-emitting layer guest material, and the light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, especially a thermally activated delayed fluorescence material. It can be understood that when the OLED adopts a stacked structure, a charge generation layer CGL may also be provided in the light-emitting functional layer EFL.

[0105] For another example, when the light-emitting element is a QLED, the light-emitting functional layer EFL may include a quantum dot layer QDL, and may include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the quantum dot layer QDL may have quantum dot particles, and the quantum dot particles may be connected to each other through surface modification groups. It can be understood that when the QLED adopts a stacked structure, a charge generation layer CGL may also be provided in the light-emitting functional layer EFL.

[0106] See Figure 3 , in the display panel PNL, a gate driving circuit GOA is provided in the peripheral region BB to provide a scanning signal to the pixel driving circuit PDC. According to the needs of the pixel driving circuit PDC, a plurality of gate driving circuits GOA may be provided in the peripheral region BB to respectively provide different scanning signals. Of course, some scanning signals may also share a single gate driving circuit GOA.

[0107] Optionally, according to the needs of the pixel driving circuit PDC, the scanning signal may include, but is not limited to, one or more of the following signals: a write control signal for controlling the writing of a data voltage into the pixel driving circuit PDC, a light-emitting control signal for controlling the pixel driving circuit PDC to output a driving current, a reset control signal for controlling the reset of the pixel driving circuit PDC, and the like.

[0108] Take Figure 4Taking the 3T1C pixel driving circuit PDC shown as an example, the pixel driving circuit PDC includes a first transistor T1X to a third transistor T3X, and a storage capacitor Cst. Among them, the first pole of the first transistor T1X is electrically connected to the data voltage terminal, and the second pole of the first transistor T1X, the first electrode plate of the storage capacitor Cst, the control terminal of the third transistor T3X, and the first node N1 are electrically connected to each other. The control terminal of the first transistor T1X is electrically connected to the write control signal terminal. The first transistor T1X is configured to load the data voltage DATA to the first node N1 in response to the selected on-level of the write control signal G1; the first pole of the second transistor T2X is electrically connected to the compensation signal terminal, and the second pole of the second transistor T2X, the second pole of the third transistor T3X, the second electrode plate of the storage capacitor Cst, and the second node N2 are electrically connected to each other. The control terminal of the second transistor T2X is electrically connected to the compensation control signal terminal. The second transistor T2X is configured to load the voltage of the compensation signal SENSE to the second node N2 in response to the selected on-level of the compensation control signal G2; the first pole of the third transistor T3X is electrically connected to the driving power supply voltage terminal. The third transistor T3X is configured to generate a driving current in response to the selected on-level of the first node N1 to drive the sub-pixel to emit light.

[0109] Figure 5 For Figure 4 the driving timing diagram corresponding to the example 3T1C pixel driving circuit PDC, the following uses Figure 5 the shown driving timing diagram to illustrate each stage of this example. Among them, the first transistor T1X to the third transistor T3X are N-type transistors. The selected on-level of the write control signal G1, the selected on-level of the compensation control signal G2, and the selected on-level of the first node N1 are high levels, and the driving power supply voltage is the high-level power supply voltage ELVDD.

[0110] In the Write stage, referring to Figure 4 and Figure 5 , the write control signal G1 and the compensation control signal G2 are at high levels, causing the first transistor T1X and the second transistor T2X to turn on. However, in the first half of this stage, the data voltage DATA is at a low level. Therefore, the first node N1 is at a low level, and the compensation signal SENSE is loaded to the second node N2, making N2 at a low level. In the second half of this stage, the data voltage DATA changes from low level to high level. Therefore, the first node N1 is gradually pulled up to a high level to write the data voltage DATA into the storage capacitor Cst; the compensation signal SENSE is loaded to the second node N2, making N2 still at a low level.

[0111] In the Emssion stage, referring to Figure 4 and Figure 5, the write control signal G1 and the compensation control signal G2 are at low level, turning off the first transistor T1X and the second transistor T2X. Under the coupling effect of the storage capacitor Cst, the third transistor T3X is turned on, thereby generating a driving current to drive the sub-pixel to emit light.

[0112] In this way, in the first half of the Write stage, the write control signal G1 controls the first transistor T1X to turn on in advance, and no data voltage DATA is written to the first node N1; on the one hand, the first node N1 is pre-charged, which can improve the charging efficiency, and on the other hand, the first transistor T1X is turned on in advance, so that when data is written in the second half of the Write stage, the situation that the first node N1 is undercharged due to the slow turn-on of the first transistor T1X can be avoided, so as to achieve the effect of fast charging and fast response. Therefore, in this example, the waveforms of the write control signal G1 and the compensation control signal G2 need to be wide enough.

[0113] Take... as an example again Figure 6Taking the exemplified 6T2C pixel driving circuit PDC as an example, the pixel driving circuit PDC includes a first transistor T1X to a sixth transistor T6X, as well as a storage capacitor Cst1 and a voltage stabilizing capacitor Cst2. Among them, the first pole of the first transistor T1X is electrically connected to the data voltage terminal, and the second pole of the first transistor T1X, the first electrode plate of the storage capacitor Cst1, the second pole of the third transistor T3X, the control terminal of the sixth transistor T6X, and the first node N1 are electrically connected to each other. The control terminal of the first transistor T1X is electrically connected to the write control signal terminal. The first transistor T1X is configured to load the data voltage DATA to the first node N1 in response to the selected conduction level of the write control signal G1; the first pole of the second transistor T2X, the first electrode plate of the voltage stabilizing capacitor Cst2, and the driving power supply voltage terminal are electrically connected to each other. The second pole of the second transistor T2X is electrically connected to the first pole of the sixth transistor T6X. The control terminal of the second transistor T2X is electrically connected to the first light emission control signal terminal. The second transistor T2X is configured to load the driving power supply voltage to the first pole of the sixth transistor T6X in response to the selected conduction level of the first light emission control signal EM1; the first pole of the third transistor T3X is electrically connected to the reference voltage terminal, and the control terminal of the third transistor T3X is electrically connected to the first reset control signal terminal. The third transistor T3X is configured to load the reference voltage Vref to the first node N1 in response to the selected conduction level of the first reset control signal RST1; the first pole of the fourth transistor T4X, the second electrode plate of the storage capacitor Cst1, the second electrode plate of the voltage stabilizing capacitor Cst2, the second pole of the sixth transistor T6X, and the second node N2 are electrically connected to each other. The second pole of the fourth transistor T4X, the second pole of the fifth transistor T5X, and the third node N3 are electrically connected to the pixel electrode. The control terminal of the fourth transistor T4X is electrically connected to the second light emission control signal terminal. The fourth transistor T4X is configured to load the voltage of the second node N2 to the third node N3 in response to the selected conduction level of the second light emission control signal EM2; the first pole of the fifth transistor T5X is electrically connected to the initialization signal terminal, and the control terminal of the fifth transistor T5X is electrically connected to the second reset control signal terminal. The fifth transistor T5X is configured to load the initialization signal Vini to the third node in response to the selected conduction level of the second reset control signal RST2; the sixth transistor T6X is configured to generate a driving current in response to the selected conduction level of the first node N1.

[0114] In this example, the selected conduction levels of the first reset control signal RST1 and the second reset control signal RST2 can be provided to the pixel driving circuit PDC first. This causes the third transistor T3X to conduct and reset the first node N1, and the fifth transistor T5X to conduct and reset the pixel electrode of the sub-pixel. Then, the selected conduction level of the write control signal G1 can be provided to the pixel driving circuit PDC; this can cause the first transistor T1X to conduct and load the data voltage DATA to the first node N1. This can achieve writing the data voltage DATA and the threshold voltage of the sixth transistor T6X to the first node N1. Then, the selected conduction levels of the first emission control signal EM1 and the second emission control signal EM2 can be provided to the pixel driving circuit PDC, thereby causing the second transistor T2X and the fourth transistor T4X to conduct. The sixth transistor T6X outputs a driving current to the sub-pixel under the control of the first node N1, thereby controlling the emission brightness of the sub-pixel. In this example, the waveform of the write control signal G1 needs to be wide enough.

[0115] In the embodiment of the present disclosure, referring to Figure 7 , a gate driving circuit GOA and first, second, and third control traces CL1, CL2, and CL3 for driving the gate driving circuit GOA are provided in the peripheral area BB of the display panel PNL to provide a scan signal to the display area AA of the display panel PNL. The gate driving circuit GOA includes a plurality of cascaded shift registers SR. In adjacent two-stage shift registers SR, the cascaded output signal terminal of the upper-stage shift register SR is electrically connected to the cascaded input signal terminal of the lower-stage shift register SR. Referring to Figure 8 , the shift register SR includes an input circuit CRIM, a cascaded output circuit CROM, a control circuit CTR, and a scan output circuit GOM. Among them, the input circuit CRIM is used to control the levels of the first node Q1 and the control node QB under the control of the first clock signal CKA and the cascaded output signal CROUT of the upper-stage cascaded output circuit CROM; the cascaded output circuit CROM is used to output the cascaded output signal CROUT under the control of the first node Q1, the control node QB, and the second clock signal CKB; the control circuit CTR is used to control the level of the fourth node Q4 under the control of the first node Q1, the control node QB, and the first clock signal CKA; the scan output circuit GOM is used to output a scan signal under the control of the control node QB, the fourth node Q4, and the output clock signal GCK.

[0116] Referring to Figure 10, the effective level duration of the cascaded output signal CROUT output by the cascaded output circuit CROM is less than the effective level duration of the scan signal output by the scan output circuit GOM. In this way, the scan signal of the sub-pixel row is output by the scan output circuit GOM, and the cascaded input signal CRIN of the next stage is output by the cascaded output circuit CROM, so that cascading and output are separated. When the scan output of the scan output circuit GOM of the previous stage shift register SR has not ended, the next stage shift register SR also outputs. On the one hand, it causes the scan signal output by the previous stage shift register SR to overlap with the scan signal output by the next stage shift register SR, so as to offset the influence of the rising edge of the scan signals of two adjacent sub-pixel rows output, and improve the display quality of the display panel PNL. On the other hand, it can improve the refresh frequency and charging efficiency of the pixel driving circuit.

[0117] It can be understood that, in two adjacent stages of shift registers SR, the effective level of the cascaded output signal CROUT refers to the level output by the cascaded output circuit CROM of the previous stage shift register SR, and is the level used to activate the input circuit CRIM of the next stage shift register SR. The cascaded output signal CROUT of the previous stage and the cascaded input signal CRIN of the next stage are the same signal. In the embodiments of the present disclosure, the effective level of the cascaded output signal CROUT is a low level. The effective level of the scan signal output by the scan output circuit GOM is a high level.

[0118] In an embodiment of the present disclosure, referring to Figure 8 , the cascaded output circuit CROM includes a first cascaded output sub-circuit CROC1 and a second cascaded output sub-circuit CROC2.

[0119] Among them, the first pole of the first cascaded output sub-circuit CROC1 is electrically connected to the first power supply voltage terminal, the second pole is electrically connected to the cascaded output signal terminal, and the control terminal is electrically connected to the control node QB. The first cascaded output sub-circuit CROC1 is configured to load the first power supply voltage V1 to the cascaded output signal terminal in response to the selected power level of the control node QB.

[0120] In an embodiment of the present disclosure, referring to Figure 8 , the first pole of the second cascaded output sub-circuit CROC2 is electrically connected to the second clock signal terminal, the second pole of the second cascaded output sub-circuit CROC2 is electrically connected to the cascaded output signal terminal, and the control terminal of the second cascaded output sub-circuit CROC2 is electrically connected to the first node Q1. The second cascaded output sub-circuit CROC2 is configured to load the voltage of the second clock signal CKB to the cascaded output signal terminal in response to the selected power level of the first node Q1.

[0121] In an embodiment of the present disclosure, referring to Figure 8, the scan output circuit GOM includes a first scan output sub - circuit GOC1 and a second scan output sub - circuit GOC2.

[0122] Among them, the first pole of the first scan output sub - circuit GOC1 is electrically connected to the second power supply voltage terminal, the second pole is electrically connected to the scan output signal terminal GOUT, and the control terminal is electrically connected to the control node QB. The first scan output sub - circuit GOC1 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the selected - on level of the control node QB.

[0123] In an embodiment of the present disclosure, refer to Figure 8 , the first pole of the second scan output sub - circuit GOC2 is electrically connected to the output clock signal terminal, the second pole is electrically connected to the scan output signal terminal GOUT, and the control terminal is electrically connected to the fourth node Q4. The second scan output sub - circuit GOC2 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the selected - on level of the fourth node Q4.

[0124] In an embodiment of the present disclosure, refer to Figure 8 , the input circuit CRIM includes a cascaded input sub - circuit CRIC, a first sub - circuit VSC1, and a second sub - circuit VSC2.

[0125] Among them, the first pole of the cascaded input sub - circuit CRIC is electrically connected to the cascaded input signal terminal, the second pole is electrically connected to the first node Q1, and the control terminal is electrically connected to the first clock signal terminal. The cascaded input sub - circuit CRIC is configured to load the voltage of the cascaded input signal CRIN to the first node Q1 in response to the selected - on level of the first clock signal CKA. It should be noted that in the first - stage shift register SR, the signal of the cascaded input signal terminal is the start signal STV.

[0126] In an embodiment of the present disclosure, refer to Figure 8 , the first pole of the first sub - circuit VSC1 is electrically connected to the second power supply voltage terminal, the second pole is electrically connected to the control node QB, and the control terminal is electrically connected to the first clock signal terminal. The first sub - circuit VSC1 is configured to load the second power supply voltage V2 to the control node QB in response to the selected - on level of the first clock signal CKA.

[0127] In an embodiment of the present disclosure, refer to Figure 8 , the first pole of the second sub - circuit VSC2 is electrically connected to the first clock signal terminal, the second pole is electrically connected to the control node QB, and the control terminal is electrically connected to the first node Q1. The second sub - circuit VSC2 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selected - on level of the first node Q1.

[0128] In an embodiment of the present disclosure, refer toFigure 8 , the control circuit CTR includes a third sub-circuit VSC3, a fourth sub-circuit VSC4, and a fifth sub-circuit VSC5.

[0129] Among them, the first pole of the third sub-circuit VSC3 is electrically connected to the first clock signal terminal, the second pole is electrically connected to the third node Q3, and the control terminal is electrically connected to the control node QB. The third sub-circuit VSC3 is configured to load the voltage of the first clock signal CKA to the third node Q3 in response to the selected power level of the control node QB.

[0130] In an embodiment of the present disclosure, refer to Figure 8 , the first pole of the fourth sub-circuit VSC4 is electrically connected to the second power supply voltage terminal, the second pole is electrically connected to the third node Q3, and the control terminal is electrically connected to the first node Q1. The fourth sub-circuit VSC4 is configured to load the second power supply voltage V2 to the third node Q3 in response to the selected power level of the first node Q1.

[0131] In an embodiment of the present disclosure, refer to Figure 8 , the first pole of the fifth sub-circuit VSC5 is electrically connected to the third node Q3, the second pole is electrically connected to the fourth node Q4, and the control terminal is electrically connected to either the second clock signal terminal or the second power supply voltage terminal. The fifth sub-circuit VSC5 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected power level of the second clock signal CKB or the second power supply voltage V2. In one example, the control terminal of the fifth sub-circuit VSC5 is electrically connected to the second clock signal terminal. In another example, the control terminal of the fifth sub-circuit VSC5 is electrically connected to the second power supply voltage terminal.

[0132] In an embodiment of the present disclosure, refer to Figure 8 , the first cascaded output sub-circuit CROC1 includes a third transistor T3 and a first capacitor C1. The first pole of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected. The second pole of the third transistor T3 is electrically connected to the cascaded output signal terminal. The control terminal of the third transistor T3, the second electrode plate of the first capacitor C1, and the control node QB are electrically connected. The third transistor T3 is configured to load the first power supply voltage V1 to the cascaded output signal terminal in response to the selected power level of the control node QB. In other embodiments of the present disclosure, the first cascaded output sub-circuit CROC1 may include multiple third transistors T3 connected in series or in parallel.

[0133] In an embodiment of the present disclosure, refer to Figure 8, the second cascaded output sub-circuit CROC2 includes an eighth transistor T8 and a second capacitor C2. A first pole of the eighth transistor T8 is electrically connected to a second clock signal terminal. A second pole of the eighth transistor T8, a second electrode plate of the second capacitor C2 are electrically connected to a cascaded output signal terminal. A control terminal of the eighth transistor T8, a first electrode plate of the second capacitor C2, and a second node Q2 are electrically connected to each other. The eighth transistor T8 is configured to load a voltage of the second clock signal CKB to the cascaded output signal terminal in response to an energized level of the second node Q2. In some other embodiments of the present disclosure, the second cascaded output sub-circuit CROC2 may include a plurality of eighth transistors T8 connected in series or in parallel.

[0134] In one embodiment of the present disclosure, refer to Figure 8 , the first scan output sub-circuit GOC1 includes a fifteenth transistor T15 and a fourth capacitor C4. A first pole of the fifteenth transistor T15 is electrically connected to a second power supply voltage terminal. A second pole is electrically connected to a scan output signal terminal GOUT. A control terminal of the fifteenth transistor T15, a first electrode plate of the fourth capacitor C4, and a control node QB are electrically connected to each other. The fifteenth transistor T15 is configured to output a second power supply voltage V2 to the scan output signal terminal GOUT in response to an energized level of the control node QB; a second electrode plate of the fourth capacitor C4 is electrically connected to a first clock signal terminal. In some other embodiments of the present disclosure, the first scan output sub-circuit GOC1 may include a plurality of fifteenth transistors T15 connected in series or in parallel.

[0135] In one embodiment of the present disclosure, refer to Figure 8 , the second scan output sub-circuit GOC2 includes a fourteenth transistor T14 and a third capacitor C3. A first pole of the fourteenth transistor T14 is electrically connected to an output clock signal terminal. A second pole is electrically connected to a scan output signal terminal GOUT. A control terminal of the fourteenth transistor T14, a first electrode plate of the third capacitor C3, and a fourth node Q4 are electrically connected to each other. The fourteenth transistor T14 is configured to output a voltage of an output clock signal GCK to the scan output signal terminal GOUT in response to an energized level of the fourth node Q4. In some other embodiments of the present disclosure, the second scan output sub-circuit GOC2 may include a plurality of fourteenth transistors T14 connected in series or in parallel.

[0136] In one embodiment of the present disclosure, refer to Figure 8, the cascaded input sub-circuit CRIC includes a second transistor T2. A first pole of the second transistor T2 is electrically connected to the cascaded input signal terminal, a second pole is electrically connected to the first node Q1, and a control terminal is electrically connected to the first clock signal terminal. The second transistor T2 is configured to load the voltage of the cascaded input signal CRIN to the first node Q1 in response to the selected conduction level of the first clock signal CKA. In some other embodiments of the present disclosure, the cascaded input sub-circuit CRIC may include a plurality of second transistors T2 connected in series or in parallel.

[0137] In one embodiment of the present disclosure, refer to Figure 8 , the first sub-circuit VSC1 includes a first transistor T1. A first pole of the first transistor T1 is electrically connected to the second power supply voltage terminal, a second pole is electrically connected to the control node QB, and a control terminal is electrically connected to the first clock signal terminal. The first transistor T1 is configured to load the second power supply voltage V2 to the control node QB in response to the selected conduction level of the first clock signal CKA. In some other embodiments of the present disclosure, the first sub-circuit VSC1 may further include a plurality of first transistors T1 connected in series or in parallel.

[0138] In one embodiment of the present disclosure, refer to Figure 8 , the second sub-circuit VSC2 includes a fourth transistor T4. A first pole of the fourth transistor T4 is electrically connected to the first clock signal terminal, a second pole is electrically connected to the control node QB, and a control terminal is electrically connected to the first node Q1. The fourth transistor T4 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selected conduction level of the first node Q1. In some other embodiments of the present disclosure, the second sub-circuit VSC2 may further include a plurality of fourth transistors T4 connected in series or in parallel.

[0139] In one embodiment of the present disclosure, refer to Figure 8 , the third sub-circuit VSC3 includes a tenth transistor T10. A first pole of the tenth transistor T10 is electrically connected to the first clock signal terminal, a second pole is electrically connected to the third node Q3, and a control terminal is electrically connected to the control node QB. The tenth transistor T10 is configured to load the voltage of the first clock signal CKA to the third node Q3 in response to the selected conduction level of the control node QB. In some other embodiments of the present disclosure, the third sub-circuit VSC3 may further include a plurality of tenth transistors T10 connected in series or in parallel.

[0140] In one embodiment of the present disclosure, refer to Figure 8, the fourth sub - circuit VSC4 includes a ninth transistor T9. The first pole of the ninth transistor T9 is electrically connected to the second power - voltage terminal, the second pole is electrically connected to the third node Q3, and the control terminal is electrically connected to the first node Q1. The ninth transistor T9 is configured to load the second power - voltage V2 to the third node Q3 in response to the selected - on level of the first node Q1. In some other embodiments of the present disclosure, the fourth sub - circuit VSC4 may include multiple ninth transistors T9 connected in series or in parallel.

[0141] In one embodiment of the present disclosure, referring to Figure 8 , the fifth sub - circuit VSC5 includes a twelfth transistor T12. The first pole of the twelfth transistor T12 is electrically connected to the third node Q3, and the second pole of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, and the fourth node Q4 are electrically connected to each other. The control terminal is electrically connected to either the second clock - signal terminal or the second power - voltage terminal. The twelfth transistor T12 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected - on level of the second clock signal CKB or the second power - voltage V2. In one example, the control terminal of the twelfth transistor T12 is electrically connected to the second power - voltage terminal. In another example, the control terminal of the twelfth transistor T12 is electrically connected to the second clock - signal terminal; since the second clock signal CKB is intermittently turned on, it can prevent the fourth node Q4 from being abnormally set, so as to improve the display quality of the display panel PNL.

[0142] In one embodiment of the present disclosure, referring to Figure 15 , the shift register SR further includes a sixteenth transistor T16. The first pole and the control terminal of the sixteenth transistor T16 are electrically connected to the first clock - signal terminal, and the second pole of the sixteenth transistor T16 is electrically connected to the first electrode plate of the fourth capacitor C4. The sixteenth transistor T16 is configured to load the voltage of the first clock signal CKA to the first electrode plate of the fourth capacitor C4 in response to the selected - on level of the first clock signal CKA. In this way, by providing the sixteenth transistor T16 between the fourth capacitor C4 and the first clock - signal terminal, since the sixteenth transistor T16 is only turned on under the control of the selected - on level of the first clock signal CKA and turned off under the control of the cut - off level of the first clock signal CKA, it can avoid continuous charging or discharging of the fourth capacitor C4, which is convenient for reducing the power consumption of the system.

[0143] In one embodiment of the present disclosure, referring to Figure 8, the control circuit CTR further includes a thirteenth transistor T13. A first pole of the thirteenth transistor T13, a first pole of the twelfth transistor T12, and a third node Q3 are electrically connected to each other. A second pole of the thirteenth transistor T13, a second pole of the twelfth transistor T12, a control terminal of the fourteenth transistor T14, a first electrode plate of the third capacitor C3, and a fourth node Q4 are electrically connected to each other. A control terminal of the thirteenth transistor T13 is electrically connected to any one of the first node Q1 and the second node Q2. The thirteenth transistor T13 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to a selected electrical level of the first node Q1 or the second node Q2. In some other embodiments of the present disclosure, the control circuit CTR may further include a plurality of serially or parallely connected thirteenth transistors T13.

[0144] In an embodiment of the present disclosure, referring to Figure 11 , the shift register SR further includes a seventeenth transistor T17. A first pole of the seventeenth transistor T17 is electrically connected to a second pole of the tenth transistor T10. A second pole of the seventeenth transistor T17 is electrically connected to the third node Q3. A control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal. The seventeenth transistor T17 is configured to load the voltage of the second pole of the tenth transistor T10 to the third node Q3 in response to a selected electrical level of the second clock signal CKB. Thus, the ninth transistor T9 and the tenth transistor T10 are separated by the seventeenth transistor T17. Since the control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal, the seventeenth transistor T17 is intermittently turned on, thereby preventing the third node Q3 from being abnormally set and improving the display quality of the display panel PNL.

[0145] In an embodiment of the present disclosure, referring to Figure 8 , the shift register SR further includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. A first pole of the fifth transistor T5 is electrically connected to the first power supply voltage terminal. A second pole of the fifth transistor T5 is electrically connected to a first pole of the sixth transistor T6. A control terminal of the fifth transistor T5 is electrically connected to the control node QB. The fifth transistor T5 is configured to load the first power supply voltage V1 to the first pole of the sixth transistor T6 in response to a selected electrical level of the control node QB.

[0146] A second pole of the sixth transistor T6, a second pole of the second transistor T2, a first pole of the seventh transistor T7, and the first node Q1 are electrically connected to each other. A control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to load the voltage of the first pole of the sixth transistor T6 to the first node Q1 in response to a selected electrical level of the second clock signal CKB.

[0147] The second pole of the seventh transistor T7 is electrically connected to the second node Q2, the control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal, and the seventh transistor T7 is configured to load the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.

[0148] In this way, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can stabilize the voltage of the entire circuit system to improve the stability of the circuit system.

[0149] In an embodiment of the present disclosure, refer to Figure 14 , the shift register SR further includes a thirteenth transistor T13. The first pole of the thirteenth transistor T13, the first pole of the twelfth transistor T12, and the third node Q3 are electrically connected to each other. The second pole of the thirteenth transistor T13, the second pole of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, and the fourth node Q4 are electrically connected to each other. The control terminal of the thirteenth transistor T13 is electrically connected to the cascade input signal terminal, and the thirteenth transistor T13 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected electrical level of the cascade input signal CRIN. In some other embodiments of the present disclosure, the shift register SR may further include a plurality of thirteenth transistors T13 connected in series or in parallel.

[0150] In an embodiment of the present disclosure, refer to Figure 8 , the shift register SR further includes an eleventh transistor T11. The first pole of the eleventh transistor T11 is electrically connected to the control node QB. The second pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal, and the eleventh transistor T11 is configured to load the voltage of the control node QB to the control terminal of the fifteenth transistor T15 in response to the second power supply voltage V2. In this way, the voltage of the entire circuit system can be stabilized by the eleventh transistor T11 to improve the reliability of the circuit system.

[0151] In an embodiment of the present disclosure, refer to Figure 10 and Figure 13 , the clock cycles of the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all the same. The time length of the selected electrical level of the first clock signal CKA does not exceed 1 / 4 of a clock cycle. For example, the time length of the selected electrical level of the first clock signal CKA is 1 / 4, 1 / 5, 1 / 6, etc. of the clock cycle.

[0152] The time length of the selected active level of the second clock signal CKB does not exceed 1 / 4 of a clock cycle. For example, the time length of the selected active level of the second clock signal CKB is 1 / 4, 1 / 5, 1 / 6, etc. of the clock cycle.

[0153] The time length of the active level of the output clock signal GCK is greater than 1 / 2 of a clock cycle. For example, the time length of the active level of the output clock signal GCK is 2 / 3, 3 / 4, 4 / 5, etc. of the clock cycle.

[0154] The selected active level of the first clock signal CKA is 1 / 2 of a clock cycle earlier than the selected active level of the second clock signal CKB, and the time lengths of the selected active levels of the first clock signal CKA and the second clock signal CKB are the same.

[0155] The active level of the output clock signal GCK is 1 / 4 of a clock cycle earlier than the selected active level of the second clock signal CKB. It should be noted that in the embodiments of the present disclosure, one of the active level of the output clock signal GCK and the second power supply voltage V2 is used as the high level, and the other is used as the low level. The selected active levels of the first clock signal CKA and the second clock signal CKB are the same, for example, both are low levels.

[0156] The time length of the active level of the output clock signal GCK is greater than 1 / 2 of a clock cycle. Since the output of the scan output signal terminal GOUT depends on the waveform of the output clock signal GCK, in two adjacent shift registers SR, when the output of the scan output signal terminal GOUT of the upper shift register SR has not ended, the lower shift register SR also outputs, so that the scan signal output by the upper shift register SR overlaps with the scan signal output by the lower shift register SR, so as to offset the influence of the rising edges of the scan signals of two adjacent sub-pixel rows output, and improve the display quality of the display panel PNL.

[0157] It can be understood that in the embodiments of the present disclosure, one clock cycle refers to the cycle of the clock signal. As Figure 10 shown, taking the first clock signal CKA as an example, one clock cycle refers to the time length used in the process from the first time the first clock signal CKA changes to the low level to the second time it changes to the low level. In other words, one clock cycle refers to the time length from time P1 to time P4.

[0158] In an embodiment of the present disclosure, refer to Figure 7, in adjacent two - stage shift registers SR, the cascade output signal terminal of the upper - stage shift register SR is electrically connected to the cascade input signal terminal of the lower - stage shift register SR. The first control trace CL1 is electrically connected to the first clock signal terminal of the odd - numbered stage shift register SR and is also electrically connected to the second clock signal terminal of the even - numbered stage shift register SR. The second control trace CL2 is electrically connected to the second clock signal terminal of the odd - numbered stage shift register SR and is also electrically connected to the first clock signal terminal of the even - numbered stage shift register SR. For example, as Figure 1 shown, the first control trace CL1 is electrically connected to the first clock signal terminal of shift register SR1, the first clock signal terminal of shift register SR3, the first clock signal terminal of shift register SR5, etc., and the first control trace CL1 is electrically connected to the second clock signal terminal of shift register SR2, the second clock signal terminal of shift register SR4, the second clock signal terminal of shift register SR6, etc.; the second control trace CL2 is electrically connected to the second clock signal terminal of shift register SR1, the second clock signal terminal of shift register SR3, the second clock signal terminal of shift register SR5, etc., and the second control trace CL2 is electrically connected to the first clock signal terminal of shift register SR2, the first clock signal terminal of shift register SR4, the first clock signal terminal of shift register SR6, etc. The third control trace CL3 is electrically connected to the output clock signal terminal of the shift register SR. In this way, it is beneficial to achieve a narrow border of the display panel PNL.

[0159] Based on this, in an embodiment of the present disclosure, as Figure 7 shown, a gate driving circuit GOA and the first control trace CL1, the second control trace CL2, and the third control trace CL3 for driving the gate driving circuit GOA are provided in the peripheral area BB of the display panel PNL to provide a scanning signal to the display area AA of the display panel PNL. The gate driving circuit GOA includes a plurality of shift registers SR cascaded in sequence. In adjacent two - stage shift registers SR, the cascade output signal terminal of the upper - stage shift register SR is electrically connected to the cascade input signal terminal of the lower - stage shift register SR. The first control trace CL1 is electrically connected to the first clock signal terminal of the odd - numbered stage shift register SR and is also electrically connected to the second clock signal terminal of the even - numbered stage shift register SR. The second control trace CL2 is electrically connected to the second clock signal terminal of the odd - numbered stage shift register SR and is also electrically connected to the first clock signal terminal of the even - numbered stage shift register SR. The third control trace CL3 is electrically connected to the output clock signal terminal of the shift register SR.

[0160] In the first example, as Figure 9As shown, the shift register SR includes the first transistor T1 to the fifteenth transistor T15. The first pole of the first transistor T1 is electrically connected to the second power supply voltage terminal. The second pole of the first transistor T1, the first pole of the fourth transistor T4, the control terminal of the fifth transistor T5, the first electrode plate of the first capacitor C1, the control terminal of the third transistor T3, the control terminal of the tenth transistor T10, the first pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the control node QB are electrically connected to each other. The control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to load the second power supply voltage V2 to the control node QB in response to the selected power level of the first clock signal CKA. The first pole of the second transistor T2 is electrically connected to the cascade input signal terminal. The second pole of the second transistor T2, the control terminal of the fourth transistor T4, the second pole of the sixth transistor T6, the first pole of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to load the voltage of the cascade input signal CRIN to the first node Q1 in response to the selected power level of the first clock signal CKA. The first pole of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. The second pole of the third transistor T3, the second electrode plate of the second capacitor C2, the second pole of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to load the first power supply voltage V1 to the cascade output signal terminal in response to the selected power level of the control node QB. The first pole of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selected power level of the first node Q1. The first pole of the fifth transistor T5 is electrically connected to the first power supply voltage terminal. The second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6. The fifth transistor T5 is configured to load the first power supply voltage V1 to the first pole of the sixth transistor T6 in response to the selected power level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to load the voltage of the first pole of the sixth transistor T6 to the first node Q1 in response to the selected power level of the second clock signal CKB. The second pole of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to load the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2. The first pole of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to load the voltage of the second clock signal CKB to the cascade output signal terminal in response to the selected power level of the second node Q2.The first pole of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. The second pole of the ninth transistor T9, the second pole of the tenth transistor T10, and the third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to load the second power supply voltage V2 to the third node Q3 in response to the selected power level of the first node Q1. The first pole of the tenth transistor T10 is electrically connected to the first clock signal terminal. The tenth transistor T10 is configured to load the voltage of the first clock signal CKA to the third node Q3 in response to the selected power level of the control node QB. The second pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to load the voltage of the control node QB to the control terminal of the fifteenth transistor T15 in response to the second power supply voltage V2. The first pole of the twelfth transistor T12, the first pole of the thirteenth transistor T13, and the third node Q3 are electrically connected to each other. The second pole of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, the fourth node Q4, and the second pole of the thirteenth transistor T13 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. The twelfth transistor T12 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected power level of the second clock signal CKB. The control terminal of the thirteenth transistor T13 is electrically connected to either the first node Q1 or the second node Q2. The thirteenth transistor T13 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected power level of the first node Q1 or the second node Q2. The first pole of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. The second pole of the fourteenth transistor T14, the second electrode plate of the third capacitor C3, the second pole of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the selected power level of the fourth node Q4. The first pole of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the selected power level of the control node QB; the second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal.

[0161] It should be noted that in this example, each transistor is a P-type transistor. The selected power level of each signal is a low level. The first power supply voltage V1 is the high-level power supply voltage VGH, and the second power supply voltage V2 is the low-level power supply voltage VGL. The effective level of the output clock signal GCK is a high level.

[0162] Figure 10 ForFigure 9 The driving timing diagram of the shift register SR shown. Among them, the clock cycles of the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all the same. The time length of the selected high level of the first clock signal CKA is 1 / 4 of a clock cycle. The time length of the selected high level of the second clock signal CKB is 1 / 4 of a clock cycle. The time length of the effective level of the output clock signal GCK is 3 / 4 of a clock cycle. The selected high level of the first clock signal CKA is 1 / 2 of a clock cycle earlier than the selected high level of the second clock signal CKB, and the time lengths of the selected high levels of the first clock signal CKA and the second clock signal CKB are the same. The effective level of the output clock signal GCK is 1 / 4 of a clock cycle earlier than the selected high level of the second clock signal CKB.

[0163] The following combines Figure 10 with Figure 9 to exemplarily illustrate the working principle of the shift register SR in the example.

[0164] Refer to Figure 9 and Figure 10 . At time P1, the cascade input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all at low level, and the second clock signal CKB is at high level. Then the first transistor T1, the second transistor T2, the seventh transistor T7, and the eleventh transistor T11 are turned on. The low-level power supply voltage VGL makes the control node QB at low level, so the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned on. At the same time, the cascade input signal CRIN makes the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 turned on, so that the high level of the second clock signal CKB is output at the cascade output signal terminal; since the first node Q1 and the second node Q2 are at low level, the thirteenth transistor T13 is turned on; the third node Q3 is at low level, so the fourteenth transistor T14 is turned on, and the low level of the output clock signal GCK is output at the scan output signal terminal GOUT.

[0165] At time P2, the cascaded input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all at high level, then the first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12 are turned off. Through the coupling effect of the second capacitor C2, the first node Q1 and the second node Q2 remain at low level, then the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, and the thirteenth transistor T13 are turned on. The first clock signal CKA makes the control node QB at high level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned off. Then the high level of the second clock signal CKB is output at the cascaded output signal terminal. The low-level power supply voltage VGL makes the third node Q3 and the fourth node Q4 still remain at low level, so that the fourteenth transistor T14 is turned on, and the high level of the output clock signal GCK is output at the scan output signal terminal GOUT.

[0166] At time P3, the cascaded input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all at high level, and the second clock signal CKB is at low level, then the first transistor T1 and the second transistor T2 are turned off, and the sixth transistor T6 and the twelfth transistor T12 are turned on. The first node Q1 and the second node Q2 remain at low level, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, and the thirteenth transistor T13 are turned on, so that the low level of the second clock signal CKB is output at the cascaded output signal terminal. The control node QB still remains at high level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned off. The low-level power supply voltage VGL makes the third node Q3 and the fourth node Q4 still remain at low level, so that the fourteenth transistor T14 is turned on, and the scan output signal terminal GOUT continues to output the high level of the output clock signal GCK.

[0167] At time P4, the cascaded input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all at high level, then the first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12 are turned off. The first node Q1 and the second node Q2 remain at low level, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, and the thirteenth transistor T13 are turned on, so that the high level of the second clock signal CKB is output at the cascaded output signal terminal. The first clock signal CKA makes the control node QB still remain at high level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned off. The low-level power supply voltage VGL makes the third node Q3 and the fourth node Q4 still remain at low level, so that the fourteenth transistor T14 is turned on, and the scan output signal terminal GOUT continues to output the high level of the output clock signal GCK.

[0168] At time P5, the cascaded input signal CRIN and the second clock signal CKB are both at high level, the first clock signal CKA and the output clock signal GCK are both at low level. Then the first transistor T1, the second transistor T2, the seventh transistor T7 and the eleventh transistor T11 are turned on. The low-level power supply voltage VGL makes the control node QB at low level, so the third transistor T3, the fifth transistor T5, the tenth transistor T10 and the fifteenth transistor T15 are turned on. At the same time, the cascaded input signal CRIN turns off the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9. Thus, a high level of the high-level power supply voltage VGH is output at the cascaded output signal terminal. Since the first node Q1 and the second node Q2 are at high level, the thirteenth transistor T13 is turned off. Since the fourth node Q4 is at low level, the fourteenth transistor T14 is turned on, and the low level of the output clock signal GCK is output at the scan output signal terminal GOUT.

[0169] In this way, in two adjacent stages of the shift register SR, since the output clock signal GCK is turned on in advance at time P1 of the previous-stage shift register SR, and a low level is input to the cascaded input signal CRIN of the next-stage shift register SR at time P3, the next-stage shift register SR is also started. At the scan output signal terminal GOUT of the previous-stage shift register SR ( Figure 10 G shown in <n>) with the scan output signal terminal GOUT( Figure 10 shown in G<N+1>) of the next-level shift register SR has obvious overlap, so as to offset the influence of the rising edges of the scan signals of two adjacent sub-pixel rows of the output, and improve the display quality of the display panel PNL.

[0170] In the second example, as Figure 11 As shown, the shift register SR includes the first transistor T1 to the twelfth transistor T12, the fourteenth transistor T14, the fifteenth transistor T15, and the seventeenth transistor T17. The first pole of the first transistor T1 is electrically connected to the second power supply voltage terminal. The second pole of the first transistor T1, the first pole of the fourth transistor T4, the control terminal of the fifth transistor T5, the first electrode plate of the first capacitor C1, the control terminal of the third transistor T3, the control terminal of the tenth transistor T10, the first pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the control node QB are electrically connected to each other. The control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to load the second power supply voltage V2 to the control node QB in response to the selected high level of the first clock signal CKA. The first pole of the second transistor T2 is electrically connected to the cascade input signal terminal. The second pole of the second transistor T2, the control terminal of the fourth transistor T4, the second pole of the sixth transistor T6, the first pole of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to load the voltage of the cascade input signal CRIN to the first node Q1 in response to the selected high level of the first clock signal CKA. The first pole of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. The second pole of the third transistor T3, the second electrode plate of the second capacitor C2, the second pole of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to load the first power supply voltage V1 to the cascade output signal terminal in response to the selected high level of the control node QB. The first pole of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selected high level of the first node Q1. The first pole of the fifth transistor T5 is electrically connected to the first power supply voltage terminal. The second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6. The fifth transistor T5 is configured to load the first power supply voltage V1 to the first pole of the sixth transistor T6 in response to the selected high level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to load the voltage of the first pole of the sixth transistor T6 to the first node Q1 in response to the selected high level of the second clock signal CKB. The second pole of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to load the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.The first pole of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to load the voltage of the second clock signal CKB to the cascade output signal terminal in response to the selected electrical level of the second node Q2. The first pole of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. The second pole of the ninth transistor T9 is electrically connected to the third node Q3. The ninth transistor T9 is configured to load the second power supply voltage V2 to the third node Q3 in response to the selected electrical level of the first node Q1. The first pole of the tenth transistor T10 is electrically connected to the first clock signal terminal. The second pole of the tenth transistor T10 is electrically connected to the first pole of the seventeenth transistor T17. The tenth transistor T10 is configured to load the voltage of the first clock signal CKA to the first pole of the seventeenth transistor T17 in response to the selected electrical level of the control node QB. The second pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to load the voltage of the control node QB to the control terminal of the fifteenth transistor T15 in response to the second power supply voltage V2. The first pole of the twelfth transistor T12, the second pole of the seventeenth transistor T17, and the third node Q3 are electrically connected to each other. The second pole of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, and the fourth node Q4 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second power supply voltage terminal. The twelfth transistor T12 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the second power supply voltage V2. The first pole of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. The second pole of the fourteenth transistor T14, the second electrode plate of the third capacitor C3, the second pole of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the selected electrical level of the fourth node Q4. The first pole of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the selected electrical level of the control node QB; the second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal. The control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal. The seventeenth transistor T17 is configured to load the voltage of the second pole of the tenth transistor T10 to the third node Q3 in response to the selected electrical level of the second clock signal CKB.

[0171] It should be noted that in this example, each transistor is a P-type transistor. The selected active levels of all signals are low levels. The first power supply voltage V1 is the high-level power supply voltage VGH, and the second power supply voltage V2 is the low-level power supply voltage VGL. The active level of the output clock signal GCK is high level.

[0172] In this way, the seventeenth transistor T17 separates the ninth transistor T9 and the tenth transistor T10. Since the control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal, the seventeenth transistor T17 is intermittently turned on, thereby avoiding the abnormal setting of the third node Q3 and the fourth node Q4 when the first clock signal CKA is at a low level.

[0173] In the third example, as Figure 12 As shown, the shift register SR includes the first transistor T1 to the twelfth transistor T12, the fourteenth transistor T14, and the fifteenth transistor T15. The first pole of the first transistor T1 is electrically connected to the second power supply voltage terminal. The second pole of the first transistor T1, the first pole of the fourth transistor T4, the control terminal of the fifth transistor T5, the first electrode plate of the first capacitor C1, the control terminal of the third transistor T3, the control terminal of the tenth transistor T10, the first pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the control node QB are electrically connected to each other. The control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to load the second power supply voltage V2 to the control node QB in response to the selected on level of the first clock signal CKA. The first pole of the second transistor T2 is electrically connected to the cascade input signal terminal. The second pole of the second transistor T2, the control terminal of the fourth transistor T4, the second pole of the sixth transistor T6, the first pole of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to load the voltage of the cascade input signal CRIN to the first node Q1 in response to the selected on level of the first clock signal CKA. The first pole of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. The second pole of the third transistor T3, the second electrode plate of the second capacitor C2, the second pole of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to load the first power supply voltage V1 to the cascade output signal terminal in response to the selected on level of the control node QB. The first pole of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selected on level of the first node Q1. The first pole of the fifth transistor T5 is electrically connected to the first power supply voltage terminal. The second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6. The fifth transistor T5 is configured to load the first power supply voltage V1 to the first pole of the sixth transistor T6 in response to the selected on level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to load the voltage of the first pole of the sixth transistor T6 to the first node Q1 in response to the selected on level of the second clock signal CKB. The second pole of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to load the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.The first pole of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to load the voltage of the second clock signal CKB to the cascaded output signal terminal in response to the selected power level of the second node Q2. The first pole of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. The second pole of the ninth transistor T9, the second pole of the tenth transistor T10, and the third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to load the second power supply voltage V2 to the third node Q3 in response to the selected power level of the first node Q1. The first pole of the tenth transistor T10 is electrically connected to the first clock signal terminal. The tenth transistor T10 is configured to load the voltage of the first clock signal CKA to the third node Q3 in response to the selected power level of the control node QB. The second pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to load the voltage of the control node QB to the control terminal of the fifteenth transistor T15 in response to the second power supply voltage V2. The first pole of the twelfth transistor T12 is electrically connected to the third node Q3. The second pole of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, and the fourth node Q4 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. The twelfth transistor T12 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected power level of the second clock signal CKB. The first pole of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. The second pole of the fourteenth transistor T14, the second electrode plate of the third capacitor C3, the second pole of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the selected power level of the fourth node Q4. The first pole of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the selected power level of the control node QB; the second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal.

[0174] It should be noted that in this example, each transistor is a P-type transistor. The selected power level of each signal is a low level. The first power supply voltage V1 is the high-level power supply voltage VGH, and the second power supply voltage V2 is the low-level power supply voltage VGL. The effective level of the output clock signal GCK is a high level.

[0175] Figure 13 For Figure 12 The driving timing diagram of the shift register SR shown. Among them, the clock cycles of the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all the same. The time length of the selected high level of the first clock signal CKA is 1 / 4 of a clock cycle. The time length of the selected high level of the second clock signal CKB is 1 / 4 of a clock cycle. The time length of the effective high level of the output clock signal GCK is 3 / 4 of a clock cycle. The selected high level of the first clock signal CKA is 1 / 2 of a clock cycle earlier than the selected high level of the second clock signal CKB, and the time lengths of the selected high levels of the first clock signal CKA and the second clock signal CKB are the same. The effective high level of the output clock signal GCK is 1 / 4 of a clock cycle earlier than the selected high level of the second clock signal CKB.

[0176] The following combines Figure 13 to Figure 12 exemplarily illustrate the working principle of the exemplary shift register SR.

[0177] Refer to Figure 12 and Figure 13 . At time P1, the cascaded input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all at low level, and the second clock signal CKB is at high level. Then the first transistor T1, the second transistor T2, the seventh transistor T7, and the eleventh transistor T11 are turned on, and the twelfth transistor T12 is turned off; the fourth node Q4 is at high level, making the fourteenth transistor T14 turned off; the low-level power supply voltage VGL makes the control node QB at low level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned on. At the same time, the cascaded input signal CRIN makes the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 turned on, so that the high level of the second clock signal CKB is output at the cascaded output signal terminal; since the fifteenth transistor T15 is turned on, the low level of the low-level power supply voltage VGL is output at the scan output signal terminal GOUT.

[0178] At time P2, the cascaded input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all at high level, then the first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12 are turned off. Through the coupling effect of the second capacitor C2, the first node Q1 and the second node Q2 remain at low level, then the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 are turned on. The first clock signal CKA makes the control node QB at high level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned off. Then the high level of the second clock signal CKB is output at the cascaded output signal terminal. Through the coupling effect of the third capacitor C3, the fourth node Q4 is made at low level, so that the fourteenth transistor T14 is turned on, and the high level of the output clock signal GCK is output at the scan output signal terminal GOUT.

[0179] At time P3, the cascaded input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all at high level, and the second clock signal CKB is at low level, then the first transistor T1 and the second transistor T2 are turned off, and the sixth transistor T6 and the twelfth transistor T12 are turned on. The first node Q1 and the second node Q2 remain at low level, the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 are turned on, so that the low level of the second clock signal CKB is output at the cascaded output signal terminal. The control node QB remains at high level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned off. The low-level power supply voltage VGL makes the third node Q3 and the fourth node Q4 still remain at low level, so that the fourteenth transistor T14 is turned on, and the scan output signal terminal GOUT continues to output the high level of the output clock signal GCK.

[0180] At time P4, the cascaded input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all at high level, then the first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12 are turned off. The first node Q1 and the second node Q2 remain at low level, the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 are turned on, so that the high level of the second clock signal CKB is output at the cascaded output signal terminal. The first clock signal CKA makes the control node QB still remain at high level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned off. The low-level power supply voltage VGL makes the third node Q3 still remain at low level. Due to the coupling effect of the third capacitor C3, the fourteenth transistor T14 is turned on, and the high level of the output clock signal GCK is output at the scan output signal terminal GOUT.

[0181] At time P5, the cascaded input signal CRIN and the second clock signal CKB are both at high level, the first clock signal CKA and the output clock signal GCK are both at low level. Then the first transistor T1, the second transistor T2, the seventh transistor T7 and the eleventh transistor T11 are turned on, and the twelfth transistor T12 is turned off. The low-level power supply voltage VGL makes the control node QB at low level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10 and the fifteenth transistor T15 are turned on. At the same time, the cascaded input signal CRIN makes the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 turned off, so that the cascaded output signal terminal outputs a high level of the high-level power supply voltage VGH. The fourth node Q4 is at low level, then the fourteenth transistor T14 is turned on, and the scan output signal terminal GOUT outputs a low level of the output clock signal GCK.

[0182] In this way, by using the second clock signal CKB to control the switch of the twelfth transistor T12, at time P1, it is possible to prevent the abnormal setting of the fourth node Q4 when the first clock signal CKA is at low level.

[0183] In the fourth example, as Figure 14 As shown, the shift register SR includes the first transistor T1 to the fifteenth transistor T15. The first pole of the first transistor T1 is electrically connected to the second power supply voltage terminal. The second pole of the first transistor T1, the first pole of the fourth transistor T4, the control terminal of the fifth transistor T5, the first electrode plate of the first capacitor C1, the control terminal of the third transistor T3, the control terminal of the tenth transistor T10, the first pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the control node QB are electrically connected to each other. The control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to load the second power supply voltage V2 to the control node QB in response to the selected high level of the first clock signal CKA. The first pole of the second transistor T2 is electrically connected to the cascade input signal terminal. The second pole of the second transistor T2, the control terminal of the fourth transistor T4, the second pole of the sixth transistor T6, the first pole of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to load the voltage of the cascade input signal CRIN to the first node Q1 in response to the selected high level of the first clock signal CKA. The first pole of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. The second pole of the third transistor T3, the second electrode plate of the second capacitor C2, the second pole of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to load the first power supply voltage V1 to the cascade output signal terminal in response to the selected high level of the control node QB. The first pole of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selected high level of the first node Q1. The first pole of the fifth transistor T5 is electrically connected to the first power supply voltage terminal. The second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6. The fifth transistor T5 is configured to load the first power supply voltage V1 to the first pole of the sixth transistor T6 in response to the selected high level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to load the voltage of the first pole of the sixth transistor T6 to the first node Q1 in response to the selected high level of the second clock signal CKB. The second pole of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to load the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2. The first pole of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to load the voltage of the second clock signal CKB to the cascade output signal terminal in response to the selected high level of the second node Q2.The first pole of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. The second pole of the ninth transistor T9, the second pole of the tenth transistor T10, and the third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to load the second power supply voltage V2 to the third node Q3 in response to the selected electrical level of the first node Q1. The first pole of the tenth transistor T10 is electrically connected to the first clock signal terminal. The tenth transistor T10 is configured to load the voltage of the first clock signal CKA to the third node Q3 in response to the selected electrical level of the control node QB. The second pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to load the voltage of the control node QB to the control terminal of the fifteenth transistor T15 in response to the second power supply voltage V2. The first pole of the twelfth transistor T12, the first pole of the thirteenth transistor T13, and the third node Q3 are electrically connected to each other. The second pole of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, the fourth node Q4, and the second pole of the thirteenth transistor T13 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. The twelfth transistor T12 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected electrical level of the second clock signal CKB. The control terminal of the thirteenth transistor T13 is electrically connected to the cascade input signal terminal. The thirteenth transistor T13 is configured to load the voltage of the third node Q3 to the fourth node Q4 in response to the selected electrical level of the cascade input signal CRIN. The first pole of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. The second pole of the fourteenth transistor T14, the second electrode plate of the third capacitor C3, the second pole of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the selected electrical level of the fourth node Q4. The first pole of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the selected electrical level of the control node QB; the second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal.

[0184] It should be noted that in this example, each transistor is a P-type transistor. The selected electrical level of each signal is a low level. The first power supply voltage V1 is the high-level power supply voltage VGH, and the second power supply voltage V2 is the low-level power supply voltage VGL. The effective level of the output clock signal GCK is a high level.

[0185] In this way, by multiplexing the cascaded input signal CRIN at the control terminal of the thirteenth transistor T13, it is convenient for the narrow border of the display panel PNL.

[0186] In the fifth example, as Figure 15 As shown, the shift register SR includes the first transistor T1 to the sixteenth transistor T16. The first pole of the first transistor T1 is electrically connected to the second power supply voltage terminal. The second pole of the first transistor T1, the first pole of the fourth transistor T4, the control terminal of the fifth transistor T5, the first electrode plate of the first capacitor C1, the control terminal of the third transistor T3, the control terminal of the tenth transistor T10, the first pole of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the control node QB are electrically connected to each other. The control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to load the second power supply voltage V2 to the control node QB in response to the selected high level of the first clock signal CKA. The first pole of the second transistor T2 is electrically connected to the cascade input signal terminal. The second pole of the second transistor T2, the control terminal of the fourth transistor T4, the second pole of the sixth transistor T6, the first pole of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to load the voltage of the cascade input signal CRIN to the first node Q1 in response to the selected high level of the first clock signal CKA. The first pole of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. The second pole of the third transistor T3, the second electrode plate of the second capacitor C2, the second pole of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to load the first power supply voltage V1 to the cascade output signal terminal in response to the selected high level of the control node QB. The first pole of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selected high level of the first node Q1. The first pole of the fifth transistor T5 is electrically connected to the first power supply voltage terminal. The second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6. The fifth transistor T5 is configured to load the first power supply voltage V1 to the first pole of the sixth transistor T6 in response to the selected high level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to load the voltage of the first pole of the sixth transistor T6 to the first node Q1 in response to the selected high level of the second clock signal CKB. The second pole of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to load the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2. The first pole of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to load the voltage of the second clock signal CKB to the cascade output signal terminal in response to the selected high level of the second node Q2.A first pole of a ninth transistor T9 is electrically connected to a second power supply voltage terminal. A second pole of the ninth transistor T9, a second pole of a tenth transistor T10, and a third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to load a second power supply voltage V2 to the third node Q3 in response to a selected electrical level of a first node Q1. A first pole of the tenth transistor T10 is electrically connected to a first clock signal terminal. The tenth transistor T10 is configured to load a voltage of a first clock signal CKA to the third node Q3 in response to a selected electrical level of a control node QB. A second pole of an eleventh transistor T11, a control terminal of a fifteenth transistor T15, and a second electrode plate of a fourth capacitor C4 are electrically connected to each other. A control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to load a voltage of the control node QB to the control terminal of the fifteenth transistor T15 in response to the second power supply voltage V2. A first pole of a twelfth transistor T12, a first pole of a thirteenth transistor T13, and the third node Q3 are electrically connected to each other. A second pole of the twelfth transistor T12, a control terminal of a fourteenth transistor T14, a first electrode plate of a third capacitor C3, a fourth node Q4, and a second pole of the thirteenth transistor T13 are electrically connected to each other. A control terminal of the twelfth transistor T12 is electrically connected to a second clock signal terminal. The twelfth transistor T12 is configured to load a voltage of the third node Q3 to the fourth node Q4 in response to a selected electrical level of a second clock signal CKB. A control terminal of the thirteenth transistor T13 is electrically connected to a cascaded input signal terminal. The thirteenth transistor T13 is configured to load a voltage of the third node Q3 to the fourth node Q4 in response to a selected electrical level of a cascaded input signal CRIN. A first pole of the fourteenth transistor T14 is electrically connected to an output clock signal terminal. A second pole of the fourteenth transistor T14, a second electrode plate of the third capacitor C3, a second pole of the fifteenth transistor T15, and a scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to output a voltage of an output clock signal GCK to the scan output signal terminal GOUT in response to a selected electrical level of the fourth node Q4. A first pole of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to a selected electrical level of the control node QB; the second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal. A first pole of a sixteenth transistor T16, a control terminal of the sixteenth transistor T16, and the first clock signal terminal are electrically connected to each other. A second pole of the sixteenth transistor T16 is electrically connected to a first electrode plate of the fourth capacitor C4. The sixteenth transistor T16 is configured to load a voltage of the first clock signal CKA to the first electrode plate of the fourth capacitor C4 in response to a selected electrical level of the first clock signal CKA.

[0187] It should be noted that in this example, each transistor is a P-type transistor. The selected conduction voltages of all signals are low levels. The first power supply voltage V1 is the high-level power supply voltage VGH, and the second power supply voltage V2 is the low-level power supply voltage VGL. The effective level of the output clock signal GCK is high level.

[0188] In this way, by providing the sixteenth transistor T16 between the fourth capacitor C4 and the first clock signal terminal, since the sixteenth transistor T16 is only turned on under the control of the selected conduction voltage of the first clock signal CKA and turned off under the control of the cut-off voltage of the first clock signal CKA, it is possible to prevent the fourth capacitor C4 from continuously charging or discharging, which is convenient for reducing the power consumption of the system.

[0189] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only considered exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.< / n>

Claims

1. A shift register, wherein: The shift register includes an input circuit, a cascade output circuit, a control circuit, and a scan output circuit; The input circuit is used to control the levels of the first node and the control node under the control of the first clock signal and the cascade output signal of the previous stage cascade output circuit; The cascade output circuit is used to output a cascade output signal under the control of the first node, the control node and the second clock signal; The control circuit is used to control the level of the fourth node under the control of the first node, the control node and the first clock signal; The scan output circuit is used to output a scan signal under the control of the control node, the fourth node, and the output clock signal; The effective level duration of the cascade output signal output by the cascade output circuit is shorter than the effective level duration of the scan signal output by the scan output circuit.

2. The shift register according to claim 1, wherein: The cascade output circuit comprises a first cascade output subcircuit and a second cascade output subcircuit; The first electrode of the first cascade output subcircuit is electrically connected to the first power supply voltage terminal, the second electrode is electrically connected to the cascade output signal terminal, and the control terminal is electrically connected to the control node. The first cascade output subcircuit is configured to load the first power supply voltage to the cascade output signal terminal in response to the gating level of the control node; The first pole of the second cascade output subcircuit is electrically connected to the second clock signal terminal, the second pole of the second cascade output subcircuit is electrically connected to the cascade output signal terminal, the control terminal of the second cascade output subcircuit is electrically connected to the first node, and the second cascade output subcircuit is configured to respond to the selection level of the first node so that the voltage of the second clock signal is loaded to the cascade output signal terminal.

3. The shift register according to claim 1, wherein: The scan output circuit includes a first scan output subcircuit and a second scan output subcircuit; The first scan output subcircuit has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the scan output signal terminal, and a control terminal electrically connected to the control node, and the first scan output subcircuit is configured to output the second power supply voltage to the scan output signal terminal in response to a gating level of the control node; The first pole of the second scan output sub-circuit is electrically connected to the output clock signal terminal, the second pole is electrically connected to the scan output signal terminal, and the control terminal is electrically connected to the fourth node. The second scan output sub-circuit is configured to output the voltage of the output clock signal to the scan output signal terminal in response to the selection level of the fourth node.

4. The shift register according to claim 1, wherein: The input circuit includes a cascade input subcircuit, a first subcircuit, and a second subcircuit; The first pole of the cascade input subcircuit is electrically connected to the cascade input signal terminal, the second pole of the cascade input subcircuit is electrically connected to the first node, the control terminal of the cascade input subcircuit is electrically connected to the first clock signal terminal, and the cascade input subcircuit is configured to load the voltage of the cascade input signal to the first node in response to the gating level of the first clock signal; The first subcircuit has a first electrode electrically connected to a second power supply voltage terminal, a second electrode electrically connected to the control node, and a control terminal electrically connected to the first clock signal terminal, and the first subcircuit is configured to load the second power supply voltage to the control node in response to a gating level of the first clock signal; The first pole of the second sub-circuit is electrically connected to the first clock signal terminal, the second pole is electrically connected to the control node, the control terminal is electrically connected to the first node, and the second sub-circuit is configured to load the voltage of the first clock signal to the control node in response to the selection level of the first node.

5. The shift register according to claim 1, wherein: The control circuit includes a third sub-circuit, a fourth sub-circuit and a fifth sub-circuit; The first electrode of the third sub-circuit is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the third node, and the control terminal is electrically connected to the control node. The third sub-circuit is configured to load the voltage of the first clock signal to the third node in response to the gating level of the control node; The first electrode of the fourth sub-circuit is electrically connected to the second power supply voltage terminal, the second electrode is electrically connected to the third node, and the control terminal is electrically connected to the first node. The fourth sub-circuit is configured to load the second power supply voltage to the third node in response to the gating level of the first node; The first pole of the fifth sub-circuit is electrically connected to the third node, the second pole is electrically connected to the fourth node, and the control terminal is electrically connected to any one of the second clock signal terminal and the second power supply voltage terminal. The fifth sub-circuit is configured to load the voltage of the third node to the fourth node in response to the selection level of the second clock signal or the second power supply voltage.

6. The shift register according to claim 2, wherein: The first cascade output subcircuit includes a third transistor and a first capacitor; The first electrode of the third transistor, the first electrode plate of the first capacitor, and the first power supply voltage terminal are electrically connected, the second electrode of the third transistor is electrically connected to the cascade output signal terminal, the control terminal of the third transistor, the second electrode plate of the first capacitor, and the control node are electrically connected, and the third transistor is configured to load the first power supply voltage to the cascade output signal terminal in response to the gating level of the control node; The second cascade output subcircuit includes an eighth transistor and a second capacitor; The first electrode of the eighth transistor is electrically connected to the second clock signal terminal, the second electrode of the eighth transistor, the second electrode plate of the second capacitor and the cascade output signal terminal are electrically connected to each other, the control terminal of the eighth transistor, the first electrode plate of the second capacitor and the second node are electrically connected to each other, and the eighth transistor is configured to respond to the selection level of the second node so that the voltage of the second clock signal is loaded to the cascade output signal terminal.

7. The shift register according to claim 3, wherein: The first scan output subcircuit includes a fifteenth transistor and a fourth capacitor; The first electrode of the fifteenth transistor is electrically connected to the second power supply voltage terminal, the second electrode is electrically connected to the scan output signal terminal, the control terminal of the fifteenth transistor, the first electrode plate of the fourth capacitor and the control node are electrically connected to each other, and the fifteenth transistor is configured to output the second power supply voltage to the scan output signal terminal in response to the gating level of the control node; the second electrode plate of the fourth capacitor is electrically connected to the first clock signal terminal; The second scan output subcircuit includes a fourteenth transistor and a third capacitor; The first electrode of the fourteenth transistor is electrically connected to the output clock signal terminal, and the second electrode is electrically connected to the scan output signal terminal. The control terminal of the fourteenth transistor, the first electrode plate of the third capacitor, and the fourth node are electrically connected to each other. The fourteenth transistor is configured to output the voltage of the output clock signal to the scan output signal terminal in response to the selection level of the fourth node.

8. The shift register according to claim 4, wherein: The cascade input subcircuit includes a second transistor; The first electrode of the second transistor is electrically connected to the cascade input signal terminal, the second electrode is electrically connected to the first node, and the control terminal is electrically connected to the first clock signal terminal. The second transistor is configured to load the voltage of the cascade input signal to the first node in response to the gating level of the first clock signal; The first subcircuit includes a first transistor; The first transistor has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the control node, and a control terminal electrically connected to the first clock signal terminal, and the first transistor is configured to load the second power supply voltage to the control node in response to a gating level of the first clock signal; The second sub-circuit includes a fourth transistor; The first electrode of the fourth transistor is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the control node, the control terminal is electrically connected to the first node, and the fourth transistor is configured to load the voltage of the first clock signal to the control node in response to the selection level of the first node.

9. The shift register according to claim 5, wherein: The third sub-circuit includes a tenth transistor; The first electrode of the tenth transistor is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the third node, and the control terminal is electrically connected to the control node. The tenth transistor is configured to load the voltage of the first clock signal to the third node in response to the gating level of the control node; The fourth sub-circuit includes a ninth transistor; The first electrode of the ninth transistor is electrically connected to the second power supply voltage terminal, the second electrode is electrically connected to the third node, and the control terminal is electrically connected to the first node. The ninth transistor is configured to load the second power supply voltage to the third node in response to the gating level of the first node; The fifth sub-circuit includes a twelfth transistor; The first electrode of the twelfth transistor is electrically connected to the third node, the second electrode of the twelfth transistor is electrically connected to the fourth node, the control terminal of the twelfth transistor is electrically connected to any one of the second clock signal terminal and the second power supply voltage terminal, and the twelfth transistor is configured to load the voltage of the third node to the fourth node in response to the selection level of the second clock signal or the second power supply voltage.

10. The shift register according to claim 7, wherein: The shift register further includes a sixteenth transistor; The first electrode of the sixteenth transistor, the control end of the sixteenth transistor and the first clock signal end are electrically connected to each other, the second electrode of the sixteenth transistor is electrically connected to the first electrode plate of the fourth capacitor, and the sixteenth transistor is configured to respond to the selection level of the first clock signal so that the voltage of the first clock signal is loaded onto the first electrode plate of the fourth capacitor.

11. The shift register according to claim 9, wherein: The control circuit further includes a thirteenth transistor; The first electrode of the thirteenth transistor is electrically connected to the third node, the second electrode of the thirteenth transistor is electrically connected to the fourth node, the control end of the thirteenth transistor is electrically connected to any one of the first node, the second node, and the cascade input signal end, and the thirteenth transistor is configured to load the voltage of the third node to the fourth node in response to the selection level of the first node or the second node or the cascade input signal.

12. The shift register according to claim 9, wherein: The shift register further includes a seventeenth transistor; The first electrode of the seventeenth transistor is electrically connected to the second electrode of the tenth transistor, the second electrode of the seventeenth transistor is electrically connected to the third node, the control terminal of the seventeenth transistor is electrically connected to the second clock signal terminal, and the seventeenth transistor is configured to respond to the selection level of the second clock signal so that the voltage of the second electrode of the tenth transistor is loaded to the third node.

13. The shift register according to any one of claims 1 to 12, wherein: The shift register further includes a fifth transistor, a sixth transistor, and a seventh transistor; The first electrode of the fifth transistor is electrically connected to the first power supply voltage terminal, the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, the control terminal of the fifth transistor is electrically connected to the control node, and the fifth transistor is configured to load the first power supply voltage to the first electrode of the sixth transistor in response to the gating level of the control node; The second electrode of the sixth transistor, the first electrode of the seventh transistor and the first node are electrically connected to each other, the control terminal of the sixth transistor is electrically connected to the second clock signal terminal, and the sixth transistor is configured to load the voltage of the first electrode of the sixth transistor to the first node in response to the gating level of the second clock signal; The second electrode of the seventh transistor is electrically connected to the second node, the control terminal of the seventh transistor is electrically connected to the second power supply voltage terminal, and the seventh transistor is configured to load the voltage of the first node to the second node in response to the second power supply voltage; The clock period of the first clock signal, the clock period of the second clock signal and the clock period of the output clock signal are all the same; The duration of the gating level of the first clock signal does not exceed 1 / 4 of a clock cycle; The duration of the gating level of the second clock signal does not exceed 1 / 4 of a clock cycle; The time length of the effective level of the output clock signal is greater than 1 / 2 clock cycle; The gating level of the first clock signal is 1 / 2 clock cycle earlier than the gating level of the second clock signal; The effective level of the output clock signal is 1 / 4 clock cycle earlier than the selection level of the second clock signal.

14. A gate drive circuit, comprising a plurality of shift registers according to any one of claims 1 to 13 connected in cascade sequence; wherein: The cascade output signal terminal of the shift register at the previous stage is electrically connected to the cascade input signal terminal of the shift register at the next stage.

15. A display panel, comprising a gate drive circuit and a first control line, a second control line and a third control line for driving the gate drive circuit; The gate drive circuit comprises a plurality of shift registers according to any one of claims 1 to 13 which are cascaded in sequence; the cascade output signal terminal of the shift register of the previous stage is electrically connected to the cascade input signal terminal of the shift register of the next stage; The first control wiring is electrically connected to the first clock signal terminal of the odd-numbered shift register, and is electrically connected to the second clock signal terminal of the even-numbered shift register; The second control wiring is electrically connected to the second clock signal terminal of the odd-numbered shift register, and is electrically connected to the first clock signal terminal of the even-numbered shift register; The third control wiring is electrically connected to the output clock signal terminal of the shift register.

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