Display panel and display device

Abstract

The present application discloses a display panel and a display device; the display panel comprises a first data signal line, a second data signal line and a plurality of repeating units, the first sub-pixel unit is electrically connected to the first data signal line via a first electrical connection component, the second sub-pixel unit is electrically connected to the second data signal line via a second electrical connection component, the first electrical connection component, the second electrical connection component, the first data signal line and the second data signal line are all arranged on the same side of the repeating unit; the present application arranges the first data signal line and the first electrical connection component connected to the first sub-pixel unit in the repeating unit and the second data signal line and the second electrical connection component connected to the second sub-pixel unit on the same side of the repeating unit, thereby avoiding the first electrical connection component or the second electrical connection component from crossing the corresponding pixel driving circuit, reducing the parasitic capacitance on the data signal line, and improving the display picture of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology. It has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the related art, the film layer structure of the sub-pixel units of the OLED display panel is the same, and the data lines are usually arranged on both sides of the sub-pixel units. Some sub-pixel units in the same column require an electrical connection line that spans the sub-pixel units to be electrically connected to the corresponding data lines. The electrical connection line overlaps with the film layers in the sub-pixel units, which makes the parasitic capacitance of the data signal line larger, thereby affecting the transmission of the data signal and causing abnormal display of the display panel. Summary of the invention

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display of existing display panels.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a display panel, comprising a plurality of repeating units and a first data signal line and a second data signal line arranged on one side of the repeating unit, wherein the repeating unit comprises at least one first sub-pixel unit and at least one second sub-pixel unit, wherein the first sub-pixel unit and the second sub-pixel unit both comprise a pixel driving circuit and a light-emitting device connected to the pixel driving circuit;

[0007] In which, the display panel also includes a first electrically connecting component and a second electrically connecting component, the pixel driving circuit of the first sub-pixel unit is electrically connected to the first data signal line through the first electrically connecting component, and the pixel driving circuit of the second sub-pixel unit is electrically connected to the second data signal line through the second electrically connecting component, and the first electrically connecting component, the second electrically connecting component, the first data signal line and the second data signal line are all arranged on the same side of the repeating unit.

[0008] The present application also proposes a display device, which includes the above-mentioned display panel.

[0009] Beneficial effects: The present application discloses a display panel and a display device; the display panel includes a first data signal line, a second data signal line and a plurality of repeating units, the first sub-pixel unit is electrically connected to the first data signal line through a first electrical connection component, the second sub-pixel unit is electrically connected to the second data signal line through a second electrical connection component, and the first electrical connection component, the second electrical connection component, the first data signal line and the second data signal line are all arranged on the same side of the repeating unit; the present application arranges the first data signal line and the first electrical connection component connected to the first sub-pixel unit in the repeating unit and the second data signal line and the second electrical connection component connected to the second sub-pixel unit on the same side of the repeating unit, thereby avoiding the first electrical connection component or the second electrical connection component crossing the corresponding pixel driving circuit, reducing the parasitic capacitance on the data signal line, and improving the display picture of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0011] Figure 1 A connection diagram of different sub-pixel units and different data lines of a display panel in the prior art;

[0012] Figure 2 This is a connection diagram of different sub-pixel units and different data lines of the display panel of this application;

[0013] Figure 3 A simplified structural diagram of the display panel of this application;

[0014] Figure 4 is an equivalent circuit diagram of a pixel driving circuit in a display panel of the present application;

[0015] Figure 5 This is a schematic diagram of the film layer in the display panel of this application;

[0016] Figure 6 A film layer diagram of the first gate layer in the display panel of the present application;

[0017] Figure 7 A film layer diagram of the first active layer in the display panel of the present application;

[0018] Figure 8 A film layer stack diagram of a first gate layer and a first active layer in a display panel of the present application;

[0019] Fig. 9 A film layer diagram of the second gate layer in the display panel of the present application;

[0020] Fig.10 A film layer stack diagram of a first gate layer and a second gate layer in a display panel of the present application;

[0021] Fig.11 A film layer diagram of the second active layer in the display panel of the present application;

[0022] Fig.12 A film layer diagram of the third gate layer in the display panel of the present application;

[0023] Fig.13 A film layer diagram of a first active layer, a second active layer, a second gate layer and a third gate layer in the display panel of the present application;

[0024] Fig.14 A film layer diagram of a first source and drain electrode layer of a first sub-pixel unit in a display panel of the present application;

[0025] Fig.15 A film layer diagram of a first gate layer, a third gate layer, a first active layer, a second active layer and a first source and drain electrode layer of a first sub-pixel unit in the display panel of the present application;

[0026] Fig.16 A film layer diagram of a second active layer, a second gate layer, and a first source and drain layer of a first sub-pixel unit in a display panel of the present application;

[0027] Fig.17 A film layer diagram of a first gate layer, a second gate layer, a third gate layer, a first active layer, a second active layer and a first source and drain electrode layer of a first sub-pixel unit in the display panel of the present application;

[0028] Fig.18 This is a first film layer diagram of the second source and drain electrode layer in the display panel of the present application;

[0029] Fig.19 A film layer superposition diagram of a first active layer, a second active layer, a third gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a first sub-pixel unit in the display panel of the present application;

[0030] Fig. 20 This is a film layer overlay diagram of the pixel driving circuit of this application;

[0031] Fig.21 A film layer diagram of a first source and drain electrode layer of a second sub-pixel unit in a display panel of the present application;

[0032] Fig. 22 A film layer superposition diagram of a first active layer, a second active layer, a third gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a second sub-pixel unit in the display panel of the present application;

[0033] Fig.23 A second film layer diagram of a second source-drain electrode layer in the display panel of the present application;

[0034] Fig.24A film layer diagram of the third source and drain electrode layer in the display panel of the present application;

[0035] Fig.25 A film layer diagram of the superposition of the second source-drain electrode layer and the third source-drain electrode layer in the display panel of the present application;

[0036] Fig.26 This is a fourth film layer stacking diagram of the pixel driving circuit of the present application;

[0037] Fig. 27 A film layer diagram of a third source-drain electrode layer in a plurality of sub-pixel units in a display panel of the present application;

[0038] Fig.28 A connection relationship diagram of a first reset signal line, a second reset signal line, a third reset signal line and a fourth reset signal line in a display panel of the present application;

[0039] Fig.29 This is a superimposed diagram of the film layers of the third source and drain electrode layer, the data signal line and the anode of the light-emitting device in the display panel of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0041] In the prior art, the structures of the pixel driving circuits in different sub-pixel units are the same, that is, the data signal input terminals of the pixel driving circuits are all located on the same side, while the data signal lines in the current display panel are all located on both sides of the sub-pixel unit, for example Figure 1In the structure, the first data signal line Data1 is set on the left side of the sub-pixel unit P, and the second data signal line Data2 is set on the right side of the sub-pixel unit P. Then the data signal input terminal of the sub-pixel unit P in the first row is adjacent to the first data signal line Data1, and the spacing between the data signal input terminal of the sub-pixel unit P in the second row and the second data signal line Data2 is the width of a sub-pixel unit P, that is, a connecting line across the sub-pixel unit P is required to electrically connect the second data signal line Data2 and the data signal input terminal of the sub-pixel unit P in the second row. The connecting line overlaps with multiple film layer structures in the sub-pixel unit P, and the coupling capacitance between the second data signal line Data2 and the corresponding film layer increases, thereby affecting the transmission of the data signal of the second data signal line Data2, resulting in abnormal display of the display panel. Based on the above technical problems, the present application proposes a display panel to solve the above technical problems.

[0042] See also Figures 2 to 28 The present application provides a display panel 100 , which may include a display unit 200 and a gate driving circuit 300 located at one side of the display unit 200 , and the gate driving circuit 300 is used to input a control signal to the display unit 200 .

[0043] In this example, see Figure 3 The display unit 200 includes a plurality of sub-pixel rows 210, each sub-pixel row 210 includes a plurality of sub-pixel units 211, each sub-pixel unit 211 is provided with a light-emitting device 211b and a pixel driving circuit 211a connected to the light-emitting device 211b, and the gate driving circuit 300 is used to input a gate control signal to the transistor in the pixel driving circuit 211a.

[0044] See also Figure 2 , the multiple sub-pixel units 211 may include multiple repeating units 500, the repeating unit 500 includes at least one first sub-pixel unit 211c and at least one second sub-pixel unit 211d, the first sub-pixel unit 211c and the second sub-pixel unit 211d both include a pixel driving circuit 211a; the following embodiments are described by taking an example in which only the first sub-pixel unit 211c and the second sub-pixel unit 211d are provided in a repeating unit 500.

[0045] In this embodiment, the display panel 100 also includes a first data signal line Data1 and a second data signal line Data2, as well as a first electrical connection component 610 and a second electrical connection component 620, which are arranged on one side of the repeating unit 500. The pixel driving circuit 211a of the first sub-pixel unit 211c is electrically connected to the first data signal line Data1 through the first electrical connection component 610, and the pixel driving circuit 211a of the second sub-pixel unit 211d is electrically connected to the second data signal line Data2 through the second electrical connection component 620.

[0046] In this embodiment, the first electrical connection member 610 , the second electrical connection member 620 , the first data signal line Data1 , and the second data signal line Data2 are all disposed on the same side of the repeating unit 500 .

[0047] The present application arranges the first data signal line Data1 and the first electrical connection component 610 connected to the first sub-pixel unit 211c in the repeating unit 500 and the second data signal line Data2 and the second electrical connection component 620 connected to the second sub-pixel unit 211d on the same side of the repeating unit 500, thereby reducing the connection distance between the data signal line and the input end of the data signal in the sub-pixel unit 211, avoiding the first electrical connection component 610 or the second electrical connection component 620 crossing the corresponding pixel driving circuit 211a, reducing the parasitic capacitance on the data signal line, improving the stability of the pixel driving circuit 211a, and improving the display image of the display panel 100.

[0048] It should be noted that the structure of the pixel driving circuit 211a in different sub-pixel units 211 of the present application can be the same, the only difference is that different sub-pixel units 211 are provided with different electrical connection components, for example, the first electrical connection component 610 in the first sub-pixel unit 211c and the second electrical connection component 620 in the second sub-pixel unit 211d are arranged at different positions in the corresponding sub-pixel unit 211.

[0049] It should be noted that the light-emitting device 211b of the present application can be an organic light-emitting diode, Mini LED, MicroLED, a conventional-sized LED or other light-emitting source.

[0050] The technical solution of the present application is now described in conjunction with specific embodiments.

[0051] See also Figure 3The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA, and a display unit 200 is disposed in the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for performing a display function, and a plurality of sub-pixel units 211 for realizing its display function are disposed therein. The non-display area NA may be a frame area of ​​the display panel 100, and a functional component for displaying the sub-pixel unit 211 in the auxiliary display area AA may be disposed therein.

[0052] See also Figure 3 The lower side of the display area AA is provided with a binding terminal 400, which can be connected to an external circuit, and transmits the signal input by the external circuit to the data line, thereby driving the display panel 100 to display the picture. For example, the binding terminal 400 can be bound and connected to a chip or a flip chip film, etc., to provide power and driving signals for the display panel 100.

[0053] In this embodiment, the gate driving circuit 300 is arranged in the non-display area NA, and the gate driving circuit 300 can be arranged on both sides of the display area AA; the gate driving circuit 300 may include a plurality of cascaded gate driving units, and the plurality of gate driving units may be arranged along the first direction X. The structure of the gate driving unit is not specifically limited in this application.

[0054] In this embodiment, a plurality of light-emitting devices 211b and a pixel driving circuit 211a for driving the light-emitting devices 211b may be arranged in an array in the display area AA. The pixel driving circuit 211a may be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C or other pixel driving circuit 211a. In the following embodiments, the 8T3C pixel driving circuit 211a is used as an example for description. Since the structures of the pixel driving circuits 211a in different sub-pixel units 211 are the same, the structure of the pixel driving circuit 211a of the first sub-pixel unit 211c is first described below.

[0055] See also Figure 4 The pixel driving circuit 211a may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a third reset transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a boost capacitor Cboost and a storage capacitor Cst, the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2, and the boost capacitor Cboost includes a third plate and a fourth plate.

[0056] See also Figure 4, the first electrode of the switching transistor T2 is connected to the first data signal line Data1, the second electrode of the switching transistor T2 is connected to the first node A, and the switching gate T2G of the switching transistor T2 is connected to the second control signal line Pscan1; the first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the second node B, and the driving gate T1G of the driving transistor T1 is connected to the third node Q; the first electrode of the compensation transistor T3 is connected to the third node Q, the second electrode of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the first control signal line Nscan1; the first electrode of the first reset transistor T4 is connected to the first reset signal line Vi1, the second electrode of the first reset transistor T4 is connected to the third node Q, and the first reset gate T4G of the first reset transistor T4 is connected to the third control signal line Nscan2; the first electrode of the second reset transistor T7 is connected to the second reset signal line Vi2, the second electrode of the second reset transistor T7 is connected to the anode of the light emitting device 211b, and the second reset gate T4G of the second reset transistor T7 is connected to the third control signal line Nscan2. T7G is connected to the fourth control signal line Pscan2; the first electrode of the third reset transistor T8 is connected to the third reset signal line Vi3, the second electrode of the third reset transistor T8 is connected to the first node A, and the third reset gate T8G of the third reset transistor T8 is connected to the fourth control signal line Pscan2; the first electrode of the first light-emitting transistor T5 is connected to the first high potential line VDD1, the second electrode of the first light-emitting transistor T5 is connected to the first node A, and the first light-emitting gate T5G of the first light-emitting transistor T5 is connected to the light-emitting signal line EM; the first electrode of the second light-emitting transistor T6 is connected to the second node B, the second electrode of the second light-emitting transistor T6 is connected to the anode of the light-emitting device 211b, and the second light-emitting gate T6G of the second light-emitting transistor T6 is connected to the light-emitting signal line EM; the third plate of the boost capacitor Cboost is connected to the third node Q, and the fourth plate of the boost capacitor Cboost is connected to the second control signal line Pscan1; the first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the second plate Cst2 of the storage capacitor Cst is connected to the first high potential line VDD1.

[0057] It should be noted that the switch transistors T2 in different sub-pixel units 211 are connected to different data signal lines, and the present application only takes one of them as an example for description.

[0058] In this embodiment, the first high potential line VDD1 is used to provide a constant high voltage level to the pixel driving circuit 211 a , and the first low potential line VSS is used to provide a constant low voltage level to the pixel driving circuit 211 a .

[0059] In this embodiment, the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 can be one of P-type transistors or N-type transistors, and the compensation transistor T3 and the first reset transistor T4 can be the other of P-type transistors or N-type transistors; this application is described by taking the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 as N-type transistors as an example.

[0060] In this embodiment, the capacitance value of the boost capacitor Cboost is smaller than the capacitance value of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is mainly used to maintain the stability of the potential of the third node Q, so the capacitance of the storage capacitor Cst is relatively large, for example, the capacitance value range of the storage capacitor Cst may be 45fF to 55fF, and the capacitance value range of the boost capacitor Cboost may be 5fF to 15fF.

[0061] In this embodiment, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

[0062] In the following embodiments, the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°. For example, the first direction X is the horizontal direction and the second direction Y is the vertical direction.

[0063] The following is for Figure 4 The structure of the film layer structure of the pixel driving circuit 211a of the present application is described.

[0064] See also Figure 5 The display area AA and the non-display area NA of the display panel 100 may be provided with a base substrate 110 and an array driving layer 120 provided on the base substrate 110; in the display area AA, the display panel 100 may also be provided with a pixel definition layer (not shown) provided on the array driving layer 120, a light emitting device layer (not shown) provided on the same layer as the pixel definition layer, and an encapsulation layer (not shown) provided on the pixel definition layer. The following mainly describes the film layer structure in the display area AA.

[0065] In the present embodiment, the base substrate 110 supports various layers disposed on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate may be used.

[0066] In the present embodiment, the base substrate 110 is used to support various film layers disposed on the base substrate 110, and the base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0067] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0068] In the present embodiment, the first flexible substrate 111 is formed by coating a polymer material on a support substrate (not shown) and then curing the polymer material, the second flexible substrate 113 is formed by coating the same material as the first flexible substrate 111 and curing the material, and the second flexible substrate 113 is formed by the same method as the method of forming the first flexible substrate 111. Each of the first flexible substrate 111 and the second flexible substrate 113 may be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the base substrate 110 is formed of the first flexible substrate 111 and the second flexible substrate 113, small holes, cracks, etc. formed during the manufacture of the first flexible substrate 111 are covered by the second flexible substrate 113, so that the above-mentioned defects can be removed.

[0069] See also Figure 5 , the array driving layer 120 may include a plurality of thin film transistors, the thin film transistors may be of an etching barrier type, a back channel etching type, or may be divided into a bottom gate thin film transistor, a top gate thin film transistor and the like structure according to the position of the gate and the active layer, or may be divided into an N-type thin film transistor, a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 5 The thin film transistor does not represent Figure 4 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of the present application.

[0070] See also Figure 5The array driving layer 120 may include a light shielding layer 121 disposed on the base substrate 110, a buffer layer 122 disposed on the light shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, a third gate insulating layer 128 disposed on the second gate layer 127, a second active layer 129 disposed on the third gate insulating layer 128, and a A fourth gate insulating layer 130 is disposed on the second active layer 129, a third gate layer 131 is disposed on the fourth gate insulating layer 130, a first interlayer insulating layer 132 is disposed on the third gate layer 131, a first source-drain layer 133 is disposed on the first interlayer insulating layer 132, a second interlayer insulating layer 134 is disposed on the first source-drain layer 133, a second source-drain layer 135 is disposed on the second interlayer insulating layer 134, a third interlayer insulating layer 136 is disposed on the second source-drain layer 135, a third source-drain layer 137 is disposed on the third interlayer insulating layer 136, and a planarization layer 138 is disposed on the third source-drain layer 137.

[0071] See also Figure 5 The light shielding layer 121 is disposed on the second barrier layer 114. The light shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be composed of a black light shielding material, such as a black light shielding metal or a black organic material.

[0072] See also Figure 5 The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0073] See also Figure 5 The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low-temperature polycrystalline silicon. For example, in the present application, the material of the first active layer 123 can be low-temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0074] See also Figure 5The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132, the second interlayer insulating layer 134, and the third interlayer insulating layer 136 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the material of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130, the second interlayer insulating layer 134, and the third interlayer insulating layer 136 can be an inorganic substance composed of nitride oxide silicon or an organic material with flatness.

[0075] See also Figure 5 The first gate layer 125, the second gate layer 127 and the third gate layer 131 are respectively arranged on the corresponding insulating layers. The materials of the first gate layer 125, the second gate layer 127 and the third gate layer 131 can be copper, molybdenum or molybdenum-titanium alloy, etc. The material of the three gate layers of the present application can be molybdenum.

[0076] See also Figure 5 The first source-drain electrode layer 133 is disposed on the first interlayer insulating layer 132, the second source-drain electrode layer 135 is disposed on the second interlayer insulating layer 134, and the third source-drain electrode layer 137 is disposed on the third interlayer insulating layer 136. The materials of the first source-drain electrode layer 133, the second source-drain electrode layer 135, and the third source-drain electrode layer 137 can be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium three-layer metal, etc. The material of the three-layer source-drain electrode layer of the present application can be titanium-aluminum-titanium.

[0077] See also Figure 5 The planarization layer 138 is laid as a whole layer to ensure the flatness of the film layer of the array driving layer 120. The material of the planarization layer 138 can be an inorganic material composed of nitride oxide silicon or an organic material with flatness.

[0078] See also Figure 6 The first gate layer 125 includes a light-emitting signal line EM, a first reset signal line Vi1, a third reset signal line Vi3, and a fourth control signal line Pscan2. The light-emitting signal line EM, the first reset signal line Vi1, the third reset signal line Vi3, and the fourth control signal line Pscan2 all extend along the first direction X, and the third reset signal line Vi3, the fourth control signal line Pscan2, the light-emitting signal line EM and the first reset signal line Vi1 are arranged at intervals along the second direction Y.

[0079] See also Figure 6The first gate layer 125 also includes a switch gate T2G and a first electrode plate Cst1 of a storage capacitor Cst, which are arranged between the light-emitting signal line EM and the first reset signal line Vi1. The switch gate T2G and the first electrode plate Cst1 are arranged at intervals in the second direction Y, and the first electrode plate Cst1 is arranged close to the light-emitting signal line EM, and the switch gate T2G is arranged away from the light-emitting signal line EM.

[0080] In this embodiment, the light emitting signal line EM can directly serve as the first light emitting gate T5G and the second light emitting gate T6G, and the fourth control signal line Pscan2 can directly serve as the second reset gate T7G and the third reset gate T8G.

[0081] See also Figure 6 The switch gate T2G and the first electrode plate Cst1 may be in a rectangular shape, and the four corners of the first electrode plate Cst1 may be chamfered.

[0082] See also Figure 7 The first active layer 123 includes a switch active portion T2A of the switch transistor T2, a drive active portion T1A of the drive transistor T1, a second reset active portion T7A of the second reset transistor T7, a third reset active portion T8A of the third reset transistor T8, a first light emitting active portion T5A of the first light emitting transistor T5, and a second light emitting active portion T6A of the second light emitting transistor T6.

[0083] See also Figure 7 The switch active part T2A, the driving active part T1A, the second reset active part T7A, the first light emitting active part T5A, and the second light emitting active part T6A are connected to each other, the third reset active part T8A is arranged separately from the other active parts, the switch active part T2A, the second reset active part T7A, the third reset active part T8A, the first light emitting active part T5A, and the second light emitting active part T6A are all strip-shaped and extend along the second direction Y, the driving active part T1A is in a "X" shape and is arranged between the first light emitting active part T5A and the second light emitting active part T6A, the first end of the switch active part T2A, the first end of the driving active part T1A, and the first end of the first light emitting active part T5A are connected to the first connection point P1, the second end of the driving active part T1A and the first end of the second light emitting active part T6A are connected to the second connection point P2, and the first end of the second reset active part T7A and the second end of the second light emitting active part T6A are connected to the third connection point P3.

[0084] In this embodiment, the first connection point P1 is the first node A, the second connection point P2 is the second node B, and the third connection point P3 is the point where the anode of the light emitting device 211b is located.

[0085] It should be noted that the patterns of the switch active portion of the first sub-pixel unit 211 c and the switch active portion of the second sub-pixel unit 211 d are the same.

[0086] See also Figure 8 , the light-emitting signal line EM partially overlaps with the first light-emitting active part T5A, and the overlapping part is the channel of the first light-emitting active part T5A; the light-emitting signal line EM partially overlaps with the second light-emitting active part T6A, and the overlapping part is the channel of the second light-emitting active part T6A; the switch gate T2G partially overlaps with the switch active part T2A, and the overlapping part is the channel of the switch active part T2A; the fourth control signal line Pscan2 partially overlaps with the second reset active part T7A, and the overlapping part is the channel of the second reset active part T7A; the fourth control signal line Pscan2 partially overlaps with the third reset active part T8A, and the overlapping part is the channel of the third reset active part T8A; the driving active part T1A partially overlaps with the first electrode plate Cst1, and the overlapping part is the channel of the driving active part T1A. The first electrode plate Cst1 of the present application is multiplexed as the driving gate T1G of the driving transistor T1.

[0087] See also Fig. 9 and Fig.10 The second gate layer 127 includes a second plate Cst2 of a storage capacitor Cst arranged along a second direction Y, a first shading unit T3S of a compensation transistor T3, and a second shading unit T4S of a first reset transistor T4. The second plate Cst2, the first shading unit T3S and the second shading unit T4S are located between the light-emitting signal line EM and the first reset signal line Vi1. The first plate Cst1 is arranged close to the light-emitting signal line EM, the second shading unit T4S is arranged close to the first reset signal line Vi1, and the first shading unit T3S is located between the second shading unit T4S and the second plate Cst2.

[0088] See also Fig. 9 and Fig.10 The area of ​​the second electrode plate Cst2 is greater than that of the first electrode plate Cst1, and the orthographic projection of the first electrode plate Cst1 on the second electrode plate Cst2 is located inside the second electrode plate Cst2. A first through hole HL0 is opened on the second electrode plate Cst2 to expose a portion of the first electrode plate Cst1.

[0089] See also Fig.10 The first light shielding unit T3S, the second light shielding unit T4S and the second electrode plate Cst2 may be in the shape of a rectangle, and at least part of the top corners of the three may be chamfered.

[0090] See also Fig.10The second gate layer 127 also includes first electrical connection segments 311 arranged on both sides of the second electrode Cst2, and the two first electrical connection segments 311 extend along the first direction X, and in two adjacent sub-pixel units 211 arranged along the first direction X, the second electrodes Cst2 in the two sub-pixel units 211 are electrically connected through the first electrical connection segments 311; the second electrode Cst2 of the present embodiment is connected to the first high potential line VDD1, and in order to reduce the impedance on the second electrode Cst2, the present application can connect the second electrodes Cst2 in the sub-pixel units 211 arranged along the first direction X to each other, and set them in parallel with the first high potential line VDD1 of the upper layer, so as to reduce the impedance of the first high potential line VDD1 and the second electrode Cst2.

[0091] See also Fig.11 and Fig.13 The second active layer 129 includes a compensation active portion T3A of the compensation transistor T3 and a first reset active portion T4A of the first reset transistor T4, the compensation active portion T3A and the first reset active portion T4A both extend along the second direction Y, a first end of the compensation active portion T3A and a first end of the first reset active portion T4A are connected to a fourth connection point P4, a second end of the compensation active portion T3A extends toward the second connection point P2 and is separated from the second connection point P2, and a second end of the first reset active portion T4A extends toward the first reset signal line Vi1 and overlaps with the first reset signal line Vi1.

[0092] In this embodiment, the fourth connection point P4 may be the third node Q.

[0093] See also Fig.11 and Fig.13 The second active layer 129 also includes a first extension segment 321 connected to the fourth connection point P4 and a second extension segment 322 connected to the second end of the first reset active portion T4A; the first extension segment 321 extends along the second direction Y and extends toward the location of the storage capacitor Cst, and the first extension segment 321 is separated from the storage capacitor Cst; the second extension segment 322 extends along the first direction X, and the second extension segment 322 at least partially overlaps with the first reset signal line Vi1.

[0094] See also Fig.12 and Fig.13 The third gate layer 131 includes a compensation gate T3G and a first reset gate T4G of the first reset transistor T4, the area of ​​the compensation gate T3G is smaller than the area of ​​the first shading unit T3S, the orthographic projection of the compensation gate T3G on the first shading unit T3S is located in the first shading unit T3S, the area of ​​the first reset gate T4G is smaller than the area of ​​the second shading unit T4S, and the orthographic projection of the first reset gate T4G on the second shading unit T4S is located in the second shading unit T4S.

[0095] See also Fig.12 and Fig.13 The first reset gate T4G and the first reset active portion T4A partially overlap, and the overlapping portion is the channel of the first reset active portion T4A; the compensation gate T3G and the compensation active portion T3A partially overlap, and the overlapping portion is the channel of the compensation active portion T3A.

[0096] See also Fig.12 and Fig.13 The first reset gate T4G and the compensation gate T3G may both be in the shape of a rectangle, and part of the top corners of the first reset gate T4G and the compensation gate T3G may be chamfered.

[0097] See also Fig.12 and Fig.13 The third gate layer 131 further includes a first conductive segment 331 connected to the compensation gate T3G, and a second conductive segment 332 connected to the first reset gate T4G. The first conductive segment 331 extends along the second direction Y and toward a side away from the compensation gate T3G, and the second conductive segment 332 extends along the second direction Y and toward a side away from the first reset gate T4G.

[0098] See also Fig. 9 and Fig.13 The second gate layer 127 further includes a third conductive segment 333 connected to the first light shielding unit T3S, and a fourth conductive segment 334 connected to the second light shielding unit T4S. The third conductive segment 333 extends along the second direction Y and toward the side away from the compensation gate T3G, the line width of the first conductive segment 331 may be less than or equal to the line width of the third conductive segment 333, and the orthographic projection of the first conductive segment 331 on the third conductive segment 333 may be located within the third conductive segment 333; the fourth conductive segment 334 may first extend along the second direction Y and toward the side away from the first reset gate T4G, and then may extend along the first direction X and toward the side away from the compensation transistor T3, and the ends of the second conductive segment 332 and the fourth conductive segment 334 away from the first reset gate T4G may be located on the same horizontal line.

[0099] See also Fig.14 The first source-drain layer 133 includes a second reset signal line Vi2, a second control signal line Nscan3, a second high potential line VDD2, a second control signal line Pscan1, a first control signal line Nscan1, and a third control signal line Nscan2 arranged along the second direction Y. The second reset signal line Vi2, the second control signal line Nscan3, the second high potential line VDD2, the second control signal line Pscan1, the first control signal line Nscan1, and the third control signal line Nscan2 can all extend along the first direction X.

[0100] See also Figures 14 to 17The second reset signal line Vi2 is arranged between the third reset signal line Vi3 and the first control signal line Nscan1, the second control signal line Nscan3 and the fourth control signal line Pscan2 partially overlap, the second high potential line VDD2 is arranged between the light-emitting signal line EM and the first electrical connection section 311, the second control signal line Pscan1, the first control signal line Nscan1 and the third control signal line Nscan2 are arranged between the first electrical connection section 311 and the first reset signal line Vi1, and the second control signal line Pscan1 is arranged close to the first electrical connection section 311, the third control signal line Nscan2 is arranged close to the first reset signal line Vi1, and the first control signal line Nscan1 is arranged between the second control signal line Pscan1 and the third control signal line Nscan2.

[0101] See also Figures 14 to 17 The first source-drain layer 133 also includes a second electrical connection segment 312 disposed between the second reset signal line Vi2 and the third reset signal line Vi3, a first end of the second electrical connection segment 312 is electrically connected to the third reset signal line Vi3 through the first via hole HL1, a second end of the second electrical connection segment 312 is electrically connected to the first end of the third reset active portion T8A through the second via hole HL2, and the third reset signal line Vi3 transmits the reference voltage to the third reset transistor T8 through the second electrical connection segment 312.

[0102] In this embodiment, the first via hole HL1 penetrates the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first inter-insulation layer 132 , and the second via hole HL2 penetrates the first gate insulation layer 124 , the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first inter-insulation layer 132 .

[0103] In this embodiment, in order to avoid interference between the second electrical connection section 312 and the second reset signal line Vi2, the second reset signal line Vi2 is designed to be sunken at a position corresponding to the second electrical connection section 312, that is, the signal line in this area is offset to the side away from the third reset signal line Vi3; at the same time, in order to ensure the line distance between the second control signal line Nscan3 and the second reset signal line Vi2, the second control signal line Nscan3 is also designed to be sunken.

[0104] See also Figures 14 to 17 The first source-drain layer 133 also includes a third extension segment 323, a third electrical connection segment 313 and a fourth electrical connection segment 314 arranged between the second high potential line VDD2 and the second control signal line Nscan3. The third extension segment 323 and the third electrical connection segment 313 both extend along the second direction Y, and the fourth electrical connection segment 314 extends along the first direction X.

[0105] In this embodiment, the first end of the third extension segment 323 is electrically connected to the second high potential line VDD2, the second end of the third extension segment 323 extends to a side away from the second high potential line VDD2, and the third extension segment 323 overlaps with a portion of the first light emitting active portion T5A, and the second end of the third extension segment 323 passes through the third via hole HL3 and is electrically connected to the second end of the first light emitting active portion T5A; the first end of the third electrical connection segment 313 passes through the fourth via hole HL4 and is electrically connected to the second end of the third reset active portion T8A, and the first active layer 123 further includes a fourth extension segment connected to the first light emitting active portion T5A. 324, the fourth extension segment 324 extends along the first direction X, the second end of the third electrical connection segment 313 passes through the fifth via HL5 and is electrically connected to the fourth extension segment 324, the third reset signal line Vi3 transmits the reference voltage to the first connection point P1 through the second electrical connection segment 312, the third electrical connection segment 313 and the fourth extension segment 324 to reset the potential of the first node A; one end of the fourth electrical connection segment 314 passes through a via and is electrically connected to the third connection point P3 in the first active layer 123, and the other end of the fourth electrical connection segment 314 passes through another via and is electrically connected to the conductive layer in the second source and drain layer 135.

[0106] In this embodiment, the third via hole HL3 penetrates the first gate insulation layer 124, the second gate insulation layer 126, the third gate insulation layer 128, the fourth gate insulation layer 130, and the first interinsulation layer 132, and the fourth via hole HL4 and the fifth via hole HL5 both penetrate the first gate insulation layer 124, the second gate insulation layer 126, the third gate insulation layer 128, the fourth gate insulation layer 130, and the first interinsulation layer 132.

[0107] See also Figures 14 to 17 The first source-drain layer 133 further includes a fifth electrical connection segment 315 and a sixth electrical connection segment 316 disposed between the second high potential line VDD2 and the second control signal line Pscan1 , and the fifth electrical connection segment 315 and the sixth electrical connection segment 316 both extend along the second direction Y.

[0108] In this embodiment, the first end of the fifth electrical connection section 315 passes through the sixth via hole HL6 and is electrically connected to an end of the first extension section 321 away from the second control signal line Pscan1, and the second end of the fifth electrical connection section 315 extends into the storage capacitor Cst and passes through the seventh via hole HL7 and is electrically connected to the first electrode plate Cst1 of the storage capacitor Cst. Fig.16In the structure, the seventh via hole HL7 passes through the first through hole HL0 on the second electrode plate Cst2, and the center of the first through hole HL0 and the center of the seventh through hole HL7 can be located on the same straight line perpendicular to the light emitting surface of the display panel 100; the fifth electrical connection segment 315 of the present application serves as an electrical connection component, one end of which passes through the sixth via hole HL6 and is electrically connected to the first extension segment 321, and the other end passes through the seventh via hole HL7 and is electrically connected to the first electrode plate Cst1 of the storage capacitor Cst, that is, the wires of the third node Q in the first gate layer 125 and the second active layer 129 are electrically connected through the metal of the first source and drain layer 133.

[0109] In this embodiment, a first end of the sixth electrical connection section 316 is electrically connected to the second connection point P2 in the first active layer 123 through the eighth via hole HL8 , and a second end of the sixth electrical connection section 316 is electrically connected to the second end in the compensation active portion T3A through the ninth via hole HL9 .

[0110] In this embodiment, the sixth via hole HL6 and the ninth via hole HL9 penetrate the fourth gate insulation layer 130 and the first inter-insulation layer 132 , and the seventh via hole HL7 and the eighth via hole HL8 penetrate the first gate insulation layer 124 , the second gate insulation layer 126 , the third gate insulation layer 128 , the fourth gate insulation layer 130 , and the first inter-insulation layer 132 .

[0111] See also Figures 14 to 17 The first source-drain layer 133 further includes a fifth extension segment 325, one end of the fifth extension segment 325 is electrically connected to the first control signal line Nscan1, and the fifth extension segment 325 extends along the second direction Y and toward the side away from the first control signal line Nscan1; one end of the fifth extension segment 325 away from the first control signal line Nscan1 passes through the tenth via HL10 and is electrically connected to the first conductive segment 331, and the first control signal line Nscan1 transmits the control signal to the compensation gate T3G of the compensation transistor T3 through the fifth extension segment 325 and the first conductive segment 331; at the same time, one end of the second conductive segment 332 away from the first reset gate T4G overlaps with the third control signal line Nscan2, and is electrically connected to the third control signal line Nscan2 through the eleventh via HL11, and the third control signal line Nscan2 transmits the control signal to the first reset gate T4G of the first reset transistor T4 through the second conductive segment 332.

[0112] In this embodiment, the tenth via hole HL10 and the eleventh via hole HL11 both penetrate the first inter-insulating layer 132 .

[0113] See also Figures 14 to 17, the third conductive segment 333 overlaps with the first conductive segment 331 and the third conductive segment 333, and the third conductive segment 333 passes through the twelfth via HL12 and is electrically connected to the first control signal line Nscan1, and the first control signal line Nscan1 transmits the control signal to the first shading unit T3S through the third conductive segment 333, that is, the first shading unit T3S can be reused as the bottom gate of the compensation transistor T3, and the compensation gate T3G is the top gate of the compensation transistor T3. The setting of the first shading unit T3S and the compensation gate T3G can increase the conduction rate of the compensation transistor T3 and improve the device effect of the compensation transistor T3; The fourth conductive segment 334 overlaps with a portion of the third control signal line Nscan2, and is electrically connected to the third control signal line Nscan2 through the thirteenth through hole HL13. The third control signal line Nscan2 transmits the control signal to the second shading unit T4S through the fourth conductive segment 334, that is, the second shading unit T4S can be reused as the bottom gate of the first reset transistor T4, and the first reset gate T4G is the top gate of the first reset transistor T4. The setting of the second shading unit T4S and the first reset gate T4G can increase the conduction rate of the first reset transistor T4 and improve the device effect of the first reset transistor T4.

[0114] In this embodiment, the twelfth via hole HL12 and the thirteenth via hole HL13 both penetrate the third gate insulating layer 128 , the fourth gate insulating layer 130 , and the first inter-insulating layer 132 .

[0115] It should be noted that the third conductive segment 333 may be insulated from the first control signal line Nscan1 , and the fourth conductive segment 334 may be insulated from the third control signal line Nscan2 .

[0116] See also Figures 14 to 17 The second control signal line Nscan3 can pass through the fourteenth via hole HL14 and be connected in parallel with the fourth control signal line Pscan2, that is, the fifth control signal and the fourth control signal line Pscan2 are arranged in parallel, thereby reducing the impedance of the second control signal line Nscan3 and the fourth control signal line Pscan2.

[0117] In this embodiment, the fourteenth via hole HL14 penetrates the second gate insulating layer 126 , the third gate insulating layer 128 , the fourth gate insulating layer 130 , and the first inter-insulating layer 132 .

[0118] See also Figures 14 to 17The first control signal line Nscan1 partially overlaps with the first reset active portion T4A, the second control signal line Pscan1 partially overlaps with the first extension segment 321, and the second control signal line Pscan1 partially overlaps with the compensation active portion T3A, and the third control signal line Nscan2 partially overlaps with the first reset active portion T4A. The four overlapping areas are all overlaps of the material of the second active layer 129 and the material of the first source-drain electrode layer 133, and the fourth gate insulating layer 130 and the first inter-insulating layer 132 are interposed between the first source-drain electrode layer 133 and the second active layer 129, and the material of the third gate layer 131 is not arranged in between, thereby avoiding the technical problem that the third gate layer 131 is easily short-circuited with the first source-drain electrode layer 133.

[0119] See also Figures 14 to 17 The overlapping portion of the second control signal line Pscan1 and the first extension section 321 is the boost capacitor Cboost of the present application, the third electrode plate of the boost capacitor Cboost can be the portion of the first extension section 321 that overlaps with the second control signal line Pscan1, and the fourth electrode plate of the boost capacitor Cboost can be the portion of the second control signal line Pscan1 that overlaps with the first extension section 321.

[0120] See also Figures 14 to 17 The first source-drain layer 133 also includes a seventh electrical connection segment 317 arranged between the second reset signal line Vi2 and the third control signal line Nscan2, and the seventh electrical connection segment 317 extends along the second direction Y and toward a side away from the second reset signal line Vi2; the seventh electrical connection segment 317 and the second extension segment 322 are overlapped, which is equivalent to forming a capacitor between the first reset signal line Vi1 and the second reset signal line Vi2, thereby ensuring the stability of the voltage on the first reset signal line Vi1 and the second reset signal line Vi2.

[0121] In this embodiment, the fifth electrical connection segment 315 and the first extension segment 321 are both wires in the area where the third node of the present application is located, that is, the potentials on the fifth electrical connection segment 315 and the first extension segment 321 are the potentials of the third node Q; at the same time, the second control signal line Pscan1 and the first extension segment 321 are overlapped in the first area M1, that is, the first extension segment 321 of the present application is in the second active layer 129, and the second control signal line Pscan1 is in the first source and drain layer 133. Part of the wires in the area where the third node Q is located are replaced from the original third gate layer 131 to the second active layer 129 of the present application, thereby avoiding the technical problem of cracks in the upper insulating layer and the technical problem of short-circuiting the horizontally arranged second control signal line Pscan1 with the lower wire in the first area M1.

[0122] At the same time, the first control signal line Nscan1 and the compensation active part T3A are overlapped in the second region M2, the second control signal line Pscan1 and the first reset active part T4A are overlapped in the third region M3, and the third control signal line Nscan2 and the first reset active part T4A are overlapped in the fourth region M4; that is, the compensation active part T3A and the first reset active part T4A of the present application are both in the second active layer 129, the first control signal line Nscan1 and the third control signal line Nscan2 are both in the first source and drain layer 133, so that the first control signal line Nscan1 can1, the second control signal line Pscan1 and the third control signal line Nscan2 are replaced from the gate layer with larger impedance to the first source and drain layer 133 with smaller impedance, for example, the original metal molybdenum is replaced with the titanium aluminum titanium of the present application, thereby reducing the impedance of the three control signal lines; secondly, since there is a risk of short circuit due to the overlap of the first source and drain layer 133 and the third gate layer 131, the present application replaces the wires in the area where the third node Q is located from the third gate layer 131 to the second active layer 129 to avoid short circuit between the wires in the area where the third node Q is located and the first source and drain layer 133.

[0123] See also Fig.18 The second source-drain layer 135 includes a first data signal line Data1, a second data signal line Data2 and a first high potential line VDD1. The second data signal line Data2, the first data signal line Data1 and the first high potential line VDD1 are arranged along a first direction X and extend along a second direction Y. The first data signal line Data1 is disposed between the second data signal line Data2 and the first high potential line VDD1.

[0124] See also Figures 18 to 20 The first high potential line VDD1 includes a first sub-board 341, a second sub-board 342, a third sub-board 343, a fourth sub-board 344 and a fifth sub-board 345. The third sub-board 343, the first sub-board 341, the fourth sub-board 344, the second sub-board 342 and the fifth sub-board 345 are arranged along the second direction Y, the first sub-board 341 is arranged between the third sub-board 343 and the fourth sub-board 344, and the second sub-board 342 is arranged between the fourth sub-board 344 and the fifth sub-board 345; in the first direction X, the width of the first sub-board 341 is smaller than the width of the second sub-board 342, the width of the first sub-board 341 can be greater than the width of the fourth sub-board 344, and the width of the fourth sub-board 344 can be greater than or equal to the width of the third sub-board 343 and the fifth sub-board 345.

[0125] In this embodiment, since the potential of the driving gate T1G is the potential of the third node Q, the potential change of the third node Q directly affects the working current of the light-emitting device 211b, so the present application needs to ensure the stability of the potential of the third node Q; the present application can make the positive projection of the driving gate T1G on the first high potential line VDD1 located in the first sub-plate 341, which is equivalent to using the first sub-plate 341 as a shielding layer to maintain the stability of the potential of the third node Q, so the present application needs to increase the lateral width of the first sub-plate 341 so that the first sub-plate 341 fully covers the driving gate T1G, and the first electrode Cst1 of the storage capacitor Cst is reused as the driving gate T1G, that is, the positive projection of the first electrode Cst1 on the first high potential line VDD1 can be located in the first sub-plate 341, so the width of the first sub-plate 341 of the present application can be greater than the widths of the third sub-plate 343, the fourth sub-plate 344 and the fifth sub-plate 345.

[0126] In this embodiment, the fifth electrical connection segment 315 and the first extension segment 321 are both electrically connected to the driving gate T1G, so changes in the potentials on the fifth electrical connection segment 315 and the first extension segment 321 will also affect the potential of the driving gate T1G. Therefore, the present application can increase the width of the fourth sub-board 344 to fully cover the fifth electrical connection segment 315 and the first extension segment 321. Therefore, the lateral width of the fourth sub-board 344 of the present application can be greater than the lateral widths of the third sub-board 343 and the fifth sub-board 345.

[0127] See also Fig.18 and Fig.19 The positive projection of the compensation gate T3G on the first high potential line VDD1 is located in the second sub-board 342, and part of the first high potential line VDD1 overlaps with the compensation gate T3G and part of the first control signal line Nscan1. The two can form a capacitor, thereby improving the anti-coupling ability of the first control signal line Nscan1, thereby improving the stability of the control signal transmitted by the first control signal line Nscan1, avoiding abnormal start-up of the compensation transistor T3, and ensuring the stability of the potential of the gate of the driving transistor T1.

[0128] See also Figures 18 to 20 The first source-drain layer 133 of the first sub-pixel unit 211c may include an eighth electrical connection segment 318a disposed between the first control signal line Nscan1 and the second control signal line Pscan1, one end of the eighth electrical connection segment 318a is electrically connected to the second end of the switch active portion T2A, the other end of the eighth electrical connection segment 318a is electrically connected to the first data signal line Data1, and the first data signal line Data1 transmits the data signal to the switch transistor T2 through the eighth electrical connection segment 318a.

[0129] In this embodiment, Figures 18 to 20The eighth electrical connection segment 318a may be the first electrical connection component 610 of the first sub-pixel unit 211c of the present application, that is, the switch active portion T2A of the first sub-pixel unit 211c is electrically connected to the first data signal line Data1 through the first electrical connection component 610.

[0130] See also Fig.21 and Fig. 22 The first source-drain layer 133 of the second sub-pixel unit 211d may include an eighth electrical connection segment 318b disposed between the first control signal line Nscan1 and the second control signal line Pscan1, one end of the eighth electrical connection segment 318b is electrically connected to the second end of the switch active portion T2A, the other end of the eighth electrical connection segment 318b is electrically connected to the second data signal line Data2, and the second data signal line Data2 transmits the data signal to the switch transistor T2 through the eighth electrical connection segment 318b.

[0131] In this embodiment, Fig.21 and Fig. 22 The eighth electrical connection segment 318b may be the second electrical connection component 620 of the second sub-pixel unit 211d of the present application, that is, the switch active portion T2A of the second sub-pixel unit 211d is electrically connected to the second data signal line Data2 through the second electrical connection component 620.

[0132] exist Figure 2 In the structure, the present application lists 6 sub-pixel units 211, the sub-pixel units 211 in the first row are all connected to the first data signal line Data1, and the sub-pixel units 211 in the second row are all connected to the second data signal line Data2. Fig.19 and Fig. 20 The sub-pixel units 211 listed in Figure 2 The first sub-pixel unit 211c of the first row in this application Fig.21 and Fig. 22 The sub-pixel units 211 listed in Figure 2 The second sub-pixel unit 211d of the second row in .

[0133] exist Fig.19 and Fig. 22 In the embodiment, the switch active portion T2A of the first sub-pixel unit 211c and the switch active portion T2A of the second sub-pixel unit 211d both extend between the first data signal line Data1 and the second data signal line Data2, and partially overlap with one of the first data signal line Data1 or the second data signal line Data2. Fig.19 and Fig. 22 The switch active portion T2A of the first sub-pixel unit 211c and the switch active portion T2A of the second sub-pixel unit 211d are both overlapped with the first data signal line Data1.

[0134] exist Fig.19 and Fig. 22 In the figure, since the switch active portion T2A of the first sub-pixel unit 211c and the switch active portion T2A of the second sub-pixel unit 211d have the same pattern, the switch active portion T2A of the first sub-pixel unit 211c has a first connection end electrically connected to the first electrical connection component 610, and the switch active portion T2A of the second sub-pixel unit 211d has a second connection end electrically connected to the second electrical connection component 620, and the center line between the first connection end and the second connection end is parallel to the second direction Y; at the same time, the first connection end and the second connection end are both arranged between the first data signal line Data1 and the second data signal line Data2.

[0135] exist Fig.19 and Fig. 22 In the figure, the first electrical connection member 610 extends toward the side close to the repeating unit 500, the second electrical connection member 620 extends toward the side away from the repeating unit 500, the first electrical connection member 610 and the first data signal line Data1 partially overlap, so that the first electrical connection member 610 and the first data signal line Data1 are electrically connected, the first electrical connection member 610 and the second data signal line Data2 do not overlap, the second electrical connection member 620 and the second data signal line Data2 partially overlap, the second electrical connection member 620 and the first data signal line Data1 do not overlap, so that the second electrical connection member 620 and the second data signal line Data2 are electrically connected.

[0136] See also Fig.19 The first data signal line Data1 includes a plurality of first longitudinal segments Data1a and a first avoidance segment Data1b disposed between two adjacent first longitudinal segments Data1a. The spacing between the first avoidance segment Data1b and the repeating unit 500 is smaller than the spacing between the first longitudinal segment Data1a and the repeating unit 500. The switch active portion T2A of the first sub-pixel unit 211c is electrically connected to the first avoidance segment Data1b through the first electrical connection component 610.

[0137] See also Fig. 22 The second data signal line Data2 includes a plurality of second longitudinal segments Data2a and a second avoidance segment Data2b disposed between two adjacent second longitudinal segments Data2a. The first avoidance segment Data1b and the second avoidance segment Data2b are disposed oppositely and in parallel. The spacing between the second avoidance segment Data2b and the repeating unit 500 is greater than the spacing between the second longitudinal segment Data2a and the repeating unit 500. The switch active portion T2A of the second sub-pixel unit 211d is electrically connected to the second avoidance segment Data2b through the second electrical connection component 620.

[0138] The setting of the first avoidance segment Data1b and the second avoidance segment Data2b in the present application is mainly that the first avoidance segment Data1b needs to pass through the via hole to be electrically connected to the first electrical connection component 610, and the second avoidance segment Data2b needs to pass through the corresponding via hole to be electrically connected to the second electrical connection component 620. In order to avoid interference between the via hole and the adjacent data signal line, avoidance segments are respectively set at the position of the via hole.

[0139] See also Fig.18 There is a central axis O1 between the first data signal line Data1 and the second data signal line Data2, and the first avoidance section Data1b and the second avoidance section Data2b are symmetrically arranged around the central axis O1.

[0140] See also Fig.23 , there is a central axis O1 between the first data signal line Data1 and the second data signal line Data2, and the distance between the first avoidance segment Data1b and the central axis O1 is smaller than the distance between the second avoidance segment Data2b and the central axis O1; since the distance between the first avoidance segment Data1b and the adjacent first high potential line VDD1 is smaller than the distance between the second avoidance segment Data2b and the adjacent first high potential line VDD1, the present application can reduce the distance between the first avoidance segment Data1b and the central axis O1, so that the distance between the first avoidance segment Data1b and the adjacent first high potential line VDD1 and the distance between the second avoidance segment Data2b and the adjacent first high potential line VDD1 are equal, avoiding the capacitance difference between the data signal line and the first high potential line VDD1, which causes the difference in data signals transmitted by the first data signal line Data1 and the second data signal line Data2.

[0141] See also Fig.24 and Fig.26 The third source-drain layer 137 may include a third high potential line VDD3 extending along the second direction Y, the third high potential line VDD3 is electrically connected to the second high potential line VDD2, and the third high potential line VDD3 is mainly used to reduce the impedance of the wire transmitting the constant voltage high level.

[0142] It should be noted that in Figures 18 to 24In the present application, the first high potential line VDD1 can be electrically connected to the second high potential line VDD2, and then the second high potential line VDD2 is electrically connected to the second electrode plate Cst2 of the storage capacitor Cst, and the second electrode plate Cst2 located in the same row is electrically connected through the first electrical connection segment 311; therefore, the wire for transmitting a constant voltage high level in the present application has four layers of metal, namely, the second electrode plate Cst2 and the first electrical connection segment 311 located in the second gate layer 127, the second high potential line VDD2 located in the first source and drain layer 133, and the second high potential line VDD2 located in the first source and drain layer 133. The first high potential line VDD1 in the second source-drain layer 135, the third high potential line VDD3 in the third source-drain layer 137, the second electrode plate Cst2, the first electrical connection section 311, and the second high potential line VDD2 all extend along the first direction X, and the first high potential line VDD1 and the third high potential line VDD3 all extend along the second direction Y. Therefore, the present application utilizes four layers of metal to transmit a constant voltage high level to form a metal mesh that is crisscrossed in a mesh shape to reduce the impedance of the wire, thereby reducing the loss of the constant voltage high level on the transmitted wire.

[0143] See also Fig. 27 The third source-drain electrode layer 137 of the present application includes a plurality of potential line units 137a, each of which is arranged along the first direction X and corresponds to three adjacent sub-pixel units 211, such as a red sub-pixel unit 212, a green sub-pixel unit 213, and a blue sub-pixel unit 214. For example, the three sub-pixel units 211 are respectively the red sub-pixel unit 212, the green sub-pixel unit 213, and the blue sub-pixel unit 214. For example, each potential line unit 137a may include a corresponding red sub-pixel unit 212. The first third high potential line VDD3, the third third high potential line VDD3 corresponding to the blue sub-pixel unit 214, the second high potential line corresponding to the green sub-pixel unit 213, and the fourth reset signal line Vi4, the patterns of the first third high potential line VDD3 and the third third high potential line VDD3 may be the same, the patterns of the second third high potential line VDD3 and the third third high potential line VDD3 are different, and the lateral width of the second third high potential line VDD3 is smaller than the lateral width of the third third high potential line VDD3.

[0144] It should be noted that the sub-pixel colors corresponding to the above three high-potential lines can be arranged randomly and are not limited to the above embodiment.

[0145] See also Fig. 27Each potential line unit 137a is provided with a longitudinal reset signal line and three transverse reset signal lines, that is, each potential line unit 137a can also include a fourth reset signal line Vi4 located in the green sub-pixel unit 213, and the fourth reset signal line Vi4 in each potential line unit 137a is electrically connected to one of the first reset signal line Vi1, the second reset signal line Vi2 and the third reset signal line Vi3, and the reset signal lines connected to the fourth reset signal line Vi4 in three adjacent potential line units 137a are different.

[0146] In order to reduce the impedance of the reset signal line, the vertically arranged reset signal line can be electrically connected to one of the three horizontal reset signal lines; for example Fig.28 Three rows of potential line units 137a are arranged in the middle, each row of potential line units 137a includes three potential line units 137a, and each potential line unit 137a is provided with a fourth reset signal line Vi4. The fourth reset signal line Vi4 in the first potential line unit 137a can be electrically connected to the first reset signal line Vi1 of each row, the fourth reset signal line Vi4 in the second potential line unit 137a can be electrically connected to the second reset signal line Vi2 of each row, and the fourth reset signal line Vi4 in the third potential line unit 137a can be electrically connected to the third reset signal line Vi3 of each row, so that each horizontally arranged reset signal line is electrically connected to the fourth reset signal line Vi4 to form a metal mesh that is crisscrossed horizontally and vertically, thereby reducing the impedance of the reset signal line.

[0147] It should be noted that Fig. 27 The first sub-pixel unit 212, the second sub-pixel unit 213 and the third sub-pixel unit 214 only represent the position of the pixel driving circuit 211a of the corresponding sub-pixel unit 211, and the position of the anode in the sub-pixel unit 211 may not be in the corresponding area; for example, see Fig.29 In the present application, the pixel driving circuit 211a in the first sub-pixel unit 212 is electrically connected to the first anode 211b1, and the pixel driving circuit 211a in the second sub-pixel unit 213 is electrically connected to the second anode 211b2. The first anode 211b1 and the second anode 211b2 are arranged along the second direction Y, and the first anode 211b1 and the second anode 211b2 both span the first sub-pixel unit 212 and the second sub-pixel unit 213.

[0148] It should be noted that in Fig.29In the embodiment, the third source-drain electrode layer 137 may further include a ninth electrical connection segment 319 and a tenth electrical connection segment 320, the ninth electrical connection segment 319 is arranged between the fourth reset signal line Vi4 and the second third high potential line VDD3, the tenth electrical connection segment 320 is arranged on one side of the first third high potential line VDD3 and the third third high potential line VDD3, the tenth electrical connection segment 320 corresponds to the fourth electrical connection segment 314; the second source-drain electrode layer 135 may further include an eleventh electrical connection segment 321, the second anode 211b2 may be connected to the second sub-pixel unit 213 through the ninth electrical connection segment 319 and the eleventh electrical connection segment 321. The connecting segment 321, the fourth electrical connection segment 314 and the third connection point P3 of the first active layer 123 in the pixel driving circuit 211a of the second sub-pixel unit 213 are electrically connected; similarly, the first anode 211b1 can be electrically connected through the tenth electrical connection segment 320, the eleventh electrical connection segment 321, the fourth electrical connection segment 314 and the third connection point P3 of the first active layer 123 in the pixel driving circuit 211a of the first sub-pixel unit 212; similarly, the connection method of the anode in the third sub-pixel unit 314 is the same as the connection method of the first anode 211b1.

[0149] The present application also provides a display device, which includes the above-mentioned display panel. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0150] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0151] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: It comprises a plurality of repeating units and a first data signal line and a second data signal line arranged on one side of the repeating unit, the repeating unit comprises at least one first sub-pixel unit and at least one second sub-pixel unit, the first sub-pixel unit and the second sub-pixel unit both comprise a pixel driving circuit and a light emitting device connected to the pixel driving circuit; Wherein, the display panel further comprises a first electrical connection member and a second electrical connection member, the pixel driving circuit of the first sub-pixel unit is electrically connected to the first data signal line through the first electrical connection member, the pixel driving circuit of the second sub-pixel unit is electrically connected to the second data signal line through the second electrical connection member, and the first electrical connection member, the second electrical connection member, the first data signal line and the second data signal line are all arranged on the same side of the repeating unit; The pixel driving circuits of the first sub-pixel unit and the second sub-pixel unit both include: a switch transistor, wherein a first electrode of the switch transistor is connected to one of the first data signal line or the second data signal line, and a second electrode of the switch transistor is connected to a first node; a driving transistor, wherein a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to the second node, and a driving gate of the driving transistor is connected to a third node; a compensation transistor, wherein a first electrode of the compensation transistor is connected to the third node, and a second electrode of the compensation transistor is connected to the second node; Among them, the compensation gate of the compensation transistor is connected to the first control signal line, the switch gate of the switching transistor is connected to the second control signal line, and the first electrical connection component and the second electrical connection component are both arranged between the first control signal line and the second control signal line in the corresponding pixel driving circuit.

2. The display panel according to claim 1, characterized in that: The switching transistor includes a switch active portion; The switch active portion of the first sub-pixel unit is electrically connected to the first data signal line through the first electrical connection member, and the switch active portion of the second sub-pixel unit is electrically connected to the second data signal line through the second electrical connection member.

3. The display panel according to claim 2, characterized in that: The switch active portion of the first sub-pixel unit and the switch active portion of the second sub-pixel unit have the same pattern; The switch active portion of the first sub-pixel unit and the switch active portion of the second sub-pixel unit both partially overlap with one of the first data signal line or the second data signal line.

4. The display panel according to claim 3, characterized in that: The switch active portion of the first sub-pixel unit has a first connection end electrically connected to the first electrical connection member, and the switch active portion of the second sub-pixel unit has a second connection end electrically connected to the second electrical connection member; The first connection end and the second connection end are both arranged between the first data signal line and the second data signal line, and a center line connecting the first connection end and the second connection end is parallel to an extension direction of the first data signal line or the second data signal line.

5. The display panel according to claim 3, characterized in that: The first data signal line is arranged between the repeating unit and the second data signal line; Among them, the first electrical connection member extends toward the side close to the repeating unit, the second electrical connection member extends toward the side away from the repeating unit, the first electrical connection member and the first data signal line partially overlap, the first electrical connection member and the second data signal line do not overlap, the second electrical connection member and the second data signal line partially overlap, and the second electrical connection member and the first data signal line do not overlap.

6. The display panel according to claim 5, characterized in that: The first data signal line includes a plurality of first longitudinal segments and a first avoidance segment provided between two adjacent first longitudinal segments, the second data signal line includes a plurality of second longitudinal segments and a second avoidance segment provided between two adjacent second longitudinal segments, the first avoidance segment and the second avoidance segment are arranged oppositely and in parallel; Among them, the distance between the first avoidance section and the repeating unit is smaller than the distance between the first longitudinal section and the repeating unit, the distance between the second avoidance section and the repeating unit is larger than the distance between the second longitudinal section and the repeating unit, the switch active part of the first sub-pixel unit is electrically connected to the first avoidance section through the first electrical connection component, and the switch active part of the second sub-pixel unit is electrically connected to the second avoidance section through the second electrical connection component.

7. The display panel according to claim 6, characterized in that: A central axis is defined between the first data signal line and the second data signal line, and the first avoidance section and the second avoidance section are symmetrically arranged with the central axis as an axis.

8. The display panel according to any one of claims 1 to 7, characterized in that: The pixel driving circuit further includes: a first reset transistor, wherein a first electrode of the first reset transistor is connected to a first reset signal line, a second electrode of the first reset transistor is connected to a third node, and a first reset gate of the first reset transistor is connected to a third control signal line; a second reset transistor, wherein a first electrode of the second reset transistor is connected to a second reset signal line, a second electrode of the second reset transistor is connected to an anode of the light emitting device, and a second reset gate of the second reset transistor is connected to a fourth control signal line; a third reset transistor, wherein a first electrode of the third reset transistor is connected to a third reset signal line, a second electrode of the third reset transistor is connected to the first node, and a third reset gate of the third reset transistor is connected to the fourth control signal line; a first light emitting transistor, wherein a first electrode of the first light emitting transistor is connected to a first high potential line, a second electrode of the first light emitting transistor is connected to the first node, and a first light emitting gate of the first light emitting transistor is connected to a light emitting signal line; a second light emitting transistor, wherein a first electrode of the second light emitting transistor is connected to a second node, a second electrode of the second light emitting transistor is connected to an anode of the light emitting device, and a second light emitting gate of the second light emitting transistor is connected to the light emitting signal line; A storage capacitor, the storage capacitor comprising a first plate and a second plate, the first plate being connected to the third node, and the second plate being connected to the first high potential line; A boost capacitor, the boost capacitor includes a third plate and a fourth plate, the third plate is connected to the third node, and the fourth plate is connected to the second control signal line.

9. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 8.

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