Semiconductor terminal structure, method for preparing same, and semiconductor device

Abstract

The present invention provides a semiconductor terminal structure, a preparation method thereof, and a semiconductor device, belonging to the technical field of semiconductor devices. The semiconductor terminal structure is located in the terminal region of an epitaxial wafer, and the epitaxial wafer further includes a cell region. The epitaxial wafer includes a substrate and an epitaxial layer located on the substrate, and a plurality of floating islands are arranged at intervals in the epitaxial layer; each floating island contains at least one clamping layer; the doping type of the clamping layer is different from that of the floating island, and the doping types of the clamping layer, the epitaxial layer, and the substrate are the same. The terminal structure and the semiconductor device including the terminal structure clamp the potential of the floating island and accelerate the recovery of the depletion region by arranging a clamping layer in the floating island, relieve the dynamic degradation effect, and at the same time ensure that the breakdown voltage of the device will not decrease.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor terminal structure, a semiconductor device including the terminal structure, and a preparation method of the terminal structure. Background Art

[0002] Although certain achievements have been made in the research of wide-bandgap semiconductor devices, there are still some technical problems. Taking SiC as an example, the performance of SiC devices is gradually approaching the one-dimensional theoretical limit of SiC unipolar devices. The superjunction technology can break through the one-dimensional theoretical limit of unipolar devices, break the original restrictive relationship between the specific on-resistance and the breakdown voltage of the device, and improve the conduction performance of the device. However, due to the differences in material characteristics, the preparation methods of Si superjunctions, such as deep trench etching, deep trench epitaxial backfilling and other technologies, are difficult to be directly applied to the preparation of wide-bandgap semiconductor superjunctions.

[0003] In addition, in order to alleviate the problem that the device blocking ability is reduced due to the premature breakdown of the edges and four corners of the PN junction caused by the curvature effect, a junction terminal structure is usually formed around the PN junction. The introduced junction terminal structure can disperse the electric field originally concentrated at the edge of the PN junction, reduce the electric field strength at the edge of the PN junction, and increase the breakdown voltage of the device. However, the traditional terminal structure is limited by the structure design and the depth of ion implantation in SiC, and can only alleviate the problem of the electric field near the surface of the drift region, and cannot protect the PN junction deep in the drift region. To solve this problem, a floating structure superjunction and its terminal have been developed in the industry.

[0004] Compared with the traditional superjunction structure, the floating structure superjunction has a simpler manufacturing process and a wider processing window. The principle of the junction terminal of the floating structure superjunction is as follows: in the blocking state, the floating P island is depleted, and the negatively charged space charge in the depletion region can modulate the electric field distribution in the cell region and the terminal region, alleviate the curvature effect in the terminal region, and increase the breakdown voltage of the device. However, the floating structure superjunction has a serious problem of turn-on recovery hysteresis, which is specifically manifested as follows: (1) when the device switches from the reverse blocking state to the forward conduction state, the floating P island and its depletion region in the cell region cannot be replenished with holes in time under the high-frequency switching state and cannot recover, the potential of the floating P island and the surrounding drift region increases, which hinders the carrier transport and leads to an increase in the loss of the device (dynamic degradation). (2) when the device switches from the reverse blocking state to the forward conduction state, the floating P island and its depletion region in the terminal region cannot be replenished with holes in time under the high-frequency switching state. After multiple repeated switchings, the charge and potential distributions near the floating P island in the terminal region are in an uncertain state, resulting in a decrease in the breakdown voltage of the device. Summary of the Invention

[0005] To solve the above problems, the present invention provides a semiconductor terminal structure. By disposing a clamping layer with a doping type opposite to that of the floating island in the floating island of the terminal structure, the potential of the floating island is clamped and the recovery of the depletion region is accelerated, the dynamic degradation effect is alleviated, and at the same time, the breakdown voltage of the device is ensured not to decrease.

[0006] To achieve the above object, the present invention specifically adopts the following technical solutions:

[0007] A semiconductor terminal structure is located in the terminal region of an epitaxial wafer. The epitaxial wafer further includes a cell region. The epitaxial wafer includes a substrate and an epitaxial layer on the substrate. A plurality of floating islands arranged at intervals are provided in the epitaxial layer; each of the floating islands contains at least one clamping layer; the doping type of the clamping layer is different from that of the floating island, and the doping types of the clamping layer, the epitaxial layer, and the substrate are the same. It can be understood that in some technical solutions, the doping type of the floating island is P-type, which is called a floating P island; the doping types of the clamping layer, the epitaxial layer, and the substrate are N-type (for example, the clamping layer is an N+ clamping layer, the epitaxial layer is an N- epitaxial layer, and the substrate is an N++ substrate). In some other technical solutions, the doping type of the floating island is N-type, which is called a floating N island; the doping types of the clamping layer, the epitaxial layer, and the substrate are P-type (for example, the clamping layer is a P+ clamping layer, the epitaxial layer is a P- epitaxial layer, and the substrate is a P++ substrate). In some technical solutions, a plurality of the floating islands are arranged at intervals in a single layer in the epitaxial layer. In some other embodiments, a plurality of the floating islands are distributed in multiple layers at intervals in the epitaxial layer, and the number of the floating islands in each layer may be the same or different.

[0008] In a preferred embodiment, a plurality of the floating islands are distributed in multiple layers at intervals in the epitaxial layer, and the multiple layers of floating islands are aligned in the direction of the epitaxial layer pointing to the substrate.

[0009] In a preferred embodiment, at least one of the clamping layers is not completely wrapped in the floating island.

[0010] In a preferred embodiment, along the direction from the cell region to the terminal region, a plurality of the floating islands are arranged at intervals; along the direction from the epitaxial layer to the substrate, a plurality of the floating islands are arranged at intervals; along the direction perpendicular to the direction from the cell region to the terminal region and perpendicular to the direction from the epitaxial layer to the substrate, a plurality of the floating islands are arranged at intervals and the clamping layers of the same layer are connected into a whole.

[0011] In a preferred embodiment, a plurality of the floating islands are distributed in multiple layers at intervals in the epitaxial layer, and the number of the floating islands in each layer is the same.

[0012] In a preferred embodiment, along the direction from the cell region to the terminal region, the distances between adjacent floating islands are different.

[0013] In a preferred embodiment, along the direction from the epitaxial layer to the substrate, the distances between adjacent floating islands are different.

[0014] In a preferred embodiment, in the terminal region, at least one of a junction termination extension structure, a beveled terminal structure, a field plate, and a field limiting ring is provided in the surface layer on the side of the epitaxial layer away from the substrate.

[0015] The present invention also provides a method for manufacturing the semiconductor terminal structure in any of the above solutions, including the following steps:

[0016] S1. Grow an epitaxial layer on a substrate;

[0017] S2. Form a plurality of floating islands arranged at intervals in the epitaxial layer by ion implantation;

[0018] S3. Form a clamping layer in each of the floating islands by ion implantation.

[0019] In a preferred embodiment, the manufacturing method further includes the following step: Form a junction termination extension structure or / and a field limiting ring in the surface layer on the side of the epitaxial layer away from the substrate by ion implantation.

[0020] In a preferred embodiment, the manufacturing method further includes the following step: Continuously grow a second epitaxial layer on the epitaxial layer, and then repeat steps S2 to S3.

[0021] The present invention also provides a semiconductor device, which includes the semiconductor terminal structure in any of the above solutions and a cell structure located in the cell region, and the terminal region is located around the cell region.

[0022] In a preferred embodiment, the doping dose of the floating islands inside at least one of the cell structures is different from the doping dose of the floating islands inside other cell structures.

[0023] In a preferred embodiment, the doping dose of the clamping layers inside at least one of the cell structures is different from the doping dose of other clamping layers.

[0024] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) In the semiconductor terminal structure of the present invention, a clamping layer with a doping type opposite to that of the floating island is formed in the floating island by using the ion implantation method. When the semiconductor device with this terminal structure switches from the blocking state to the conducting state, the clamping layer can clamp the potential of the floating island and accelerate the recovery of the depletion region, thereby ensuring that the breakdown voltage of the device will not decrease. (2) In the semiconductor device structure of the present invention, in addition to forming a clamping layer with a doping type opposite to that of the floating island in the floating island by using the ion implantation method in the terminal structure, a structure in which the floating island in the cell region also contains a clamping layer with a doping type opposite to that of it is formed. When the semiconductor device switches from the blocking state to the conducting state, the clamping layers in the cell region and the terminal region simultaneously clamp the potential of the floating island and accelerate the recovery of the depletion region, thereby making the on-state voltage drop of the device lower, achieving the effect of alleviating dynamic degradation, and ensuring that the breakdown voltage of the device will not decrease. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of a semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0026] Figure 2 is Figure 1 Cross-sectional schematic diagram of the upper edge cross-section LL';

[0027] Figure 3 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0028] Figure 4 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0029] Figure 5 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0030] Figure 6 is Figure 5 Cross-sectional schematic diagram of the upper edge cross-section LL';

[0031] Figure 7 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0032] Figure 8 is Figure 7 Cross-sectional schematic diagram of the upper edge cross-section LL';

[0033] Figure 9Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0034] Figure 10 For Figure 9 Cross-sectional schematic diagram of the upper edge cross-section LL';

[0035] Figure 11 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0036] Figure 12 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0037] Figure 13 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0038] Figure 14 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0039] Figure 15 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0040] Figure 16 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0041] Figure 17 Schematic diagram of another semiconductor terminal structure provided by an embodiment of the present invention and a semiconductor device including the terminal structure;

[0042] Figure 18 Schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0043] Figure 19 Schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0044] Figure 20 Schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0045] Figure 21 Schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0046] Figure 22 Schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0047] Figure 23Schematic diagram of the cell region of another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 24 Schematic diagram of the cell region of another semiconductor device provided by an embodiment of the present invention;

[0049] Figure 25 Schematic diagram of the cell region of another semiconductor device provided by an embodiment of the present invention;

[0050] Figure 26 Schematic diagram of the structure obtained in step S2 in the preparation method of a semiconductor terminal structure provided by an embodiment of the present invention;

[0051] Figure 27 Schematic diagram of the terminal structure obtained in step S3 in the preparation method of a semiconductor terminal structure provided by an embodiment of the present invention;

[0052] Figure 28 Schematic diagram of another terminal structure obtained in step S3 in the preparation method of a semiconductor terminal structure provided by an embodiment of the present invention;

[0053] Figure 29 Schematic diagram of the structure of a conventional floating structure superjunction device;

[0054] Figure 30 Doping concentration distribution diagram of the cell region of a semiconductor device provided by the present invention;

[0055] Figure 31 For Figure 30 Electric field distribution diagram of the cell region of the semiconductor device at the breakdown moment;

[0056] Figure 32 For Figure 30 Doping concentration distribution diagram of the terminal region of the semiconductor device;

[0057] Figure 33 For Figure 30 Electric field distribution diagram of the terminal region of the semiconductor device at the breakdown moment;

[0058] Figure 34 For Figure 29 Doping concentration distribution diagram of the cell region of the conventional floating structure superjunction device in

[0059] Figure 35 For Figure 30 In the semiconductor device and Figure 34 Breakdown curve diagram of the semiconductor device in

[0060] Figure 36 For Figure 30 In the semiconductor device and Figure 34Schematic diagrams of the on-state voltage drops after the semiconductor devices in are switched from the blocking state to the on-state, respectively.

[0061] In the figure: 1, substrate; 2, epitaxial layer; 3, floating P island; 4, N+ clamping layer; 5, junction termination extension structure; 6, dielectric passivation layer; 7, field limiting ring; 8, metal pad; 91, trench gate; 92, planar gate; 10, gate dielectric layer; 11, P well region; 12, source P+ region; 13, source N+ region; 14, interlayer dielectric layer; 15, JFET region; A, cell region; B, terminal region; A1, first type of cell structure; A2, second type of cell structure; A3, third type of cell structure; A4, fourth type of cell structure; LL’, cross section. Detailed implementation manners

[0062] The following content describes the technical solutions of the present invention clearly and completely in combination with embodiments, so that those skilled in the art can fully understand the present invention. Obviously, the described embodiments are only some preferred embodiments of the present invention, rather than all embodiments. Any equivalent transformation or substitution made by those of ordinary skill in the art to the following implementation manners without creative efforts shall fall within the protection scope of the present invention.

[0063] The directional terms mentioned in the present invention, such as "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship in the specification drawings, or the orientation or positional relationship when the product of the present invention is usually placed during use. It is only for the convenience of describing and understanding the product structure of the present invention. Therefore, the directional terms cannot be understood as a limitation to the present invention. In the present invention, unless otherwise clearly defined, expressions such as "on", "above", "over", and "upper surface" of the first feature with respect to the second feature mean that the first feature and the second feature can be in direct contact or indirectly in contact through an intermediate medium; it can be that the first feature is directly above or obliquely above the second feature, or only means that the first feature has a higher horizontal height than the second feature. Expressions such as "under", "below", "beneath", and "lower surface" of the first feature with respect to the second feature mean that the first feature and the second feature can be in direct contact or indirectly in contact through an intermediate medium; it can be that the first feature is directly below or obliquely below the second feature, or only means that the first feature has a lower horizontal height than the second feature. The ordinal numbers used in the present invention, such as "first", "second", etc., are only for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. In the present invention, JFET refers to a junction field effect transistor. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0064] Such as Figure 1 And Figure 2As shown in the figure, an embodiment of the present invention provides a semiconductor terminal structure. This terminal structure is located in the terminal region B of the epitaxial wafer. The epitaxial wafer further includes a cell region A, and the terminal region B is disposed around the cell region A. The epitaxial wafer includes a substrate 1 and an epitaxial layer 2 located on the substrate 1. The doping type of the substrate 1 is N-type, the doping type of the epitaxial layer 2 is N-type, and the doping concentration of the epitaxial layer 2 is lower than that of the substrate 1. A plurality of floating P islands 3 are formed in the epitaxial layer 2 (including the cell region A and the terminal region B) by ion implantation. Along the direction from the cell region A to the terminal region B (or along the direction from the terminal region B to the cell region A, that is Figure 1 in the direction from left to right or from right to left on the figure), a plurality of floating P islands 3 are arranged at intervals in the epitaxial layer 2. Along the direction from the epitaxial layer 2 to the substrate 1 (or along the direction from the substrate 1 to the epitaxial layer 2, that is Figure 1 in the direction from top to bottom or from bottom to top on the figure), a plurality of floating P islands 3 are arranged at intervals and are aligned in the epitaxial layer 2. Along the direction perpendicular to the direction from the cell region A to the terminal region B and perpendicular to the direction from the epitaxial layer 2 to the substrate 1 (that is Figure 1 in the direction perpendicular to the paper surface on the figure), a plurality of the floating P islands 3 are arranged at intervals in the epitaxial layer 2. In each floating P island 3, a layer of N+ clamping layer 4 is formed by ion implantation. Along the direction perpendicular to the direction from the cell region A to the terminal region B and perpendicular to the direction from the epitaxial layer 2 to the substrate 1 (that is Figure 1 in the direction perpendicular to the paper surface on the figure), the number of the N+ clamping layers 4 in the same layer is one or more. Figure 2 is Figure 1 a cross-sectional view along the cross-section LL' as shown in Figure 2 the figure. Along Figure 1 the direction perpendicular to the paper surface on the figure, the N+ clamping layers 4 exposed from the floating P islands 3 in the same layer are connected into a whole. Therefore, the N+ clamping layer 4 between two adjacent floating P islands 3 in the same layer is in direct contact with the epitaxial layer 2. This terminal structure further includes a junction termination extension structure 5. The doping type of the junction termination extension structure 5 is P-type and is located in the surface layer on the side of the epitaxial layer 2 away from the substrate 1. This terminal structure further includes a dielectric passivation layer 6 located on the surface of the epitaxial layer 2 on the side away from the substrate 1.

[0065] It can be understood that Figure 2 the N+ clamping layer 4 on the figure is exposed from the floating P island 3 in the direction perpendicular to the paper surface, that is, the N+ clamping layer 4 is not completely wrapped in the floating P island 3, and the part exposed from the floating P island 3 can be in direct contact with the epitaxial layer 2. In some other embodiments, as Figure 3 shown in the figure, along the direction from the substrate 1 to the epitaxial layer 2 (or along the direction from the epitaxial layer 2 to the substrate 1), the N+ clamping layer 4 is exposed from the floating P island 3, and the exposed part is in direct contact with the epitaxial layer 2. In some other embodiments, as Figure 4As shown, along the direction from the cell region A to the terminal region B (or from the terminal region B to the cell region A), the N+ clamping layer 4 exposes the floating P island 3, and the exposed part is in direct contact with the epitaxial layer 2; along the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), the N+ clamping layer 4 exposes the floating P island 3, and the exposed part is in direct contact with the epitaxial layer 2. In some other embodiments, such as Figure 5 and Figure 6 As shown, along the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1) and along the direction perpendicular to the paper surface, the upper surface of the N+ clamping layer 4 is flush with the upper surface of the floating P island, so the upper surface of the N+ clamping layer 4 is in direct contact with the epitaxial layer 2. In some other embodiments, such as Figure 7 and Figure 8 As shown, no matter in which direction, the N+ clamping layer 4 is completely wrapped inside the floating P island 3. When the N+ clamping layer 4 is not completely wrapped inside the floating P island 3 (that is, a part of the N+ clamping layer 4 is located outside the floating P island 3), the N+ clamping layer 4 can be in direct contact with the epitaxial layer. During the switching process of the device, the electrons in the N+ clamping layer 4 can more quickly replenish the depletion region around the floating P island 3, accelerating the device recovery. When the N+ clamping layer 4 is completely wrapped inside the floating P island 3, the electrons in the N+ clamping layer 4 can flow to the epitaxial layer 2 through the tunneling effect, realizing the functions of replenishing electrons and clamping.

[0066] Different from the structure of Figure 2 in some other embodiments, such as Figure 9 and Figure 10 As shown, in the direction perpendicular to the paper surface, a part of the N+ clamping layer 4 exposes the floating P island 3 and is in direct contact with the epitaxial layer 2, and the N+ clamping layers 4 of the same layer are arranged at intervals in the epitaxial layer 2. In some other embodiments, such as Figure 7 and Figure 8 As shown, in the direction perpendicular to the paper surface, the N+ clamping layer 4 is completely wrapped inside the floating P island 3. Since the floating P islands 3 are arranged at intervals in the epitaxial layer 2, the N+ clamping layers 4 are also arranged at intervals in the epitaxial layer 2.

[0067] Figure 1 Along the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), the positions of the multi-layer floating P islands 3 are aligned, and the number of floating P islands 3 in each layer is different. In some other embodiments, such as Figure 11 As shown, along the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), the positions of the multi-layer floating P islands 3 are aligned, and the number of floating P islands 3 in each layer is the same. In some other embodiments, such as Figure 12As shown, in the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), the positions of the multiple floating P islands 3 are staggered, and the number of floating P islands 3 in each layer is different. In some other embodiments, such as Figure 13 As shown, in the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), the positions of the multiple floating P islands 3 are staggered, and the number of floating P islands 3 in each layer is the same.

[0068] Figure 1 In the direction from the upper-edge cell region A to the terminal region B (or from the terminal region B to the cell region A), the spacing between adjacent floating P islands 3 is the same; in the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), the spacing between adjacent floating P islands 3 is the same. In some other embodiments, such as Figure 14 As shown, in the direction from the cell region A to the terminal region B (or from the terminal region B to the cell region A), the spacing between adjacent floating P islands 3 is different (for example, the spacing gradually increases). In some other embodiments, such as Figure 15 As shown, in the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), the spacing between adjacent floating P islands 3 is different (for example, the spacing gradually increases).

[0069] Different from the structure in Figure 1 , such as Figure 16 As shown, in the direction from the substrate 1 to the epitaxial layer 2 (or from the epitaxial layer 2 to the substrate 1), each floating P island 3 contains multiple (for example, two layers) of N+ clamping layers 4.

[0070] Different from the structure in Figure 1 , in some other embodiments, such as Figure 17 As shown, the terminal structure further includes multiple field limiting rings 7, and the doping type of each field limiting ring 7 is P-type. The multiple field limiting rings 7 are located in the surface layer on the side of the epitaxial layer 2 away from the substrate 1 and are arranged at intervals in the epitaxial layer 2. In some other embodiments, the terminal structure further includes an inclined terminal structure located in the surface layer on the side of the epitaxial layer 2 away from the substrate 1. In some other embodiments, the terminal structure further includes a field plate structure located in the surface layer on the side of the epitaxial layer 2 away from the substrate 1.

[0071] Such as Figure 1 As shown, an embodiment of the present invention further provides a semiconductor device including the semiconductor terminal structure provided in any one of the above embodiments. The semiconductor device further includes a cell structure provided in the cell region A. The cell structure includes a metal pad 8 provided on the surface of the epitaxial layer 2 on the side away from the substrate 1. In some other embodiments, such as Figure 18As shown, the cell structure includes a metal pad 8 disposed on the surface of the epitaxial layer 2 on the side away from the substrate 1 and a plurality of field limiting rings 7 disposed in the surface layer on the side of the epitaxial layer 2 away from the substrate 1. The doping type of each field limiting ring 7 is P-type, and the field limiting ring 7 is located between the metal pad 8 and the floating P island 3. In some other embodiments, such as Figure 19 As shown, the cell structure includes a metal pad 8 disposed on the surface of the epitaxial layer 2 on the side away from the substrate 1 and a junction termination extension structure 5 disposed in the surface layer on the side of the epitaxial layer 2 away from the substrate 1. The junction termination extension structure 5 is located between the metal pad 8 and the floating P island 3, and the doping type of the junction termination extension structure 5 is P-type. In some other embodiments, such as Figure 20 As shown, the cell structure includes a metal pad 8 disposed on the surface of the epitaxial layer 2 on the side away from the substrate 1 and a trench gate 91 disposed in the epitaxial layer 2. A gate dielectric layer 10 is provided on the outer wall of the trench of the trench gate 91. In the epitaxial layer 2, a P-well region 11 is provided around the trench gate 91. In the epitaxial layer 2 between the metal pad 8 and the P-well region 11, a source P+ region 12 and a source N+ region 13 are provided around the trench gate 91, and the source N+ region 13 is located inside the source P+ region 12. The metal pad 8 is isolated from the upper surface of the trench gate 91 by an interlayer dielectric layer 14. In some other embodiments, such as Figure 21 As shown, the cell structure includes a planar gate 92 and a metal pad 8 disposed on the surface of the epitaxial layer 2 away from the substrate 1. The planar gate 92 is coated with an interlayer dielectric layer 14 (at this time, the interlayer dielectric layer 14 also serves as a gate dielectric layer), and the portion of the interlayer dielectric layer 14 exposed outside the epitaxial layer 2 is surrounded by the metal pad 8. A P-well region 11 and a junction termination extension structure 5 are disposed at intervals in the epitaxial layer 2 between the metal pad 8 and the floating P island 3. The junction termination extension structure 5 extends to the terminal region, and its doping type is P-type. The epitaxial layer 2 between the P-well region 11 and the junction termination extension structure 5 is a JFET region 15, and the JFET region 15 is located directly below the planar gate 92. In the epitaxial layer 2 between the P-well region 11 and the metal pad 8 and in the epitaxial layer 2 between the junction termination extension structure 5 and the metal pad 8, a source N+ region 13 is provided around the JFET region 15, and a source P+ region 12 is provided around the source N+ region 13. Further, as Figure 22 As shown, a floating P island 3 is provided in the JFET region 15, and an N+ clamping layer 4 is provided in the floating P island 3. The floating P island 3 and the N+ clamping layer 4 in the JFET region 15 can improve the reliability of the gate dielectric layer.

[0072] Further, as Figure 20 、 Figure 21 、 Figure 22 As shown, several N+ clamping layers 4 arranged at intervals are also doped in the junction termination extension structure 5 of the terminal structure.

[0073] Further, the cell structures with the same P-type doping dose in the epitaxial layer 2 are referred to as the first type of cell structure A1, and the cell structures with a P-type doping dose different from that of the first type of cell structure A1 are referred to as the second type of cell structure A2. In some other embodiments, in the cell region of the semiconductor device, the P-type doping dose in the epitaxial layer 2 inside at least one cell structure is different from the P-type doping dose in the epitaxial layer 2 inside other cell structures, that is, there is at least one second type of cell structure A2 in the cell region. Changing the P-type doping dose in the second type of cell structure A2 can be achieved by increasing the number of floating P islands 3 or changing the volume of the floating P islands 3. For example, as Figure 23 shown, the P-type doping dose in the epitaxial layer 2 of the second type of cell structure A2 is higher than the P-type doping dose in the epitaxial layer 2 of the first type of cell structure A1; or as Figure 24 shown, the P-type doping dose in the epitaxial layer 2 of the second type of cell structure A2 is higher than the P-type doping dose in the epitaxial layer 2 of the first type of cell structure A1.

[0074] Further, the cell structures with the same N-type doping dose in the epitaxial layer 2 are referred to as the third type of cell structure A3, and the cell structures with an N-type doping dose different from that of the third type of cell structure A3 are referred to as the fourth type of cell structure A4. In some other embodiments, in the cell region of the semiconductor device, the N-type doping dose in the N+ clamping layer 4 inside at least one cell structure is different from the N-type doping dose in the N+ clamping layer 4 inside other cell structures, that is, there is at least one fourth type of cell structure A4 in the cell region. Changing the N-type doping dose in the fourth type of cell structure A4 can be achieved by changing the volume of the N+ clamping layer 4. For example, as Figure 25 shown, the doping dose in the N+ clamping layer 4 inside the fourth type of cell structure A4 is higher than the doping dose in the N+ clamping layer 4 inside the third type of cell structure A3.

[0075] It can be understood that in some other embodiments, when the doping type of the substrate 1 is P-type, the doping type of the epitaxial layer 2 is also P-type, the doping type of the floating island is N-type, and the doping type of the clamping layer is P-type.

[0076] As Figure 26 and Figure 27 shown, the embodiments of the present invention also provide a preparation method for a semiconductor terminal structure, including the following steps:

[0077] S1. Grow an epitaxial layer 2 on the substrate 1; the material of the substrate 1 is a wide-bandgap semiconductor material, for example, the material of the substrate 1 is any one of SiC, GaN, Ga2O3, diamond, AlN, and indium phosphide. The doping type of the substrate 1 is N+ type, and the doping type of the epitaxial layer 2 is N- type.

[0078] S2. Form a plurality of floating P islands 3 arranged at intervals in the epitaxial layer 2 by means of ion implantation;

[0079] S3. Form an N+ clamping layer 4 in each floating P island 3 by means of ion implantation.

[0080] Further, in some other embodiments, as Figure 28 shown, continue to grow a second epitaxial layer on the upper surface of the epitaxial layer, and then repeat steps S2 and S3 to form multiple layers of floating P islands 3, and an N+ clamping layer 4 is formed inside each floating P island 3.

[0081] Use the Slivaco simulation software to respectively perform simulation tests on the cell structure and semiconductor terminal structure of the semiconductor device provided by the embodiment of the present invention and the cell region of the traditional floating structure superjunction device. The structural schematic diagram of the traditional floating structure superjunction device is as Figure 29 shown. The doping concentration distribution in the floating structure superjunction cell region in the present invention is as Figure 30 shown, and the electric field distribution at the breakdown moment is as Figure 31 shown; the doping concentration distribution in the floating structure superjunction terminal region is as Figure 32 shown, the electric field distribution at the breakdown moment is as Figure 33 shown, the breakdown curve is as Figure 35 shown, and the on-state voltage drop after the semiconductor device switches from the blocking state to the on-state is as Figure 36 shown. The doping concentration distribution in the cell region of the traditional floating structure superjunction device is as Figure 34 shown, the breakdown curve is as Figure 35 shown, and the on-state voltage drop after the semiconductor device switches from the blocking state to the on-state is as Figure 36 shown. It can be seen from Figures 30 - 36 that in the present invention, by forming a clamping layer by ion implantation in the floating islands in the cell region and the terminal region (for example, forming an N+ clamping layer by ion implantation in the floating P island), when the semiconductor device switches from the blocking state to the on-state, the clamping layer can clamp the potential of the floating island, accelerate the recovery of the depletion region, reduce the on-state voltage drop, and finally play a role in alleviating dynamic degradation and ensuring that the breakdown voltage of the device does not decrease.

[0082] The above are only the preferred embodiments of the present invention and are not used to limit the protection scope of the present invention. For any person skilled in the art, the present invention can have various changes and modifications. Any simple equivalent changes and modifications made according to the protection scope of the present invention application and the content of the specification shall be included in the protection scope of the present invention.

Claims

1. A semiconductor terminal structure, located in a terminal region of an epitaxial wafer, the epitaxial wafer further comprising a cell region, the epitaxial wafer comprising a substrate and an epitaxial layer located on the substrate, characterized in that: A plurality of floating islands are arranged at intervals in the epitaxial layer; each of the floating islands contains at least one clamping layer; the clamping layer and the floating island have different doping types, and the clamping layer, the epitaxial layer and the substrate have the same doping type; along the direction from the cell area to the terminal area, a plurality of the floating islands are arranged at intervals; along the direction from the epitaxial layer to the substrate, a plurality of the floating islands are arranged at intervals; along the direction perpendicular to the direction from the cell area to the terminal area and perpendicular to the direction from the epitaxial layer to the substrate, a plurality of the floating islands are arranged at intervals and the clamping layers of the same layer are connected as a whole.

2. The semiconductor terminal structure according to claim 1, characterized in that: The plurality of floating islands are distributed in the epitaxial layer in a multi-layered manner, and the plurality of floating islands are aligned in a direction from the epitaxial layer to the substrate.

3. The semiconductor terminal structure according to claim 1, characterized in that: The plurality of floating islands are distributed in the epitaxial layer in multiple layers at intervals, and the number of the floating islands in each layer is the same.

4. The semiconductor terminal structure according to claim 1, characterized in that: The spacings between adjacent floating islands are different along the direction from the cell region to the terminal region; or / and the spacings between adjacent floating islands are different along the direction from the epitaxial layer to the substrate.

5. The semiconductor terminal structure according to claim 1, characterized in that: In the terminal region, at least one structure selected from the group consisting of a junction terminal extension structure, a bevel terminal structure, a field plate, and a field limiting ring is disposed in a surface layer of the epitaxial layer on a side away from the substrate.

6. The method for preparing a semiconductor terminal structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, growing an epitaxial layer on a substrate; S2, forming a plurality of floating islands arranged at intervals in the epitaxial layer by ion implantation; S3. Forming a clamping layer in each of the floating islands by ion implantation.

7. A semiconductor device, characterized in that: It comprises the semiconductor terminal structure according to any one of claims 1 to 5 and a cellular structure located in the cellular region, wherein the terminal region is located around the cellular region.

8. The semiconductor device according to claim 7, characterized in that The doping dose of the floating islands in at least one of the cellular structures is different from the doping doses of the floating islands in other cellular structures; or / and the doping dose of the clamping layer in at least one of the cellular structures is different from the doping doses of the other clamping layers.

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