Crystal oscillator circuit and clock signal generating method

Abstract

The present invention discloses a crystal oscillator circuit, comprising a crystal oscillation amplifier circuit, a duty cycle correction circuit and a frequency doubling circuit, wherein the duty cycle correction circuit comprises a first inverter, a single-ended to differential circuit, a comparator, a feedback circuit and a frequency doubling circuit, wherein the crystal oscillation amplifier circuit outputs a clock signal; the first inverter performs reverse processing on the clock signal; the single-ended to differential circuit generates a differential clock signal according to the clock signal output by the first inverter, and the differential clock signal comprises a positive clock signal and a reverse clock signal; the comparator receives the positive clock signal and the reverse clock signal, and outputs a current feedback signal after performing comparison processing; the feedback circuit outputs a voltage feedback signal to the input end of the first inverter according to the current feedback signal, so as to adjust the bias voltage of the first inverter, thereby adjusting the duty cycle of the clock signal output by the first inverter; the output end of the frequency doubling circuit outputs the doubled frequency clock signal to the clock system, so as to serve as a reference clock source.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a crystal oscillator circuit and a clock signal generating method. Background Art

[0002] In a circuit system, the performance of the clock system is related to the performance of other modules in the circuit. Therefore, in advanced process circuits that pay more and more attention to performance and integration, accurate clock signals are an indispensable part.

[0003] Crystal oscillator circuits are the most commonly used clock reference sources in high-performance clock systems because they can generate stable and accurate clock signals. However, affected by process, voltage, and temperature, the oscillation amplitude and DC operating point of the crystal oscillator circuit are prone to offset, causing the duty cycle of the oscillating clock signal to change, thereby introducing a lot of noise, which makes it difficult to directly apply it in high-performance clock systems. Crystal oscillator circuits with integrated duty cycle calibration can calibrate the duty cycle through real-time feedback of their own clock signals, so that they have higher performance and lower power consumption when used as clock reference sources.

[0004] The patent document with publication number CN110957998A provides a circuit for accurately correcting the duty cycle of a clock signal, which uses a delay unit and a phase detection unit to output an indication signal representing whether the duty cycle of the inverter chain output signal reaches the target value, thereby realizing the calibration of the duty cycle. The patent document with publication number CN114793108A discloses a crystal oscillator circuit, in which the duty cycle correction circuit uses an inverter chain, a third inverter and a feedback control module to realize the duty cycle correction of a square wave clock signal, and also uses an XOR gate to realize the double frequency function. The delay module occupies a large chip area, has high power consumption, and a long circuit stabilization time. The signal input to the XOR gate will be multiplexed after passing through the delay unit, which will cause the input signal to be unbalanced. Summary of the invention

[0005] Based on the above situation, the main purpose of the present invention is to provide a crystal oscillator circuit and method, which integrates duty cycle calibration and a frequency multiplier, sets a comparator to compare two differential bias signals to generate a feedback signal, and calibrates the duty cycle by adjusting the inverter gate bias voltage through negative feedback, and uses the clock after calibrating the duty cycle as the output of the frequency multiplier to output a multiplied reference clock signal with a stable duty cycle and smaller jitter.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] A crystal oscillator circuit comprises a crystal oscillation amplifier circuit, a duty cycle correction circuit and a frequency doubling circuit, wherein the duty cycle correction circuit comprises a first inverter, a single-ended to differential circuit, a comparator, a feedback circuit and a frequency doubling circuit.

[0008] The output end of the crystal oscillation amplifier circuit is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the single-ended to differential circuit, the first output end of the single-ended to differential circuit is connected to the first input end of the comparator, the second output end of the single-ended to differential circuit is connected to the second input end of the comparator, the output end of the comparator is connected to the input end of the feedback circuit, the output end of the feedback circuit is connected to the input end of the first inverter, the first input end of the double frequency circuit is connected to the first output end of the single-ended to differential circuit, and the second input end of the double frequency circuit is connected to the second output end of the unit to differential circuit.

[0009] The crystal oscillator amplifier circuit is used to output a clock signal;

[0010] The duty cycle correction circuit is used to adjust the duty cycle of the clock signal output by the first inverter, wherein the first inverter is used to reversely process the clock signal output by the crystal oscillation amplifier circuit; the single-ended to differential circuit is used to generate a differential clock signal according to the clock signal output by the first inverter, the differential clock signal includes a positive clock signal and a negative clock signal, the first output end of the single-ended to differential circuit outputs the positive clock signal, and the second output end outputs the negative clock signal; the comparator is used to receive the positive clock signal and the negative clock signal, and output a current feedback signal after comparison processing; the feedback circuit is used to output a voltage feedback signal to the input end of the first inverter according to the current feedback signal, so as to adjust the bias voltage of the first inverter, thereby adjusting the duty cycle of the clock signal output by the first inverter;

[0011] The frequency doubling circuit is used to output a frequency-doubled clock signal to a clock system according to the forward clock signal and the reverse clock signal, so as to serve as a reference clock source.

[0012] Preferably, the single-ended to differential circuit comprises a transmission gate, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a sixth inverter;

[0013] The clock signal output by the first inverter is connected to the input terminals of the transmission gate and the second inverter respectively;

[0014] The clock signal passing through the transmission gate is input to the input end of the third inverter, and the clock signal passing through the second inverter is input to the input end of the fourth inverter;

[0015] The input end of the fifth inverter is connected to the output end of the third inverter, and the output end of the fifth inverter is connected to the output end of the fourth inverter;

[0016] The input end of the sixth inverter is connected to the output end of the fourth inverter, and the output end of the sixth inverter is connected to the output end of the third inverter;

[0017] The output signal of the fifth inverter is the forward clock signal, and the output signal of the sixth inverter is the reverse clock signal.

[0018] Preferably, the comparator is a transconductance comparator.

[0019] The first input terminal of the transconductance comparator is connected to the first output terminal of the single-ended to differential circuit, the second input terminal of the transconductance comparator is connected to the second output terminal of the single-ended to differential circuit, and the output terminal of the transconductance comparator is connected to the input terminal of the feedback circuit;

[0020] The positive clock signal and the reverse clock signal are input to the first input terminal and the second input terminal of the transconductance comparator respectively. The transconductance comparator compares the positive clock signal with the reverse clock signal and outputs a current feedback signal.

[0021] Preferably, the comparator is a chopper comparator, which includes a first chopper circuit, a transconductance comparator and a second chopper circuit.

[0022] The first input terminal and the second input terminal of the first chopper circuit are respectively the first input terminal and the second input terminal of the chopper comparator, the first output terminal and the second output terminal of the first chopper circuit are respectively connected to the first input terminal and the second input terminal of the transconductance comparator, the first output terminal and the second output terminal of the transconductance comparator are respectively connected to the first input terminal and the second input terminal of the second chopper circuit, and the output terminal of the second chopper circuit is the output terminal of the chopper comparator.

[0023] The forward clock signal and the reverse clock signal are input into the first input terminal and the second input terminal of the first chopping circuit respectively, and the forward chopping clock signal and the reverse chopping clock signal are outputted after being processed by the first chopping circuit;

[0024] The forward chopping clock signal and the reverse chopping clock signal are input to the first input terminal and the second input terminal of the transconductance comparator respectively, and the transconductance comparator compares the forward chopping clock signal and the reverse chopping clock signal, and outputs a forward clock current signal and a reverse clock current signal;

[0025] The positive clock current signal and the reverse clock current signal are respectively input to the first input terminal and the second input terminal of the second chopper circuit, and the current feedback signal is output after being processed by the second chopper circuit.

[0026] Preferably, the first input end of the transconductance comparator includes a first field effect transistor, the second input end includes a second field effect transistor, the first output end of the transconductance comparator includes a third field effect transistor and a fourth field effect transistor, and the second output end includes a fifth field effect transistor and a sixth field effect transistor.

[0027] The gate of the first field effect transistor is connected to the first output end of the first chopping circuit, the gate of the second field effect transistor is connected to the second output end of the first chopping circuit, the drain of the third field effect transistor is connected to the drain of the fourth field effect transistor and outputs the forward clock current signal, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor and outputs the reverse clock current signal.

[0028] Preferably, the feedback circuit comprises a seventh inverter, a first resistor and a second resistor.

[0029] The input end of the seventh inverter is connected to the current feedback signal, the output end of the seventh inverter is connected to one end of the second resistor, the first resistor is connected across the input end and the output end of the seventh inverter, and the other end of the second resistor outputs the voltage feedback signal.

[0030] Preferably, when the duty cycle of the clock signal output by the first inverter is 50%, the forward clock signal and the reverse clock signal are equal, a constant current feedback signal is output, the voltage feedback signal output by the feedback circuit does not change, and the duty cycle of the clock signal remains constant;

[0031] When the duty cycle of the clock signal output by the first inverter is greater than 50%, the voltage of the forward clock signal is greater than the voltage of the reverse clock signal, and a pull-up current feedback signal is output. The voltage feedback signal output by the pull-up current feedback signal increases after passing through the feedback circuit, thereby reducing the duty cycle of the clock signal;

[0032] When the duty cycle of the clock signal output by the first inverter is less than 50%, the voltage of the forward clock signal is less than the voltage of the reverse clock signal, and a pull-down current feedback signal is output. The voltage feedback signal output by the pull-down current feedback signal after passing through the feedback circuit decreases, thereby increasing the duty cycle of the clock signal.

[0033] Preferably, the duty cycle correction circuit further includes an eighth inverter, a ninth inverter and a low-pass filter circuit.

[0034] The input end of the eighth inverter is connected to the first output end of the single-ended to differential circuit, and the output end of the eighth inverter is connected to the first input end of the low-pass filter;

[0035] The input end of the ninth inverter is connected to the second output end of the single-ended to differential circuit, and the output end of the ninth inverter is connected to the second input end of the low-pass filter;

[0036] The first output terminal of the low-pass filter is connected to the first input terminal of the chopper comparator, and the second output terminal of the low-pass filter is connected to the second input terminal of the chopper comparator;

[0037] The low-pass filter is used to filter the forward clock signal and the reverse clock signal, and output a DC bias differential voltage signal, wherein the DC bias differential voltage signal includes a forward bias voltage signal and a reverse bias voltage signal, wherein the forward bias voltage signal is input to the first input terminal of the chopper comparator, and the reverse bias voltage signal is input to the second input terminal of the chopper comparator.

[0038] Preferably, the frequency doubling circuit includes a tenth inverter, an eleventh inverter, a twelfth inverter, a multiplexer and a delay circuit.

[0039] The input end of the tenth inverter is connected to the first output end of the single-ended to differential circuit, the output end of the tenth inverter is connected to the first input end of the multiplexer, the input end of the eleventh inverter is connected to the second output end of the single-ended to differential circuit, the output end of the eleventh inverter is connected to the second input end of the multiplexer, the input end of the delay circuit is connected to the second output end of the single-ended to differential circuit, the output end of the delay circuit is connected to the enable end of the multiplexer, the output end of the multiplexer is connected to the input end of the twelfth inverter, and the twelfth inverter outputs the multiplied clock signal.

[0040] Preferably, it further includes a thirteenth inverter and a fourteenth inverter,

[0041] The input end of the thirteenth inverter is connected to the first output end of the single-ended to differential circuit, the output end of the thirteenth inverter is connected to the first input end of the double frequency circuit, the input end of the fourteenth inverter is connected to the second output end of the single-ended to differential circuit, and the output end of the fourteenth inverter is connected to the second input end of the double frequency circuit.

[0042] The invention also discloses a chip, comprising the crystal oscillator circuit of the invention.

[0043] The invention also discloses an electronic device, comprising the crystal oscillator circuit of the invention, or comprising the chip of the invention.

[0044] The present invention also discloses a clock signal generating method, which is applied to a clock signal generating circuit, wherein the clock signal generating circuit comprises a crystal oscillation amplifier circuit, a duty cycle correction circuit and a frequency doubling circuit, wherein the duty cycle correction circuit comprises a first inverter, a single-ended to differential circuit, a comparator, a feedback circuit and a frequency doubling circuit.

[0045] The output end of the crystal oscillation amplifier circuit is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the single-ended to differential circuit, the first output end of the single-ended to differential circuit is connected to the first input end of the comparator, the second output end of the single-ended to differential circuit is connected to the second input end of the comparator, the output end of the comparator is connected to the input end of the feedback circuit, the output end of the feedback circuit is connected to the input end of the first inverter, the first input end of the double frequency circuit is connected to the first output end of the single-ended to differential circuit, the second input end of the double frequency circuit is connected to the second output end of the unit to differential circuit, and the method includes:

[0046] The feedback circuit outputs a voltage feedback signal according to the current feedback signal output by the comparator, thereby adjusting the duty cycle of the clock signal output by the first inverter according to the voltage feedback signal, wherein the differential clock signal includes a positive clock signal and a negative clock signal, the first output terminal of the single-ended to differential circuit outputs the positive clock signal, and the second output terminal outputs the negative clock signal, and the comparator outputs the current feedback signal according to the differential clock signal output by the single-ended to differential circuit;

[0047] When the duty cycle of the clock signal output by the first inverter is 50%, the positive clock signal and the reverse clock signal output by the single-ended to differential circuit are equal, the current feedback signal output by the comparator is a constant current signal, the voltage feedback signal output by the feedback circuit according to the current feedback signal does not change, and the duty cycle of the clock signal remains constant;

[0048] When the duty cycle of the clock signal output by the first inverter is greater than 50%, the voltage of the positive clock signal output by the single-ended to differential circuit is greater than the voltage of the reverse clock signal, the current feedback signal output by the comparator is a pull-up feedback current, the voltage feedback signal output by the feedback circuit according to the current feedback signal increases, and the duty cycle of the clock signal decreases;

[0049] When the duty cycle of the clock signal output by the first inverter is less than 50%, the voltage of the positive clock signal output by the single-ended to differential circuit is less than the voltage of the reverse clock signal, the current feedback signal output by the comparator is a pull-down feedback current, the voltage feedback signal output by the feedback circuit according to the current feedback signal decreases, and the duty cycle of the clock signal increases;

[0050] The frequency doubling circuit performs frequency doubling processing on the differential clock signal output by the single-ended to differential circuit, and outputs a frequency doubling clock signal.

[0051] The crystal oscillator circuit of the present invention converts the input clock signal into a differential clock signal through a single-ended to differential circuit, and then a comparator compares the differential clock signal to generate a current feedback signal, and outputs a voltage feedback signal through a feedback circuit, thereby adjusting the duty cycle of the input clock signal according to the voltage feedback signal. Using a comparator, both the input offset voltage and the output noise can be reduced, thereby improving the stability of the entire negative feedback loop and reducing the random mismatch and system mismatch of the entire system. At the same time, the calibrated clock signal is converted through a single-ended to differential circuit to generate two differential clock signals, which are input into a double frequency circuit, and a double frequency clock signal is output, so that the two input clocks of the double frequency circuit will not be unbalanced like the traditional method, so the jitter of the output clock is smaller and the performance is higher.

[0052] Other beneficial effects of the present invention will be explained in the specific implementation manner through the introduction of specific technical features and technical solutions. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The preferred implementation of the crystal oscillator circuit of the present invention will be described below with reference to the accompanying drawings. In the drawings:

[0054] Figure 1 A block diagram of a crystal oscillator circuit according to a preferred embodiment of the present invention;

[0055] Figure 2 A schematic diagram of a single-ended to differential circuit according to a preferred embodiment of the present invention;

[0056] Figure 3 A block diagram of a chopper comparator circuit according to a preferred embodiment of the present invention;

[0057] Figure 4 A schematic diagram of a feedback circuit according to a preferred embodiment of the present invention;

[0058] Figure 5 A schematic diagram of a transconductance comparator (GM) circuit according to a preferred embodiment of the present invention;

[0059] Figure 6 A block diagram of a crystal oscillator circuit according to another preferred embodiment of the present invention;

[0060] Figure 7 A schematic diagram of a frequency doubling circuit according to a preferred embodiment of the present invention;

[0061] Figure 8 The figure is a schematic diagram of a crystal oscillator circuit according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0062] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. In order to avoid confusing the essence of the present invention, known methods, processes, procedures, and components are not described in detail.

[0063] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0064] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0065] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0066] Figure 1 The present invention is a block diagram of a crystal oscillator circuit according to a preferred embodiment of the present invention, comprising a crystal oscillator amplifier circuit 10, a duty cycle correction circuit 20 and a frequency doubling circuit 30. The duty cycle correction circuit 20 comprises a first inverter 21 (INV1), a single-ended to differential circuit 22, a comparator 23 and a feedback circuit 24. The output end of the crystal oscillator amplifier circuit 10 is connected to the input end of the first inverter 21, the output end of the first inverter 21 is connected to the input end of the single-ended to differential circuit 22, the first output end of the single-ended to differential circuit 22 is connected to the first input end of the comparator 23, the second output end of the single-ended to differential circuit 22 is connected to the second input end of the comparator 23, the output end of the comparator 23 is connected to the input end of the feedback circuit 24, the output end of the feedback circuit 24 is connected to the input end of the first inverter 21, the first input end of the frequency doubling circuit 30 is connected to the first output end of the single-ended to differential circuit 22, and the second input end of the frequency doubling circuit 30 is connected to the second output end of the unit to differential circuit 22.

[0067] Among them, the crystal oscillator amplifier circuit 10 is used to output the clock signal Fosc, and the first inverter 21 is used to reversely process the clock signal Fosc output by the crystal oscillator circuit; the single-ended differential circuit 22 is used to generate a differential clock signal according to the clock signal output by the first inverter 21, and the differential clock signal includes a positive clock signal CLKP and a reverse clock signal CLKN. The first output end of the single-ended differential circuit 22 outputs the positive clock signal CLKP, and the second output end outputs the reverse clock signal CLKN; the comparator 23 is used to receive the positive clock signal CLKP and the reverse clock signal CLKN, and output a current feedback signal after comparison processing; the feedback circuit 24 is used to output a voltage feedback signal to the input end of the first inverter 21 according to the current feedback signal, so as to adjust the bias voltage of the first inverter 21, thereby adjusting the duty cycle of the clock signal output by the first inverter 21, and the double frequency circuit 30 outputs the doubled frequency clock signal to the clock system according to the positive clock signal and the reverse clock signal output by the single-ended differential circuit 22, so as to serve as a reference clock source.

[0068] The crystal oscillator amplifier circuit 10 generally includes a quartz crystal oscillator and an amplifier circuit. The amplifier circuit provides sufficient gain for both ends of the quartz crystal oscillator to enable it to oscillate stably, and amplifies the oscillation signal to generate a clock signal with a frequency of Fosc.

[0069] The crystal oscillator circuit of the present invention converts the input clock signal into a differential clock signal through a single-ended differential circuit, and then a comparator compares the differential clock signal to generate a current feedback signal, and a voltage feedback signal is output through a feedback circuit, thereby adjusting the duty cycle of the input clock signal according to the voltage feedback signal. Using a comparator, both the input offset voltage and the output noise can be reduced, thereby improving the stability of the entire negative feedback loop and reducing the random mismatch and system mismatch of the system. At the same time, the calibrated clock signal is passed through a single-ended differential circuit to generate two differential clock signals (CLKP and CLKN) that are input into a double frequency circuit, and a double frequency clock signal is output, so that the two input clocks of the double frequency circuit are not unbalanced like the traditional method, so the jitter of the output clock is smaller and the performance is higher.

[0070] In a preferred embodiment, Figure 2 As shown, the single-ended to differential circuit 22 may include a transmission gate Tg, a second inverter INV2, a third unidirectional device INV3, a fourth inverter INV4, a fifth inverter INV5 and a sixth inverter INV6, wherein the clock signal (i.e. Figure 2The CLKIN in the transmission gate Tg is respectively connected to the input end of the transmission gate Tg and the input end of the second inverter INV2, the clock signal passing through the transmission gate Tg is input to the input end of the third inverter INV3, the clock signal passing through the second inverter INV2 is input to the input end of the fourth inverter INV4, the input end of the fifth inverter INV5 is connected to the output end of the third inverter INV3, the output end of the fifth inverter INV5 is connected to the output end of the fourth inverter INV4, the input end of the sixth inverter INV6 is connected to the output end of the fourth inverter INV4, the output end of the sixth inverter INV6 is connected to the output end of the third inverter INV3, the output signal of the fifth inverter INV5 is the forward clock signal CLKP, and the output signal of the sixth inverter INV6 is the reverse clock signal CLKN. In this embodiment, a fifth inverter INV5 and a sixth inverter INV6 are additionally provided. These two inverters are connected end to end and are respectively connected to the output ends of the third inverter INV3 and the fourth inverter INV4. Such a design makes the output differential clock signal more balanced.

[0071] In a preferred embodiment, the comparator 23 can be a transconductance comparator, a first input terminal of the transconductance comparator is connected to the first output terminal of the single-ended to differential circuit, a second input terminal of the transconductance comparator is connected to the second output terminal of the single-ended to differential circuit, an output terminal of the transconductance comparator is connected to the input terminal of the feedback circuit, a positive clock signal and a reverse clock signal are respectively input to the first input terminal and the second input terminal of the transconductance comparator, the transconductance comparator compares the positive clock signal and the reverse clock signal, and outputs a current feedback signal.

[0072] In a preferred embodiment, Figure 3As shown, the comparator 23 is a chopper comparator, which may include a first chopper circuit 231, a transconductance comparator 232, and a second chopper circuit 233. The first input terminal and the second input terminal of the first chopper circuit 231 are respectively the first input terminal and the second input terminal of the chopper comparator. The first output terminal and the second output terminal of the first chopper circuit 231 are respectively connected to the first input terminal and the second input terminal of the transconductance comparator 232. The first output terminal and the second output terminal of the transconductance comparator 232 are respectively connected to the first input terminal and the second input terminal of the second chopper circuit 233. The output terminal of the second chopper circuit 233 is the output terminal of the chopper comparator. The positive clock signal C output by the single-ended to differential circuit 22 is LKP and the reverse clock signal CLKN are respectively input to the first input end and the second input end of the first chopping circuit 231, and after being processed by the first chopping circuit 231, a forward chopping clock signal and a reverse chopping clock signal are output; the forward chopping clock signal and the reverse chopping clock signal are respectively input to the first input end and the second input end of the transconductance comparator 232, and the transconductance comparator 232 compares the forward chopping clock signal and the reverse chopping clock signal, and outputs a forward clock current signal and a reverse clock current signal; the forward clock current signal and the reverse clock current signal are respectively input to the first input end and the second input end of the second chopping circuit 233, and after being processed by the second chopping circuit 233, a current feedback signal is output. Using a comparator with chopping can further reduce the input offset voltage and further reduce the output noise, so that the stability of the entire negative feedback loop is further improved, and the random mismatch and system mismatch of the system are further reduced.

[0073] In a preferred embodiment, the first input end of the transconductance comparator 232 may include a first field effect transistor, the second input end may include a second field effect transistor, the first output end of the transconductance comparator 232 may include a third field effect transistor and a fourth field effect transistor, and the second output end may include a fifth field effect transistor and a sixth field effect transistor, wherein the gate of the first field effect transistor is connected to the first output end of the first chopping circuit 231, the gate of the second field effect transistor is connected to the second output end of the first chopping circuit, the drain of the third field effect transistor is connected to the drain of the fourth field effect transistor, and outputs the forward clock current signal, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor, and outputs the reverse clock current signal.

[0074] In a preferred embodiment, Figure 4 As shown, the feedback circuit 24 may include a seventh inverter INV7, a first resistor R1 and a second resistor R2, wherein the input end of the seventh inverter INV7 is connected to a current feedback signal, the output end of the seventh inverter INV7 is connected to one end of the second resistor R2, the first resistor R1 is connected across the input end and the output end of the seventh inverter INV7, and the other end of the second resistor R2 outputs a voltage feedback signal.

[0075] In a preferred embodiment, when the duty cycle of the clock signal output by the first inverter 21 is 50%, the positive clock signal CLKP and the reverse clock signal CLKN are equal, the current feedback signal is a constant current signal, the voltage feedback signal output by the current feedback signal through the feedback circuit 24 does not change, and the duty cycle of the clock signal remains constant; when the duty cycle of the clock signal output by the first inverter 21 is greater than 50%, the voltage of the positive clock signal CLKP is greater than the voltage of the reverse clock signal CLKN, the current feedback signal is a pull-up feedback current, the voltage feedback signal output by the current feedback signal after passing through the feedback circuit 24 increases, and the duty cycle of the clock signal decreases; when the duty cycle of the clock signal output by the first inverter 21 is less than 50%, the voltage of the positive clock signal CLKP is less than the voltage of the reverse clock signal CLKN, the current feedback signal is a pull-down feedback current, the voltage feedback signal output by the current feedback signal after passing through the feedback circuit 24 decreases, and the duty cycle of the clock signal increases.

[0076] Figure 5 This is a transconductance comparator circuit diagram of a preferred embodiment of the present invention. This is only a specific embodiment, and other circuits with the same function can also be used. It should be noted that the "K", "M" and "1" marked in the figure represent the current multiple relationship between the current mirror and each field effect tube, not a specific value, and can be set according to circuit requirements. In the figure, the input differential pair tubes Mnip and Mnin are provided with current bias by current sources I1 and I2 as well as Mp6 and Mp3. The bias voltages Vip and Vin of the input differential pair tubes are amplified and converted into current signal output. In a specific example, K=4 and M=5 can be selected. When the input signal remains unchanged, the currents of Mnip and Mnin are both 5 parts, and the current of the current source I3 is 10 parts and no longer changes. At this time, the output signal is a constant signal.

[0077] When the input is unbalanced, assuming that the current flows entirely through Mnip in 10 parts, since K=4, the current flowing through field effect transistor Mp6 becomes 6 parts. After mirroring, the current of field effect transistor Mp7 changes from M=5 to M=30. Therefore, the current is amplified, and the pulled-up current feedback signal is output through the output field effect transistors Mn1, Mp8 and Mn4. The voltage feedback signal output after the pulled-up current feedback signal passes through the feedback circuit 24 increases, and the increased voltage feedback signal is output to the input end of the single-ended differential circuit, thereby reducing the duty cycle of the clock signal.

[0078] On the contrary, assuming that all the current flows through Mnin in 10 parts, since K=4, the current flowing through the field effect transistor Mp3 becomes 6 parts. After mirroring, the current of the field effect transistor Mp4 changes from M=5 to M=30. Therefore, the current is amplified, and the pull-down current feedback signal is output through the output field effect transistors Mn2, Mp5 and Mn3. The voltage feedback signal output after the pull-up current feedback signal passes through the feedback circuit 24 is reduced, and the reduced voltage feedback signal is output to the input end of the single-ended differential circuit, thereby increasing the duty cycle of the clock signal.

[0079] In a preferred embodiment, Figure 6 As shown, the duty cycle correction circuit also includes an eighth inverter INV8, a ninth inverter INV9 and a low-pass filter circuit 25, the input end of the eighth inverter INV8 is connected to the first output end of the single-ended differential circuit 22, and the output end of the eighth inverter INV8 is connected to the first input end of the low-pass filter 25; the input end of the ninth inverter INV9 is connected to the second output end of the single-ended differential circuit 22, and the output end of the ninth inverter INV9 is connected to the second input end of the low-pass filter 25; the first output end of the low-pass filter 25 is connected to the first input end of the comparator 23, and the second output end of the low-pass filter 25 is connected to the second input end of the comparator 23; the low-pass filter 25 is used to filter the forward clock signal and the reverse clock signal, and output a DC bias differential voltage signal, wherein the DC bias differential voltage signal includes a forward bias voltage signal VP and a reverse bias voltage signal VN, the forward bias voltage signal VP is input to the first input end of the comparator 23, and the reverse bias voltage signal VN is input to the second input end of the comparator 23. In one embodiment, the low-pass filter 25 is two sets of RC low-pass filters.

[0080] In a preferred embodiment, Figure 7 As shown, the double frequency circuit 30 may include a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12, a multiplexer Mux and a delay circuit TD, the input end of the tenth inverter INV10 is connected to the first output end CLKP of the single-ended differential circuit 22, the output end of the tenth inverter INV10 is connected to the first input end A of the multiplexer Mux, the input end of the eleventh inverter INV11 is connected to the second output end CLKN of the single-ended differential circuit 22, the output end of the eleventh inverter INV11 is connected to the second input end B of the multiplexer Mux, the input end of the delay circuit TD is connected to the second output end CLKN of the single-ended differential circuit 22, the output end of the delay circuit TD is connected to the enable end S of the multiplexer Mux, the output end of the multiplexer Mux is connected to the input end of the twelfth inverter INV12, and the twelfth inverter INV12 outputs the doubled frequency clock signal.

[0081] The delay time of the delay module TD may be 1 / 4T, where T=1 / Fosc.

[0082] In a preferred embodiment, the crystal oscillator circuit also includes a thirteenth inverter and a fourteenth inverter, the input end of the thirteenth inverter INV13 is connected to the first output end CLKP of the single-ended to differential circuit 22, the output end of the thirteenth inverter INV13 is connected to the first input end of the double frequency circuit 30, the input end of the fourteenth inverter INV14 is connected to the second output end of the single-ended to differential circuit 22, and the output end of the fourteenth inverter INV14 is connected to the second input end of the double frequency circuit 30.

[0083] like Figure 8 As shown, it is a schematic diagram of a crystal oscillator circuit according to a preferred embodiment of the present invention, including a crystal oscillation amplifier circuit 10, a duty cycle correction circuit 20 and a double frequency circuit 30, the duty cycle correction circuit 20 includes a first inverter 21, a single-ended differential circuit 22, a chopper comparator 23, a feedback circuit 24, a low-pass filter 25 and inverters INV8, INV9, INV13, and INV14, wherein 11 in the crystal oscillation amplifier circuit 10 is a quartz crystal oscillator, and the rest are amplifier circuits.

[0084] The crystal oscillator circuit 10 includes a current source I1, an oscillator tube Mnosc, a feedback resistor R3, a quartz crystal oscillator 11, and load capacitors C1 and C2. One end of I1 is connected to the power supply VDD, and the other end is connected to the drain of the oscillator tube Mnosc. The source of the oscillator tube Mnosc is grounded, and the gate is connected to the feedback resistor R3. The other end of the feedback resistor R3 is connected to the drain of the oscillator tube Mnosc. The quartz crystal oscillator 11 is connected across the gate and drain of the oscillator tube Mnosc. The load capacitors C1 and C2 are connected to the quartz crystal oscillator 11 respectively, and the other end is grounded. The output clock Fosc of the crystal oscillator amplifier circuit 10 is output from the gate of the oscillator tube Mnosc, enters the input end of the first inverter INV1 through AC coupling of the capacitor C3, and the output end of the first inverter INV1 is connected to the single-ended differential circuit 22.

[0085] The input end of the single-ended to differential circuit 22 is connected to the output end of the first inverter INV1, and the low-pass filter 25 includes two groups of RC low-pass filters, wherein the output clock CLKN of the single-ended to differential circuit 22 is connected to the resistor R4 through the inverter INV8, and the other end of the resistor is connected to the capacitor C4, and the other end of the capacitor C4 is grounded, forming a group of low-pass filters; the other group of low-pass filters is formed by the output clock CLKP of the single-ended to differential circuit 22 being connected to the resistor R5 through the inverter INV9, and the other end of the resistor is connected to the capacitor C5, and the other end of the capacitor C5 is grounded. The output VP and VN signals of the low-pass filter are connected to the chopper comparator 23.

[0086] The chopper comparator 23 includes two self-choppers and comparators. The input of the low-pass filter 25 is input to the transconductance comparator (GM module) through the chopper circuit. The output of the GM module generates a feedback current signal Ifb after passing through the chopper circuit and input into the feedback circuit 24. The voltage feedback signal output by the feedback circuit 24 adjusts the input bias voltage of the first inverter INV1, thereby changing the duty cycle of the clock signal output by the first inverter INV1.

[0087] First, the amplifier circuit composed of the current source I1, the oscillator tube Mnosc and the feedback resistor R3 provides enough gain for both ends of the quartz crystal oscillator 11, so that it can oscillate stably, and the oscillation signal is feedback-amplified to generate a clock signal with a frequency of Fosc. The clock signal passes through the capacitor C3, is AC-coupled and input into the first inverter INV1, and is output to the single-ended differential circuit 22 through the first inverter INV1 to generate two differential clock signals CLKN and CLKP. The differential signal passes through the inverters INV8 and INV9 and is input into the low-pass filter 25. The low-pass filter 25 filters the clock signal and converts it into two DC bias differential voltage signals and inputs them into the chopping comparator 23. The chopping comparator 23 chops, compares and chops the two differential voltage signals and then outputs a current feedback signal to the feedback circuit, so as to adjust the bias voltage of the first inverter INV1, thereby adjusting the duty cycle of the clock signal. When the duty cycle of the clock signal output by the first inverter INV1 is 50%, the DC bias voltage VP and VN after passing through the low-pass filter 25 are equal. At this time, the feedback signal Ifb output is a constant current signal. After the signal passes through the feedback circuit, the feedback voltage Vfb generated does not change. The gate bias voltage of the first inverter INV1 remains unchanged, and the duty cycle of the clock signal remains constant. When the duty cycle of the clock signal Fosc increases, the VP voltage of the input GM increases and is greater than the VN signal. At this time, after comparison with GM, a pull-up feedback current is output. After passing through the feedback circuit, the generated feedback voltage Vfb increases. At this time, the pull-down capability of the first inverter INV1 is enhanced, and the duty cycle of the clock signal after passing through the inverter decreases, and vice versa, thereby achieving the purpose of adjusting the duty cycle.

[0088] The crystal oscillator circuit integrates duty cycle calibration and frequency multiplier, and is provided with a chopper comparator to compare two differential bias signals converted by a quartz crystal oscillator to generate a feedback signal, and calibrates the duty cycle by adjusting the inverter gate bias voltage through negative feedback, and uses the clock after calibrating the duty cycle as the output of the frequency multiplier, and outputs a multiplied reference clock signal with a stable duty cycle and smaller jitter for use in high-performance clock systems.

[0089] The invention also discloses a chip, comprising the crystal oscillator circuit of the invention.

[0090] The invention also discloses an electronic device, comprising the crystal oscillator circuit of the invention, or comprising the chip of the invention.

[0091] The present invention also discloses a clock signal generating method, which is applied to a clock signal generating circuit, wherein the crystal oscillator circuit comprises a crystal oscillation amplifier circuit, a duty cycle correction circuit and a frequency doubling circuit, wherein the duty cycle correction circuit comprises a first inverter, a single-ended to differential circuit, a comparator and a feedback circuit, wherein the output end of the crystal oscillation amplifier circuit is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the single-ended to differential circuit, the first output end of the single-ended to differential circuit is connected to the first input end of the comparator, the second output end of the single-ended to differential circuit is connected to the second input end of the comparator, the output end of the comparator is connected to the input end of the feedback circuit, the output end of the feedback circuit is connected to the input end of the first inverter, the first input end of the frequency doubling circuit is connected to the first output end of the single-ended to differential circuit, the second input end of the frequency doubling circuit is connected to the second output end of the unit to differential circuit, and the method comprises:

[0092] The feedback circuit outputs a voltage feedback signal according to the current feedback signal output by the comparator, thereby adjusting the duty cycle of the clock signal output by the first inverter according to the voltage feedback signal, wherein the differential clock signal includes a positive clock signal and a negative clock signal, the first output terminal of the single-ended to differential circuit outputs the positive clock signal, and the second output terminal outputs the negative clock signal, and the comparator outputs the current feedback signal according to the differential clock signal output by the single-ended to differential circuit;

[0093] When the duty cycle of the clock signal output by the first inverter is 50%, the positive clock signal and the reverse clock signal output by the single-ended to differential circuit are equal, the current feedback signal output by the chopper comparator is a constant current signal, the voltage feedback signal output by the feedback circuit according to the current feedback signal does not change, and the duty cycle of the clock signal remains constant;

[0094] When the duty cycle of the clock signal output by the first inverter is greater than 50%, the voltage of the positive clock signal output by the single-ended to differential circuit is greater than the voltage of the reverse clock signal, the current feedback signal output by the chopper comparator is a pull-up feedback current, the voltage feedback signal output by the feedback circuit according to the current feedback signal increases, and the duty cycle of the clock signal decreases;

[0095] When the duty cycle of the clock signal output by the first inverter is less than 50%, the voltage of the positive clock signal output by the single-ended to differential circuit is less than the voltage of the reverse clock signal, the current feedback signal output by the chopper comparator is a pull-down feedback current, the voltage feedback signal output by the feedback circuit according to the current feedback signal decreases, and the duty cycle of the clock signal increases;

[0096] The frequency doubling circuit performs frequency doubling processing on the differential clock signal output by the single-ended to differential circuit, and outputs a frequency doubling clock signal.

[0097] It will be appreciated by those skilled in the art that, under the premise of no conflict, the above-mentioned preferred solutions can be freely combined and superimposed. Among them, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the module, program segment, or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings, for example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. The numbering of each step in this article is only for the convenience of description and reference, and is not used to limit the order of execution. The specific execution order is determined by the technology itself, and those skilled in the art can determine various allowable and reasonable orders based on the technology itself.

[0098] It should be noted that the use of step numbers (letters or numbers) to refer to certain specific method steps in the present invention is only for the purpose of convenience and brevity of description, and is by no means intended to limit the order of these method steps by letters or numbers. Those skilled in the art will understand that the order of the relevant method steps should be determined by the technology itself and should not be inappropriately limited by the existence of step numbers. Those skilled in the art can determine various permissible and reasonable step orders based on the technology itself.

[0099] Those skilled in the art will appreciate that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0100] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present invention, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will all be included in the scope of the claims of the present invention.

Claims

1. A crystal oscillator circuit, characterized in that: It includes a crystal oscillation amplifier circuit, a duty cycle correction circuit and a double frequency circuit. The duty cycle correction circuit includes a first inverter, a single-ended to differential circuit, a comparator and a feedback circuit. The output end of the crystal oscillation amplifier circuit is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the single-ended to differential circuit, the first output end of the single-ended to differential circuit is connected to the first input end of the comparator, the second output end of the single-ended to differential circuit is connected to the second input end of the comparator, the output end of the comparator is connected to the input end of the feedback circuit, the output end of the feedback circuit is connected to the input end of the first inverter, the first input end of the double frequency circuit is connected to the first output end of the single-ended to differential circuit, and the second input end of the double frequency circuit is connected to the second output end of the single-ended to differential circuit. The crystal oscillator amplifier circuit is used to output a clock signal; The duty cycle correction circuit is used to adjust the duty cycle of the clock signal output by the first inverter, wherein the first inverter is used to reversely process the clock signal output by the crystal oscillation amplifier circuit; the single-ended to differential circuit is used to generate a differential clock signal according to the clock signal output by the first inverter, the differential clock signal includes a positive clock signal and a negative clock signal, the first output end of the single-ended to differential circuit outputs the positive clock signal, and the second output end outputs the negative clock signal; the comparator is used to receive the positive clock signal and the negative clock signal, and output a current feedback signal after comparison processing; the feedback circuit is used to output a voltage feedback signal to the input end of the first inverter according to the current feedback signal, so as to adjust the bias voltage of the first inverter, thereby adjusting the duty cycle of the clock signal output by the first inverter; The frequency doubling circuit is used to output a frequency-doubled clock signal to a clock system according to the forward clock signal and the reverse clock signal, so as to serve as a reference clock source; The comparator is a chopper comparator, which includes a first chopper circuit, a transconductance comparator and a second chopper circuit. The first input terminal and the second input terminal of the first chopper circuit are respectively the first input terminal and the second input terminal of the chopper comparator. The first output terminal and the second output terminal of the first chopper circuit are respectively connected to the first input terminal and the second input terminal of the transconductance comparator. The first output terminal and the second output terminal of the transconductance comparator are respectively connected to the first input terminal and the second input terminal of the second chopper circuit. The output terminal of the second chopper circuit is the output terminal of the chopper comparator. The positive clock signal and the reverse clock signal are respectively The first chopping circuit is input to the first input terminal and the second input terminal, and a forward chopping clock signal and a reverse chopping clock signal are output after being processed by the first chopping circuit; the forward chopping clock signal and the reverse chopping clock signal are respectively input to the first input terminal and the second input terminal of the transconductance comparator, and the transconductance comparator compares the forward chopping clock signal and the reverse chopping clock signal, and outputs a forward clock current signal and a reverse clock current signal; the forward clock current signal and the reverse clock current signal are respectively input to the first input terminal and the second input terminal of the second chopping circuit, and the current feedback signal is output after being processed by the second chopping circuit.

2. The crystal oscillator circuit according to claim 1, characterized in that: The single-ended to differential circuit comprises a transmission gate, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a sixth inverter; The clock signal output by the first inverter is connected to the input terminals of the transmission gate and the second inverter respectively; The clock signal passing through the transmission gate is input to the input end of the third inverter, and the clock signal passing through the second inverter is input to the input end of the fourth inverter; The input end of the fifth inverter is connected to the output end of the third inverter, and the output end of the fifth inverter is connected to the output end of the fourth inverter; The input end of the sixth inverter is connected to the output end of the fourth inverter, and the output end of the sixth inverter is connected to the output end of the third inverter; The output signal of the fifth inverter is the forward clock signal, and the output signal of the sixth inverter is the reverse clock signal.

3. The crystal oscillator circuit according to claim 1, characterized in that: The comparator is a transconductance comparator, The first input terminal of the transconductance comparator is connected to the first output terminal of the single-ended to differential circuit, the second input terminal of the transconductance comparator is connected to the second output terminal of the single-ended to differential circuit, and the output terminal of the transconductance comparator is connected to the input terminal of the feedback circuit; The positive clock signal and the reverse clock signal are input to the first input terminal and the second input terminal of the transconductance comparator respectively. The transconductance comparator compares the positive clock signal with the reverse clock signal and outputs a current feedback signal.

4. The crystal oscillator circuit according to claim 1, characterized in that: The first input end of the transconductance comparator includes a first field effect transistor, the second input end includes a second field effect transistor, the first output end of the transconductance comparator includes a third field effect transistor and a fourth field effect transistor, and the second output end includes a fifth field effect transistor and a sixth field effect transistor. The gate of the first field effect transistor is connected to the first output end of the first chopping circuit, the gate of the second field effect transistor is connected to the second output end of the first chopping circuit, the drain of the third field effect transistor is connected to the drain of the fourth field effect transistor and outputs the forward clock current signal, and the drain of the fifth field effect transistor is connected to the drain of the sixth field effect transistor and outputs the reverse clock current signal.

5. The crystal oscillator circuit according to claim 1, characterized in that: The feedback circuit includes a seventh inverter, a first resistor and a second resistor. The input end of the seventh inverter is connected to the current feedback signal, the output end of the seventh inverter is connected to one end of the second resistor, the first resistor is connected across the input end and the output end of the seventh inverter, and the other end of the second resistor outputs the voltage feedback signal.

6. The crystal oscillator circuit according to claim 1, characterized in that: When the duty cycle of the clock signal output by the first inverter is 50%, the forward clock signal and the reverse clock signal are equal, a constant current feedback signal is output, the voltage feedback signal output by the feedback circuit does not change, and the duty cycle of the clock signal remains constant; When the duty cycle of the clock signal output by the first inverter is greater than 50%, the voltage of the forward clock signal is greater than the voltage of the reverse clock signal, and a pull-up current feedback signal is output. The voltage feedback signal output by the pull-up current feedback signal after passing through the feedback circuit increases, thereby reducing the duty cycle of the clock signal; When the duty cycle of the clock signal output by the first inverter is less than 50%, the voltage of the forward clock signal is less than the voltage of the reverse clock signal, and a pull-down current feedback signal is output. The voltage feedback signal output by the pull-down current feedback signal after passing through the feedback circuit decreases, thereby increasing the duty cycle of the clock signal.

7. The crystal oscillator circuit according to claim 1, characterized in that: The duty cycle correction circuit also includes an eighth inverter, a ninth inverter and a low-pass filter circuit. The input end of the eighth inverter is connected to the first output end of the single-ended to differential circuit, and the output end of the eighth inverter is connected to the first input end of the low-pass filter circuit; The input end of the ninth inverter is connected to the second output end of the single-ended to differential circuit, and the output end of the ninth inverter is connected to the second input end of the low-pass filter circuit; The first output end of the low-pass filter circuit is connected to the first input end of the chopper comparator, and the second output end of the low-pass filter circuit is connected to the second input end of the chopper comparator; The low-pass filter circuit is used to filter the forward clock signal and the reverse clock signal, and output a DC bias differential voltage signal, wherein the DC bias differential voltage signal includes a forward bias voltage signal and a reverse bias voltage signal, wherein the forward bias voltage signal is input to the first input terminal of the chopper comparator, and the reverse bias voltage signal is input to the second input terminal of the chopper comparator.

8. The crystal oscillator circuit according to claim 1, characterized in that: The frequency doubling circuit includes a tenth inverter, an eleventh inverter, a twelfth inverter, a multiplexer and a delay circuit. The input end of the tenth inverter is connected to the first output end of the single-ended to differential circuit, the output end of the tenth inverter is connected to the first input end of the multiplexer, the input end of the eleventh inverter is connected to the second output end of the single-ended to differential circuit, the output end of the eleventh inverter is connected to the second input end of the multiplexer, the input end of the delay circuit is connected to the second output end of the single-ended to differential circuit, the output end of the delay circuit is connected to the enable end of the multiplexer, the output end of the multiplexer is connected to the input end of the twelfth inverter, and the twelfth inverter outputs the multiplied clock signal.

9. The crystal oscillator circuit according to claim 1, characterized in that: further comprising a thirteenth inverter and a fourteenth inverter, The input end of the thirteenth inverter is connected to the first output end of the single-ended to differential circuit, the output end of the thirteenth inverter is connected to the first input end of the double frequency circuit, the input end of the fourteenth inverter is connected to the second output end of the single-ended to differential circuit, and the output end of the fourteenth inverter is connected to the second input end of the double frequency circuit.

10. A chip, characterized in that: Comprising the crystal oscillator circuit as described in any one of claims 1-9.

11. An electronic device, characterized in that: Includes the crystal oscillator circuit as described in any one of claims 1 to 9, or includes the chip as described in claim 10.

12. A clock signal generating method, applied to a clock signal generating circuit, characterized in that: The clock signal generating circuit includes a crystal oscillator amplifier circuit, a duty cycle correction circuit and a frequency doubling circuit. The duty cycle correction circuit includes a first inverter, a single-ended to differential circuit, a comparator and a feedback circuit. The output end of the crystal oscillator amplifier circuit is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the single-ended to differential circuit, the first output end of the single-ended to differential circuit is connected to the first input end of the comparator, the second output end of the single-ended to differential circuit is connected to the second input end of the comparator, the output end of the comparator is connected to the input end of the feedback circuit, the output end of the feedback circuit is connected to the input end of the first inverter, the first input end of the double frequency circuit is connected to the first output end of the single-ended to differential circuit, the second input end of the double frequency circuit is connected to the second output end of the single-ended to differential circuit, wherein the comparator is a chopper comparator, the chopper comparator includes a first chopper circuit, a transconductance comparator and a second chopper circuit, the first input end and the second input end of the first chopper circuit are respectively the first input end and the second input end of the chopper comparator, the first output end and the second output end of the first chopper circuit are respectively The first and second output ends of the transconductance comparator are respectively connected to the first and second input ends of the second chopping circuit, the output end of the second chopping circuit is the output end of the chopping comparator, the positive clock signal and the negative clock signal are respectively input to the first and second input ends of the first chopping circuit, and the positive chopping clock signal and the negative chopping clock signal are output after being processed by the first chopping circuit; the positive chopping clock signal and the negative chopping clock signal are respectively input to the first and second input ends of the transconductance comparator, the transconductance comparator compares the positive chopping clock signal and the negative chopping clock signal, and outputs the positive clock current signal and the negative clock current signal; the positive clock current signal and the negative clock current signal are respectively input to the first and second input ends of the second chopping circuit, and the current feedback signal is output after being processed by the second chopping circuit. The method comprises: The feedback circuit outputs a voltage feedback signal according to the current feedback signal output by the comparator, thereby adjusting the duty cycle of the clock signal output by the first inverter according to the voltage feedback signal, wherein the first output terminal of the single-ended to differential circuit outputs a positive clock signal and the second output terminal outputs a reverse clock signal, and the comparator outputs the current feedback signal according to the differential clock signal output by the single-ended to differential circuit, and the differential clock signal includes the positive clock signal and the reverse clock signal; When the duty cycle of the clock signal output by the first inverter is 50%, the forward clock signal and the reverse clock signal output by the single-ended to differential circuit are equal, the current feedback signal output by the comparator is a constant current signal, the voltage feedback signal output by the feedback circuit according to the current feedback signal does not change, and the duty cycle of the clock signal remains constant; When the duty cycle of the clock signal output by the first inverter is greater than 50%, the voltage of the positive clock signal output by the single-ended to differential circuit is greater than the voltage of the reverse clock signal, the current feedback signal output by the comparator is a pull-up feedback current, the voltage feedback signal output by the feedback circuit according to the current feedback signal increases, and the duty cycle of the clock signal decreases; When the duty cycle of the clock signal output by the first inverter is less than 50%, the voltage of the positive clock signal output by the single-ended to differential circuit is less than the voltage of the reverse clock signal, the current feedback signal output by the comparator is a pull-down feedback current, the voltage feedback signal output by the feedback circuit according to the current feedback signal decreases, and the duty cycle of the clock signal increases; The frequency doubling circuit performs frequency doubling processing on the differential clock signal output by the single-ended to differential circuit, and outputs a frequency doubling clock signal.

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